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[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / broadcom / brcm80211 / brcmfmac / sdio.c
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/types.h>
18 #include <linux/atomic.h>
19 #include <linux/kernel.h>
20 #include <linux/kthread.h>
21 #include <linux/printk.h>
22 #include <linux/pci_ids.h>
23 #include <linux/netdevice.h>
24 #include <linux/interrupt.h>
25 #include <linux/sched/signal.h>
26 #include <linux/mmc/sdio.h>
27 #include <linux/mmc/sdio_ids.h>
28 #include <linux/mmc/sdio_func.h>
29 #include <linux/mmc/card.h>
30 #include <linux/semaphore.h>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
33 #include <linux/bcma/bcma.h>
34 #include <linux/debugfs.h>
35 #include <linux/vmalloc.h>
36 #include <asm/unaligned.h>
37 #include <defs.h>
38 #include <brcmu_wifi.h>
39 #include <brcmu_utils.h>
40 #include <brcm_hw_ids.h>
41 #include <soc.h>
42 #include "sdio.h"
43 #include "chip.h"
44 #include "firmware.h"
45 #include "core.h"
46 #include "common.h"
47 #include "bcdc.h"
48
49 #define DCMD_RESP_TIMEOUT msecs_to_jiffies(2500)
50 #define CTL_DONE_TIMEOUT msecs_to_jiffies(2500)
51
52 #ifdef DEBUG
53
54 #define BRCMF_TRAP_INFO_SIZE 80
55
56 #define CBUF_LEN (128)
57
58 /* Device console log buffer state */
59 #define CONSOLE_BUFFER_MAX 2024
60
61 struct rte_log_le {
62 __le32 buf; /* Can't be pointer on (64-bit) hosts */
63 __le32 buf_size;
64 __le32 idx;
65 char *_buf_compat; /* Redundant pointer for backward compat. */
66 };
67
68 struct rte_console {
69 /* Virtual UART
70 * When there is no UART (e.g. Quickturn),
71 * the host should write a complete
72 * input line directly into cbuf and then write
73 * the length into vcons_in.
74 * This may also be used when there is a real UART
75 * (at risk of conflicting with
76 * the real UART). vcons_out is currently unused.
77 */
78 uint vcons_in;
79 uint vcons_out;
80
81 /* Output (logging) buffer
82 * Console output is written to a ring buffer log_buf at index log_idx.
83 * The host may read the output when it sees log_idx advance.
84 * Output will be lost if the output wraps around faster than the host
85 * polls.
86 */
87 struct rte_log_le log_le;
88
89 /* Console input line buffer
90 * Characters are read one at a time into cbuf
91 * until <CR> is received, then
92 * the buffer is processed as a command line.
93 * Also used for virtual UART.
94 */
95 uint cbuf_idx;
96 char cbuf[CBUF_LEN];
97 };
98
99 #endif /* DEBUG */
100 #include <chipcommon.h>
101
102 #include "bus.h"
103 #include "debug.h"
104 #include "tracepoint.h"
105
106 #define TXQLEN 2048 /* bulk tx queue length */
107 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
108 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
109 #define PRIOMASK 7
110
111 #define TXRETRIES 2 /* # of retries for tx frames */
112
113 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
114 one scheduling */
115
116 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
117 one scheduling */
118
119 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
120
121 #define MEMBLOCK 2048 /* Block size used for downloading
122 of dongle image */
123 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
124 biggest possible glom */
125
126 #define BRCMF_FIRSTREAD (1 << 6)
127
128 #define BRCMF_CONSOLE 10 /* watchdog interval to poll console */
129
130 /* SBSDIO_DEVICE_CTL */
131
132 /* 1: device will assert busy signal when receiving CMD53 */
133 #define SBSDIO_DEVCTL_SETBUSY 0x01
134 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
135 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
136 /* 1: mask all interrupts to host except the chipActive (rev 8) */
137 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
138 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
139 * sdio bus power cycle to clear (rev 9) */
140 #define SBSDIO_DEVCTL_PADS_ISO 0x08
141 /* Force SD->SB reset mapping (rev 11) */
142 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
143 /* Determined by CoreControl bit */
144 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
145 /* Force backplane reset */
146 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
147 /* Force no backplane reset */
148 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
149
150 /* direct(mapped) cis space */
151
152 /* MAPPED common CIS address */
153 #define SBSDIO_CIS_BASE_COMMON 0x1000
154 /* maximum bytes in one CIS */
155 #define SBSDIO_CIS_SIZE_LIMIT 0x200
156 /* cis offset addr is < 17 bits */
157 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
158
159 /* manfid tuple length, include tuple, link bytes */
160 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
161
162 #define CORE_BUS_REG(base, field) \
163 (base + offsetof(struct sdpcmd_regs, field))
164
165 /* SDIO function 1 register CHIPCLKCSR */
166 /* Force ALP request to backplane */
167 #define SBSDIO_FORCE_ALP 0x01
168 /* Force HT request to backplane */
169 #define SBSDIO_FORCE_HT 0x02
170 /* Force ILP request to backplane */
171 #define SBSDIO_FORCE_ILP 0x04
172 /* Make ALP ready (power up xtal) */
173 #define SBSDIO_ALP_AVAIL_REQ 0x08
174 /* Make HT ready (power up PLL) */
175 #define SBSDIO_HT_AVAIL_REQ 0x10
176 /* Squelch clock requests from HW */
177 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
178 /* Status: ALP is ready */
179 #define SBSDIO_ALP_AVAIL 0x40
180 /* Status: HT is ready */
181 #define SBSDIO_HT_AVAIL 0x80
182 #define SBSDIO_CSR_MASK 0x1F
183 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
184 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
185 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
186 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
187 #define SBSDIO_CLKAV(regval, alponly) \
188 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
189
190 /* intstatus */
191 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
192 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
193 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
194 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
195 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
196 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
197 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
198 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
199 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
200 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
201 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
202 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
203 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
204 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
205 #define I_PC (1 << 10) /* descriptor error */
206 #define I_PD (1 << 11) /* data error */
207 #define I_DE (1 << 12) /* Descriptor protocol Error */
208 #define I_RU (1 << 13) /* Receive descriptor Underflow */
209 #define I_RO (1 << 14) /* Receive fifo Overflow */
210 #define I_XU (1 << 15) /* Transmit fifo Underflow */
211 #define I_RI (1 << 16) /* Receive Interrupt */
212 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
213 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
214 #define I_XI (1 << 24) /* Transmit Interrupt */
215 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
216 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
217 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
218 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
219 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
220 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
221 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
222 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
223 #define I_DMA (I_RI | I_XI | I_ERRORS)
224
225 /* corecontrol */
226 #define CC_CISRDY (1 << 0) /* CIS Ready */
227 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
228 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
229 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
230 #define CC_XMTDATAAVAIL_MODE (1 << 4)
231 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
232
233 /* SDA_FRAMECTRL */
234 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
235 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
236 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
237 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
238
239 /*
240 * Software allocation of To SB Mailbox resources
241 */
242
243 /* tosbmailbox bits corresponding to intstatus bits */
244 #define SMB_NAK (1 << 0) /* Frame NAK */
245 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
246 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
247 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
248
249 /* tosbmailboxdata */
250 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
251
252 /*
253 * Software allocation of To Host Mailbox resources
254 */
255
256 /* intstatus bits */
257 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
258 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
259 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
260 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
261
262 /* tohostmailboxdata */
263 #define HMB_DATA_NAKHANDLED 0x0001 /* retransmit NAK'd frame */
264 #define HMB_DATA_DEVREADY 0x0002 /* talk to host after enable */
265 #define HMB_DATA_FC 0x0004 /* per prio flowcontrol update flag */
266 #define HMB_DATA_FWREADY 0x0008 /* fw ready for protocol activity */
267 #define HMB_DATA_FWHALT 0x0010 /* firmware halted */
268
269 #define HMB_DATA_FCDATA_MASK 0xff000000
270 #define HMB_DATA_FCDATA_SHIFT 24
271
272 #define HMB_DATA_VERSION_MASK 0x00ff0000
273 #define HMB_DATA_VERSION_SHIFT 16
274
275 /*
276 * Software-defined protocol header
277 */
278
279 /* Current protocol version */
280 #define SDPCM_PROT_VERSION 4
281
282 /*
283 * Shared structure between dongle and the host.
284 * The structure contains pointers to trap or assert information.
285 */
286 #define SDPCM_SHARED_VERSION 0x0003
287 #define SDPCM_SHARED_VERSION_MASK 0x00FF
288 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
289 #define SDPCM_SHARED_ASSERT 0x0200
290 #define SDPCM_SHARED_TRAP 0x0400
291
292 /* Space for header read, limit for data packets */
293 #define MAX_HDR_READ (1 << 6)
294 #define MAX_RX_DATASZ 2048
295
296 /* Bump up limit on waiting for HT to account for first startup;
297 * if the image is doing a CRC calculation before programming the PMU
298 * for HT availability, it could take a couple hundred ms more, so
299 * max out at a 1 second (1000000us).
300 */
301 #undef PMU_MAX_TRANSITION_DLY
302 #define PMU_MAX_TRANSITION_DLY 1000000
303
304 /* Value for ChipClockCSR during initial setup */
305 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
306 SBSDIO_ALP_AVAIL_REQ)
307
308 /* Flags for SDH calls */
309 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
310
311 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
312 * when idle
313 */
314 #define BRCMF_IDLE_INTERVAL 1
315
316 #define KSO_WAIT_US 50
317 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
318 #define BRCMF_SDIO_MAX_ACCESS_ERRORS 5
319
320 /*
321 * Conversion of 802.1D priority to precedence level
322 */
323 static uint prio2prec(u32 prio)
324 {
325 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
326 (prio^2) : prio;
327 }
328
329 #ifdef DEBUG
330 /* Device console log buffer state */
331 struct brcmf_console {
332 uint count; /* Poll interval msec counter */
333 uint log_addr; /* Log struct address (fixed) */
334 struct rte_log_le log_le; /* Log struct (host copy) */
335 uint bufsize; /* Size of log buffer */
336 u8 *buf; /* Log buffer (host copy) */
337 uint last; /* Last buffer read index */
338 };
339
340 struct brcmf_trap_info {
341 __le32 type;
342 __le32 epc;
343 __le32 cpsr;
344 __le32 spsr;
345 __le32 r0; /* a1 */
346 __le32 r1; /* a2 */
347 __le32 r2; /* a3 */
348 __le32 r3; /* a4 */
349 __le32 r4; /* v1 */
350 __le32 r5; /* v2 */
351 __le32 r6; /* v3 */
352 __le32 r7; /* v4 */
353 __le32 r8; /* v5 */
354 __le32 r9; /* sb/v6 */
355 __le32 r10; /* sl/v7 */
356 __le32 r11; /* fp/v8 */
357 __le32 r12; /* ip */
358 __le32 r13; /* sp */
359 __le32 r14; /* lr */
360 __le32 pc; /* r15 */
361 };
362 #endif /* DEBUG */
363
364 struct sdpcm_shared {
365 u32 flags;
366 u32 trap_addr;
367 u32 assert_exp_addr;
368 u32 assert_file_addr;
369 u32 assert_line;
370 u32 console_addr; /* Address of struct rte_console */
371 u32 msgtrace_addr;
372 u8 tag[32];
373 u32 brpt_addr;
374 };
375
376 struct sdpcm_shared_le {
377 __le32 flags;
378 __le32 trap_addr;
379 __le32 assert_exp_addr;
380 __le32 assert_file_addr;
381 __le32 assert_line;
382 __le32 console_addr; /* Address of struct rte_console */
383 __le32 msgtrace_addr;
384 u8 tag[32];
385 __le32 brpt_addr;
386 };
387
388 /* dongle SDIO bus specific header info */
389 struct brcmf_sdio_hdrinfo {
390 u8 seq_num;
391 u8 channel;
392 u16 len;
393 u16 len_left;
394 u16 len_nxtfrm;
395 u8 dat_offset;
396 bool lastfrm;
397 u16 tail_pad;
398 };
399
400 /*
401 * hold counter variables
402 */
403 struct brcmf_sdio_count {
404 uint intrcount; /* Count of device interrupt callbacks */
405 uint lastintrs; /* Count as of last watchdog timer */
406 uint pollcnt; /* Count of active polls */
407 uint regfails; /* Count of R_REG failures */
408 uint tx_sderrs; /* Count of tx attempts with sd errors */
409 uint fcqueued; /* Tx packets that got queued */
410 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
411 uint rx_toolong; /* Receive frames too long to receive */
412 uint rxc_errors; /* SDIO errors when reading control frames */
413 uint rx_hdrfail; /* SDIO errors on header reads */
414 uint rx_badhdr; /* Bad received headers (roosync?) */
415 uint rx_badseq; /* Mismatched rx sequence number */
416 uint fc_rcvd; /* Number of flow-control events received */
417 uint fc_xoff; /* Number which turned on flow-control */
418 uint fc_xon; /* Number which turned off flow-control */
419 uint rxglomfail; /* Failed deglom attempts */
420 uint rxglomframes; /* Number of glom frames (superframes) */
421 uint rxglompkts; /* Number of packets from glom frames */
422 uint f2rxhdrs; /* Number of header reads */
423 uint f2rxdata; /* Number of frame data reads */
424 uint f2txdata; /* Number of f2 frame writes */
425 uint f1regdata; /* Number of f1 register accesses */
426 uint tickcnt; /* Number of watchdog been schedule */
427 ulong tx_ctlerrs; /* Err of sending ctrl frames */
428 ulong tx_ctlpkts; /* Ctrl frames sent to dongle */
429 ulong rx_ctlerrs; /* Err of processing rx ctrl frames */
430 ulong rx_ctlpkts; /* Ctrl frames processed from dongle */
431 ulong rx_readahead_cnt; /* packets where header read-ahead was used */
432 };
433
434 /* misc chip info needed by some of the routines */
435 /* Private data for SDIO bus interaction */
436 struct brcmf_sdio {
437 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
438 struct brcmf_chip *ci; /* Chip info struct */
439
440 u32 hostintmask; /* Copy of Host Interrupt Mask */
441 atomic_t intstatus; /* Intstatus bits (events) pending */
442 atomic_t fcstate; /* State of dongle flow-control */
443
444 uint blocksize; /* Block size of SDIO transfers */
445 uint roundup; /* Max roundup limit */
446
447 struct pktq txq; /* Queue length used for flow-control */
448 u8 flowcontrol; /* per prio flow control bitmask */
449 u8 tx_seq; /* Transmit sequence number (next) */
450 u8 tx_max; /* Maximum transmit sequence allowed */
451
452 u8 *hdrbuf; /* buffer for handling rx frame */
453 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
454 u8 rx_seq; /* Receive sequence number (expected) */
455 struct brcmf_sdio_hdrinfo cur_read;
456 /* info of current read frame */
457 bool rxskip; /* Skip receive (awaiting NAK ACK) */
458 bool rxpending; /* Data frame pending in dongle */
459
460 uint rxbound; /* Rx frames to read before resched */
461 uint txbound; /* Tx frames to send before resched */
462 uint txminmax;
463
464 struct sk_buff *glomd; /* Packet containing glomming descriptor */
465 struct sk_buff_head glom; /* Packet list for glommed superframe */
466
467 u8 *rxbuf; /* Buffer for receiving control packets */
468 uint rxblen; /* Allocated length of rxbuf */
469 u8 *rxctl; /* Aligned pointer into rxbuf */
470 u8 *rxctl_orig; /* pointer for freeing rxctl */
471 uint rxlen; /* Length of valid data in buffer */
472 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */
473
474 u8 sdpcm_ver; /* Bus protocol reported by dongle */
475
476 bool intr; /* Use interrupts */
477 bool poll; /* Use polling */
478 atomic_t ipend; /* Device interrupt is pending */
479 uint spurious; /* Count of spurious interrupts */
480 uint pollrate; /* Ticks between device polls */
481 uint polltick; /* Tick counter */
482
483 #ifdef DEBUG
484 uint console_interval;
485 struct brcmf_console console; /* Console output polling support */
486 uint console_addr; /* Console address from shared struct */
487 #endif /* DEBUG */
488
489 uint clkstate; /* State of sd and backplane clock(s) */
490 s32 idletime; /* Control for activity timeout */
491 s32 idlecount; /* Activity timeout counter */
492 s32 idleclock; /* How to set bus driver when idle */
493 bool rxflow_mode; /* Rx flow control mode */
494 bool rxflow; /* Is rx flow control on */
495 bool alp_only; /* Don't use HT clock (ALP only) */
496
497 u8 *ctrl_frame_buf;
498 u16 ctrl_frame_len;
499 bool ctrl_frame_stat;
500 int ctrl_frame_err;
501
502 spinlock_t txq_lock; /* protect bus->txq */
503 wait_queue_head_t ctrl_wait;
504 wait_queue_head_t dcmd_resp_wait;
505
506 struct timer_list timer;
507 struct completion watchdog_wait;
508 struct task_struct *watchdog_tsk;
509 bool wd_active;
510
511 struct workqueue_struct *brcmf_wq;
512 struct work_struct datawork;
513 bool dpc_triggered;
514 bool dpc_running;
515
516 bool txoff; /* Transmit flow-controlled */
517 struct brcmf_sdio_count sdcnt;
518 bool sr_enabled; /* SaveRestore enabled */
519 bool sleeping;
520
521 u8 tx_hdrlen; /* sdio bus header length for tx packet */
522 bool txglom; /* host tx glomming enable flag */
523 u16 head_align; /* buffer pointer alignment */
524 u16 sgentry_align; /* scatter-gather buffer alignment */
525 };
526
527 /* clkstate */
528 #define CLK_NONE 0
529 #define CLK_SDONLY 1
530 #define CLK_PENDING 2
531 #define CLK_AVAIL 3
532
533 #ifdef DEBUG
534 static int qcount[NUMPRIO];
535 #endif /* DEBUG */
536
537 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
538
539 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
540
541 /* Limit on rounding up frames */
542 static const uint max_roundup = 512;
543
544 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
545 #define ALIGNMENT 8
546 #else
547 #define ALIGNMENT 4
548 #endif
549
550 enum brcmf_sdio_frmtype {
551 BRCMF_SDIO_FT_NORMAL,
552 BRCMF_SDIO_FT_SUPER,
553 BRCMF_SDIO_FT_SUB,
554 };
555
556 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
557
558 /* SDIO Pad drive strength to select value mappings */
559 struct sdiod_drive_str {
560 u8 strength; /* Pad Drive Strength in mA */
561 u8 sel; /* Chip-specific select value */
562 };
563
564 /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */
565 static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
566 {32, 0x6},
567 {26, 0x7},
568 {22, 0x4},
569 {16, 0x5},
570 {12, 0x2},
571 {8, 0x3},
572 {4, 0x0},
573 {0, 0x1}
574 };
575
576 /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
577 static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
578 {6, 0x7},
579 {5, 0x6},
580 {4, 0x5},
581 {3, 0x4},
582 {2, 0x2},
583 {1, 0x1},
584 {0, 0x0}
585 };
586
587 /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
588 static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
589 {3, 0x3},
590 {2, 0x2},
591 {1, 0x1},
592 {0, 0x0} };
593
594 /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
595 static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
596 {16, 0x7},
597 {12, 0x5},
598 {8, 0x3},
599 {4, 0x1}
600 };
601
602 BRCMF_FW_NVRAM_DEF(43143, "brcmfmac43143-sdio.bin", "brcmfmac43143-sdio.txt");
603 BRCMF_FW_NVRAM_DEF(43241B0, "brcmfmac43241b0-sdio.bin",
604 "brcmfmac43241b0-sdio.txt");
605 BRCMF_FW_NVRAM_DEF(43241B4, "brcmfmac43241b4-sdio.bin",
606 "brcmfmac43241b4-sdio.txt");
607 BRCMF_FW_NVRAM_DEF(43241B5, "brcmfmac43241b5-sdio.bin",
608 "brcmfmac43241b5-sdio.txt");
609 BRCMF_FW_NVRAM_DEF(4329, "brcmfmac4329-sdio.bin", "brcmfmac4329-sdio.txt");
610 BRCMF_FW_NVRAM_DEF(4330, "brcmfmac4330-sdio.bin", "brcmfmac4330-sdio.txt");
611 BRCMF_FW_NVRAM_DEF(4334, "brcmfmac4334-sdio.bin", "brcmfmac4334-sdio.txt");
612 BRCMF_FW_NVRAM_DEF(43340, "brcmfmac43340-sdio.bin", "brcmfmac43340-sdio.txt");
613 BRCMF_FW_NVRAM_DEF(4335, "brcmfmac4335-sdio.bin", "brcmfmac4335-sdio.txt");
614 BRCMF_FW_NVRAM_DEF(43362, "brcmfmac43362-sdio.bin", "brcmfmac43362-sdio.txt");
615 BRCMF_FW_NVRAM_DEF(4339, "brcmfmac4339-sdio.bin", "brcmfmac4339-sdio.txt");
616 BRCMF_FW_NVRAM_DEF(43430A0, "brcmfmac43430a0-sdio.bin", "brcmfmac43430a0-sdio.txt");
617 /* Note the names are not postfixed with a1 for backward compatibility */
618 BRCMF_FW_NVRAM_DEF(43430A1, "brcmfmac43430-sdio.bin", "brcmfmac43430-sdio.txt");
619 BRCMF_FW_NVRAM_DEF(43455, "brcmfmac43455-sdio.bin", "brcmfmac43455-sdio.txt");
620 BRCMF_FW_NVRAM_DEF(4354, "brcmfmac4354-sdio.bin", "brcmfmac4354-sdio.txt");
621 BRCMF_FW_NVRAM_DEF(4356, "brcmfmac4356-sdio.bin", "brcmfmac4356-sdio.txt");
622 BRCMF_FW_NVRAM_DEF(4373, "brcmfmac4373-sdio.bin", "brcmfmac4373-sdio.txt");
623
624 static struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
625 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143),
626 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0),
627 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4),
628 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, 43241B5),
629 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, 4329),
630 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, 4330),
631 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334),
632 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340),
633 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43341_CHIP_ID, 0xFFFFFFFF, 43340),
634 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335),
635 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362),
636 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339),
637 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000001, 43430A0),
638 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFE, 43430A1),
639 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFFC0, 43455),
640 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354),
641 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356),
642 BRCMF_FW_NVRAM_ENTRY(CY_CC_4373_CHIP_ID, 0xFFFFFFFF, 4373)
643 };
644
645 static void pkt_align(struct sk_buff *p, int len, int align)
646 {
647 uint datalign;
648 datalign = (unsigned long)(p->data);
649 datalign = roundup(datalign, (align)) - datalign;
650 if (datalign)
651 skb_pull(p, datalign);
652 __skb_trim(p, len);
653 }
654
655 /* To check if there's window offered */
656 static bool data_ok(struct brcmf_sdio *bus)
657 {
658 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
659 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
660 }
661
662 /*
663 * Reads a register in the SDIO hardware block. This block occupies a series of
664 * adresses on the 32 bit backplane bus.
665 */
666 static int r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset)
667 {
668 struct brcmf_core *core;
669 int ret;
670
671 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
672 *regvar = brcmf_sdiod_regrl(bus->sdiodev, core->base + offset, &ret);
673
674 return ret;
675 }
676
677 static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset)
678 {
679 struct brcmf_core *core;
680 int ret;
681
682 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
683 brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret);
684
685 return ret;
686 }
687
688 static int
689 brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
690 {
691 u8 wr_val = 0, rd_val, cmp_val, bmask;
692 int err = 0;
693 int err_cnt = 0;
694 int try_cnt = 0;
695
696 brcmf_dbg(TRACE, "Enter: on=%d\n", on);
697
698 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
699 /* 1st KSO write goes to AOS wake up core if device is asleep */
700 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
701 wr_val, &err);
702
703 if (on) {
704 /* device WAKEUP through KSO:
705 * write bit 0 & read back until
706 * both bits 0 (kso bit) & 1 (dev on status) are set
707 */
708 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
709 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
710 bmask = cmp_val;
711 usleep_range(2000, 3000);
712 } else {
713 /* Put device to sleep, turn off KSO */
714 cmp_val = 0;
715 /* only check for bit0, bit1(dev on status) may not
716 * get cleared right away
717 */
718 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
719 }
720
721 do {
722 /* reliable KSO bit set/clr:
723 * the sdiod sleep write access is synced to PMU 32khz clk
724 * just one write attempt may fail,
725 * read it back until it matches written value
726 */
727 rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
728 &err);
729 if (!err) {
730 if ((rd_val & bmask) == cmp_val)
731 break;
732 err_cnt = 0;
733 }
734 /* bail out upon subsequent access errors */
735 if (err && (err_cnt++ > BRCMF_SDIO_MAX_ACCESS_ERRORS))
736 break;
737 udelay(KSO_WAIT_US);
738 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
739 wr_val, &err);
740 } while (try_cnt++ < MAX_KSO_ATTEMPTS);
741
742 if (try_cnt > 2)
743 brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt,
744 rd_val, err);
745
746 if (try_cnt > MAX_KSO_ATTEMPTS)
747 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err);
748
749 return err;
750 }
751
752 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
753
754 /* Turn backplane clock on or off */
755 static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
756 {
757 int err;
758 u8 clkctl, clkreq, devctl;
759 unsigned long timeout;
760
761 brcmf_dbg(SDIO, "Enter\n");
762
763 clkctl = 0;
764
765 if (bus->sr_enabled) {
766 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
767 return 0;
768 }
769
770 if (on) {
771 /* Request HT Avail */
772 clkreq =
773 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
774
775 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
776 clkreq, &err);
777 if (err) {
778 brcmf_err("HT Avail request error: %d\n", err);
779 return -EBADE;
780 }
781
782 /* Check current status */
783 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
784 SBSDIO_FUNC1_CHIPCLKCSR, &err);
785 if (err) {
786 brcmf_err("HT Avail read error: %d\n", err);
787 return -EBADE;
788 }
789
790 /* Go to pending and await interrupt if appropriate */
791 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
792 /* Allow only clock-available interrupt */
793 devctl = brcmf_sdiod_regrb(bus->sdiodev,
794 SBSDIO_DEVICE_CTL, &err);
795 if (err) {
796 brcmf_err("Devctl error setting CA: %d\n",
797 err);
798 return -EBADE;
799 }
800
801 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
802 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
803 devctl, &err);
804 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
805 bus->clkstate = CLK_PENDING;
806
807 return 0;
808 } else if (bus->clkstate == CLK_PENDING) {
809 /* Cancel CA-only interrupt filter */
810 devctl = brcmf_sdiod_regrb(bus->sdiodev,
811 SBSDIO_DEVICE_CTL, &err);
812 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
813 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
814 devctl, &err);
815 }
816
817 /* Otherwise, wait here (polling) for HT Avail */
818 timeout = jiffies +
819 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
820 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
821 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
822 SBSDIO_FUNC1_CHIPCLKCSR,
823 &err);
824 if (time_after(jiffies, timeout))
825 break;
826 else
827 usleep_range(5000, 10000);
828 }
829 if (err) {
830 brcmf_err("HT Avail request error: %d\n", err);
831 return -EBADE;
832 }
833 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
834 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
835 PMU_MAX_TRANSITION_DLY, clkctl);
836 return -EBADE;
837 }
838
839 /* Mark clock available */
840 bus->clkstate = CLK_AVAIL;
841 brcmf_dbg(SDIO, "CLKCTL: turned ON\n");
842
843 #if defined(DEBUG)
844 if (!bus->alp_only) {
845 if (SBSDIO_ALPONLY(clkctl))
846 brcmf_err("HT Clock should be on\n");
847 }
848 #endif /* defined (DEBUG) */
849
850 } else {
851 clkreq = 0;
852
853 if (bus->clkstate == CLK_PENDING) {
854 /* Cancel CA-only interrupt filter */
855 devctl = brcmf_sdiod_regrb(bus->sdiodev,
856 SBSDIO_DEVICE_CTL, &err);
857 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
858 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
859 devctl, &err);
860 }
861
862 bus->clkstate = CLK_SDONLY;
863 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
864 clkreq, &err);
865 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
866 if (err) {
867 brcmf_err("Failed access turning clock off: %d\n",
868 err);
869 return -EBADE;
870 }
871 }
872 return 0;
873 }
874
875 /* Change idle/active SD state */
876 static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on)
877 {
878 brcmf_dbg(SDIO, "Enter\n");
879
880 if (on)
881 bus->clkstate = CLK_SDONLY;
882 else
883 bus->clkstate = CLK_NONE;
884
885 return 0;
886 }
887
888 /* Transition SD and backplane clock readiness */
889 static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
890 {
891 #ifdef DEBUG
892 uint oldstate = bus->clkstate;
893 #endif /* DEBUG */
894
895 brcmf_dbg(SDIO, "Enter\n");
896
897 /* Early exit if we're already there */
898 if (bus->clkstate == target)
899 return 0;
900
901 switch (target) {
902 case CLK_AVAIL:
903 /* Make sure SD clock is available */
904 if (bus->clkstate == CLK_NONE)
905 brcmf_sdio_sdclk(bus, true);
906 /* Now request HT Avail on the backplane */
907 brcmf_sdio_htclk(bus, true, pendok);
908 break;
909
910 case CLK_SDONLY:
911 /* Remove HT request, or bring up SD clock */
912 if (bus->clkstate == CLK_NONE)
913 brcmf_sdio_sdclk(bus, true);
914 else if (bus->clkstate == CLK_AVAIL)
915 brcmf_sdio_htclk(bus, false, false);
916 else
917 brcmf_err("request for %d -> %d\n",
918 bus->clkstate, target);
919 break;
920
921 case CLK_NONE:
922 /* Make sure to remove HT request */
923 if (bus->clkstate == CLK_AVAIL)
924 brcmf_sdio_htclk(bus, false, false);
925 /* Now remove the SD clock */
926 brcmf_sdio_sdclk(bus, false);
927 break;
928 }
929 #ifdef DEBUG
930 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate);
931 #endif /* DEBUG */
932
933 return 0;
934 }
935
936 static int
937 brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
938 {
939 int err = 0;
940 u8 clkcsr;
941
942 brcmf_dbg(SDIO, "Enter: request %s currently %s\n",
943 (sleep ? "SLEEP" : "WAKE"),
944 (bus->sleeping ? "SLEEP" : "WAKE"));
945
946 /* If SR is enabled control bus state with KSO */
947 if (bus->sr_enabled) {
948 /* Done if we're already in the requested state */
949 if (sleep == bus->sleeping)
950 goto end;
951
952 /* Going to sleep */
953 if (sleep) {
954 clkcsr = brcmf_sdiod_regrb(bus->sdiodev,
955 SBSDIO_FUNC1_CHIPCLKCSR,
956 &err);
957 if ((clkcsr & SBSDIO_CSR_MASK) == 0) {
958 brcmf_dbg(SDIO, "no clock, set ALP\n");
959 brcmf_sdiod_regwb(bus->sdiodev,
960 SBSDIO_FUNC1_CHIPCLKCSR,
961 SBSDIO_ALP_AVAIL_REQ, &err);
962 }
963 err = brcmf_sdio_kso_control(bus, false);
964 } else {
965 err = brcmf_sdio_kso_control(bus, true);
966 }
967 if (err) {
968 brcmf_err("error while changing bus sleep state %d\n",
969 err);
970 goto done;
971 }
972 }
973
974 end:
975 /* control clocks */
976 if (sleep) {
977 if (!bus->sr_enabled)
978 brcmf_sdio_clkctl(bus, CLK_NONE, pendok);
979 } else {
980 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok);
981 brcmf_sdio_wd_timer(bus, true);
982 }
983 bus->sleeping = sleep;
984 brcmf_dbg(SDIO, "new state %s\n",
985 (sleep ? "SLEEP" : "WAKE"));
986 done:
987 brcmf_dbg(SDIO, "Exit: err=%d\n", err);
988 return err;
989
990 }
991
992 #ifdef DEBUG
993 static inline bool brcmf_sdio_valid_shared_address(u32 addr)
994 {
995 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
996 }
997
998 static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
999 struct sdpcm_shared *sh)
1000 {
1001 u32 addr = 0;
1002 int rv;
1003 u32 shaddr = 0;
1004 struct sdpcm_shared_le sh_le;
1005 __le32 addr_le;
1006
1007 sdio_claim_host(bus->sdiodev->func[1]);
1008 brcmf_sdio_bus_sleep(bus, false, false);
1009
1010 /*
1011 * Read last word in socram to determine
1012 * address of sdpcm_shared structure
1013 */
1014 shaddr = bus->ci->rambase + bus->ci->ramsize - 4;
1015 if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci))
1016 shaddr -= bus->ci->srsize;
1017 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr,
1018 (u8 *)&addr_le, 4);
1019 if (rv < 0)
1020 goto fail;
1021
1022 /*
1023 * Check if addr is valid.
1024 * NVRAM length at the end of memory should have been overwritten.
1025 */
1026 addr = le32_to_cpu(addr_le);
1027 if (!brcmf_sdio_valid_shared_address(addr)) {
1028 brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr);
1029 rv = -EINVAL;
1030 goto fail;
1031 }
1032
1033 brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr);
1034
1035 /* Read hndrte_shared structure */
1036 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
1037 sizeof(struct sdpcm_shared_le));
1038 if (rv < 0)
1039 goto fail;
1040
1041 sdio_release_host(bus->sdiodev->func[1]);
1042
1043 /* Endianness */
1044 sh->flags = le32_to_cpu(sh_le.flags);
1045 sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
1046 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
1047 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
1048 sh->assert_line = le32_to_cpu(sh_le.assert_line);
1049 sh->console_addr = le32_to_cpu(sh_le.console_addr);
1050 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
1051
1052 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) {
1053 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
1054 SDPCM_SHARED_VERSION,
1055 sh->flags & SDPCM_SHARED_VERSION_MASK);
1056 return -EPROTO;
1057 }
1058 return 0;
1059
1060 fail:
1061 brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n",
1062 rv, addr);
1063 sdio_release_host(bus->sdiodev->func[1]);
1064 return rv;
1065 }
1066
1067 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1068 {
1069 struct sdpcm_shared sh;
1070
1071 if (brcmf_sdio_readshared(bus, &sh) == 0)
1072 bus->console_addr = sh.console_addr;
1073 }
1074 #else
1075 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1076 {
1077 }
1078 #endif /* DEBUG */
1079
1080 static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus)
1081 {
1082 u32 intstatus = 0;
1083 u32 hmb_data;
1084 u8 fcbits;
1085 int ret;
1086
1087 brcmf_dbg(SDIO, "Enter\n");
1088
1089 /* Read mailbox data and ack that we did so */
1090 ret = r_sdreg32(bus, &hmb_data,
1091 offsetof(struct sdpcmd_regs, tohostmailboxdata));
1092
1093 if (ret == 0)
1094 w_sdreg32(bus, SMB_INT_ACK,
1095 offsetof(struct sdpcmd_regs, tosbmailbox));
1096 bus->sdcnt.f1regdata += 2;
1097
1098 /* dongle indicates the firmware has halted/crashed */
1099 if (hmb_data & HMB_DATA_FWHALT)
1100 brcmf_err("mailbox indicates firmware halted\n");
1101
1102 /* Dongle recomposed rx frames, accept them again */
1103 if (hmb_data & HMB_DATA_NAKHANDLED) {
1104 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n",
1105 bus->rx_seq);
1106 if (!bus->rxskip)
1107 brcmf_err("unexpected NAKHANDLED!\n");
1108
1109 bus->rxskip = false;
1110 intstatus |= I_HMB_FRAME_IND;
1111 }
1112
1113 /*
1114 * DEVREADY does not occur with gSPI.
1115 */
1116 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1117 bus->sdpcm_ver =
1118 (hmb_data & HMB_DATA_VERSION_MASK) >>
1119 HMB_DATA_VERSION_SHIFT;
1120 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1121 brcmf_err("Version mismatch, dongle reports %d, "
1122 "expecting %d\n",
1123 bus->sdpcm_ver, SDPCM_PROT_VERSION);
1124 else
1125 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n",
1126 bus->sdpcm_ver);
1127
1128 /*
1129 * Retrieve console state address now that firmware should have
1130 * updated it.
1131 */
1132 brcmf_sdio_get_console_addr(bus);
1133 }
1134
1135 /*
1136 * Flow Control has been moved into the RX headers and this out of band
1137 * method isn't used any more.
1138 * remaining backward compatible with older dongles.
1139 */
1140 if (hmb_data & HMB_DATA_FC) {
1141 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1142 HMB_DATA_FCDATA_SHIFT;
1143
1144 if (fcbits & ~bus->flowcontrol)
1145 bus->sdcnt.fc_xoff++;
1146
1147 if (bus->flowcontrol & ~fcbits)
1148 bus->sdcnt.fc_xon++;
1149
1150 bus->sdcnt.fc_rcvd++;
1151 bus->flowcontrol = fcbits;
1152 }
1153
1154 /* Shouldn't be any others */
1155 if (hmb_data & ~(HMB_DATA_DEVREADY |
1156 HMB_DATA_NAKHANDLED |
1157 HMB_DATA_FC |
1158 HMB_DATA_FWREADY |
1159 HMB_DATA_FWHALT |
1160 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1161 brcmf_err("Unknown mailbox data content: 0x%02x\n",
1162 hmb_data);
1163
1164 return intstatus;
1165 }
1166
1167 static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
1168 {
1169 uint retries = 0;
1170 u16 lastrbc;
1171 u8 hi, lo;
1172 int err;
1173
1174 brcmf_err("%sterminate frame%s\n",
1175 abort ? "abort command, " : "",
1176 rtx ? ", send NAK" : "");
1177
1178 if (abort)
1179 brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
1180
1181 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
1182 SFC_RF_TERM, &err);
1183 bus->sdcnt.f1regdata++;
1184
1185 /* Wait until the packet has been flushed (device/FIFO stable) */
1186 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1187 hi = brcmf_sdiod_regrb(bus->sdiodev,
1188 SBSDIO_FUNC1_RFRAMEBCHI, &err);
1189 lo = brcmf_sdiod_regrb(bus->sdiodev,
1190 SBSDIO_FUNC1_RFRAMEBCLO, &err);
1191 bus->sdcnt.f1regdata += 2;
1192
1193 if ((hi == 0) && (lo == 0))
1194 break;
1195
1196 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1197 brcmf_err("count growing: last 0x%04x now 0x%04x\n",
1198 lastrbc, (hi << 8) + lo);
1199 }
1200 lastrbc = (hi << 8) + lo;
1201 }
1202
1203 if (!retries)
1204 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc);
1205 else
1206 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries);
1207
1208 if (rtx) {
1209 bus->sdcnt.rxrtx++;
1210 err = w_sdreg32(bus, SMB_NAK,
1211 offsetof(struct sdpcmd_regs, tosbmailbox));
1212
1213 bus->sdcnt.f1regdata++;
1214 if (err == 0)
1215 bus->rxskip = true;
1216 }
1217
1218 /* Clear partial in any case */
1219 bus->cur_read.len = 0;
1220 }
1221
1222 static void brcmf_sdio_txfail(struct brcmf_sdio *bus)
1223 {
1224 struct brcmf_sdio_dev *sdiodev = bus->sdiodev;
1225 u8 i, hi, lo;
1226
1227 /* On failure, abort the command and terminate the frame */
1228 brcmf_err("sdio error, abort command and terminate frame\n");
1229 bus->sdcnt.tx_sderrs++;
1230
1231 brcmf_sdiod_abort(sdiodev, SDIO_FUNC_2);
1232 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL);
1233 bus->sdcnt.f1regdata++;
1234
1235 for (i = 0; i < 3; i++) {
1236 hi = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL);
1237 lo = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL);
1238 bus->sdcnt.f1regdata += 2;
1239 if ((hi == 0) && (lo == 0))
1240 break;
1241 }
1242 }
1243
1244 /* return total length of buffer chain */
1245 static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus)
1246 {
1247 struct sk_buff *p;
1248 uint total;
1249
1250 total = 0;
1251 skb_queue_walk(&bus->glom, p)
1252 total += p->len;
1253 return total;
1254 }
1255
1256 static void brcmf_sdio_free_glom(struct brcmf_sdio *bus)
1257 {
1258 struct sk_buff *cur, *next;
1259
1260 skb_queue_walk_safe(&bus->glom, cur, next) {
1261 skb_unlink(cur, &bus->glom);
1262 brcmu_pkt_buf_free_skb(cur);
1263 }
1264 }
1265
1266 /**
1267 * brcmfmac sdio bus specific header
1268 * This is the lowest layer header wrapped on the packets transmitted between
1269 * host and WiFi dongle which contains information needed for SDIO core and
1270 * firmware
1271 *
1272 * It consists of 3 parts: hardware header, hardware extension header and
1273 * software header
1274 * hardware header (frame tag) - 4 bytes
1275 * Byte 0~1: Frame length
1276 * Byte 2~3: Checksum, bit-wise inverse of frame length
1277 * hardware extension header - 8 bytes
1278 * Tx glom mode only, N/A for Rx or normal Tx
1279 * Byte 0~1: Packet length excluding hw frame tag
1280 * Byte 2: Reserved
1281 * Byte 3: Frame flags, bit 0: last frame indication
1282 * Byte 4~5: Reserved
1283 * Byte 6~7: Tail padding length
1284 * software header - 8 bytes
1285 * Byte 0: Rx/Tx sequence number
1286 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
1287 * Byte 2: Length of next data frame, reserved for Tx
1288 * Byte 3: Data offset
1289 * Byte 4: Flow control bits, reserved for Tx
1290 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
1291 * Byte 6~7: Reserved
1292 */
1293 #define SDPCM_HWHDR_LEN 4
1294 #define SDPCM_HWEXT_LEN 8
1295 #define SDPCM_SWHDR_LEN 8
1296 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
1297 /* software header */
1298 #define SDPCM_SEQ_MASK 0x000000ff
1299 #define SDPCM_SEQ_WRAP 256
1300 #define SDPCM_CHANNEL_MASK 0x00000f00
1301 #define SDPCM_CHANNEL_SHIFT 8
1302 #define SDPCM_CONTROL_CHANNEL 0 /* Control */
1303 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
1304 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
1305 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
1306 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
1307 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
1308 #define SDPCM_NEXTLEN_MASK 0x00ff0000
1309 #define SDPCM_NEXTLEN_SHIFT 16
1310 #define SDPCM_DOFFSET_MASK 0xff000000
1311 #define SDPCM_DOFFSET_SHIFT 24
1312 #define SDPCM_FCMASK_MASK 0x000000ff
1313 #define SDPCM_WINDOW_MASK 0x0000ff00
1314 #define SDPCM_WINDOW_SHIFT 8
1315
1316 static inline u8 brcmf_sdio_getdatoffset(u8 *swheader)
1317 {
1318 u32 hdrvalue;
1319 hdrvalue = *(u32 *)swheader;
1320 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT);
1321 }
1322
1323 static inline bool brcmf_sdio_fromevntchan(u8 *swheader)
1324 {
1325 u32 hdrvalue;
1326 u8 ret;
1327
1328 hdrvalue = *(u32 *)swheader;
1329 ret = (u8)((hdrvalue & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT);
1330
1331 return (ret == SDPCM_EVENT_CHANNEL);
1332 }
1333
1334 static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header,
1335 struct brcmf_sdio_hdrinfo *rd,
1336 enum brcmf_sdio_frmtype type)
1337 {
1338 u16 len, checksum;
1339 u8 rx_seq, fc, tx_seq_max;
1340 u32 swheader;
1341
1342 trace_brcmf_sdpcm_hdr(SDPCM_RX, header);
1343
1344 /* hw header */
1345 len = get_unaligned_le16(header);
1346 checksum = get_unaligned_le16(header + sizeof(u16));
1347 /* All zero means no more to read */
1348 if (!(len | checksum)) {
1349 bus->rxpending = false;
1350 return -ENODATA;
1351 }
1352 if ((u16)(~(len ^ checksum))) {
1353 brcmf_err("HW header checksum error\n");
1354 bus->sdcnt.rx_badhdr++;
1355 brcmf_sdio_rxfail(bus, false, false);
1356 return -EIO;
1357 }
1358 if (len < SDPCM_HDRLEN) {
1359 brcmf_err("HW header length error\n");
1360 return -EPROTO;
1361 }
1362 if (type == BRCMF_SDIO_FT_SUPER &&
1363 (roundup(len, bus->blocksize) != rd->len)) {
1364 brcmf_err("HW superframe header length error\n");
1365 return -EPROTO;
1366 }
1367 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) {
1368 brcmf_err("HW subframe header length error\n");
1369 return -EPROTO;
1370 }
1371 rd->len = len;
1372
1373 /* software header */
1374 header += SDPCM_HWHDR_LEN;
1375 swheader = le32_to_cpu(*(__le32 *)header);
1376 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) {
1377 brcmf_err("Glom descriptor found in superframe head\n");
1378 rd->len = 0;
1379 return -EINVAL;
1380 }
1381 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK);
1382 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT;
1383 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
1384 type != BRCMF_SDIO_FT_SUPER) {
1385 brcmf_err("HW header length too long\n");
1386 bus->sdcnt.rx_toolong++;
1387 brcmf_sdio_rxfail(bus, false, false);
1388 rd->len = 0;
1389 return -EPROTO;
1390 }
1391 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) {
1392 brcmf_err("Wrong channel for superframe\n");
1393 rd->len = 0;
1394 return -EINVAL;
1395 }
1396 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL &&
1397 rd->channel != SDPCM_EVENT_CHANNEL) {
1398 brcmf_err("Wrong channel for subframe\n");
1399 rd->len = 0;
1400 return -EINVAL;
1401 }
1402 rd->dat_offset = brcmf_sdio_getdatoffset(header);
1403 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
1404 brcmf_err("seq %d: bad data offset\n", rx_seq);
1405 bus->sdcnt.rx_badhdr++;
1406 brcmf_sdio_rxfail(bus, false, false);
1407 rd->len = 0;
1408 return -ENXIO;
1409 }
1410 if (rd->seq_num != rx_seq) {
1411 brcmf_dbg(SDIO, "seq %d, expected %d\n", rx_seq, rd->seq_num);
1412 bus->sdcnt.rx_badseq++;
1413 rd->seq_num = rx_seq;
1414 }
1415 /* no need to check the reset for subframe */
1416 if (type == BRCMF_SDIO_FT_SUB)
1417 return 0;
1418 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT;
1419 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
1420 /* only warm for NON glom packet */
1421 if (rd->channel != SDPCM_GLOM_CHANNEL)
1422 brcmf_err("seq %d: next length error\n", rx_seq);
1423 rd->len_nxtfrm = 0;
1424 }
1425 swheader = le32_to_cpu(*(__le32 *)(header + 4));
1426 fc = swheader & SDPCM_FCMASK_MASK;
1427 if (bus->flowcontrol != fc) {
1428 if (~bus->flowcontrol & fc)
1429 bus->sdcnt.fc_xoff++;
1430 if (bus->flowcontrol & ~fc)
1431 bus->sdcnt.fc_xon++;
1432 bus->sdcnt.fc_rcvd++;
1433 bus->flowcontrol = fc;
1434 }
1435 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT;
1436 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
1437 brcmf_err("seq %d: max tx seq number error\n", rx_seq);
1438 tx_seq_max = bus->tx_seq + 2;
1439 }
1440 bus->tx_max = tx_seq_max;
1441
1442 return 0;
1443 }
1444
1445 static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length)
1446 {
1447 *(__le16 *)header = cpu_to_le16(frm_length);
1448 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length);
1449 }
1450
1451 static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header,
1452 struct brcmf_sdio_hdrinfo *hd_info)
1453 {
1454 u32 hdrval;
1455 u8 hdr_offset;
1456
1457 brcmf_sdio_update_hwhdr(header, hd_info->len);
1458 hdr_offset = SDPCM_HWHDR_LEN;
1459
1460 if (bus->txglom) {
1461 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24);
1462 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1463 hdrval = (u16)hd_info->tail_pad << 16;
1464 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval);
1465 hdr_offset += SDPCM_HWEXT_LEN;
1466 }
1467
1468 hdrval = hd_info->seq_num;
1469 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) &
1470 SDPCM_CHANNEL_MASK;
1471 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) &
1472 SDPCM_DOFFSET_MASK;
1473 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1474 *(((__le32 *)(header + hdr_offset)) + 1) = 0;
1475 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header);
1476 }
1477
1478 static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq)
1479 {
1480 u16 dlen, totlen;
1481 u8 *dptr, num = 0;
1482 u16 sublen;
1483 struct sk_buff *pfirst, *pnext;
1484
1485 int errcode;
1486 u8 doff, sfdoff;
1487
1488 struct brcmf_sdio_hdrinfo rd_new;
1489
1490 /* If packets, issue read(s) and send up packet chain */
1491 /* Return sequence numbers consumed? */
1492
1493 brcmf_dbg(SDIO, "start: glomd %p glom %p\n",
1494 bus->glomd, skb_peek(&bus->glom));
1495
1496 /* If there's a descriptor, generate the packet chain */
1497 if (bus->glomd) {
1498 pfirst = pnext = NULL;
1499 dlen = (u16) (bus->glomd->len);
1500 dptr = bus->glomd->data;
1501 if (!dlen || (dlen & 1)) {
1502 brcmf_err("bad glomd len(%d), ignore descriptor\n",
1503 dlen);
1504 dlen = 0;
1505 }
1506
1507 for (totlen = num = 0; dlen; num++) {
1508 /* Get (and move past) next length */
1509 sublen = get_unaligned_le16(dptr);
1510 dlen -= sizeof(u16);
1511 dptr += sizeof(u16);
1512 if ((sublen < SDPCM_HDRLEN) ||
1513 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1514 brcmf_err("descriptor len %d bad: %d\n",
1515 num, sublen);
1516 pnext = NULL;
1517 break;
1518 }
1519 if (sublen % bus->sgentry_align) {
1520 brcmf_err("sublen %d not multiple of %d\n",
1521 sublen, bus->sgentry_align);
1522 }
1523 totlen += sublen;
1524
1525 /* For last frame, adjust read len so total
1526 is a block multiple */
1527 if (!dlen) {
1528 sublen +=
1529 (roundup(totlen, bus->blocksize) - totlen);
1530 totlen = roundup(totlen, bus->blocksize);
1531 }
1532
1533 /* Allocate/chain packet for next subframe */
1534 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align);
1535 if (pnext == NULL) {
1536 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
1537 num, sublen);
1538 break;
1539 }
1540 skb_queue_tail(&bus->glom, pnext);
1541
1542 /* Adhere to start alignment requirements */
1543 pkt_align(pnext, sublen, bus->sgentry_align);
1544 }
1545
1546 /* If all allocations succeeded, save packet chain
1547 in bus structure */
1548 if (pnext) {
1549 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1550 totlen, num);
1551 if (BRCMF_GLOM_ON() && bus->cur_read.len &&
1552 totlen != bus->cur_read.len) {
1553 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1554 bus->cur_read.len, totlen, rxseq);
1555 }
1556 pfirst = pnext = NULL;
1557 } else {
1558 brcmf_sdio_free_glom(bus);
1559 num = 0;
1560 }
1561
1562 /* Done with descriptor packet */
1563 brcmu_pkt_buf_free_skb(bus->glomd);
1564 bus->glomd = NULL;
1565 bus->cur_read.len = 0;
1566 }
1567
1568 /* Ok -- either we just generated a packet chain,
1569 or had one from before */
1570 if (!skb_queue_empty(&bus->glom)) {
1571 if (BRCMF_GLOM_ON()) {
1572 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1573 skb_queue_walk(&bus->glom, pnext) {
1574 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1575 pnext, (u8 *) (pnext->data),
1576 pnext->len, pnext->len);
1577 }
1578 }
1579
1580 pfirst = skb_peek(&bus->glom);
1581 dlen = (u16) brcmf_sdio_glom_len(bus);
1582
1583 /* Do an SDIO read for the superframe. Configurable iovar to
1584 * read directly into the chained packet, or allocate a large
1585 * packet and and copy into the chain.
1586 */
1587 sdio_claim_host(bus->sdiodev->func[1]);
1588 errcode = brcmf_sdiod_recv_chain(bus->sdiodev,
1589 &bus->glom, dlen);
1590 sdio_release_host(bus->sdiodev->func[1]);
1591 bus->sdcnt.f2rxdata++;
1592
1593 /* On failure, kill the superframe */
1594 if (errcode < 0) {
1595 brcmf_err("glom read of %d bytes failed: %d\n",
1596 dlen, errcode);
1597
1598 sdio_claim_host(bus->sdiodev->func[1]);
1599 brcmf_sdio_rxfail(bus, true, false);
1600 bus->sdcnt.rxglomfail++;
1601 brcmf_sdio_free_glom(bus);
1602 sdio_release_host(bus->sdiodev->func[1]);
1603 return 0;
1604 }
1605
1606 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1607 pfirst->data, min_t(int, pfirst->len, 48),
1608 "SUPERFRAME:\n");
1609
1610 rd_new.seq_num = rxseq;
1611 rd_new.len = dlen;
1612 sdio_claim_host(bus->sdiodev->func[1]);
1613 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new,
1614 BRCMF_SDIO_FT_SUPER);
1615 sdio_release_host(bus->sdiodev->func[1]);
1616 bus->cur_read.len = rd_new.len_nxtfrm << 4;
1617
1618 /* Remove superframe header, remember offset */
1619 skb_pull(pfirst, rd_new.dat_offset);
1620 sfdoff = rd_new.dat_offset;
1621 num = 0;
1622
1623 /* Validate all the subframe headers */
1624 skb_queue_walk(&bus->glom, pnext) {
1625 /* leave when invalid subframe is found */
1626 if (errcode)
1627 break;
1628
1629 rd_new.len = pnext->len;
1630 rd_new.seq_num = rxseq++;
1631 sdio_claim_host(bus->sdiodev->func[1]);
1632 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new,
1633 BRCMF_SDIO_FT_SUB);
1634 sdio_release_host(bus->sdiodev->func[1]);
1635 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1636 pnext->data, 32, "subframe:\n");
1637
1638 num++;
1639 }
1640
1641 if (errcode) {
1642 /* Terminate frame on error */
1643 sdio_claim_host(bus->sdiodev->func[1]);
1644 brcmf_sdio_rxfail(bus, true, false);
1645 bus->sdcnt.rxglomfail++;
1646 brcmf_sdio_free_glom(bus);
1647 sdio_release_host(bus->sdiodev->func[1]);
1648 bus->cur_read.len = 0;
1649 return 0;
1650 }
1651
1652 /* Basic SD framing looks ok - process each packet (header) */
1653
1654 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1655 dptr = (u8 *) (pfirst->data);
1656 sublen = get_unaligned_le16(dptr);
1657 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]);
1658
1659 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1660 dptr, pfirst->len,
1661 "Rx Subframe Data:\n");
1662
1663 __skb_trim(pfirst, sublen);
1664 skb_pull(pfirst, doff);
1665
1666 if (pfirst->len == 0) {
1667 skb_unlink(pfirst, &bus->glom);
1668 brcmu_pkt_buf_free_skb(pfirst);
1669 continue;
1670 }
1671
1672 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1673 pfirst->data,
1674 min_t(int, pfirst->len, 32),
1675 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1676 bus->glom.qlen, pfirst, pfirst->data,
1677 pfirst->len, pfirst->next,
1678 pfirst->prev);
1679 skb_unlink(pfirst, &bus->glom);
1680 if (brcmf_sdio_fromevntchan(&dptr[SDPCM_HWHDR_LEN]))
1681 brcmf_rx_event(bus->sdiodev->dev, pfirst);
1682 else
1683 brcmf_rx_frame(bus->sdiodev->dev, pfirst,
1684 false);
1685 bus->sdcnt.rxglompkts++;
1686 }
1687
1688 bus->sdcnt.rxglomframes++;
1689 }
1690 return num;
1691 }
1692
1693 static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
1694 bool *pending)
1695 {
1696 DECLARE_WAITQUEUE(wait, current);
1697 int timeout = DCMD_RESP_TIMEOUT;
1698
1699 /* Wait until control frame is available */
1700 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1701 set_current_state(TASK_INTERRUPTIBLE);
1702
1703 while (!(*condition) && (!signal_pending(current) && timeout))
1704 timeout = schedule_timeout(timeout);
1705
1706 if (signal_pending(current))
1707 *pending = true;
1708
1709 set_current_state(TASK_RUNNING);
1710 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1711
1712 return timeout;
1713 }
1714
1715 static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus)
1716 {
1717 wake_up_interruptible(&bus->dcmd_resp_wait);
1718
1719 return 0;
1720 }
1721 static void
1722 brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
1723 {
1724 uint rdlen, pad;
1725 u8 *buf = NULL, *rbuf;
1726 int sdret;
1727
1728 brcmf_dbg(TRACE, "Enter\n");
1729
1730 if (bus->rxblen)
1731 buf = vzalloc(bus->rxblen);
1732 if (!buf)
1733 goto done;
1734
1735 rbuf = bus->rxbuf;
1736 pad = ((unsigned long)rbuf % bus->head_align);
1737 if (pad)
1738 rbuf += (bus->head_align - pad);
1739
1740 /* Copy the already-read portion over */
1741 memcpy(buf, hdr, BRCMF_FIRSTREAD);
1742 if (len <= BRCMF_FIRSTREAD)
1743 goto gotpkt;
1744
1745 /* Raise rdlen to next SDIO block to avoid tail command */
1746 rdlen = len - BRCMF_FIRSTREAD;
1747 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1748 pad = bus->blocksize - (rdlen % bus->blocksize);
1749 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1750 ((len + pad) < bus->sdiodev->bus_if->maxctl))
1751 rdlen += pad;
1752 } else if (rdlen % bus->head_align) {
1753 rdlen += bus->head_align - (rdlen % bus->head_align);
1754 }
1755
1756 /* Drop if the read is too big or it exceeds our maximum */
1757 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
1758 brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
1759 rdlen, bus->sdiodev->bus_if->maxctl);
1760 brcmf_sdio_rxfail(bus, false, false);
1761 goto done;
1762 }
1763
1764 if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
1765 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1766 len, len - doff, bus->sdiodev->bus_if->maxctl);
1767 bus->sdcnt.rx_toolong++;
1768 brcmf_sdio_rxfail(bus, false, false);
1769 goto done;
1770 }
1771
1772 /* Read remain of frame body */
1773 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen);
1774 bus->sdcnt.f2rxdata++;
1775
1776 /* Control frame failures need retransmission */
1777 if (sdret < 0) {
1778 brcmf_err("read %d control bytes failed: %d\n",
1779 rdlen, sdret);
1780 bus->sdcnt.rxc_errors++;
1781 brcmf_sdio_rxfail(bus, true, true);
1782 goto done;
1783 } else
1784 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen);
1785
1786 gotpkt:
1787
1788 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
1789 buf, len, "RxCtrl:\n");
1790
1791 /* Point to valid data and indicate its length */
1792 spin_lock_bh(&bus->rxctl_lock);
1793 if (bus->rxctl) {
1794 brcmf_err("last control frame is being processed.\n");
1795 spin_unlock_bh(&bus->rxctl_lock);
1796 vfree(buf);
1797 goto done;
1798 }
1799 bus->rxctl = buf + doff;
1800 bus->rxctl_orig = buf;
1801 bus->rxlen = len - doff;
1802 spin_unlock_bh(&bus->rxctl_lock);
1803
1804 done:
1805 /* Awake any waiters */
1806 brcmf_sdio_dcmd_resp_wake(bus);
1807 }
1808
1809 /* Pad read to blocksize for efficiency */
1810 static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
1811 {
1812 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1813 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1814 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1815 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1816 *rdlen += *pad;
1817 } else if (*rdlen % bus->head_align) {
1818 *rdlen += bus->head_align - (*rdlen % bus->head_align);
1819 }
1820 }
1821
1822 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
1823 {
1824 struct sk_buff *pkt; /* Packet for event or data frames */
1825 u16 pad; /* Number of pad bytes to read */
1826 uint rxleft = 0; /* Remaining number of frames allowed */
1827 int ret; /* Return code from calls */
1828 uint rxcount = 0; /* Total frames read */
1829 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new;
1830 u8 head_read = 0;
1831
1832 brcmf_dbg(TRACE, "Enter\n");
1833
1834 /* Not finished unless we encounter no more frames indication */
1835 bus->rxpending = true;
1836
1837 for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
1838 !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA;
1839 rd->seq_num++, rxleft--) {
1840
1841 /* Handle glomming separately */
1842 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
1843 u8 cnt;
1844 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1845 bus->glomd, skb_peek(&bus->glom));
1846 cnt = brcmf_sdio_rxglom(bus, rd->seq_num);
1847 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1848 rd->seq_num += cnt - 1;
1849 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1850 continue;
1851 }
1852
1853 rd->len_left = rd->len;
1854 /* read header first for unknow frame length */
1855 sdio_claim_host(bus->sdiodev->func[1]);
1856 if (!rd->len) {
1857 ret = brcmf_sdiod_recv_buf(bus->sdiodev,
1858 bus->rxhdr, BRCMF_FIRSTREAD);
1859 bus->sdcnt.f2rxhdrs++;
1860 if (ret < 0) {
1861 brcmf_err("RXHEADER FAILED: %d\n",
1862 ret);
1863 bus->sdcnt.rx_hdrfail++;
1864 brcmf_sdio_rxfail(bus, true, true);
1865 sdio_release_host(bus->sdiodev->func[1]);
1866 continue;
1867 }
1868
1869 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
1870 bus->rxhdr, SDPCM_HDRLEN,
1871 "RxHdr:\n");
1872
1873 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd,
1874 BRCMF_SDIO_FT_NORMAL)) {
1875 sdio_release_host(bus->sdiodev->func[1]);
1876 if (!bus->rxpending)
1877 break;
1878 else
1879 continue;
1880 }
1881
1882 if (rd->channel == SDPCM_CONTROL_CHANNEL) {
1883 brcmf_sdio_read_control(bus, bus->rxhdr,
1884 rd->len,
1885 rd->dat_offset);
1886 /* prepare the descriptor for the next read */
1887 rd->len = rd->len_nxtfrm << 4;
1888 rd->len_nxtfrm = 0;
1889 /* treat all packet as event if we don't know */
1890 rd->channel = SDPCM_EVENT_CHANNEL;
1891 sdio_release_host(bus->sdiodev->func[1]);
1892 continue;
1893 }
1894 rd->len_left = rd->len > BRCMF_FIRSTREAD ?
1895 rd->len - BRCMF_FIRSTREAD : 0;
1896 head_read = BRCMF_FIRSTREAD;
1897 }
1898
1899 brcmf_sdio_pad(bus, &pad, &rd->len_left);
1900
1901 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
1902 bus->head_align);
1903 if (!pkt) {
1904 /* Give up on data, request rtx of events */
1905 brcmf_err("brcmu_pkt_buf_get_skb failed\n");
1906 brcmf_sdio_rxfail(bus, false,
1907 RETRYCHAN(rd->channel));
1908 sdio_release_host(bus->sdiodev->func[1]);
1909 continue;
1910 }
1911 skb_pull(pkt, head_read);
1912 pkt_align(pkt, rd->len_left, bus->head_align);
1913
1914 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt);
1915 bus->sdcnt.f2rxdata++;
1916 sdio_release_host(bus->sdiodev->func[1]);
1917
1918 if (ret < 0) {
1919 brcmf_err("read %d bytes from channel %d failed: %d\n",
1920 rd->len, rd->channel, ret);
1921 brcmu_pkt_buf_free_skb(pkt);
1922 sdio_claim_host(bus->sdiodev->func[1]);
1923 brcmf_sdio_rxfail(bus, true,
1924 RETRYCHAN(rd->channel));
1925 sdio_release_host(bus->sdiodev->func[1]);
1926 continue;
1927 }
1928
1929 if (head_read) {
1930 skb_push(pkt, head_read);
1931 memcpy(pkt->data, bus->rxhdr, head_read);
1932 head_read = 0;
1933 } else {
1934 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
1935 rd_new.seq_num = rd->seq_num;
1936 sdio_claim_host(bus->sdiodev->func[1]);
1937 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new,
1938 BRCMF_SDIO_FT_NORMAL)) {
1939 rd->len = 0;
1940 brcmu_pkt_buf_free_skb(pkt);
1941 }
1942 bus->sdcnt.rx_readahead_cnt++;
1943 if (rd->len != roundup(rd_new.len, 16)) {
1944 brcmf_err("frame length mismatch:read %d, should be %d\n",
1945 rd->len,
1946 roundup(rd_new.len, 16) >> 4);
1947 rd->len = 0;
1948 brcmf_sdio_rxfail(bus, true, true);
1949 sdio_release_host(bus->sdiodev->func[1]);
1950 brcmu_pkt_buf_free_skb(pkt);
1951 continue;
1952 }
1953 sdio_release_host(bus->sdiodev->func[1]);
1954 rd->len_nxtfrm = rd_new.len_nxtfrm;
1955 rd->channel = rd_new.channel;
1956 rd->dat_offset = rd_new.dat_offset;
1957
1958 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
1959 BRCMF_DATA_ON()) &&
1960 BRCMF_HDRS_ON(),
1961 bus->rxhdr, SDPCM_HDRLEN,
1962 "RxHdr:\n");
1963
1964 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) {
1965 brcmf_err("readahead on control packet %d?\n",
1966 rd_new.seq_num);
1967 /* Force retry w/normal header read */
1968 rd->len = 0;
1969 sdio_claim_host(bus->sdiodev->func[1]);
1970 brcmf_sdio_rxfail(bus, false, true);
1971 sdio_release_host(bus->sdiodev->func[1]);
1972 brcmu_pkt_buf_free_skb(pkt);
1973 continue;
1974 }
1975 }
1976
1977 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1978 pkt->data, rd->len, "Rx Data:\n");
1979
1980 /* Save superframe descriptor and allocate packet frame */
1981 if (rd->channel == SDPCM_GLOM_CHANNEL) {
1982 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) {
1983 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
1984 rd->len);
1985 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1986 pkt->data, rd->len,
1987 "Glom Data:\n");
1988 __skb_trim(pkt, rd->len);
1989 skb_pull(pkt, SDPCM_HDRLEN);
1990 bus->glomd = pkt;
1991 } else {
1992 brcmf_err("%s: glom superframe w/o "
1993 "descriptor!\n", __func__);
1994 sdio_claim_host(bus->sdiodev->func[1]);
1995 brcmf_sdio_rxfail(bus, false, false);
1996 sdio_release_host(bus->sdiodev->func[1]);
1997 }
1998 /* prepare the descriptor for the next read */
1999 rd->len = rd->len_nxtfrm << 4;
2000 rd->len_nxtfrm = 0;
2001 /* treat all packet as event if we don't know */
2002 rd->channel = SDPCM_EVENT_CHANNEL;
2003 continue;
2004 }
2005
2006 /* Fill in packet len and prio, deliver upward */
2007 __skb_trim(pkt, rd->len);
2008 skb_pull(pkt, rd->dat_offset);
2009
2010 if (pkt->len == 0)
2011 brcmu_pkt_buf_free_skb(pkt);
2012 else if (rd->channel == SDPCM_EVENT_CHANNEL)
2013 brcmf_rx_event(bus->sdiodev->dev, pkt);
2014 else
2015 brcmf_rx_frame(bus->sdiodev->dev, pkt,
2016 false);
2017
2018 /* prepare the descriptor for the next read */
2019 rd->len = rd->len_nxtfrm << 4;
2020 rd->len_nxtfrm = 0;
2021 /* treat all packet as event if we don't know */
2022 rd->channel = SDPCM_EVENT_CHANNEL;
2023 }
2024
2025 rxcount = maxframes - rxleft;
2026 /* Message if we hit the limit */
2027 if (!rxleft)
2028 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes);
2029 else
2030 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2031 /* Back off rxseq if awaiting rtx, update rx_seq */
2032 if (bus->rxskip)
2033 rd->seq_num--;
2034 bus->rx_seq = rd->seq_num;
2035
2036 return rxcount;
2037 }
2038
2039 static void
2040 brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus)
2041 {
2042 wake_up_interruptible(&bus->ctrl_wait);
2043 return;
2044 }
2045
2046 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt)
2047 {
2048 struct brcmf_bus_stats *stats;
2049 u16 head_pad;
2050 u8 *dat_buf;
2051
2052 dat_buf = (u8 *)(pkt->data);
2053
2054 /* Check head padding */
2055 head_pad = ((unsigned long)dat_buf % bus->head_align);
2056 if (head_pad) {
2057 if (skb_headroom(pkt) < head_pad) {
2058 stats = &bus->sdiodev->bus_if->stats;
2059 atomic_inc(&stats->pktcowed);
2060 if (skb_cow_head(pkt, head_pad)) {
2061 atomic_inc(&stats->pktcow_failed);
2062 return -ENOMEM;
2063 }
2064 head_pad = 0;
2065 }
2066 skb_push(pkt, head_pad);
2067 dat_buf = (u8 *)(pkt->data);
2068 }
2069 memset(dat_buf, 0, head_pad + bus->tx_hdrlen);
2070 return head_pad;
2071 }
2072
2073 /*
2074 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
2075 * bus layer usage.
2076 */
2077 /* flag marking a dummy skb added for DMA alignment requirement */
2078 #define ALIGN_SKB_FLAG 0x8000
2079 /* bit mask of data length chopped from the previous packet */
2080 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
2081
2082 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus,
2083 struct sk_buff_head *pktq,
2084 struct sk_buff *pkt, u16 total_len)
2085 {
2086 struct brcmf_sdio_dev *sdiodev;
2087 struct sk_buff *pkt_pad;
2088 u16 tail_pad, tail_chop, chain_pad;
2089 unsigned int blksize;
2090 bool lastfrm;
2091 int ntail, ret;
2092
2093 sdiodev = bus->sdiodev;
2094 blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize;
2095 /* sg entry alignment should be a divisor of block size */
2096 WARN_ON(blksize % bus->sgentry_align);
2097
2098 /* Check tail padding */
2099 lastfrm = skb_queue_is_last(pktq, pkt);
2100 tail_pad = 0;
2101 tail_chop = pkt->len % bus->sgentry_align;
2102 if (tail_chop)
2103 tail_pad = bus->sgentry_align - tail_chop;
2104 chain_pad = (total_len + tail_pad) % blksize;
2105 if (lastfrm && chain_pad)
2106 tail_pad += blksize - chain_pad;
2107 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) {
2108 pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop +
2109 bus->head_align);
2110 if (pkt_pad == NULL)
2111 return -ENOMEM;
2112 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad);
2113 if (unlikely(ret < 0)) {
2114 kfree_skb(pkt_pad);
2115 return ret;
2116 }
2117 memcpy(pkt_pad->data,
2118 pkt->data + pkt->len - tail_chop,
2119 tail_chop);
2120 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop;
2121 skb_trim(pkt, pkt->len - tail_chop);
2122 skb_trim(pkt_pad, tail_pad + tail_chop);
2123 __skb_queue_after(pktq, pkt, pkt_pad);
2124 } else {
2125 ntail = pkt->data_len + tail_pad -
2126 (pkt->end - pkt->tail);
2127 if (skb_cloned(pkt) || ntail > 0)
2128 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC))
2129 return -ENOMEM;
2130 if (skb_linearize(pkt))
2131 return -ENOMEM;
2132 __skb_put(pkt, tail_pad);
2133 }
2134
2135 return tail_pad;
2136 }
2137
2138 /**
2139 * brcmf_sdio_txpkt_prep - packet preparation for transmit
2140 * @bus: brcmf_sdio structure pointer
2141 * @pktq: packet list pointer
2142 * @chan: virtual channel to transmit the packet
2143 *
2144 * Processes to be applied to the packet
2145 * - Align data buffer pointer
2146 * - Align data buffer length
2147 * - Prepare header
2148 * Return: negative value if there is error
2149 */
2150 static int
2151 brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2152 uint chan)
2153 {
2154 u16 head_pad, total_len;
2155 struct sk_buff *pkt_next;
2156 u8 txseq;
2157 int ret;
2158 struct brcmf_sdio_hdrinfo hd_info = {0};
2159
2160 txseq = bus->tx_seq;
2161 total_len = 0;
2162 skb_queue_walk(pktq, pkt_next) {
2163 /* alignment packet inserted in previous
2164 * loop cycle can be skipped as it is
2165 * already properly aligned and does not
2166 * need an sdpcm header.
2167 */
2168 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG)
2169 continue;
2170
2171 /* align packet data pointer */
2172 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next);
2173 if (ret < 0)
2174 return ret;
2175 head_pad = (u16)ret;
2176 if (head_pad)
2177 memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad);
2178
2179 total_len += pkt_next->len;
2180
2181 hd_info.len = pkt_next->len;
2182 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next);
2183 if (bus->txglom && pktq->qlen > 1) {
2184 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq,
2185 pkt_next, total_len);
2186 if (ret < 0)
2187 return ret;
2188 hd_info.tail_pad = (u16)ret;
2189 total_len += (u16)ret;
2190 }
2191
2192 hd_info.channel = chan;
2193 hd_info.dat_offset = head_pad + bus->tx_hdrlen;
2194 hd_info.seq_num = txseq++;
2195
2196 /* Now fill the header */
2197 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info);
2198
2199 if (BRCMF_BYTES_ON() &&
2200 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
2201 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)))
2202 brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len,
2203 "Tx Frame:\n");
2204 else if (BRCMF_HDRS_ON())
2205 brcmf_dbg_hex_dump(true, pkt_next->data,
2206 head_pad + bus->tx_hdrlen,
2207 "Tx Header:\n");
2208 }
2209 /* Hardware length tag of the first packet should be total
2210 * length of the chain (including padding)
2211 */
2212 if (bus->txglom)
2213 brcmf_sdio_update_hwhdr(pktq->next->data, total_len);
2214 return 0;
2215 }
2216
2217 /**
2218 * brcmf_sdio_txpkt_postp - packet post processing for transmit
2219 * @bus: brcmf_sdio structure pointer
2220 * @pktq: packet list pointer
2221 *
2222 * Processes to be applied to the packet
2223 * - Remove head padding
2224 * - Remove tail padding
2225 */
2226 static void
2227 brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq)
2228 {
2229 u8 *hdr;
2230 u32 dat_offset;
2231 u16 tail_pad;
2232 u16 dummy_flags, chop_len;
2233 struct sk_buff *pkt_next, *tmp, *pkt_prev;
2234
2235 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2236 dummy_flags = *(u16 *)(pkt_next->cb);
2237 if (dummy_flags & ALIGN_SKB_FLAG) {
2238 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK;
2239 if (chop_len) {
2240 pkt_prev = pkt_next->prev;
2241 skb_put(pkt_prev, chop_len);
2242 }
2243 __skb_unlink(pkt_next, pktq);
2244 brcmu_pkt_buf_free_skb(pkt_next);
2245 } else {
2246 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN;
2247 dat_offset = le32_to_cpu(*(__le32 *)hdr);
2248 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >>
2249 SDPCM_DOFFSET_SHIFT;
2250 skb_pull(pkt_next, dat_offset);
2251 if (bus->txglom) {
2252 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2));
2253 skb_trim(pkt_next, pkt_next->len - tail_pad);
2254 }
2255 }
2256 }
2257 }
2258
2259 /* Writes a HW/SW header into the packet and sends it. */
2260 /* Assumes: (a) header space already there, (b) caller holds lock */
2261 static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2262 uint chan)
2263 {
2264 int ret;
2265 struct sk_buff *pkt_next, *tmp;
2266
2267 brcmf_dbg(TRACE, "Enter\n");
2268
2269 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan);
2270 if (ret)
2271 goto done;
2272
2273 sdio_claim_host(bus->sdiodev->func[1]);
2274 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq);
2275 bus->sdcnt.f2txdata++;
2276
2277 if (ret < 0)
2278 brcmf_sdio_txfail(bus);
2279
2280 sdio_release_host(bus->sdiodev->func[1]);
2281
2282 done:
2283 brcmf_sdio_txpkt_postp(bus, pktq);
2284 if (ret == 0)
2285 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP;
2286 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2287 __skb_unlink(pkt_next, pktq);
2288 brcmf_proto_bcdc_txcomplete(bus->sdiodev->dev, pkt_next,
2289 ret == 0);
2290 }
2291 return ret;
2292 }
2293
2294 static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes)
2295 {
2296 struct sk_buff *pkt;
2297 struct sk_buff_head pktq;
2298 u32 intstatus = 0;
2299 int ret = 0, prec_out, i;
2300 uint cnt = 0;
2301 u8 tx_prec_map, pkt_num;
2302
2303 brcmf_dbg(TRACE, "Enter\n");
2304
2305 tx_prec_map = ~bus->flowcontrol;
2306
2307 /* Send frames until the limit or some other event */
2308 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) {
2309 pkt_num = 1;
2310 if (bus->txglom)
2311 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq,
2312 bus->sdiodev->txglomsz);
2313 pkt_num = min_t(u32, pkt_num,
2314 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol));
2315 __skb_queue_head_init(&pktq);
2316 spin_lock_bh(&bus->txq_lock);
2317 for (i = 0; i < pkt_num; i++) {
2318 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map,
2319 &prec_out);
2320 if (pkt == NULL)
2321 break;
2322 __skb_queue_tail(&pktq, pkt);
2323 }
2324 spin_unlock_bh(&bus->txq_lock);
2325 if (i == 0)
2326 break;
2327
2328 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL);
2329
2330 cnt += i;
2331
2332 /* In poll mode, need to check for other events */
2333 if (!bus->intr) {
2334 /* Check device status, signal pending interrupt */
2335 sdio_claim_host(bus->sdiodev->func[1]);
2336 ret = r_sdreg32(bus, &intstatus,
2337 offsetof(struct sdpcmd_regs,
2338 intstatus));
2339 sdio_release_host(bus->sdiodev->func[1]);
2340 bus->sdcnt.f2txdata++;
2341 if (ret != 0)
2342 break;
2343 if (intstatus & bus->hostintmask)
2344 atomic_set(&bus->ipend, 1);
2345 }
2346 }
2347
2348 /* Deflow-control stack if needed */
2349 if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) &&
2350 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
2351 bus->txoff = false;
2352 brcmf_proto_bcdc_txflowblock(bus->sdiodev->dev, false);
2353 }
2354
2355 return cnt;
2356 }
2357
2358 static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len)
2359 {
2360 u8 doff;
2361 u16 pad;
2362 uint retries = 0;
2363 struct brcmf_sdio_hdrinfo hd_info = {0};
2364 int ret;
2365
2366 brcmf_dbg(TRACE, "Enter\n");
2367
2368 /* Back the pointer to make room for bus header */
2369 frame -= bus->tx_hdrlen;
2370 len += bus->tx_hdrlen;
2371
2372 /* Add alignment padding (optional for ctl frames) */
2373 doff = ((unsigned long)frame % bus->head_align);
2374 if (doff) {
2375 frame -= doff;
2376 len += doff;
2377 memset(frame + bus->tx_hdrlen, 0, doff);
2378 }
2379
2380 /* Round send length to next SDIO block */
2381 pad = 0;
2382 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2383 pad = bus->blocksize - (len % bus->blocksize);
2384 if ((pad > bus->roundup) || (pad >= bus->blocksize))
2385 pad = 0;
2386 } else if (len % bus->head_align) {
2387 pad = bus->head_align - (len % bus->head_align);
2388 }
2389 len += pad;
2390
2391 hd_info.len = len - pad;
2392 hd_info.channel = SDPCM_CONTROL_CHANNEL;
2393 hd_info.dat_offset = doff + bus->tx_hdrlen;
2394 hd_info.seq_num = bus->tx_seq;
2395 hd_info.lastfrm = true;
2396 hd_info.tail_pad = pad;
2397 brcmf_sdio_hdpack(bus, frame, &hd_info);
2398
2399 if (bus->txglom)
2400 brcmf_sdio_update_hwhdr(frame, len);
2401
2402 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
2403 frame, len, "Tx Frame:\n");
2404 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
2405 BRCMF_HDRS_ON(),
2406 frame, min_t(u16, len, 16), "TxHdr:\n");
2407
2408 do {
2409 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len);
2410
2411 if (ret < 0)
2412 brcmf_sdio_txfail(bus);
2413 else
2414 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
2415 } while (ret < 0 && retries++ < TXRETRIES);
2416
2417 return ret;
2418 }
2419
2420 static void brcmf_sdio_bus_stop(struct device *dev)
2421 {
2422 u32 local_hostintmask;
2423 u8 saveclk;
2424 int err;
2425 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2426 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2427 struct brcmf_sdio *bus = sdiodev->bus;
2428
2429 brcmf_dbg(TRACE, "Enter\n");
2430
2431 if (bus->watchdog_tsk) {
2432 send_sig(SIGTERM, bus->watchdog_tsk, 1);
2433 kthread_stop(bus->watchdog_tsk);
2434 bus->watchdog_tsk = NULL;
2435 }
2436
2437 if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
2438 sdio_claim_host(sdiodev->func[1]);
2439
2440 /* Enable clock for device interrupts */
2441 brcmf_sdio_bus_sleep(bus, false, false);
2442
2443 /* Disable and clear interrupts at the chip level also */
2444 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask));
2445 local_hostintmask = bus->hostintmask;
2446 bus->hostintmask = 0;
2447
2448 /* Force backplane clocks to assure F2 interrupt propagates */
2449 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2450 &err);
2451 if (!err)
2452 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2453 (saveclk | SBSDIO_FORCE_HT), &err);
2454 if (err)
2455 brcmf_err("Failed to force clock for F2: err %d\n",
2456 err);
2457
2458 /* Turn off the bus (F2), free any pending packets */
2459 brcmf_dbg(INTR, "disable SDIO interrupts\n");
2460 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
2461
2462 /* Clear any pending interrupts now that F2 is disabled */
2463 w_sdreg32(bus, local_hostintmask,
2464 offsetof(struct sdpcmd_regs, intstatus));
2465
2466 sdio_release_host(sdiodev->func[1]);
2467 }
2468 /* Clear the data packet queues */
2469 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
2470
2471 /* Clear any held glomming stuff */
2472 brcmu_pkt_buf_free_skb(bus->glomd);
2473 brcmf_sdio_free_glom(bus);
2474
2475 /* Clear rx control and wake any waiters */
2476 spin_lock_bh(&bus->rxctl_lock);
2477 bus->rxlen = 0;
2478 spin_unlock_bh(&bus->rxctl_lock);
2479 brcmf_sdio_dcmd_resp_wake(bus);
2480
2481 /* Reset some F2 state stuff */
2482 bus->rxskip = false;
2483 bus->tx_seq = bus->rx_seq = 0;
2484 }
2485
2486 static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus)
2487 {
2488 struct brcmf_sdio_dev *sdiodev;
2489 unsigned long flags;
2490
2491 sdiodev = bus->sdiodev;
2492 if (sdiodev->oob_irq_requested) {
2493 spin_lock_irqsave(&sdiodev->irq_en_lock, flags);
2494 if (!sdiodev->irq_en && !atomic_read(&bus->ipend)) {
2495 enable_irq(sdiodev->settings->bus.sdio.oob_irq_nr);
2496 sdiodev->irq_en = true;
2497 }
2498 spin_unlock_irqrestore(&sdiodev->irq_en_lock, flags);
2499 }
2500 }
2501
2502 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
2503 {
2504 struct brcmf_core *buscore;
2505 u32 addr;
2506 unsigned long val;
2507 int ret;
2508
2509 buscore = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
2510 addr = buscore->base + offsetof(struct sdpcmd_regs, intstatus);
2511
2512 val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret);
2513 bus->sdcnt.f1regdata++;
2514 if (ret != 0)
2515 return ret;
2516
2517 val &= bus->hostintmask;
2518 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE));
2519
2520 /* Clear interrupts */
2521 if (val) {
2522 brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret);
2523 bus->sdcnt.f1regdata++;
2524 atomic_or(val, &bus->intstatus);
2525 }
2526
2527 return ret;
2528 }
2529
2530 static void brcmf_sdio_dpc(struct brcmf_sdio *bus)
2531 {
2532 u32 newstatus = 0;
2533 unsigned long intstatus;
2534 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2535 uint framecnt; /* Temporary counter of tx/rx frames */
2536 int err = 0;
2537
2538 brcmf_dbg(TRACE, "Enter\n");
2539
2540 sdio_claim_host(bus->sdiodev->func[1]);
2541
2542 /* If waiting for HTAVAIL, check status */
2543 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) {
2544 u8 clkctl, devctl = 0;
2545
2546 #ifdef DEBUG
2547 /* Check for inconsistent device control */
2548 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2549 SBSDIO_DEVICE_CTL, &err);
2550 #endif /* DEBUG */
2551
2552 /* Read CSR, if clock on switch to AVAIL, else ignore */
2553 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
2554 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2555
2556 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2557 devctl, clkctl);
2558
2559 if (SBSDIO_HTAV(clkctl)) {
2560 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2561 SBSDIO_DEVICE_CTL, &err);
2562 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2563 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
2564 devctl, &err);
2565 bus->clkstate = CLK_AVAIL;
2566 }
2567 }
2568
2569 /* Make sure backplane clock is on */
2570 brcmf_sdio_bus_sleep(bus, false, true);
2571
2572 /* Pending interrupt indicates new device status */
2573 if (atomic_read(&bus->ipend) > 0) {
2574 atomic_set(&bus->ipend, 0);
2575 err = brcmf_sdio_intr_rstatus(bus);
2576 }
2577
2578 /* Start with leftover status bits */
2579 intstatus = atomic_xchg(&bus->intstatus, 0);
2580
2581 /* Handle flow-control change: read new state in case our ack
2582 * crossed another change interrupt. If change still set, assume
2583 * FC ON for safety, let next loop through do the debounce.
2584 */
2585 if (intstatus & I_HMB_FC_CHANGE) {
2586 intstatus &= ~I_HMB_FC_CHANGE;
2587 err = w_sdreg32(bus, I_HMB_FC_CHANGE,
2588 offsetof(struct sdpcmd_regs, intstatus));
2589
2590 err = r_sdreg32(bus, &newstatus,
2591 offsetof(struct sdpcmd_regs, intstatus));
2592 bus->sdcnt.f1regdata += 2;
2593 atomic_set(&bus->fcstate,
2594 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)));
2595 intstatus |= (newstatus & bus->hostintmask);
2596 }
2597
2598 /* Handle host mailbox indication */
2599 if (intstatus & I_HMB_HOST_INT) {
2600 intstatus &= ~I_HMB_HOST_INT;
2601 intstatus |= brcmf_sdio_hostmail(bus);
2602 }
2603
2604 sdio_release_host(bus->sdiodev->func[1]);
2605
2606 /* Generally don't ask for these, can get CRC errors... */
2607 if (intstatus & I_WR_OOSYNC) {
2608 brcmf_err("Dongle reports WR_OOSYNC\n");
2609 intstatus &= ~I_WR_OOSYNC;
2610 }
2611
2612 if (intstatus & I_RD_OOSYNC) {
2613 brcmf_err("Dongle reports RD_OOSYNC\n");
2614 intstatus &= ~I_RD_OOSYNC;
2615 }
2616
2617 if (intstatus & I_SBINT) {
2618 brcmf_err("Dongle reports SBINT\n");
2619 intstatus &= ~I_SBINT;
2620 }
2621
2622 /* Would be active due to wake-wlan in gSPI */
2623 if (intstatus & I_CHIPACTIVE) {
2624 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2625 intstatus &= ~I_CHIPACTIVE;
2626 }
2627
2628 /* Ignore frame indications if rxskip is set */
2629 if (bus->rxskip)
2630 intstatus &= ~I_HMB_FRAME_IND;
2631
2632 /* On frame indication, read available frames */
2633 if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) {
2634 brcmf_sdio_readframes(bus, bus->rxbound);
2635 if (!bus->rxpending)
2636 intstatus &= ~I_HMB_FRAME_IND;
2637 }
2638
2639 /* Keep still-pending events for next scheduling */
2640 if (intstatus)
2641 atomic_or(intstatus, &bus->intstatus);
2642
2643 brcmf_sdio_clrintr(bus);
2644
2645 if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) &&
2646 data_ok(bus)) {
2647 sdio_claim_host(bus->sdiodev->func[1]);
2648 if (bus->ctrl_frame_stat) {
2649 err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf,
2650 bus->ctrl_frame_len);
2651 bus->ctrl_frame_err = err;
2652 wmb();
2653 bus->ctrl_frame_stat = false;
2654 }
2655 sdio_release_host(bus->sdiodev->func[1]);
2656 brcmf_sdio_wait_event_wakeup(bus);
2657 }
2658 /* Send queued frames (limit 1 if rx may still be pending) */
2659 if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
2660 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit &&
2661 data_ok(bus)) {
2662 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
2663 txlimit;
2664 brcmf_sdio_sendfromq(bus, framecnt);
2665 }
2666
2667 if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) {
2668 brcmf_err("failed backplane access over SDIO, halting operation\n");
2669 atomic_set(&bus->intstatus, 0);
2670 if (bus->ctrl_frame_stat) {
2671 sdio_claim_host(bus->sdiodev->func[1]);
2672 if (bus->ctrl_frame_stat) {
2673 bus->ctrl_frame_err = -ENODEV;
2674 wmb();
2675 bus->ctrl_frame_stat = false;
2676 brcmf_sdio_wait_event_wakeup(bus);
2677 }
2678 sdio_release_host(bus->sdiodev->func[1]);
2679 }
2680 } else if (atomic_read(&bus->intstatus) ||
2681 atomic_read(&bus->ipend) > 0 ||
2682 (!atomic_read(&bus->fcstate) &&
2683 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
2684 data_ok(bus))) {
2685 bus->dpc_triggered = true;
2686 }
2687 }
2688
2689 static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev)
2690 {
2691 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2692 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2693 struct brcmf_sdio *bus = sdiodev->bus;
2694
2695 return &bus->txq;
2696 }
2697
2698 static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec)
2699 {
2700 struct sk_buff *p;
2701 int eprec = -1; /* precedence to evict from */
2702
2703 /* Fast case, precedence queue is not full and we are also not
2704 * exceeding total queue length
2705 */
2706 if (!pktq_pfull(q, prec) && !pktq_full(q)) {
2707 brcmu_pktq_penq(q, prec, pkt);
2708 return true;
2709 }
2710
2711 /* Determine precedence from which to evict packet, if any */
2712 if (pktq_pfull(q, prec)) {
2713 eprec = prec;
2714 } else if (pktq_full(q)) {
2715 p = brcmu_pktq_peek_tail(q, &eprec);
2716 if (eprec > prec)
2717 return false;
2718 }
2719
2720 /* Evict if needed */
2721 if (eprec >= 0) {
2722 /* Detect queueing to unconfigured precedence */
2723 if (eprec == prec)
2724 return false; /* refuse newer (incoming) packet */
2725 /* Evict packet according to discard policy */
2726 p = brcmu_pktq_pdeq_tail(q, eprec);
2727 if (p == NULL)
2728 brcmf_err("brcmu_pktq_pdeq_tail() failed\n");
2729 brcmu_pkt_buf_free_skb(p);
2730 }
2731
2732 /* Enqueue */
2733 p = brcmu_pktq_penq(q, prec, pkt);
2734 if (p == NULL)
2735 brcmf_err("brcmu_pktq_penq() failed\n");
2736
2737 return p != NULL;
2738 }
2739
2740 static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt)
2741 {
2742 int ret = -EBADE;
2743 uint prec;
2744 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2745 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2746 struct brcmf_sdio *bus = sdiodev->bus;
2747
2748 brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len);
2749 if (sdiodev->state != BRCMF_SDIOD_DATA)
2750 return -EIO;
2751
2752 /* Add space for the header */
2753 skb_push(pkt, bus->tx_hdrlen);
2754 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2755
2756 prec = prio2prec((pkt->priority & PRIOMASK));
2757
2758 /* Check for existing queue, current flow-control,
2759 pending event, or pending clock */
2760 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2761 bus->sdcnt.fcqueued++;
2762
2763 /* Priority based enq */
2764 spin_lock_bh(&bus->txq_lock);
2765 /* reset bus_flags in packet cb */
2766 *(u16 *)(pkt->cb) = 0;
2767 if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) {
2768 skb_pull(pkt, bus->tx_hdrlen);
2769 brcmf_err("out of bus->txq !!!\n");
2770 ret = -ENOSR;
2771 } else {
2772 ret = 0;
2773 }
2774
2775 if (pktq_len(&bus->txq) >= TXHI) {
2776 bus->txoff = true;
2777 brcmf_proto_bcdc_txflowblock(dev, true);
2778 }
2779 spin_unlock_bh(&bus->txq_lock);
2780
2781 #ifdef DEBUG
2782 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2783 qcount[prec] = pktq_plen(&bus->txq, prec);
2784 #endif
2785
2786 brcmf_sdio_trigger_dpc(bus);
2787 return ret;
2788 }
2789
2790 #ifdef DEBUG
2791 #define CONSOLE_LINE_MAX 192
2792
2793 static int brcmf_sdio_readconsole(struct brcmf_sdio *bus)
2794 {
2795 struct brcmf_console *c = &bus->console;
2796 u8 line[CONSOLE_LINE_MAX], ch;
2797 u32 n, idx, addr;
2798 int rv;
2799
2800 /* Don't do anything until FWREADY updates console address */
2801 if (bus->console_addr == 0)
2802 return 0;
2803
2804 /* Read console log struct */
2805 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2806 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
2807 sizeof(c->log_le));
2808 if (rv < 0)
2809 return rv;
2810
2811 /* Allocate console buffer (one time only) */
2812 if (c->buf == NULL) {
2813 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2814 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2815 if (c->buf == NULL)
2816 return -ENOMEM;
2817 }
2818
2819 idx = le32_to_cpu(c->log_le.idx);
2820
2821 /* Protect against corrupt value */
2822 if (idx > c->bufsize)
2823 return -EBADE;
2824
2825 /* Skip reading the console buffer if the index pointer
2826 has not moved */
2827 if (idx == c->last)
2828 return 0;
2829
2830 /* Read the console buffer */
2831 addr = le32_to_cpu(c->log_le.buf);
2832 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
2833 if (rv < 0)
2834 return rv;
2835
2836 while (c->last != idx) {
2837 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2838 if (c->last == idx) {
2839 /* This would output a partial line.
2840 * Instead, back up
2841 * the buffer pointer and output this
2842 * line next time around.
2843 */
2844 if (c->last >= n)
2845 c->last -= n;
2846 else
2847 c->last = c->bufsize - n;
2848 goto break2;
2849 }
2850 ch = c->buf[c->last];
2851 c->last = (c->last + 1) % c->bufsize;
2852 if (ch == '\n')
2853 break;
2854 line[n] = ch;
2855 }
2856
2857 if (n > 0) {
2858 if (line[n - 1] == '\r')
2859 n--;
2860 line[n] = 0;
2861 pr_debug("CONSOLE: %s\n", line);
2862 }
2863 }
2864 break2:
2865
2866 return 0;
2867 }
2868 #endif /* DEBUG */
2869
2870 static int
2871 brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
2872 {
2873 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2874 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2875 struct brcmf_sdio *bus = sdiodev->bus;
2876 int ret;
2877
2878 brcmf_dbg(TRACE, "Enter\n");
2879 if (sdiodev->state != BRCMF_SDIOD_DATA)
2880 return -EIO;
2881
2882 /* Send from dpc */
2883 bus->ctrl_frame_buf = msg;
2884 bus->ctrl_frame_len = msglen;
2885 wmb();
2886 bus->ctrl_frame_stat = true;
2887
2888 brcmf_sdio_trigger_dpc(bus);
2889 wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat,
2890 CTL_DONE_TIMEOUT);
2891 ret = 0;
2892 if (bus->ctrl_frame_stat) {
2893 sdio_claim_host(bus->sdiodev->func[1]);
2894 if (bus->ctrl_frame_stat) {
2895 brcmf_dbg(SDIO, "ctrl_frame timeout\n");
2896 bus->ctrl_frame_stat = false;
2897 ret = -ETIMEDOUT;
2898 }
2899 sdio_release_host(bus->sdiodev->func[1]);
2900 }
2901 if (!ret) {
2902 brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n",
2903 bus->ctrl_frame_err);
2904 rmb();
2905 ret = bus->ctrl_frame_err;
2906 }
2907
2908 if (ret)
2909 bus->sdcnt.tx_ctlerrs++;
2910 else
2911 bus->sdcnt.tx_ctlpkts++;
2912
2913 return ret;
2914 }
2915
2916 #ifdef DEBUG
2917 static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus,
2918 struct sdpcm_shared *sh)
2919 {
2920 u32 addr, console_ptr, console_size, console_index;
2921 char *conbuf = NULL;
2922 __le32 sh_val;
2923 int rv;
2924
2925 /* obtain console information from device memory */
2926 addr = sh->console_addr + offsetof(struct rte_console, log_le);
2927 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2928 (u8 *)&sh_val, sizeof(u32));
2929 if (rv < 0)
2930 return rv;
2931 console_ptr = le32_to_cpu(sh_val);
2932
2933 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
2934 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2935 (u8 *)&sh_val, sizeof(u32));
2936 if (rv < 0)
2937 return rv;
2938 console_size = le32_to_cpu(sh_val);
2939
2940 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
2941 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2942 (u8 *)&sh_val, sizeof(u32));
2943 if (rv < 0)
2944 return rv;
2945 console_index = le32_to_cpu(sh_val);
2946
2947 /* allocate buffer for console data */
2948 if (console_size <= CONSOLE_BUFFER_MAX)
2949 conbuf = vzalloc(console_size+1);
2950
2951 if (!conbuf)
2952 return -ENOMEM;
2953
2954 /* obtain the console data from device */
2955 conbuf[console_size] = '\0';
2956 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
2957 console_size);
2958 if (rv < 0)
2959 goto done;
2960
2961 rv = seq_write(seq, conbuf + console_index,
2962 console_size - console_index);
2963 if (rv < 0)
2964 goto done;
2965
2966 if (console_index > 0)
2967 rv = seq_write(seq, conbuf, console_index - 1);
2968
2969 done:
2970 vfree(conbuf);
2971 return rv;
2972 }
2973
2974 static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus,
2975 struct sdpcm_shared *sh)
2976 {
2977 int error;
2978 struct brcmf_trap_info tr;
2979
2980 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) {
2981 brcmf_dbg(INFO, "no trap in firmware\n");
2982 return 0;
2983 }
2984
2985 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
2986 sizeof(struct brcmf_trap_info));
2987 if (error < 0)
2988 return error;
2989
2990 seq_printf(seq,
2991 "dongle trap info: type 0x%x @ epc 0x%08x\n"
2992 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
2993 " lr 0x%08x pc 0x%08x offset 0x%x\n"
2994 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
2995 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
2996 le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
2997 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
2998 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
2999 le32_to_cpu(tr.pc), sh->trap_addr,
3000 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
3001 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
3002 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
3003 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
3004
3005 return 0;
3006 }
3007
3008 static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus,
3009 struct sdpcm_shared *sh)
3010 {
3011 int error = 0;
3012 char file[80] = "?";
3013 char expr[80] = "<???>";
3014
3015 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
3016 brcmf_dbg(INFO, "firmware not built with -assert\n");
3017 return 0;
3018 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
3019 brcmf_dbg(INFO, "no assert in dongle\n");
3020 return 0;
3021 }
3022
3023 sdio_claim_host(bus->sdiodev->func[1]);
3024 if (sh->assert_file_addr != 0) {
3025 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3026 sh->assert_file_addr, (u8 *)file, 80);
3027 if (error < 0)
3028 return error;
3029 }
3030 if (sh->assert_exp_addr != 0) {
3031 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3032 sh->assert_exp_addr, (u8 *)expr, 80);
3033 if (error < 0)
3034 return error;
3035 }
3036 sdio_release_host(bus->sdiodev->func[1]);
3037
3038 seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n",
3039 file, sh->assert_line, expr);
3040 return 0;
3041 }
3042
3043 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3044 {
3045 int error;
3046 struct sdpcm_shared sh;
3047
3048 error = brcmf_sdio_readshared(bus, &sh);
3049
3050 if (error < 0)
3051 return error;
3052
3053 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
3054 brcmf_dbg(INFO, "firmware not built with -assert\n");
3055 else if (sh.flags & SDPCM_SHARED_ASSERT)
3056 brcmf_err("assertion in dongle\n");
3057
3058 if (sh.flags & SDPCM_SHARED_TRAP)
3059 brcmf_err("firmware trap in dongle\n");
3060
3061 return 0;
3062 }
3063
3064 static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus)
3065 {
3066 int error = 0;
3067 struct sdpcm_shared sh;
3068
3069 error = brcmf_sdio_readshared(bus, &sh);
3070 if (error < 0)
3071 goto done;
3072
3073 error = brcmf_sdio_assert_info(seq, bus, &sh);
3074 if (error < 0)
3075 goto done;
3076
3077 error = brcmf_sdio_trap_info(seq, bus, &sh);
3078 if (error < 0)
3079 goto done;
3080
3081 error = brcmf_sdio_dump_console(seq, bus, &sh);
3082
3083 done:
3084 return error;
3085 }
3086
3087 static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data)
3088 {
3089 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3090 struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus;
3091
3092 return brcmf_sdio_died_dump(seq, bus);
3093 }
3094
3095 static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data)
3096 {
3097 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3098 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3099 struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt;
3100
3101 seq_printf(seq,
3102 "intrcount: %u\nlastintrs: %u\n"
3103 "pollcnt: %u\nregfails: %u\n"
3104 "tx_sderrs: %u\nfcqueued: %u\n"
3105 "rxrtx: %u\nrx_toolong: %u\n"
3106 "rxc_errors: %u\nrx_hdrfail: %u\n"
3107 "rx_badhdr: %u\nrx_badseq: %u\n"
3108 "fc_rcvd: %u\nfc_xoff: %u\n"
3109 "fc_xon: %u\nrxglomfail: %u\n"
3110 "rxglomframes: %u\nrxglompkts: %u\n"
3111 "f2rxhdrs: %u\nf2rxdata: %u\n"
3112 "f2txdata: %u\nf1regdata: %u\n"
3113 "tickcnt: %u\ntx_ctlerrs: %lu\n"
3114 "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n"
3115 "rx_ctlpkts: %lu\nrx_readahead: %lu\n",
3116 sdcnt->intrcount, sdcnt->lastintrs,
3117 sdcnt->pollcnt, sdcnt->regfails,
3118 sdcnt->tx_sderrs, sdcnt->fcqueued,
3119 sdcnt->rxrtx, sdcnt->rx_toolong,
3120 sdcnt->rxc_errors, sdcnt->rx_hdrfail,
3121 sdcnt->rx_badhdr, sdcnt->rx_badseq,
3122 sdcnt->fc_rcvd, sdcnt->fc_xoff,
3123 sdcnt->fc_xon, sdcnt->rxglomfail,
3124 sdcnt->rxglomframes, sdcnt->rxglompkts,
3125 sdcnt->f2rxhdrs, sdcnt->f2rxdata,
3126 sdcnt->f2txdata, sdcnt->f1regdata,
3127 sdcnt->tickcnt, sdcnt->tx_ctlerrs,
3128 sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs,
3129 sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt);
3130
3131 return 0;
3132 }
3133
3134 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3135 {
3136 struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr;
3137 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
3138
3139 if (IS_ERR_OR_NULL(dentry))
3140 return;
3141
3142 bus->console_interval = BRCMF_CONSOLE;
3143
3144 brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read);
3145 brcmf_debugfs_add_entry(drvr, "counters",
3146 brcmf_debugfs_sdio_count_read);
3147 debugfs_create_u32("console_interval", 0644, dentry,
3148 &bus->console_interval);
3149 }
3150 #else
3151 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3152 {
3153 return 0;
3154 }
3155
3156 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3157 {
3158 }
3159 #endif /* DEBUG */
3160
3161 static int
3162 brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
3163 {
3164 int timeleft;
3165 uint rxlen = 0;
3166 bool pending;
3167 u8 *buf;
3168 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3169 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3170 struct brcmf_sdio *bus = sdiodev->bus;
3171
3172 brcmf_dbg(TRACE, "Enter\n");
3173 if (sdiodev->state != BRCMF_SDIOD_DATA)
3174 return -EIO;
3175
3176 /* Wait until control frame is available */
3177 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3178
3179 spin_lock_bh(&bus->rxctl_lock);
3180 rxlen = bus->rxlen;
3181 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3182 bus->rxctl = NULL;
3183 buf = bus->rxctl_orig;
3184 bus->rxctl_orig = NULL;
3185 bus->rxlen = 0;
3186 spin_unlock_bh(&bus->rxctl_lock);
3187 vfree(buf);
3188
3189 if (rxlen) {
3190 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3191 rxlen, msglen);
3192 } else if (timeleft == 0) {
3193 brcmf_err("resumed on timeout\n");
3194 brcmf_sdio_checkdied(bus);
3195 } else if (pending) {
3196 brcmf_dbg(CTL, "cancelled\n");
3197 return -ERESTARTSYS;
3198 } else {
3199 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3200 brcmf_sdio_checkdied(bus);
3201 }
3202
3203 if (rxlen)
3204 bus->sdcnt.rx_ctlpkts++;
3205 else
3206 bus->sdcnt.rx_ctlerrs++;
3207
3208 return rxlen ? (int)rxlen : -ETIMEDOUT;
3209 }
3210
3211 #ifdef DEBUG
3212 static bool
3213 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3214 u8 *ram_data, uint ram_sz)
3215 {
3216 char *ram_cmp;
3217 int err;
3218 bool ret = true;
3219 int address;
3220 int offset;
3221 int len;
3222
3223 /* read back and verify */
3224 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr,
3225 ram_sz);
3226 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL);
3227 /* do not proceed while no memory but */
3228 if (!ram_cmp)
3229 return true;
3230
3231 address = ram_addr;
3232 offset = 0;
3233 while (offset < ram_sz) {
3234 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK :
3235 ram_sz - offset;
3236 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len);
3237 if (err) {
3238 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3239 err, len, address);
3240 ret = false;
3241 break;
3242 } else if (memcmp(ram_cmp, &ram_data[offset], len)) {
3243 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n",
3244 offset, len);
3245 ret = false;
3246 break;
3247 }
3248 offset += len;
3249 address += len;
3250 }
3251
3252 kfree(ram_cmp);
3253
3254 return ret;
3255 }
3256 #else /* DEBUG */
3257 static bool
3258 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3259 u8 *ram_data, uint ram_sz)
3260 {
3261 return true;
3262 }
3263 #endif /* DEBUG */
3264
3265 static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
3266 const struct firmware *fw)
3267 {
3268 int err;
3269
3270 brcmf_dbg(TRACE, "Enter\n");
3271
3272 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase,
3273 (u8 *)fw->data, fw->size);
3274 if (err)
3275 brcmf_err("error %d on writing %d membytes at 0x%08x\n",
3276 err, (int)fw->size, bus->ci->rambase);
3277 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase,
3278 (u8 *)fw->data, fw->size))
3279 err = -EIO;
3280
3281 return err;
3282 }
3283
3284 static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus,
3285 void *vars, u32 varsz)
3286 {
3287 int address;
3288 int err;
3289
3290 brcmf_dbg(TRACE, "Enter\n");
3291
3292 address = bus->ci->ramsize - varsz + bus->ci->rambase;
3293 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz);
3294 if (err)
3295 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
3296 err, varsz, address);
3297 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz))
3298 err = -EIO;
3299
3300 return err;
3301 }
3302
3303 static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus,
3304 const struct firmware *fw,
3305 void *nvram, u32 nvlen)
3306 {
3307 int bcmerror;
3308 u32 rstvec;
3309
3310 sdio_claim_host(bus->sdiodev->func[1]);
3311 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
3312
3313 rstvec = get_unaligned_le32(fw->data);
3314 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec);
3315
3316 bcmerror = brcmf_sdio_download_code_file(bus, fw);
3317 release_firmware(fw);
3318 if (bcmerror) {
3319 brcmf_err("dongle image file download failed\n");
3320 brcmf_fw_nvram_free(nvram);
3321 goto err;
3322 }
3323
3324 bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen);
3325 brcmf_fw_nvram_free(nvram);
3326 if (bcmerror) {
3327 brcmf_err("dongle nvram file download failed\n");
3328 goto err;
3329 }
3330
3331 /* Take arm out of reset */
3332 if (!brcmf_chip_set_active(bus->ci, rstvec)) {
3333 brcmf_err("error getting out of ARM core reset\n");
3334 goto err;
3335 }
3336
3337 err:
3338 brcmf_sdio_clkctl(bus, CLK_SDONLY, false);
3339 sdio_release_host(bus->sdiodev->func[1]);
3340 return bcmerror;
3341 }
3342
3343 static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
3344 {
3345 int err = 0;
3346 u8 val;
3347
3348 brcmf_dbg(TRACE, "Enter\n");
3349
3350 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
3351 if (err) {
3352 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
3353 return;
3354 }
3355
3356 val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
3357 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
3358 if (err) {
3359 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
3360 return;
3361 }
3362
3363 /* Add CMD14 Support */
3364 brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
3365 (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
3366 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
3367 &err);
3368 if (err) {
3369 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
3370 return;
3371 }
3372
3373 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3374 SBSDIO_FORCE_HT, &err);
3375 if (err) {
3376 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
3377 return;
3378 }
3379
3380 /* set flag */
3381 bus->sr_enabled = true;
3382 brcmf_dbg(INFO, "SR enabled\n");
3383 }
3384
3385 /* enable KSO bit */
3386 static int brcmf_sdio_kso_init(struct brcmf_sdio *bus)
3387 {
3388 u8 val;
3389 int err = 0;
3390
3391 brcmf_dbg(TRACE, "Enter\n");
3392
3393 /* KSO bit added in SDIO core rev 12 */
3394 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12)
3395 return 0;
3396
3397 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
3398 if (err) {
3399 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
3400 return err;
3401 }
3402
3403 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
3404 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
3405 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
3406 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
3407 val, &err);
3408 if (err) {
3409 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
3410 return err;
3411 }
3412 }
3413
3414 return 0;
3415 }
3416
3417
3418 static int brcmf_sdio_bus_preinit(struct device *dev)
3419 {
3420 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3421 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3422 struct brcmf_sdio *bus = sdiodev->bus;
3423 uint pad_size;
3424 u32 value;
3425 int err;
3426
3427 /* the commands below use the terms tx and rx from
3428 * a device perspective, ie. bus:txglom affects the
3429 * bus transfers from device to host.
3430 */
3431 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) {
3432 /* for sdio core rev < 12, disable txgloming */
3433 value = 0;
3434 err = brcmf_iovar_data_set(dev, "bus:txglom", &value,
3435 sizeof(u32));
3436 } else {
3437 /* otherwise, set txglomalign */
3438 value = sdiodev->settings->bus.sdio.sd_sgentry_align;
3439 /* SDIO ADMA requires at least 32 bit alignment */
3440 value = max_t(u32, value, ALIGNMENT);
3441 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value,
3442 sizeof(u32));
3443 }
3444
3445 if (err < 0)
3446 goto done;
3447
3448 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
3449 if (sdiodev->sg_support) {
3450 bus->txglom = false;
3451 value = 1;
3452 pad_size = bus->sdiodev->func[2]->cur_blksize << 1;
3453 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom",
3454 &value, sizeof(u32));
3455 if (err < 0) {
3456 /* bus:rxglom is allowed to fail */
3457 err = 0;
3458 } else {
3459 bus->txglom = true;
3460 bus->tx_hdrlen += SDPCM_HWEXT_LEN;
3461 }
3462 }
3463 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen);
3464
3465 done:
3466 return err;
3467 }
3468
3469 static size_t brcmf_sdio_bus_get_ramsize(struct device *dev)
3470 {
3471 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3472 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3473 struct brcmf_sdio *bus = sdiodev->bus;
3474
3475 return bus->ci->ramsize - bus->ci->srsize;
3476 }
3477
3478 static int brcmf_sdio_bus_get_memdump(struct device *dev, void *data,
3479 size_t mem_size)
3480 {
3481 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3482 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3483 struct brcmf_sdio *bus = sdiodev->bus;
3484 int err;
3485 int address;
3486 int offset;
3487 int len;
3488
3489 brcmf_dbg(INFO, "dump at 0x%08x: size=%zu\n", bus->ci->rambase,
3490 mem_size);
3491
3492 address = bus->ci->rambase;
3493 offset = err = 0;
3494 sdio_claim_host(sdiodev->func[1]);
3495 while (offset < mem_size) {
3496 len = ((offset + MEMBLOCK) < mem_size) ? MEMBLOCK :
3497 mem_size - offset;
3498 err = brcmf_sdiod_ramrw(sdiodev, false, address, data, len);
3499 if (err) {
3500 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3501 err, len, address);
3502 goto done;
3503 }
3504 data += len;
3505 offset += len;
3506 address += len;
3507 }
3508
3509 done:
3510 sdio_release_host(sdiodev->func[1]);
3511 return err;
3512 }
3513
3514 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus)
3515 {
3516 if (!bus->dpc_triggered) {
3517 bus->dpc_triggered = true;
3518 queue_work(bus->brcmf_wq, &bus->datawork);
3519 }
3520 }
3521
3522 void brcmf_sdio_isr(struct brcmf_sdio *bus)
3523 {
3524 brcmf_dbg(TRACE, "Enter\n");
3525
3526 if (!bus) {
3527 brcmf_err("bus is null pointer, exiting\n");
3528 return;
3529 }
3530
3531 /* Count the interrupt call */
3532 bus->sdcnt.intrcount++;
3533 if (in_interrupt())
3534 atomic_set(&bus->ipend, 1);
3535 else
3536 if (brcmf_sdio_intr_rstatus(bus)) {
3537 brcmf_err("failed backplane access\n");
3538 }
3539
3540 /* Disable additional interrupts (is this needed now)? */
3541 if (!bus->intr)
3542 brcmf_err("isr w/o interrupt configured!\n");
3543
3544 bus->dpc_triggered = true;
3545 queue_work(bus->brcmf_wq, &bus->datawork);
3546 }
3547
3548 static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus)
3549 {
3550 brcmf_dbg(TIMER, "Enter\n");
3551
3552 /* Poll period: check device if appropriate. */
3553 if (!bus->sr_enabled &&
3554 bus->poll && (++bus->polltick >= bus->pollrate)) {
3555 u32 intstatus = 0;
3556
3557 /* Reset poll tick */
3558 bus->polltick = 0;
3559
3560 /* Check device if no interrupts */
3561 if (!bus->intr ||
3562 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
3563
3564 if (!bus->dpc_triggered) {
3565 u8 devpend;
3566
3567 sdio_claim_host(bus->sdiodev->func[1]);
3568 devpend = brcmf_sdiod_regrb(bus->sdiodev,
3569 SDIO_CCCR_INTx,
3570 NULL);
3571 sdio_release_host(bus->sdiodev->func[1]);
3572 intstatus = devpend & (INTR_STATUS_FUNC1 |
3573 INTR_STATUS_FUNC2);
3574 }
3575
3576 /* If there is something, make like the ISR and
3577 schedule the DPC */
3578 if (intstatus) {
3579 bus->sdcnt.pollcnt++;
3580 atomic_set(&bus->ipend, 1);
3581
3582 bus->dpc_triggered = true;
3583 queue_work(bus->brcmf_wq, &bus->datawork);
3584 }
3585 }
3586
3587 /* Update interrupt tracking */
3588 bus->sdcnt.lastintrs = bus->sdcnt.intrcount;
3589 }
3590 #ifdef DEBUG
3591 /* Poll for console output periodically */
3592 if (bus->sdiodev->state == BRCMF_SDIOD_DATA && BRCMF_FWCON_ON() &&
3593 bus->console_interval != 0) {
3594 bus->console.count += jiffies_to_msecs(BRCMF_WD_POLL);
3595 if (bus->console.count >= bus->console_interval) {
3596 bus->console.count -= bus->console_interval;
3597 sdio_claim_host(bus->sdiodev->func[1]);
3598 /* Make sure backplane clock is on */
3599 brcmf_sdio_bus_sleep(bus, false, false);
3600 if (brcmf_sdio_readconsole(bus) < 0)
3601 /* stop on error */
3602 bus->console_interval = 0;
3603 sdio_release_host(bus->sdiodev->func[1]);
3604 }
3605 }
3606 #endif /* DEBUG */
3607
3608 /* On idle timeout clear activity flag and/or turn off clock */
3609 if (!bus->dpc_triggered) {
3610 rmb();
3611 if ((!bus->dpc_running) && (bus->idletime > 0) &&
3612 (bus->clkstate == CLK_AVAIL)) {
3613 bus->idlecount++;
3614 if (bus->idlecount > bus->idletime) {
3615 brcmf_dbg(SDIO, "idle\n");
3616 sdio_claim_host(bus->sdiodev->func[1]);
3617 brcmf_sdio_wd_timer(bus, false);
3618 bus->idlecount = 0;
3619 brcmf_sdio_bus_sleep(bus, true, false);
3620 sdio_release_host(bus->sdiodev->func[1]);
3621 }
3622 } else {
3623 bus->idlecount = 0;
3624 }
3625 } else {
3626 bus->idlecount = 0;
3627 }
3628 }
3629
3630 static void brcmf_sdio_dataworker(struct work_struct *work)
3631 {
3632 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
3633 datawork);
3634
3635 bus->dpc_running = true;
3636 wmb();
3637 while (READ_ONCE(bus->dpc_triggered)) {
3638 bus->dpc_triggered = false;
3639 brcmf_sdio_dpc(bus);
3640 bus->idlecount = 0;
3641 }
3642 bus->dpc_running = false;
3643 if (brcmf_sdiod_freezing(bus->sdiodev)) {
3644 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN);
3645 brcmf_sdiod_try_freeze(bus->sdiodev);
3646 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
3647 }
3648 }
3649
3650 static void
3651 brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
3652 struct brcmf_chip *ci, u32 drivestrength)
3653 {
3654 const struct sdiod_drive_str *str_tab = NULL;
3655 u32 str_mask;
3656 u32 str_shift;
3657 u32 i;
3658 u32 drivestrength_sel = 0;
3659 u32 cc_data_temp;
3660 u32 addr;
3661
3662 if (!(ci->cc_caps & CC_CAP_PMU))
3663 return;
3664
3665 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) {
3666 case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12):
3667 str_tab = sdiod_drvstr_tab1_1v8;
3668 str_mask = 0x00003800;
3669 str_shift = 11;
3670 break;
3671 case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17):
3672 str_tab = sdiod_drvstr_tab6_1v8;
3673 str_mask = 0x00001800;
3674 str_shift = 11;
3675 break;
3676 case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17):
3677 /* note: 43143 does not support tristate */
3678 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1;
3679 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) {
3680 str_tab = sdiod_drvstr_tab2_3v3;
3681 str_mask = 0x00000007;
3682 str_shift = 0;
3683 } else
3684 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n",
3685 ci->name, drivestrength);
3686 break;
3687 case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13):
3688 str_tab = sdiod_drive_strength_tab5_1v8;
3689 str_mask = 0x00003800;
3690 str_shift = 11;
3691 break;
3692 default:
3693 brcmf_dbg(INFO, "No SDIO driver strength init needed for chip %s rev %d pmurev %d\n",
3694 ci->name, ci->chiprev, ci->pmurev);
3695 break;
3696 }
3697
3698 if (str_tab != NULL) {
3699 struct brcmf_core *pmu = brcmf_chip_get_pmu(ci);
3700
3701 for (i = 0; str_tab[i].strength != 0; i++) {
3702 if (drivestrength >= str_tab[i].strength) {
3703 drivestrength_sel = str_tab[i].sel;
3704 break;
3705 }
3706 }
3707 addr = CORE_CC_REG(pmu->base, chipcontrol_addr);
3708 brcmf_sdiod_regwl(sdiodev, addr, 1, NULL);
3709 cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3710 cc_data_temp &= ~str_mask;
3711 drivestrength_sel <<= str_shift;
3712 cc_data_temp |= drivestrength_sel;
3713 brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL);
3714
3715 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
3716 str_tab[i].strength, drivestrength, cc_data_temp);
3717 }
3718 }
3719
3720 static int brcmf_sdio_buscoreprep(void *ctx)
3721 {
3722 struct brcmf_sdio_dev *sdiodev = ctx;
3723 int err = 0;
3724 u8 clkval, clkset;
3725
3726 /* Try forcing SDIO core to do ALPAvail request only */
3727 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
3728 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3729 if (err) {
3730 brcmf_err("error writing for HT off\n");
3731 return err;
3732 }
3733
3734 /* If register supported, wait for ALPAvail and then force ALP */
3735 /* This may take up to 15 milliseconds */
3736 clkval = brcmf_sdiod_regrb(sdiodev,
3737 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
3738
3739 if ((clkval & ~SBSDIO_AVBITS) != clkset) {
3740 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
3741 clkset, clkval);
3742 return -EACCES;
3743 }
3744
3745 SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev,
3746 SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
3747 !SBSDIO_ALPAV(clkval)),
3748 PMU_MAX_TRANSITION_DLY);
3749 if (!SBSDIO_ALPAV(clkval)) {
3750 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n",
3751 clkval);
3752 return -EBUSY;
3753 }
3754
3755 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
3756 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3757 udelay(65);
3758
3759 /* Also, disable the extra SDIO pull-ups */
3760 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
3761
3762 return 0;
3763 }
3764
3765 static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip,
3766 u32 rstvec)
3767 {
3768 struct brcmf_sdio_dev *sdiodev = ctx;
3769 struct brcmf_core *core;
3770 u32 reg_addr;
3771
3772 /* clear all interrupts */
3773 core = brcmf_chip_get_core(chip, BCMA_CORE_SDIO_DEV);
3774 reg_addr = core->base + offsetof(struct sdpcmd_regs, intstatus);
3775 brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
3776
3777 if (rstvec)
3778 /* Write reset vector to address 0 */
3779 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec,
3780 sizeof(rstvec));
3781 }
3782
3783 static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr)
3784 {
3785 struct brcmf_sdio_dev *sdiodev = ctx;
3786 u32 val, rev;
3787
3788 val = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3789 if ((sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 ||
3790 sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4339) &&
3791 addr == CORE_CC_REG(SI_ENUM_BASE, chipid)) {
3792 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT;
3793 if (rev >= 2) {
3794 val &= ~CID_ID_MASK;
3795 val |= BRCM_CC_4339_CHIP_ID;
3796 }
3797 }
3798 return val;
3799 }
3800
3801 static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val)
3802 {
3803 struct brcmf_sdio_dev *sdiodev = ctx;
3804
3805 brcmf_sdiod_regwl(sdiodev, addr, val, NULL);
3806 }
3807
3808 static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = {
3809 .prepare = brcmf_sdio_buscoreprep,
3810 .activate = brcmf_sdio_buscore_activate,
3811 .read32 = brcmf_sdio_buscore_read32,
3812 .write32 = brcmf_sdio_buscore_write32,
3813 };
3814
3815 static bool
3816 brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
3817 {
3818 struct brcmf_sdio_dev *sdiodev;
3819 u8 clkctl = 0;
3820 int err = 0;
3821 int reg_addr;
3822 u32 reg_val;
3823 u32 drivestrength;
3824
3825 sdiodev = bus->sdiodev;
3826 sdio_claim_host(sdiodev->func[1]);
3827
3828 pr_debug("F1 signature read @0x18000000=0x%4x\n",
3829 brcmf_sdiod_regrl(sdiodev, SI_ENUM_BASE, NULL));
3830
3831 /*
3832 * Force PLL off until brcmf_chip_attach()
3833 * programs PLL control regs
3834 */
3835
3836 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3837 BRCMF_INIT_CLKCTL1, &err);
3838 if (!err)
3839 clkctl = brcmf_sdiod_regrb(sdiodev,
3840 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3841
3842 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
3843 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
3844 err, BRCMF_INIT_CLKCTL1, clkctl);
3845 goto fail;
3846 }
3847
3848 bus->ci = brcmf_chip_attach(sdiodev, &brcmf_sdio_buscore_ops);
3849 if (IS_ERR(bus->ci)) {
3850 brcmf_err("brcmf_chip_attach failed!\n");
3851 bus->ci = NULL;
3852 goto fail;
3853 }
3854 sdiodev->settings = brcmf_get_module_param(sdiodev->dev,
3855 BRCMF_BUSTYPE_SDIO,
3856 bus->ci->chip,
3857 bus->ci->chiprev);
3858 if (!sdiodev->settings) {
3859 brcmf_err("Failed to get device parameters\n");
3860 goto fail;
3861 }
3862 /* platform specific configuration:
3863 * alignments must be at least 4 bytes for ADMA
3864 */
3865 bus->head_align = ALIGNMENT;
3866 bus->sgentry_align = ALIGNMENT;
3867 if (sdiodev->settings->bus.sdio.sd_head_align > ALIGNMENT)
3868 bus->head_align = sdiodev->settings->bus.sdio.sd_head_align;
3869 if (sdiodev->settings->bus.sdio.sd_sgentry_align > ALIGNMENT)
3870 bus->sgentry_align =
3871 sdiodev->settings->bus.sdio.sd_sgentry_align;
3872
3873 /* allocate scatter-gather table. sg support
3874 * will be disabled upon allocation failure.
3875 */
3876 brcmf_sdiod_sgtable_alloc(sdiodev);
3877
3878 #ifdef CONFIG_PM_SLEEP
3879 /* wowl can be supported when KEEP_POWER is true and (WAKE_SDIO_IRQ
3880 * is true or when platform data OOB irq is true).
3881 */
3882 if ((sdio_get_host_pm_caps(sdiodev->func[1]) & MMC_PM_KEEP_POWER) &&
3883 ((sdio_get_host_pm_caps(sdiodev->func[1]) & MMC_PM_WAKE_SDIO_IRQ) ||
3884 (sdiodev->settings->bus.sdio.oob_irq_supported)))
3885 sdiodev->bus_if->wowl_supported = true;
3886 #endif
3887
3888 if (brcmf_sdio_kso_init(bus)) {
3889 brcmf_err("error enabling KSO\n");
3890 goto fail;
3891 }
3892
3893 if (sdiodev->settings->bus.sdio.drive_strength)
3894 drivestrength = sdiodev->settings->bus.sdio.drive_strength;
3895 else
3896 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH;
3897 brcmf_sdio_drivestrengthinit(sdiodev, bus->ci, drivestrength);
3898
3899 /* Set card control so an SDIO card reset does a WLAN backplane reset */
3900 reg_val = brcmf_sdiod_regrb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err);
3901 if (err)
3902 goto fail;
3903
3904 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
3905
3906 brcmf_sdiod_regwb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
3907 if (err)
3908 goto fail;
3909
3910 /* set PMUControl so a backplane reset does PMU state reload */
3911 reg_addr = CORE_CC_REG(brcmf_chip_get_pmu(bus->ci)->base, pmucontrol);
3912 reg_val = brcmf_sdiod_regrl(sdiodev, reg_addr, &err);
3913 if (err)
3914 goto fail;
3915
3916 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
3917
3918 brcmf_sdiod_regwl(sdiodev, reg_addr, reg_val, &err);
3919 if (err)
3920 goto fail;
3921
3922 sdio_release_host(sdiodev->func[1]);
3923
3924 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
3925
3926 /* allocate header buffer */
3927 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL);
3928 if (!bus->hdrbuf)
3929 return false;
3930 /* Locate an appropriately-aligned portion of hdrbuf */
3931 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
3932 bus->head_align);
3933
3934 /* Set the poll and/or interrupt flags */
3935 bus->intr = true;
3936 bus->poll = false;
3937 if (bus->poll)
3938 bus->pollrate = 1;
3939
3940 return true;
3941
3942 fail:
3943 sdio_release_host(sdiodev->func[1]);
3944 return false;
3945 }
3946
3947 static int
3948 brcmf_sdio_watchdog_thread(void *data)
3949 {
3950 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3951 int wait;
3952
3953 allow_signal(SIGTERM);
3954 /* Run until signal received */
3955 brcmf_sdiod_freezer_count(bus->sdiodev);
3956 while (1) {
3957 if (kthread_should_stop())
3958 break;
3959 brcmf_sdiod_freezer_uncount(bus->sdiodev);
3960 wait = wait_for_completion_interruptible(&bus->watchdog_wait);
3961 brcmf_sdiod_freezer_count(bus->sdiodev);
3962 brcmf_sdiod_try_freeze(bus->sdiodev);
3963 if (!wait) {
3964 brcmf_sdio_bus_watchdog(bus);
3965 /* Count the tick for reference */
3966 bus->sdcnt.tickcnt++;
3967 reinit_completion(&bus->watchdog_wait);
3968 } else
3969 break;
3970 }
3971 return 0;
3972 }
3973
3974 static void
3975 brcmf_sdio_watchdog(struct timer_list *t)
3976 {
3977 struct brcmf_sdio *bus = from_timer(bus, t, timer);
3978
3979 if (bus->watchdog_tsk) {
3980 complete(&bus->watchdog_wait);
3981 /* Reschedule the watchdog */
3982 if (bus->wd_active)
3983 mod_timer(&bus->timer,
3984 jiffies + BRCMF_WD_POLL);
3985 }
3986 }
3987
3988 static int brcmf_sdio_get_fwname(struct device *dev, u32 chip, u32 chiprev,
3989 u8 *fw_name)
3990 {
3991 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3992 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3993 int ret = 0;
3994
3995 if (sdiodev->fw_name[0] != '\0')
3996 strlcpy(fw_name, sdiodev->fw_name, BRCMF_FW_NAME_LEN);
3997 else
3998 ret = brcmf_fw_map_chip_to_name(chip, chiprev,
3999 brcmf_sdio_fwnames,
4000 ARRAY_SIZE(brcmf_sdio_fwnames),
4001 fw_name, NULL);
4002
4003 return ret;
4004 }
4005
4006 static const struct brcmf_bus_ops brcmf_sdio_bus_ops = {
4007 .stop = brcmf_sdio_bus_stop,
4008 .preinit = brcmf_sdio_bus_preinit,
4009 .txdata = brcmf_sdio_bus_txdata,
4010 .txctl = brcmf_sdio_bus_txctl,
4011 .rxctl = brcmf_sdio_bus_rxctl,
4012 .gettxq = brcmf_sdio_bus_gettxq,
4013 .wowl_config = brcmf_sdio_wowl_config,
4014 .get_ramsize = brcmf_sdio_bus_get_ramsize,
4015 .get_memdump = brcmf_sdio_bus_get_memdump,
4016 .get_fwname = brcmf_sdio_get_fwname,
4017 };
4018
4019 static void brcmf_sdio_firmware_callback(struct device *dev, int err,
4020 const struct firmware *code,
4021 void *nvram, u32 nvram_len)
4022 {
4023 struct brcmf_bus *bus_if;
4024 struct brcmf_sdio_dev *sdiodev;
4025 struct brcmf_sdio *bus;
4026 u8 saveclk;
4027
4028 brcmf_dbg(TRACE, "Enter: dev=%s, err=%d\n", dev_name(dev), err);
4029 bus_if = dev_get_drvdata(dev);
4030 sdiodev = bus_if->bus_priv.sdio;
4031 if (err)
4032 goto fail;
4033
4034 if (!bus_if->drvr)
4035 return;
4036
4037 bus = sdiodev->bus;
4038
4039 /* try to download image and nvram to the dongle */
4040 bus->alp_only = true;
4041 err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len);
4042 if (err)
4043 goto fail;
4044 bus->alp_only = false;
4045
4046 /* Start the watchdog timer */
4047 bus->sdcnt.tickcnt = 0;
4048 brcmf_sdio_wd_timer(bus, true);
4049
4050 sdio_claim_host(sdiodev->func[1]);
4051
4052 /* Make sure backplane clock is on, needed to generate F2 interrupt */
4053 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4054 if (bus->clkstate != CLK_AVAIL)
4055 goto release;
4056
4057 /* Force clocks on backplane to be sure F2 interrupt propagates */
4058 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, &err);
4059 if (!err) {
4060 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
4061 (saveclk | SBSDIO_FORCE_HT), &err);
4062 }
4063 if (err) {
4064 brcmf_err("Failed to force clock for F2: err %d\n", err);
4065 goto release;
4066 }
4067
4068 /* Enable function 2 (frame transfers) */
4069 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
4070 offsetof(struct sdpcmd_regs, tosbmailboxdata));
4071 err = sdio_enable_func(sdiodev->func[SDIO_FUNC_2]);
4072
4073
4074 brcmf_dbg(INFO, "enable F2: err=%d\n", err);
4075
4076 /* If F2 successfully enabled, set core and enable interrupts */
4077 if (!err) {
4078 /* Set up the interrupt mask and enable interrupts */
4079 bus->hostintmask = HOSTINTMASK;
4080 w_sdreg32(bus, bus->hostintmask,
4081 offsetof(struct sdpcmd_regs, hostintmask));
4082
4083 brcmf_sdiod_regwb(sdiodev, SBSDIO_WATERMARK, 8, &err);
4084 } else {
4085 /* Disable F2 again */
4086 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
4087 goto release;
4088 }
4089
4090 if (brcmf_chip_sr_capable(bus->ci)) {
4091 brcmf_sdio_sr_init(bus);
4092 } else {
4093 /* Restore previous clock setting */
4094 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
4095 saveclk, &err);
4096 }
4097
4098 if (err == 0) {
4099 /* Allow full data communication using DPC from now on. */
4100 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
4101
4102 err = brcmf_sdiod_intr_register(sdiodev);
4103 if (err != 0)
4104 brcmf_err("intr register failed:%d\n", err);
4105 }
4106
4107 /* If we didn't come up, turn off backplane clock */
4108 if (err != 0)
4109 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4110
4111 sdio_release_host(sdiodev->func[1]);
4112
4113 err = brcmf_bus_started(dev);
4114 if (err != 0) {
4115 brcmf_err("dongle is not responding\n");
4116 goto fail;
4117 }
4118 return;
4119
4120 release:
4121 sdio_release_host(sdiodev->func[1]);
4122 fail:
4123 brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err);
4124 device_release_driver(&sdiodev->func[2]->dev);
4125 device_release_driver(dev);
4126 }
4127
4128 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
4129 {
4130 int ret;
4131 struct brcmf_sdio *bus;
4132 struct workqueue_struct *wq;
4133
4134 brcmf_dbg(TRACE, "Enter\n");
4135
4136 /* Allocate private bus interface state */
4137 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
4138 if (!bus)
4139 goto fail;
4140
4141 bus->sdiodev = sdiodev;
4142 sdiodev->bus = bus;
4143 skb_queue_head_init(&bus->glom);
4144 bus->txbound = BRCMF_TXBOUND;
4145 bus->rxbound = BRCMF_RXBOUND;
4146 bus->txminmax = BRCMF_TXMINMAX;
4147 bus->tx_seq = SDPCM_SEQ_WRAP - 1;
4148
4149 /* single-threaded workqueue */
4150 wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM,
4151 dev_name(&sdiodev->func[1]->dev));
4152 if (!wq) {
4153 brcmf_err("insufficient memory to create txworkqueue\n");
4154 goto fail;
4155 }
4156 brcmf_sdiod_freezer_count(sdiodev);
4157 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
4158 bus->brcmf_wq = wq;
4159
4160 /* attempt to attach to the dongle */
4161 if (!(brcmf_sdio_probe_attach(bus))) {
4162 brcmf_err("brcmf_sdio_probe_attach failed\n");
4163 goto fail;
4164 }
4165
4166 spin_lock_init(&bus->rxctl_lock);
4167 spin_lock_init(&bus->txq_lock);
4168 init_waitqueue_head(&bus->ctrl_wait);
4169 init_waitqueue_head(&bus->dcmd_resp_wait);
4170
4171 /* Set up the watchdog timer */
4172 timer_setup(&bus->timer, brcmf_sdio_watchdog, 0);
4173 /* Initialize watchdog thread */
4174 init_completion(&bus->watchdog_wait);
4175 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread,
4176 bus, "brcmf_wdog/%s",
4177 dev_name(&sdiodev->func[1]->dev));
4178 if (IS_ERR(bus->watchdog_tsk)) {
4179 pr_warn("brcmf_watchdog thread failed to start\n");
4180 bus->watchdog_tsk = NULL;
4181 }
4182 /* Initialize DPC thread */
4183 bus->dpc_triggered = false;
4184 bus->dpc_running = false;
4185
4186 /* Assign bus interface call back */
4187 bus->sdiodev->bus_if->dev = bus->sdiodev->dev;
4188 bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops;
4189 bus->sdiodev->bus_if->chip = bus->ci->chip;
4190 bus->sdiodev->bus_if->chiprev = bus->ci->chiprev;
4191
4192 /* default sdio bus header length for tx packet */
4193 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
4194
4195 /* Attach to the common layer, reserve hdr space */
4196 ret = brcmf_attach(bus->sdiodev->dev, bus->sdiodev->settings);
4197 if (ret != 0) {
4198 brcmf_err("brcmf_attach failed\n");
4199 goto fail;
4200 }
4201
4202 /* Query the F2 block size, set roundup accordingly */
4203 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
4204 bus->roundup = min(max_roundup, bus->blocksize);
4205
4206 /* Allocate buffers */
4207 if (bus->sdiodev->bus_if->maxctl) {
4208 bus->sdiodev->bus_if->maxctl += bus->roundup;
4209 bus->rxblen =
4210 roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
4211 ALIGNMENT) + bus->head_align;
4212 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
4213 if (!(bus->rxbuf)) {
4214 brcmf_err("rxbuf allocation failed\n");
4215 goto fail;
4216 }
4217 }
4218
4219 sdio_claim_host(bus->sdiodev->func[1]);
4220
4221 /* Disable F2 to clear any intermediate frame state on the dongle */
4222 sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]);
4223
4224 bus->rxflow = false;
4225
4226 /* Done with backplane-dependent accesses, can drop clock... */
4227 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4228
4229 sdio_release_host(bus->sdiodev->func[1]);
4230
4231 /* ...and initialize clock/power states */
4232 bus->clkstate = CLK_SDONLY;
4233 bus->idletime = BRCMF_IDLE_INTERVAL;
4234 bus->idleclock = BRCMF_IDLE_ACTIVE;
4235
4236 /* SR state */
4237 bus->sr_enabled = false;
4238
4239 brcmf_sdio_debugfs_create(bus);
4240 brcmf_dbg(INFO, "completed!!\n");
4241
4242 ret = brcmf_fw_map_chip_to_name(bus->ci->chip, bus->ci->chiprev,
4243 brcmf_sdio_fwnames,
4244 ARRAY_SIZE(brcmf_sdio_fwnames),
4245 sdiodev->fw_name, sdiodev->nvram_name);
4246 if (ret)
4247 goto fail;
4248
4249 ret = brcmf_fw_get_firmwares(sdiodev->dev, BRCMF_FW_REQUEST_NVRAM,
4250 sdiodev->fw_name, sdiodev->nvram_name,
4251 brcmf_sdio_firmware_callback);
4252 if (ret != 0) {
4253 brcmf_err("async firmware request failed: %d\n", ret);
4254 goto fail;
4255 }
4256
4257 return bus;
4258
4259 fail:
4260 brcmf_sdio_remove(bus);
4261 return NULL;
4262 }
4263
4264 /* Detach and free everything */
4265 void brcmf_sdio_remove(struct brcmf_sdio *bus)
4266 {
4267 brcmf_dbg(TRACE, "Enter\n");
4268
4269 if (bus) {
4270 /* De-register interrupt handler */
4271 brcmf_sdiod_intr_unregister(bus->sdiodev);
4272
4273 brcmf_detach(bus->sdiodev->dev);
4274
4275 cancel_work_sync(&bus->datawork);
4276 if (bus->brcmf_wq)
4277 destroy_workqueue(bus->brcmf_wq);
4278
4279 if (bus->ci) {
4280 if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
4281 sdio_claim_host(bus->sdiodev->func[1]);
4282 brcmf_sdio_wd_timer(bus, false);
4283 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4284 /* Leave the device in state where it is
4285 * 'passive'. This is done by resetting all
4286 * necessary cores.
4287 */
4288 msleep(20);
4289 brcmf_chip_set_passive(bus->ci);
4290 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4291 sdio_release_host(bus->sdiodev->func[1]);
4292 }
4293 brcmf_chip_detach(bus->ci);
4294 }
4295 if (bus->sdiodev->settings)
4296 brcmf_release_module_param(bus->sdiodev->settings);
4297
4298 kfree(bus->rxbuf);
4299 kfree(bus->hdrbuf);
4300 kfree(bus);
4301 }
4302
4303 brcmf_dbg(TRACE, "Disconnected\n");
4304 }
4305
4306 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active)
4307 {
4308 /* Totally stop the timer */
4309 if (!active && bus->wd_active) {
4310 del_timer_sync(&bus->timer);
4311 bus->wd_active = false;
4312 return;
4313 }
4314
4315 /* don't start the wd until fw is loaded */
4316 if (bus->sdiodev->state != BRCMF_SDIOD_DATA)
4317 return;
4318
4319 if (active) {
4320 if (!bus->wd_active) {
4321 /* Create timer again when watchdog period is
4322 dynamically changed or in the first instance
4323 */
4324 bus->timer.expires = jiffies + BRCMF_WD_POLL;
4325 add_timer(&bus->timer);
4326 bus->wd_active = true;
4327 } else {
4328 /* Re arm the timer, at last watchdog period */
4329 mod_timer(&bus->timer, jiffies + BRCMF_WD_POLL);
4330 }
4331 }
4332 }
4333
4334 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep)
4335 {
4336 int ret;
4337
4338 sdio_claim_host(bus->sdiodev->func[1]);
4339 ret = brcmf_sdio_bus_sleep(bus, sleep, false);
4340 sdio_release_host(bus->sdiodev->func[1]);
4341
4342 return ret;
4343 }
4344
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