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brcm: adds support for BCM43341 wifi
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / broadcom / brcm80211 / brcmfmac / sdio.c
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/types.h>
18 #include <linux/atomic.h>
19 #include <linux/kernel.h>
20 #include <linux/kthread.h>
21 #include <linux/printk.h>
22 #include <linux/pci_ids.h>
23 #include <linux/netdevice.h>
24 #include <linux/interrupt.h>
25 #include <linux/sched.h>
26 #include <linux/mmc/sdio.h>
27 #include <linux/mmc/sdio_ids.h>
28 #include <linux/mmc/sdio_func.h>
29 #include <linux/mmc/card.h>
30 #include <linux/semaphore.h>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
33 #include <linux/bcma/bcma.h>
34 #include <linux/debugfs.h>
35 #include <linux/vmalloc.h>
36 #include <asm/unaligned.h>
37 #include <defs.h>
38 #include <brcmu_wifi.h>
39 #include <brcmu_utils.h>
40 #include <brcm_hw_ids.h>
41 #include <soc.h>
42 #include "sdio.h"
43 #include "chip.h"
44 #include "firmware.h"
45 #include "core.h"
46 #include "common.h"
47
48 #define DCMD_RESP_TIMEOUT msecs_to_jiffies(2500)
49 #define CTL_DONE_TIMEOUT msecs_to_jiffies(2500)
50
51 #ifdef DEBUG
52
53 #define BRCMF_TRAP_INFO_SIZE 80
54
55 #define CBUF_LEN (128)
56
57 /* Device console log buffer state */
58 #define CONSOLE_BUFFER_MAX 2024
59
60 struct rte_log_le {
61 __le32 buf; /* Can't be pointer on (64-bit) hosts */
62 __le32 buf_size;
63 __le32 idx;
64 char *_buf_compat; /* Redundant pointer for backward compat. */
65 };
66
67 struct rte_console {
68 /* Virtual UART
69 * When there is no UART (e.g. Quickturn),
70 * the host should write a complete
71 * input line directly into cbuf and then write
72 * the length into vcons_in.
73 * This may also be used when there is a real UART
74 * (at risk of conflicting with
75 * the real UART). vcons_out is currently unused.
76 */
77 uint vcons_in;
78 uint vcons_out;
79
80 /* Output (logging) buffer
81 * Console output is written to a ring buffer log_buf at index log_idx.
82 * The host may read the output when it sees log_idx advance.
83 * Output will be lost if the output wraps around faster than the host
84 * polls.
85 */
86 struct rte_log_le log_le;
87
88 /* Console input line buffer
89 * Characters are read one at a time into cbuf
90 * until <CR> is received, then
91 * the buffer is processed as a command line.
92 * Also used for virtual UART.
93 */
94 uint cbuf_idx;
95 char cbuf[CBUF_LEN];
96 };
97
98 #endif /* DEBUG */
99 #include <chipcommon.h>
100
101 #include "bus.h"
102 #include "debug.h"
103 #include "tracepoint.h"
104
105 #define TXQLEN 2048 /* bulk tx queue length */
106 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
107 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
108 #define PRIOMASK 7
109
110 #define TXRETRIES 2 /* # of retries for tx frames */
111
112 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
113 one scheduling */
114
115 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
116 one scheduling */
117
118 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
119
120 #define MEMBLOCK 2048 /* Block size used for downloading
121 of dongle image */
122 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
123 biggest possible glom */
124
125 #define BRCMF_FIRSTREAD (1 << 6)
126
127 #define BRCMF_CONSOLE 10 /* watchdog interval to poll console */
128
129 /* SBSDIO_DEVICE_CTL */
130
131 /* 1: device will assert busy signal when receiving CMD53 */
132 #define SBSDIO_DEVCTL_SETBUSY 0x01
133 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
134 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
135 /* 1: mask all interrupts to host except the chipActive (rev 8) */
136 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
137 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
138 * sdio bus power cycle to clear (rev 9) */
139 #define SBSDIO_DEVCTL_PADS_ISO 0x08
140 /* Force SD->SB reset mapping (rev 11) */
141 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
142 /* Determined by CoreControl bit */
143 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
144 /* Force backplane reset */
145 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
146 /* Force no backplane reset */
147 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
148
149 /* direct(mapped) cis space */
150
151 /* MAPPED common CIS address */
152 #define SBSDIO_CIS_BASE_COMMON 0x1000
153 /* maximum bytes in one CIS */
154 #define SBSDIO_CIS_SIZE_LIMIT 0x200
155 /* cis offset addr is < 17 bits */
156 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
157
158 /* manfid tuple length, include tuple, link bytes */
159 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
160
161 #define CORE_BUS_REG(base, field) \
162 (base + offsetof(struct sdpcmd_regs, field))
163
164 /* SDIO function 1 register CHIPCLKCSR */
165 /* Force ALP request to backplane */
166 #define SBSDIO_FORCE_ALP 0x01
167 /* Force HT request to backplane */
168 #define SBSDIO_FORCE_HT 0x02
169 /* Force ILP request to backplane */
170 #define SBSDIO_FORCE_ILP 0x04
171 /* Make ALP ready (power up xtal) */
172 #define SBSDIO_ALP_AVAIL_REQ 0x08
173 /* Make HT ready (power up PLL) */
174 #define SBSDIO_HT_AVAIL_REQ 0x10
175 /* Squelch clock requests from HW */
176 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
177 /* Status: ALP is ready */
178 #define SBSDIO_ALP_AVAIL 0x40
179 /* Status: HT is ready */
180 #define SBSDIO_HT_AVAIL 0x80
181 #define SBSDIO_CSR_MASK 0x1F
182 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
183 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
184 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
185 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
186 #define SBSDIO_CLKAV(regval, alponly) \
187 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
188
189 /* intstatus */
190 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
191 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
192 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
193 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
194 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
195 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
196 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
197 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
198 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
199 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
200 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
201 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
202 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
203 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
204 #define I_PC (1 << 10) /* descriptor error */
205 #define I_PD (1 << 11) /* data error */
206 #define I_DE (1 << 12) /* Descriptor protocol Error */
207 #define I_RU (1 << 13) /* Receive descriptor Underflow */
208 #define I_RO (1 << 14) /* Receive fifo Overflow */
209 #define I_XU (1 << 15) /* Transmit fifo Underflow */
210 #define I_RI (1 << 16) /* Receive Interrupt */
211 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
212 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
213 #define I_XI (1 << 24) /* Transmit Interrupt */
214 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
215 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
216 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
217 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
218 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
219 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
220 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
221 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
222 #define I_DMA (I_RI | I_XI | I_ERRORS)
223
224 /* corecontrol */
225 #define CC_CISRDY (1 << 0) /* CIS Ready */
226 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
227 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
228 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
229 #define CC_XMTDATAAVAIL_MODE (1 << 4)
230 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
231
232 /* SDA_FRAMECTRL */
233 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
234 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
235 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
236 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
237
238 /*
239 * Software allocation of To SB Mailbox resources
240 */
241
242 /* tosbmailbox bits corresponding to intstatus bits */
243 #define SMB_NAK (1 << 0) /* Frame NAK */
244 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
245 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
246 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
247
248 /* tosbmailboxdata */
249 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
250
251 /*
252 * Software allocation of To Host Mailbox resources
253 */
254
255 /* intstatus bits */
256 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
257 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
258 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
259 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
260
261 /* tohostmailboxdata */
262 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
263 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
264 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
265 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
266
267 #define HMB_DATA_FCDATA_MASK 0xff000000
268 #define HMB_DATA_FCDATA_SHIFT 24
269
270 #define HMB_DATA_VERSION_MASK 0x00ff0000
271 #define HMB_DATA_VERSION_SHIFT 16
272
273 /*
274 * Software-defined protocol header
275 */
276
277 /* Current protocol version */
278 #define SDPCM_PROT_VERSION 4
279
280 /*
281 * Shared structure between dongle and the host.
282 * The structure contains pointers to trap or assert information.
283 */
284 #define SDPCM_SHARED_VERSION 0x0003
285 #define SDPCM_SHARED_VERSION_MASK 0x00FF
286 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
287 #define SDPCM_SHARED_ASSERT 0x0200
288 #define SDPCM_SHARED_TRAP 0x0400
289
290 /* Space for header read, limit for data packets */
291 #define MAX_HDR_READ (1 << 6)
292 #define MAX_RX_DATASZ 2048
293
294 /* Bump up limit on waiting for HT to account for first startup;
295 * if the image is doing a CRC calculation before programming the PMU
296 * for HT availability, it could take a couple hundred ms more, so
297 * max out at a 1 second (1000000us).
298 */
299 #undef PMU_MAX_TRANSITION_DLY
300 #define PMU_MAX_TRANSITION_DLY 1000000
301
302 /* Value for ChipClockCSR during initial setup */
303 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
304 SBSDIO_ALP_AVAIL_REQ)
305
306 /* Flags for SDH calls */
307 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
308
309 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
310 * when idle
311 */
312 #define BRCMF_IDLE_INTERVAL 1
313
314 #define KSO_WAIT_US 50
315 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
316 #define BRCMF_SDIO_MAX_ACCESS_ERRORS 5
317
318 /*
319 * Conversion of 802.1D priority to precedence level
320 */
321 static uint prio2prec(u32 prio)
322 {
323 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
324 (prio^2) : prio;
325 }
326
327 #ifdef DEBUG
328 /* Device console log buffer state */
329 struct brcmf_console {
330 uint count; /* Poll interval msec counter */
331 uint log_addr; /* Log struct address (fixed) */
332 struct rte_log_le log_le; /* Log struct (host copy) */
333 uint bufsize; /* Size of log buffer */
334 u8 *buf; /* Log buffer (host copy) */
335 uint last; /* Last buffer read index */
336 };
337
338 struct brcmf_trap_info {
339 __le32 type;
340 __le32 epc;
341 __le32 cpsr;
342 __le32 spsr;
343 __le32 r0; /* a1 */
344 __le32 r1; /* a2 */
345 __le32 r2; /* a3 */
346 __le32 r3; /* a4 */
347 __le32 r4; /* v1 */
348 __le32 r5; /* v2 */
349 __le32 r6; /* v3 */
350 __le32 r7; /* v4 */
351 __le32 r8; /* v5 */
352 __le32 r9; /* sb/v6 */
353 __le32 r10; /* sl/v7 */
354 __le32 r11; /* fp/v8 */
355 __le32 r12; /* ip */
356 __le32 r13; /* sp */
357 __le32 r14; /* lr */
358 __le32 pc; /* r15 */
359 };
360 #endif /* DEBUG */
361
362 struct sdpcm_shared {
363 u32 flags;
364 u32 trap_addr;
365 u32 assert_exp_addr;
366 u32 assert_file_addr;
367 u32 assert_line;
368 u32 console_addr; /* Address of struct rte_console */
369 u32 msgtrace_addr;
370 u8 tag[32];
371 u32 brpt_addr;
372 };
373
374 struct sdpcm_shared_le {
375 __le32 flags;
376 __le32 trap_addr;
377 __le32 assert_exp_addr;
378 __le32 assert_file_addr;
379 __le32 assert_line;
380 __le32 console_addr; /* Address of struct rte_console */
381 __le32 msgtrace_addr;
382 u8 tag[32];
383 __le32 brpt_addr;
384 };
385
386 /* dongle SDIO bus specific header info */
387 struct brcmf_sdio_hdrinfo {
388 u8 seq_num;
389 u8 channel;
390 u16 len;
391 u16 len_left;
392 u16 len_nxtfrm;
393 u8 dat_offset;
394 bool lastfrm;
395 u16 tail_pad;
396 };
397
398 /*
399 * hold counter variables
400 */
401 struct brcmf_sdio_count {
402 uint intrcount; /* Count of device interrupt callbacks */
403 uint lastintrs; /* Count as of last watchdog timer */
404 uint pollcnt; /* Count of active polls */
405 uint regfails; /* Count of R_REG failures */
406 uint tx_sderrs; /* Count of tx attempts with sd errors */
407 uint fcqueued; /* Tx packets that got queued */
408 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
409 uint rx_toolong; /* Receive frames too long to receive */
410 uint rxc_errors; /* SDIO errors when reading control frames */
411 uint rx_hdrfail; /* SDIO errors on header reads */
412 uint rx_badhdr; /* Bad received headers (roosync?) */
413 uint rx_badseq; /* Mismatched rx sequence number */
414 uint fc_rcvd; /* Number of flow-control events received */
415 uint fc_xoff; /* Number which turned on flow-control */
416 uint fc_xon; /* Number which turned off flow-control */
417 uint rxglomfail; /* Failed deglom attempts */
418 uint rxglomframes; /* Number of glom frames (superframes) */
419 uint rxglompkts; /* Number of packets from glom frames */
420 uint f2rxhdrs; /* Number of header reads */
421 uint f2rxdata; /* Number of frame data reads */
422 uint f2txdata; /* Number of f2 frame writes */
423 uint f1regdata; /* Number of f1 register accesses */
424 uint tickcnt; /* Number of watchdog been schedule */
425 ulong tx_ctlerrs; /* Err of sending ctrl frames */
426 ulong tx_ctlpkts; /* Ctrl frames sent to dongle */
427 ulong rx_ctlerrs; /* Err of processing rx ctrl frames */
428 ulong rx_ctlpkts; /* Ctrl frames processed from dongle */
429 ulong rx_readahead_cnt; /* packets where header read-ahead was used */
430 };
431
432 /* misc chip info needed by some of the routines */
433 /* Private data for SDIO bus interaction */
434 struct brcmf_sdio {
435 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
436 struct brcmf_chip *ci; /* Chip info struct */
437
438 u32 hostintmask; /* Copy of Host Interrupt Mask */
439 atomic_t intstatus; /* Intstatus bits (events) pending */
440 atomic_t fcstate; /* State of dongle flow-control */
441
442 uint blocksize; /* Block size of SDIO transfers */
443 uint roundup; /* Max roundup limit */
444
445 struct pktq txq; /* Queue length used for flow-control */
446 u8 flowcontrol; /* per prio flow control bitmask */
447 u8 tx_seq; /* Transmit sequence number (next) */
448 u8 tx_max; /* Maximum transmit sequence allowed */
449
450 u8 *hdrbuf; /* buffer for handling rx frame */
451 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
452 u8 rx_seq; /* Receive sequence number (expected) */
453 struct brcmf_sdio_hdrinfo cur_read;
454 /* info of current read frame */
455 bool rxskip; /* Skip receive (awaiting NAK ACK) */
456 bool rxpending; /* Data frame pending in dongle */
457
458 uint rxbound; /* Rx frames to read before resched */
459 uint txbound; /* Tx frames to send before resched */
460 uint txminmax;
461
462 struct sk_buff *glomd; /* Packet containing glomming descriptor */
463 struct sk_buff_head glom; /* Packet list for glommed superframe */
464
465 u8 *rxbuf; /* Buffer for receiving control packets */
466 uint rxblen; /* Allocated length of rxbuf */
467 u8 *rxctl; /* Aligned pointer into rxbuf */
468 u8 *rxctl_orig; /* pointer for freeing rxctl */
469 uint rxlen; /* Length of valid data in buffer */
470 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */
471
472 u8 sdpcm_ver; /* Bus protocol reported by dongle */
473
474 bool intr; /* Use interrupts */
475 bool poll; /* Use polling */
476 atomic_t ipend; /* Device interrupt is pending */
477 uint spurious; /* Count of spurious interrupts */
478 uint pollrate; /* Ticks between device polls */
479 uint polltick; /* Tick counter */
480
481 #ifdef DEBUG
482 uint console_interval;
483 struct brcmf_console console; /* Console output polling support */
484 uint console_addr; /* Console address from shared struct */
485 #endif /* DEBUG */
486
487 uint clkstate; /* State of sd and backplane clock(s) */
488 s32 idletime; /* Control for activity timeout */
489 s32 idlecount; /* Activity timeout counter */
490 s32 idleclock; /* How to set bus driver when idle */
491 bool rxflow_mode; /* Rx flow control mode */
492 bool rxflow; /* Is rx flow control on */
493 bool alp_only; /* Don't use HT clock (ALP only) */
494
495 u8 *ctrl_frame_buf;
496 u16 ctrl_frame_len;
497 bool ctrl_frame_stat;
498 int ctrl_frame_err;
499
500 spinlock_t txq_lock; /* protect bus->txq */
501 wait_queue_head_t ctrl_wait;
502 wait_queue_head_t dcmd_resp_wait;
503
504 struct timer_list timer;
505 struct completion watchdog_wait;
506 struct task_struct *watchdog_tsk;
507 bool wd_active;
508
509 struct workqueue_struct *brcmf_wq;
510 struct work_struct datawork;
511 bool dpc_triggered;
512 bool dpc_running;
513
514 bool txoff; /* Transmit flow-controlled */
515 struct brcmf_sdio_count sdcnt;
516 bool sr_enabled; /* SaveRestore enabled */
517 bool sleeping;
518
519 u8 tx_hdrlen; /* sdio bus header length for tx packet */
520 bool txglom; /* host tx glomming enable flag */
521 u16 head_align; /* buffer pointer alignment */
522 u16 sgentry_align; /* scatter-gather buffer alignment */
523 };
524
525 /* clkstate */
526 #define CLK_NONE 0
527 #define CLK_SDONLY 1
528 #define CLK_PENDING 2
529 #define CLK_AVAIL 3
530
531 #ifdef DEBUG
532 static int qcount[NUMPRIO];
533 #endif /* DEBUG */
534
535 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
536
537 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
538
539 /* Limit on rounding up frames */
540 static const uint max_roundup = 512;
541
542 #define ALIGNMENT 4
543
544 enum brcmf_sdio_frmtype {
545 BRCMF_SDIO_FT_NORMAL,
546 BRCMF_SDIO_FT_SUPER,
547 BRCMF_SDIO_FT_SUB,
548 };
549
550 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
551
552 /* SDIO Pad drive strength to select value mappings */
553 struct sdiod_drive_str {
554 u8 strength; /* Pad Drive Strength in mA */
555 u8 sel; /* Chip-specific select value */
556 };
557
558 /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */
559 static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
560 {32, 0x6},
561 {26, 0x7},
562 {22, 0x4},
563 {16, 0x5},
564 {12, 0x2},
565 {8, 0x3},
566 {4, 0x0},
567 {0, 0x1}
568 };
569
570 /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
571 static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
572 {6, 0x7},
573 {5, 0x6},
574 {4, 0x5},
575 {3, 0x4},
576 {2, 0x2},
577 {1, 0x1},
578 {0, 0x0}
579 };
580
581 /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
582 static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
583 {3, 0x3},
584 {2, 0x2},
585 {1, 0x1},
586 {0, 0x0} };
587
588 /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
589 static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
590 {16, 0x7},
591 {12, 0x5},
592 {8, 0x3},
593 {4, 0x1}
594 };
595
596 BRCMF_FW_NVRAM_DEF(43143, "brcmfmac43143-sdio.bin", "brcmfmac43143-sdio.txt");
597 BRCMF_FW_NVRAM_DEF(43241B0, "brcmfmac43241b0-sdio.bin",
598 "brcmfmac43241b0-sdio.txt");
599 BRCMF_FW_NVRAM_DEF(43241B4, "brcmfmac43241b4-sdio.bin",
600 "brcmfmac43241b4-sdio.txt");
601 BRCMF_FW_NVRAM_DEF(43241B5, "brcmfmac43241b5-sdio.bin",
602 "brcmfmac43241b5-sdio.txt");
603 BRCMF_FW_NVRAM_DEF(4329, "brcmfmac4329-sdio.bin", "brcmfmac4329-sdio.txt");
604 BRCMF_FW_NVRAM_DEF(4330, "brcmfmac4330-sdio.bin", "brcmfmac4330-sdio.txt");
605 BRCMF_FW_NVRAM_DEF(4334, "brcmfmac4334-sdio.bin", "brcmfmac4334-sdio.txt");
606 BRCMF_FW_NVRAM_DEF(43340, "brcmfmac43340-sdio.bin", "brcmfmac43340-sdio.txt");
607 BRCMF_FW_NVRAM_DEF(43341, "brcmfmac43341-sdio.bin", "brcmfmac43341-sdio.txt");
608 BRCMF_FW_NVRAM_DEF(4335, "brcmfmac4335-sdio.bin", "brcmfmac4335-sdio.txt");
609 BRCMF_FW_NVRAM_DEF(43362, "brcmfmac43362-sdio.bin", "brcmfmac43362-sdio.txt");
610 BRCMF_FW_NVRAM_DEF(4339, "brcmfmac4339-sdio.bin", "brcmfmac4339-sdio.txt");
611 BRCMF_FW_NVRAM_DEF(43430, "brcmfmac43430-sdio.bin", "brcmfmac43430-sdio.txt");
612 BRCMF_FW_NVRAM_DEF(43455, "brcmfmac43455-sdio.bin", "brcmfmac43455-sdio.txt");
613 BRCMF_FW_NVRAM_DEF(4354, "brcmfmac4354-sdio.bin", "brcmfmac4354-sdio.txt");
614 BRCMF_FW_NVRAM_DEF(4356, "brcmfmac4356-sdio.bin", "brcmfmac4356-sdio.txt");
615
616 static struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
617 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143),
618 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0),
619 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4),
620 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, 43241B5),
621 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, 4329),
622 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, 4330),
623 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334),
624 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340),
625 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43341_CHIP_ID, 0xFFFFFFFF, 43341),
626 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335),
627 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362),
628 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339),
629 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFF, 43430),
630 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFFC0, 43455),
631 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354),
632 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356)
633 };
634
635 static void pkt_align(struct sk_buff *p, int len, int align)
636 {
637 uint datalign;
638 datalign = (unsigned long)(p->data);
639 datalign = roundup(datalign, (align)) - datalign;
640 if (datalign)
641 skb_pull(p, datalign);
642 __skb_trim(p, len);
643 }
644
645 /* To check if there's window offered */
646 static bool data_ok(struct brcmf_sdio *bus)
647 {
648 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
649 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
650 }
651
652 /*
653 * Reads a register in the SDIO hardware block. This block occupies a series of
654 * adresses on the 32 bit backplane bus.
655 */
656 static int r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset)
657 {
658 struct brcmf_core *core;
659 int ret;
660
661 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
662 *regvar = brcmf_sdiod_regrl(bus->sdiodev, core->base + offset, &ret);
663
664 return ret;
665 }
666
667 static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset)
668 {
669 struct brcmf_core *core;
670 int ret;
671
672 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
673 brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret);
674
675 return ret;
676 }
677
678 static int
679 brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
680 {
681 u8 wr_val = 0, rd_val, cmp_val, bmask;
682 int err = 0;
683 int err_cnt = 0;
684 int try_cnt = 0;
685
686 brcmf_dbg(TRACE, "Enter: on=%d\n", on);
687
688 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
689 /* 1st KSO write goes to AOS wake up core if device is asleep */
690 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
691 wr_val, &err);
692
693 if (on) {
694 /* device WAKEUP through KSO:
695 * write bit 0 & read back until
696 * both bits 0 (kso bit) & 1 (dev on status) are set
697 */
698 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
699 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
700 bmask = cmp_val;
701 usleep_range(2000, 3000);
702 } else {
703 /* Put device to sleep, turn off KSO */
704 cmp_val = 0;
705 /* only check for bit0, bit1(dev on status) may not
706 * get cleared right away
707 */
708 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
709 }
710
711 do {
712 /* reliable KSO bit set/clr:
713 * the sdiod sleep write access is synced to PMU 32khz clk
714 * just one write attempt may fail,
715 * read it back until it matches written value
716 */
717 rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
718 &err);
719 if (!err) {
720 if ((rd_val & bmask) == cmp_val)
721 break;
722 err_cnt = 0;
723 }
724 /* bail out upon subsequent access errors */
725 if (err && (err_cnt++ > BRCMF_SDIO_MAX_ACCESS_ERRORS))
726 break;
727 udelay(KSO_WAIT_US);
728 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
729 wr_val, &err);
730 } while (try_cnt++ < MAX_KSO_ATTEMPTS);
731
732 if (try_cnt > 2)
733 brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt,
734 rd_val, err);
735
736 if (try_cnt > MAX_KSO_ATTEMPTS)
737 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err);
738
739 return err;
740 }
741
742 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
743
744 /* Turn backplane clock on or off */
745 static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
746 {
747 int err;
748 u8 clkctl, clkreq, devctl;
749 unsigned long timeout;
750
751 brcmf_dbg(SDIO, "Enter\n");
752
753 clkctl = 0;
754
755 if (bus->sr_enabled) {
756 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
757 return 0;
758 }
759
760 if (on) {
761 /* Request HT Avail */
762 clkreq =
763 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
764
765 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
766 clkreq, &err);
767 if (err) {
768 brcmf_err("HT Avail request error: %d\n", err);
769 return -EBADE;
770 }
771
772 /* Check current status */
773 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
774 SBSDIO_FUNC1_CHIPCLKCSR, &err);
775 if (err) {
776 brcmf_err("HT Avail read error: %d\n", err);
777 return -EBADE;
778 }
779
780 /* Go to pending and await interrupt if appropriate */
781 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
782 /* Allow only clock-available interrupt */
783 devctl = brcmf_sdiod_regrb(bus->sdiodev,
784 SBSDIO_DEVICE_CTL, &err);
785 if (err) {
786 brcmf_err("Devctl error setting CA: %d\n",
787 err);
788 return -EBADE;
789 }
790
791 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
792 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
793 devctl, &err);
794 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
795 bus->clkstate = CLK_PENDING;
796
797 return 0;
798 } else if (bus->clkstate == CLK_PENDING) {
799 /* Cancel CA-only interrupt filter */
800 devctl = brcmf_sdiod_regrb(bus->sdiodev,
801 SBSDIO_DEVICE_CTL, &err);
802 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
803 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
804 devctl, &err);
805 }
806
807 /* Otherwise, wait here (polling) for HT Avail */
808 timeout = jiffies +
809 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
810 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
811 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
812 SBSDIO_FUNC1_CHIPCLKCSR,
813 &err);
814 if (time_after(jiffies, timeout))
815 break;
816 else
817 usleep_range(5000, 10000);
818 }
819 if (err) {
820 brcmf_err("HT Avail request error: %d\n", err);
821 return -EBADE;
822 }
823 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
824 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
825 PMU_MAX_TRANSITION_DLY, clkctl);
826 return -EBADE;
827 }
828
829 /* Mark clock available */
830 bus->clkstate = CLK_AVAIL;
831 brcmf_dbg(SDIO, "CLKCTL: turned ON\n");
832
833 #if defined(DEBUG)
834 if (!bus->alp_only) {
835 if (SBSDIO_ALPONLY(clkctl))
836 brcmf_err("HT Clock should be on\n");
837 }
838 #endif /* defined (DEBUG) */
839
840 } else {
841 clkreq = 0;
842
843 if (bus->clkstate == CLK_PENDING) {
844 /* Cancel CA-only interrupt filter */
845 devctl = brcmf_sdiod_regrb(bus->sdiodev,
846 SBSDIO_DEVICE_CTL, &err);
847 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
848 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
849 devctl, &err);
850 }
851
852 bus->clkstate = CLK_SDONLY;
853 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
854 clkreq, &err);
855 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
856 if (err) {
857 brcmf_err("Failed access turning clock off: %d\n",
858 err);
859 return -EBADE;
860 }
861 }
862 return 0;
863 }
864
865 /* Change idle/active SD state */
866 static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on)
867 {
868 brcmf_dbg(SDIO, "Enter\n");
869
870 if (on)
871 bus->clkstate = CLK_SDONLY;
872 else
873 bus->clkstate = CLK_NONE;
874
875 return 0;
876 }
877
878 /* Transition SD and backplane clock readiness */
879 static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
880 {
881 #ifdef DEBUG
882 uint oldstate = bus->clkstate;
883 #endif /* DEBUG */
884
885 brcmf_dbg(SDIO, "Enter\n");
886
887 /* Early exit if we're already there */
888 if (bus->clkstate == target)
889 return 0;
890
891 switch (target) {
892 case CLK_AVAIL:
893 /* Make sure SD clock is available */
894 if (bus->clkstate == CLK_NONE)
895 brcmf_sdio_sdclk(bus, true);
896 /* Now request HT Avail on the backplane */
897 brcmf_sdio_htclk(bus, true, pendok);
898 break;
899
900 case CLK_SDONLY:
901 /* Remove HT request, or bring up SD clock */
902 if (bus->clkstate == CLK_NONE)
903 brcmf_sdio_sdclk(bus, true);
904 else if (bus->clkstate == CLK_AVAIL)
905 brcmf_sdio_htclk(bus, false, false);
906 else
907 brcmf_err("request for %d -> %d\n",
908 bus->clkstate, target);
909 break;
910
911 case CLK_NONE:
912 /* Make sure to remove HT request */
913 if (bus->clkstate == CLK_AVAIL)
914 brcmf_sdio_htclk(bus, false, false);
915 /* Now remove the SD clock */
916 brcmf_sdio_sdclk(bus, false);
917 break;
918 }
919 #ifdef DEBUG
920 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate);
921 #endif /* DEBUG */
922
923 return 0;
924 }
925
926 static int
927 brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
928 {
929 int err = 0;
930 u8 clkcsr;
931
932 brcmf_dbg(SDIO, "Enter: request %s currently %s\n",
933 (sleep ? "SLEEP" : "WAKE"),
934 (bus->sleeping ? "SLEEP" : "WAKE"));
935
936 /* If SR is enabled control bus state with KSO */
937 if (bus->sr_enabled) {
938 /* Done if we're already in the requested state */
939 if (sleep == bus->sleeping)
940 goto end;
941
942 /* Going to sleep */
943 if (sleep) {
944 clkcsr = brcmf_sdiod_regrb(bus->sdiodev,
945 SBSDIO_FUNC1_CHIPCLKCSR,
946 &err);
947 if ((clkcsr & SBSDIO_CSR_MASK) == 0) {
948 brcmf_dbg(SDIO, "no clock, set ALP\n");
949 brcmf_sdiod_regwb(bus->sdiodev,
950 SBSDIO_FUNC1_CHIPCLKCSR,
951 SBSDIO_ALP_AVAIL_REQ, &err);
952 }
953 err = brcmf_sdio_kso_control(bus, false);
954 } else {
955 err = brcmf_sdio_kso_control(bus, true);
956 }
957 if (err) {
958 brcmf_err("error while changing bus sleep state %d\n",
959 err);
960 goto done;
961 }
962 }
963
964 end:
965 /* control clocks */
966 if (sleep) {
967 if (!bus->sr_enabled)
968 brcmf_sdio_clkctl(bus, CLK_NONE, pendok);
969 } else {
970 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok);
971 brcmf_sdio_wd_timer(bus, true);
972 }
973 bus->sleeping = sleep;
974 brcmf_dbg(SDIO, "new state %s\n",
975 (sleep ? "SLEEP" : "WAKE"));
976 done:
977 brcmf_dbg(SDIO, "Exit: err=%d\n", err);
978 return err;
979
980 }
981
982 #ifdef DEBUG
983 static inline bool brcmf_sdio_valid_shared_address(u32 addr)
984 {
985 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
986 }
987
988 static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
989 struct sdpcm_shared *sh)
990 {
991 u32 addr = 0;
992 int rv;
993 u32 shaddr = 0;
994 struct sdpcm_shared_le sh_le;
995 __le32 addr_le;
996
997 sdio_claim_host(bus->sdiodev->func[1]);
998 brcmf_sdio_bus_sleep(bus, false, false);
999
1000 /*
1001 * Read last word in socram to determine
1002 * address of sdpcm_shared structure
1003 */
1004 shaddr = bus->ci->rambase + bus->ci->ramsize - 4;
1005 if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci))
1006 shaddr -= bus->ci->srsize;
1007 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr,
1008 (u8 *)&addr_le, 4);
1009 if (rv < 0)
1010 goto fail;
1011
1012 /*
1013 * Check if addr is valid.
1014 * NVRAM length at the end of memory should have been overwritten.
1015 */
1016 addr = le32_to_cpu(addr_le);
1017 if (!brcmf_sdio_valid_shared_address(addr)) {
1018 brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr);
1019 rv = -EINVAL;
1020 goto fail;
1021 }
1022
1023 brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr);
1024
1025 /* Read hndrte_shared structure */
1026 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
1027 sizeof(struct sdpcm_shared_le));
1028 if (rv < 0)
1029 goto fail;
1030
1031 sdio_release_host(bus->sdiodev->func[1]);
1032
1033 /* Endianness */
1034 sh->flags = le32_to_cpu(sh_le.flags);
1035 sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
1036 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
1037 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
1038 sh->assert_line = le32_to_cpu(sh_le.assert_line);
1039 sh->console_addr = le32_to_cpu(sh_le.console_addr);
1040 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
1041
1042 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) {
1043 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
1044 SDPCM_SHARED_VERSION,
1045 sh->flags & SDPCM_SHARED_VERSION_MASK);
1046 return -EPROTO;
1047 }
1048 return 0;
1049
1050 fail:
1051 brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n",
1052 rv, addr);
1053 sdio_release_host(bus->sdiodev->func[1]);
1054 return rv;
1055 }
1056
1057 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1058 {
1059 struct sdpcm_shared sh;
1060
1061 if (brcmf_sdio_readshared(bus, &sh) == 0)
1062 bus->console_addr = sh.console_addr;
1063 }
1064 #else
1065 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1066 {
1067 }
1068 #endif /* DEBUG */
1069
1070 static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus)
1071 {
1072 u32 intstatus = 0;
1073 u32 hmb_data;
1074 u8 fcbits;
1075 int ret;
1076
1077 brcmf_dbg(SDIO, "Enter\n");
1078
1079 /* Read mailbox data and ack that we did so */
1080 ret = r_sdreg32(bus, &hmb_data,
1081 offsetof(struct sdpcmd_regs, tohostmailboxdata));
1082
1083 if (ret == 0)
1084 w_sdreg32(bus, SMB_INT_ACK,
1085 offsetof(struct sdpcmd_regs, tosbmailbox));
1086 bus->sdcnt.f1regdata += 2;
1087
1088 /* Dongle recomposed rx frames, accept them again */
1089 if (hmb_data & HMB_DATA_NAKHANDLED) {
1090 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n",
1091 bus->rx_seq);
1092 if (!bus->rxskip)
1093 brcmf_err("unexpected NAKHANDLED!\n");
1094
1095 bus->rxskip = false;
1096 intstatus |= I_HMB_FRAME_IND;
1097 }
1098
1099 /*
1100 * DEVREADY does not occur with gSPI.
1101 */
1102 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1103 bus->sdpcm_ver =
1104 (hmb_data & HMB_DATA_VERSION_MASK) >>
1105 HMB_DATA_VERSION_SHIFT;
1106 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1107 brcmf_err("Version mismatch, dongle reports %d, "
1108 "expecting %d\n",
1109 bus->sdpcm_ver, SDPCM_PROT_VERSION);
1110 else
1111 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n",
1112 bus->sdpcm_ver);
1113
1114 /*
1115 * Retrieve console state address now that firmware should have
1116 * updated it.
1117 */
1118 brcmf_sdio_get_console_addr(bus);
1119 }
1120
1121 /*
1122 * Flow Control has been moved into the RX headers and this out of band
1123 * method isn't used any more.
1124 * remaining backward compatible with older dongles.
1125 */
1126 if (hmb_data & HMB_DATA_FC) {
1127 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1128 HMB_DATA_FCDATA_SHIFT;
1129
1130 if (fcbits & ~bus->flowcontrol)
1131 bus->sdcnt.fc_xoff++;
1132
1133 if (bus->flowcontrol & ~fcbits)
1134 bus->sdcnt.fc_xon++;
1135
1136 bus->sdcnt.fc_rcvd++;
1137 bus->flowcontrol = fcbits;
1138 }
1139
1140 /* Shouldn't be any others */
1141 if (hmb_data & ~(HMB_DATA_DEVREADY |
1142 HMB_DATA_NAKHANDLED |
1143 HMB_DATA_FC |
1144 HMB_DATA_FWREADY |
1145 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1146 brcmf_err("Unknown mailbox data content: 0x%02x\n",
1147 hmb_data);
1148
1149 return intstatus;
1150 }
1151
1152 static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
1153 {
1154 uint retries = 0;
1155 u16 lastrbc;
1156 u8 hi, lo;
1157 int err;
1158
1159 brcmf_err("%sterminate frame%s\n",
1160 abort ? "abort command, " : "",
1161 rtx ? ", send NAK" : "");
1162
1163 if (abort)
1164 brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
1165
1166 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
1167 SFC_RF_TERM, &err);
1168 bus->sdcnt.f1regdata++;
1169
1170 /* Wait until the packet has been flushed (device/FIFO stable) */
1171 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1172 hi = brcmf_sdiod_regrb(bus->sdiodev,
1173 SBSDIO_FUNC1_RFRAMEBCHI, &err);
1174 lo = brcmf_sdiod_regrb(bus->sdiodev,
1175 SBSDIO_FUNC1_RFRAMEBCLO, &err);
1176 bus->sdcnt.f1regdata += 2;
1177
1178 if ((hi == 0) && (lo == 0))
1179 break;
1180
1181 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1182 brcmf_err("count growing: last 0x%04x now 0x%04x\n",
1183 lastrbc, (hi << 8) + lo);
1184 }
1185 lastrbc = (hi << 8) + lo;
1186 }
1187
1188 if (!retries)
1189 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc);
1190 else
1191 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries);
1192
1193 if (rtx) {
1194 bus->sdcnt.rxrtx++;
1195 err = w_sdreg32(bus, SMB_NAK,
1196 offsetof(struct sdpcmd_regs, tosbmailbox));
1197
1198 bus->sdcnt.f1regdata++;
1199 if (err == 0)
1200 bus->rxskip = true;
1201 }
1202
1203 /* Clear partial in any case */
1204 bus->cur_read.len = 0;
1205 }
1206
1207 static void brcmf_sdio_txfail(struct brcmf_sdio *bus)
1208 {
1209 struct brcmf_sdio_dev *sdiodev = bus->sdiodev;
1210 u8 i, hi, lo;
1211
1212 /* On failure, abort the command and terminate the frame */
1213 brcmf_err("sdio error, abort command and terminate frame\n");
1214 bus->sdcnt.tx_sderrs++;
1215
1216 brcmf_sdiod_abort(sdiodev, SDIO_FUNC_2);
1217 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL);
1218 bus->sdcnt.f1regdata++;
1219
1220 for (i = 0; i < 3; i++) {
1221 hi = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL);
1222 lo = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL);
1223 bus->sdcnt.f1regdata += 2;
1224 if ((hi == 0) && (lo == 0))
1225 break;
1226 }
1227 }
1228
1229 /* return total length of buffer chain */
1230 static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus)
1231 {
1232 struct sk_buff *p;
1233 uint total;
1234
1235 total = 0;
1236 skb_queue_walk(&bus->glom, p)
1237 total += p->len;
1238 return total;
1239 }
1240
1241 static void brcmf_sdio_free_glom(struct brcmf_sdio *bus)
1242 {
1243 struct sk_buff *cur, *next;
1244
1245 skb_queue_walk_safe(&bus->glom, cur, next) {
1246 skb_unlink(cur, &bus->glom);
1247 brcmu_pkt_buf_free_skb(cur);
1248 }
1249 }
1250
1251 /**
1252 * brcmfmac sdio bus specific header
1253 * This is the lowest layer header wrapped on the packets transmitted between
1254 * host and WiFi dongle which contains information needed for SDIO core and
1255 * firmware
1256 *
1257 * It consists of 3 parts: hardware header, hardware extension header and
1258 * software header
1259 * hardware header (frame tag) - 4 bytes
1260 * Byte 0~1: Frame length
1261 * Byte 2~3: Checksum, bit-wise inverse of frame length
1262 * hardware extension header - 8 bytes
1263 * Tx glom mode only, N/A for Rx or normal Tx
1264 * Byte 0~1: Packet length excluding hw frame tag
1265 * Byte 2: Reserved
1266 * Byte 3: Frame flags, bit 0: last frame indication
1267 * Byte 4~5: Reserved
1268 * Byte 6~7: Tail padding length
1269 * software header - 8 bytes
1270 * Byte 0: Rx/Tx sequence number
1271 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
1272 * Byte 2: Length of next data frame, reserved for Tx
1273 * Byte 3: Data offset
1274 * Byte 4: Flow control bits, reserved for Tx
1275 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
1276 * Byte 6~7: Reserved
1277 */
1278 #define SDPCM_HWHDR_LEN 4
1279 #define SDPCM_HWEXT_LEN 8
1280 #define SDPCM_SWHDR_LEN 8
1281 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
1282 /* software header */
1283 #define SDPCM_SEQ_MASK 0x000000ff
1284 #define SDPCM_SEQ_WRAP 256
1285 #define SDPCM_CHANNEL_MASK 0x00000f00
1286 #define SDPCM_CHANNEL_SHIFT 8
1287 #define SDPCM_CONTROL_CHANNEL 0 /* Control */
1288 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
1289 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
1290 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
1291 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
1292 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
1293 #define SDPCM_NEXTLEN_MASK 0x00ff0000
1294 #define SDPCM_NEXTLEN_SHIFT 16
1295 #define SDPCM_DOFFSET_MASK 0xff000000
1296 #define SDPCM_DOFFSET_SHIFT 24
1297 #define SDPCM_FCMASK_MASK 0x000000ff
1298 #define SDPCM_WINDOW_MASK 0x0000ff00
1299 #define SDPCM_WINDOW_SHIFT 8
1300
1301 static inline u8 brcmf_sdio_getdatoffset(u8 *swheader)
1302 {
1303 u32 hdrvalue;
1304 hdrvalue = *(u32 *)swheader;
1305 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT);
1306 }
1307
1308 static inline bool brcmf_sdio_fromevntchan(u8 *swheader)
1309 {
1310 u32 hdrvalue;
1311 u8 ret;
1312
1313 hdrvalue = *(u32 *)swheader;
1314 ret = (u8)((hdrvalue & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT);
1315
1316 return (ret == SDPCM_EVENT_CHANNEL);
1317 }
1318
1319 static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header,
1320 struct brcmf_sdio_hdrinfo *rd,
1321 enum brcmf_sdio_frmtype type)
1322 {
1323 u16 len, checksum;
1324 u8 rx_seq, fc, tx_seq_max;
1325 u32 swheader;
1326
1327 trace_brcmf_sdpcm_hdr(SDPCM_RX, header);
1328
1329 /* hw header */
1330 len = get_unaligned_le16(header);
1331 checksum = get_unaligned_le16(header + sizeof(u16));
1332 /* All zero means no more to read */
1333 if (!(len | checksum)) {
1334 bus->rxpending = false;
1335 return -ENODATA;
1336 }
1337 if ((u16)(~(len ^ checksum))) {
1338 brcmf_err("HW header checksum error\n");
1339 bus->sdcnt.rx_badhdr++;
1340 brcmf_sdio_rxfail(bus, false, false);
1341 return -EIO;
1342 }
1343 if (len < SDPCM_HDRLEN) {
1344 brcmf_err("HW header length error\n");
1345 return -EPROTO;
1346 }
1347 if (type == BRCMF_SDIO_FT_SUPER &&
1348 (roundup(len, bus->blocksize) != rd->len)) {
1349 brcmf_err("HW superframe header length error\n");
1350 return -EPROTO;
1351 }
1352 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) {
1353 brcmf_err("HW subframe header length error\n");
1354 return -EPROTO;
1355 }
1356 rd->len = len;
1357
1358 /* software header */
1359 header += SDPCM_HWHDR_LEN;
1360 swheader = le32_to_cpu(*(__le32 *)header);
1361 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) {
1362 brcmf_err("Glom descriptor found in superframe head\n");
1363 rd->len = 0;
1364 return -EINVAL;
1365 }
1366 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK);
1367 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT;
1368 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
1369 type != BRCMF_SDIO_FT_SUPER) {
1370 brcmf_err("HW header length too long\n");
1371 bus->sdcnt.rx_toolong++;
1372 brcmf_sdio_rxfail(bus, false, false);
1373 rd->len = 0;
1374 return -EPROTO;
1375 }
1376 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) {
1377 brcmf_err("Wrong channel for superframe\n");
1378 rd->len = 0;
1379 return -EINVAL;
1380 }
1381 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL &&
1382 rd->channel != SDPCM_EVENT_CHANNEL) {
1383 brcmf_err("Wrong channel for subframe\n");
1384 rd->len = 0;
1385 return -EINVAL;
1386 }
1387 rd->dat_offset = brcmf_sdio_getdatoffset(header);
1388 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
1389 brcmf_err("seq %d: bad data offset\n", rx_seq);
1390 bus->sdcnt.rx_badhdr++;
1391 brcmf_sdio_rxfail(bus, false, false);
1392 rd->len = 0;
1393 return -ENXIO;
1394 }
1395 if (rd->seq_num != rx_seq) {
1396 brcmf_dbg(SDIO, "seq %d, expected %d\n", rx_seq, rd->seq_num);
1397 bus->sdcnt.rx_badseq++;
1398 rd->seq_num = rx_seq;
1399 }
1400 /* no need to check the reset for subframe */
1401 if (type == BRCMF_SDIO_FT_SUB)
1402 return 0;
1403 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT;
1404 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
1405 /* only warm for NON glom packet */
1406 if (rd->channel != SDPCM_GLOM_CHANNEL)
1407 brcmf_err("seq %d: next length error\n", rx_seq);
1408 rd->len_nxtfrm = 0;
1409 }
1410 swheader = le32_to_cpu(*(__le32 *)(header + 4));
1411 fc = swheader & SDPCM_FCMASK_MASK;
1412 if (bus->flowcontrol != fc) {
1413 if (~bus->flowcontrol & fc)
1414 bus->sdcnt.fc_xoff++;
1415 if (bus->flowcontrol & ~fc)
1416 bus->sdcnt.fc_xon++;
1417 bus->sdcnt.fc_rcvd++;
1418 bus->flowcontrol = fc;
1419 }
1420 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT;
1421 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
1422 brcmf_err("seq %d: max tx seq number error\n", rx_seq);
1423 tx_seq_max = bus->tx_seq + 2;
1424 }
1425 bus->tx_max = tx_seq_max;
1426
1427 return 0;
1428 }
1429
1430 static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length)
1431 {
1432 *(__le16 *)header = cpu_to_le16(frm_length);
1433 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length);
1434 }
1435
1436 static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header,
1437 struct brcmf_sdio_hdrinfo *hd_info)
1438 {
1439 u32 hdrval;
1440 u8 hdr_offset;
1441
1442 brcmf_sdio_update_hwhdr(header, hd_info->len);
1443 hdr_offset = SDPCM_HWHDR_LEN;
1444
1445 if (bus->txglom) {
1446 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24);
1447 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1448 hdrval = (u16)hd_info->tail_pad << 16;
1449 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval);
1450 hdr_offset += SDPCM_HWEXT_LEN;
1451 }
1452
1453 hdrval = hd_info->seq_num;
1454 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) &
1455 SDPCM_CHANNEL_MASK;
1456 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) &
1457 SDPCM_DOFFSET_MASK;
1458 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1459 *(((__le32 *)(header + hdr_offset)) + 1) = 0;
1460 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header);
1461 }
1462
1463 static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq)
1464 {
1465 u16 dlen, totlen;
1466 u8 *dptr, num = 0;
1467 u16 sublen;
1468 struct sk_buff *pfirst, *pnext;
1469
1470 int errcode;
1471 u8 doff, sfdoff;
1472
1473 struct brcmf_sdio_hdrinfo rd_new;
1474
1475 /* If packets, issue read(s) and send up packet chain */
1476 /* Return sequence numbers consumed? */
1477
1478 brcmf_dbg(SDIO, "start: glomd %p glom %p\n",
1479 bus->glomd, skb_peek(&bus->glom));
1480
1481 /* If there's a descriptor, generate the packet chain */
1482 if (bus->glomd) {
1483 pfirst = pnext = NULL;
1484 dlen = (u16) (bus->glomd->len);
1485 dptr = bus->glomd->data;
1486 if (!dlen || (dlen & 1)) {
1487 brcmf_err("bad glomd len(%d), ignore descriptor\n",
1488 dlen);
1489 dlen = 0;
1490 }
1491
1492 for (totlen = num = 0; dlen; num++) {
1493 /* Get (and move past) next length */
1494 sublen = get_unaligned_le16(dptr);
1495 dlen -= sizeof(u16);
1496 dptr += sizeof(u16);
1497 if ((sublen < SDPCM_HDRLEN) ||
1498 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1499 brcmf_err("descriptor len %d bad: %d\n",
1500 num, sublen);
1501 pnext = NULL;
1502 break;
1503 }
1504 if (sublen % bus->sgentry_align) {
1505 brcmf_err("sublen %d not multiple of %d\n",
1506 sublen, bus->sgentry_align);
1507 }
1508 totlen += sublen;
1509
1510 /* For last frame, adjust read len so total
1511 is a block multiple */
1512 if (!dlen) {
1513 sublen +=
1514 (roundup(totlen, bus->blocksize) - totlen);
1515 totlen = roundup(totlen, bus->blocksize);
1516 }
1517
1518 /* Allocate/chain packet for next subframe */
1519 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align);
1520 if (pnext == NULL) {
1521 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
1522 num, sublen);
1523 break;
1524 }
1525 skb_queue_tail(&bus->glom, pnext);
1526
1527 /* Adhere to start alignment requirements */
1528 pkt_align(pnext, sublen, bus->sgentry_align);
1529 }
1530
1531 /* If all allocations succeeded, save packet chain
1532 in bus structure */
1533 if (pnext) {
1534 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1535 totlen, num);
1536 if (BRCMF_GLOM_ON() && bus->cur_read.len &&
1537 totlen != bus->cur_read.len) {
1538 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1539 bus->cur_read.len, totlen, rxseq);
1540 }
1541 pfirst = pnext = NULL;
1542 } else {
1543 brcmf_sdio_free_glom(bus);
1544 num = 0;
1545 }
1546
1547 /* Done with descriptor packet */
1548 brcmu_pkt_buf_free_skb(bus->glomd);
1549 bus->glomd = NULL;
1550 bus->cur_read.len = 0;
1551 }
1552
1553 /* Ok -- either we just generated a packet chain,
1554 or had one from before */
1555 if (!skb_queue_empty(&bus->glom)) {
1556 if (BRCMF_GLOM_ON()) {
1557 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1558 skb_queue_walk(&bus->glom, pnext) {
1559 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1560 pnext, (u8 *) (pnext->data),
1561 pnext->len, pnext->len);
1562 }
1563 }
1564
1565 pfirst = skb_peek(&bus->glom);
1566 dlen = (u16) brcmf_sdio_glom_len(bus);
1567
1568 /* Do an SDIO read for the superframe. Configurable iovar to
1569 * read directly into the chained packet, or allocate a large
1570 * packet and and copy into the chain.
1571 */
1572 sdio_claim_host(bus->sdiodev->func[1]);
1573 errcode = brcmf_sdiod_recv_chain(bus->sdiodev,
1574 &bus->glom, dlen);
1575 sdio_release_host(bus->sdiodev->func[1]);
1576 bus->sdcnt.f2rxdata++;
1577
1578 /* On failure, kill the superframe */
1579 if (errcode < 0) {
1580 brcmf_err("glom read of %d bytes failed: %d\n",
1581 dlen, errcode);
1582
1583 sdio_claim_host(bus->sdiodev->func[1]);
1584 brcmf_sdio_rxfail(bus, true, false);
1585 bus->sdcnt.rxglomfail++;
1586 brcmf_sdio_free_glom(bus);
1587 sdio_release_host(bus->sdiodev->func[1]);
1588 return 0;
1589 }
1590
1591 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1592 pfirst->data, min_t(int, pfirst->len, 48),
1593 "SUPERFRAME:\n");
1594
1595 rd_new.seq_num = rxseq;
1596 rd_new.len = dlen;
1597 sdio_claim_host(bus->sdiodev->func[1]);
1598 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new,
1599 BRCMF_SDIO_FT_SUPER);
1600 sdio_release_host(bus->sdiodev->func[1]);
1601 bus->cur_read.len = rd_new.len_nxtfrm << 4;
1602
1603 /* Remove superframe header, remember offset */
1604 skb_pull(pfirst, rd_new.dat_offset);
1605 sfdoff = rd_new.dat_offset;
1606 num = 0;
1607
1608 /* Validate all the subframe headers */
1609 skb_queue_walk(&bus->glom, pnext) {
1610 /* leave when invalid subframe is found */
1611 if (errcode)
1612 break;
1613
1614 rd_new.len = pnext->len;
1615 rd_new.seq_num = rxseq++;
1616 sdio_claim_host(bus->sdiodev->func[1]);
1617 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new,
1618 BRCMF_SDIO_FT_SUB);
1619 sdio_release_host(bus->sdiodev->func[1]);
1620 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1621 pnext->data, 32, "subframe:\n");
1622
1623 num++;
1624 }
1625
1626 if (errcode) {
1627 /* Terminate frame on error */
1628 sdio_claim_host(bus->sdiodev->func[1]);
1629 brcmf_sdio_rxfail(bus, true, false);
1630 bus->sdcnt.rxglomfail++;
1631 brcmf_sdio_free_glom(bus);
1632 sdio_release_host(bus->sdiodev->func[1]);
1633 bus->cur_read.len = 0;
1634 return 0;
1635 }
1636
1637 /* Basic SD framing looks ok - process each packet (header) */
1638
1639 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1640 dptr = (u8 *) (pfirst->data);
1641 sublen = get_unaligned_le16(dptr);
1642 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]);
1643
1644 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1645 dptr, pfirst->len,
1646 "Rx Subframe Data:\n");
1647
1648 __skb_trim(pfirst, sublen);
1649 skb_pull(pfirst, doff);
1650
1651 if (pfirst->len == 0) {
1652 skb_unlink(pfirst, &bus->glom);
1653 brcmu_pkt_buf_free_skb(pfirst);
1654 continue;
1655 }
1656
1657 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1658 pfirst->data,
1659 min_t(int, pfirst->len, 32),
1660 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1661 bus->glom.qlen, pfirst, pfirst->data,
1662 pfirst->len, pfirst->next,
1663 pfirst->prev);
1664 skb_unlink(pfirst, &bus->glom);
1665 if (brcmf_sdio_fromevntchan(&dptr[SDPCM_HWHDR_LEN]))
1666 brcmf_rx_event(bus->sdiodev->dev, pfirst);
1667 else
1668 brcmf_rx_frame(bus->sdiodev->dev, pfirst,
1669 false);
1670 bus->sdcnt.rxglompkts++;
1671 }
1672
1673 bus->sdcnt.rxglomframes++;
1674 }
1675 return num;
1676 }
1677
1678 static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
1679 bool *pending)
1680 {
1681 DECLARE_WAITQUEUE(wait, current);
1682 int timeout = DCMD_RESP_TIMEOUT;
1683
1684 /* Wait until control frame is available */
1685 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1686 set_current_state(TASK_INTERRUPTIBLE);
1687
1688 while (!(*condition) && (!signal_pending(current) && timeout))
1689 timeout = schedule_timeout(timeout);
1690
1691 if (signal_pending(current))
1692 *pending = true;
1693
1694 set_current_state(TASK_RUNNING);
1695 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1696
1697 return timeout;
1698 }
1699
1700 static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus)
1701 {
1702 wake_up_interruptible(&bus->dcmd_resp_wait);
1703
1704 return 0;
1705 }
1706 static void
1707 brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
1708 {
1709 uint rdlen, pad;
1710 u8 *buf = NULL, *rbuf;
1711 int sdret;
1712
1713 brcmf_dbg(TRACE, "Enter\n");
1714
1715 if (bus->rxblen)
1716 buf = vzalloc(bus->rxblen);
1717 if (!buf)
1718 goto done;
1719
1720 rbuf = bus->rxbuf;
1721 pad = ((unsigned long)rbuf % bus->head_align);
1722 if (pad)
1723 rbuf += (bus->head_align - pad);
1724
1725 /* Copy the already-read portion over */
1726 memcpy(buf, hdr, BRCMF_FIRSTREAD);
1727 if (len <= BRCMF_FIRSTREAD)
1728 goto gotpkt;
1729
1730 /* Raise rdlen to next SDIO block to avoid tail command */
1731 rdlen = len - BRCMF_FIRSTREAD;
1732 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1733 pad = bus->blocksize - (rdlen % bus->blocksize);
1734 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1735 ((len + pad) < bus->sdiodev->bus_if->maxctl))
1736 rdlen += pad;
1737 } else if (rdlen % bus->head_align) {
1738 rdlen += bus->head_align - (rdlen % bus->head_align);
1739 }
1740
1741 /* Drop if the read is too big or it exceeds our maximum */
1742 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
1743 brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
1744 rdlen, bus->sdiodev->bus_if->maxctl);
1745 brcmf_sdio_rxfail(bus, false, false);
1746 goto done;
1747 }
1748
1749 if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
1750 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1751 len, len - doff, bus->sdiodev->bus_if->maxctl);
1752 bus->sdcnt.rx_toolong++;
1753 brcmf_sdio_rxfail(bus, false, false);
1754 goto done;
1755 }
1756
1757 /* Read remain of frame body */
1758 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen);
1759 bus->sdcnt.f2rxdata++;
1760
1761 /* Control frame failures need retransmission */
1762 if (sdret < 0) {
1763 brcmf_err("read %d control bytes failed: %d\n",
1764 rdlen, sdret);
1765 bus->sdcnt.rxc_errors++;
1766 brcmf_sdio_rxfail(bus, true, true);
1767 goto done;
1768 } else
1769 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen);
1770
1771 gotpkt:
1772
1773 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
1774 buf, len, "RxCtrl:\n");
1775
1776 /* Point to valid data and indicate its length */
1777 spin_lock_bh(&bus->rxctl_lock);
1778 if (bus->rxctl) {
1779 brcmf_err("last control frame is being processed.\n");
1780 spin_unlock_bh(&bus->rxctl_lock);
1781 vfree(buf);
1782 goto done;
1783 }
1784 bus->rxctl = buf + doff;
1785 bus->rxctl_orig = buf;
1786 bus->rxlen = len - doff;
1787 spin_unlock_bh(&bus->rxctl_lock);
1788
1789 done:
1790 /* Awake any waiters */
1791 brcmf_sdio_dcmd_resp_wake(bus);
1792 }
1793
1794 /* Pad read to blocksize for efficiency */
1795 static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
1796 {
1797 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1798 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1799 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1800 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1801 *rdlen += *pad;
1802 } else if (*rdlen % bus->head_align) {
1803 *rdlen += bus->head_align - (*rdlen % bus->head_align);
1804 }
1805 }
1806
1807 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
1808 {
1809 struct sk_buff *pkt; /* Packet for event or data frames */
1810 u16 pad; /* Number of pad bytes to read */
1811 uint rxleft = 0; /* Remaining number of frames allowed */
1812 int ret; /* Return code from calls */
1813 uint rxcount = 0; /* Total frames read */
1814 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new;
1815 u8 head_read = 0;
1816
1817 brcmf_dbg(TRACE, "Enter\n");
1818
1819 /* Not finished unless we encounter no more frames indication */
1820 bus->rxpending = true;
1821
1822 for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
1823 !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA;
1824 rd->seq_num++, rxleft--) {
1825
1826 /* Handle glomming separately */
1827 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
1828 u8 cnt;
1829 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1830 bus->glomd, skb_peek(&bus->glom));
1831 cnt = brcmf_sdio_rxglom(bus, rd->seq_num);
1832 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1833 rd->seq_num += cnt - 1;
1834 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1835 continue;
1836 }
1837
1838 rd->len_left = rd->len;
1839 /* read header first for unknow frame length */
1840 sdio_claim_host(bus->sdiodev->func[1]);
1841 if (!rd->len) {
1842 ret = brcmf_sdiod_recv_buf(bus->sdiodev,
1843 bus->rxhdr, BRCMF_FIRSTREAD);
1844 bus->sdcnt.f2rxhdrs++;
1845 if (ret < 0) {
1846 brcmf_err("RXHEADER FAILED: %d\n",
1847 ret);
1848 bus->sdcnt.rx_hdrfail++;
1849 brcmf_sdio_rxfail(bus, true, true);
1850 sdio_release_host(bus->sdiodev->func[1]);
1851 continue;
1852 }
1853
1854 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
1855 bus->rxhdr, SDPCM_HDRLEN,
1856 "RxHdr:\n");
1857
1858 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd,
1859 BRCMF_SDIO_FT_NORMAL)) {
1860 sdio_release_host(bus->sdiodev->func[1]);
1861 if (!bus->rxpending)
1862 break;
1863 else
1864 continue;
1865 }
1866
1867 if (rd->channel == SDPCM_CONTROL_CHANNEL) {
1868 brcmf_sdio_read_control(bus, bus->rxhdr,
1869 rd->len,
1870 rd->dat_offset);
1871 /* prepare the descriptor for the next read */
1872 rd->len = rd->len_nxtfrm << 4;
1873 rd->len_nxtfrm = 0;
1874 /* treat all packet as event if we don't know */
1875 rd->channel = SDPCM_EVENT_CHANNEL;
1876 sdio_release_host(bus->sdiodev->func[1]);
1877 continue;
1878 }
1879 rd->len_left = rd->len > BRCMF_FIRSTREAD ?
1880 rd->len - BRCMF_FIRSTREAD : 0;
1881 head_read = BRCMF_FIRSTREAD;
1882 }
1883
1884 brcmf_sdio_pad(bus, &pad, &rd->len_left);
1885
1886 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
1887 bus->head_align);
1888 if (!pkt) {
1889 /* Give up on data, request rtx of events */
1890 brcmf_err("brcmu_pkt_buf_get_skb failed\n");
1891 brcmf_sdio_rxfail(bus, false,
1892 RETRYCHAN(rd->channel));
1893 sdio_release_host(bus->sdiodev->func[1]);
1894 continue;
1895 }
1896 skb_pull(pkt, head_read);
1897 pkt_align(pkt, rd->len_left, bus->head_align);
1898
1899 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt);
1900 bus->sdcnt.f2rxdata++;
1901 sdio_release_host(bus->sdiodev->func[1]);
1902
1903 if (ret < 0) {
1904 brcmf_err("read %d bytes from channel %d failed: %d\n",
1905 rd->len, rd->channel, ret);
1906 brcmu_pkt_buf_free_skb(pkt);
1907 sdio_claim_host(bus->sdiodev->func[1]);
1908 brcmf_sdio_rxfail(bus, true,
1909 RETRYCHAN(rd->channel));
1910 sdio_release_host(bus->sdiodev->func[1]);
1911 continue;
1912 }
1913
1914 if (head_read) {
1915 skb_push(pkt, head_read);
1916 memcpy(pkt->data, bus->rxhdr, head_read);
1917 head_read = 0;
1918 } else {
1919 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
1920 rd_new.seq_num = rd->seq_num;
1921 sdio_claim_host(bus->sdiodev->func[1]);
1922 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new,
1923 BRCMF_SDIO_FT_NORMAL)) {
1924 rd->len = 0;
1925 brcmu_pkt_buf_free_skb(pkt);
1926 }
1927 bus->sdcnt.rx_readahead_cnt++;
1928 if (rd->len != roundup(rd_new.len, 16)) {
1929 brcmf_err("frame length mismatch:read %d, should be %d\n",
1930 rd->len,
1931 roundup(rd_new.len, 16) >> 4);
1932 rd->len = 0;
1933 brcmf_sdio_rxfail(bus, true, true);
1934 sdio_release_host(bus->sdiodev->func[1]);
1935 brcmu_pkt_buf_free_skb(pkt);
1936 continue;
1937 }
1938 sdio_release_host(bus->sdiodev->func[1]);
1939 rd->len_nxtfrm = rd_new.len_nxtfrm;
1940 rd->channel = rd_new.channel;
1941 rd->dat_offset = rd_new.dat_offset;
1942
1943 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
1944 BRCMF_DATA_ON()) &&
1945 BRCMF_HDRS_ON(),
1946 bus->rxhdr, SDPCM_HDRLEN,
1947 "RxHdr:\n");
1948
1949 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) {
1950 brcmf_err("readahead on control packet %d?\n",
1951 rd_new.seq_num);
1952 /* Force retry w/normal header read */
1953 rd->len = 0;
1954 sdio_claim_host(bus->sdiodev->func[1]);
1955 brcmf_sdio_rxfail(bus, false, true);
1956 sdio_release_host(bus->sdiodev->func[1]);
1957 brcmu_pkt_buf_free_skb(pkt);
1958 continue;
1959 }
1960 }
1961
1962 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1963 pkt->data, rd->len, "Rx Data:\n");
1964
1965 /* Save superframe descriptor and allocate packet frame */
1966 if (rd->channel == SDPCM_GLOM_CHANNEL) {
1967 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) {
1968 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
1969 rd->len);
1970 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1971 pkt->data, rd->len,
1972 "Glom Data:\n");
1973 __skb_trim(pkt, rd->len);
1974 skb_pull(pkt, SDPCM_HDRLEN);
1975 bus->glomd = pkt;
1976 } else {
1977 brcmf_err("%s: glom superframe w/o "
1978 "descriptor!\n", __func__);
1979 sdio_claim_host(bus->sdiodev->func[1]);
1980 brcmf_sdio_rxfail(bus, false, false);
1981 sdio_release_host(bus->sdiodev->func[1]);
1982 }
1983 /* prepare the descriptor for the next read */
1984 rd->len = rd->len_nxtfrm << 4;
1985 rd->len_nxtfrm = 0;
1986 /* treat all packet as event if we don't know */
1987 rd->channel = SDPCM_EVENT_CHANNEL;
1988 continue;
1989 }
1990
1991 /* Fill in packet len and prio, deliver upward */
1992 __skb_trim(pkt, rd->len);
1993 skb_pull(pkt, rd->dat_offset);
1994
1995 if (pkt->len == 0)
1996 brcmu_pkt_buf_free_skb(pkt);
1997 else if (rd->channel == SDPCM_EVENT_CHANNEL)
1998 brcmf_rx_event(bus->sdiodev->dev, pkt);
1999 else
2000 brcmf_rx_frame(bus->sdiodev->dev, pkt,
2001 false);
2002
2003 /* prepare the descriptor for the next read */
2004 rd->len = rd->len_nxtfrm << 4;
2005 rd->len_nxtfrm = 0;
2006 /* treat all packet as event if we don't know */
2007 rd->channel = SDPCM_EVENT_CHANNEL;
2008 }
2009
2010 rxcount = maxframes - rxleft;
2011 /* Message if we hit the limit */
2012 if (!rxleft)
2013 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes);
2014 else
2015 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2016 /* Back off rxseq if awaiting rtx, update rx_seq */
2017 if (bus->rxskip)
2018 rd->seq_num--;
2019 bus->rx_seq = rd->seq_num;
2020
2021 return rxcount;
2022 }
2023
2024 static void
2025 brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus)
2026 {
2027 wake_up_interruptible(&bus->ctrl_wait);
2028 return;
2029 }
2030
2031 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt)
2032 {
2033 u16 head_pad;
2034 u8 *dat_buf;
2035
2036 dat_buf = (u8 *)(pkt->data);
2037
2038 /* Check head padding */
2039 head_pad = ((unsigned long)dat_buf % bus->head_align);
2040 if (head_pad) {
2041 if (skb_headroom(pkt) < head_pad) {
2042 bus->sdiodev->bus_if->tx_realloc++;
2043 head_pad = 0;
2044 if (skb_cow(pkt, head_pad))
2045 return -ENOMEM;
2046 }
2047 skb_push(pkt, head_pad);
2048 dat_buf = (u8 *)(pkt->data);
2049 memset(dat_buf, 0, head_pad + bus->tx_hdrlen);
2050 }
2051 return head_pad;
2052 }
2053
2054 /**
2055 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
2056 * bus layer usage.
2057 */
2058 /* flag marking a dummy skb added for DMA alignment requirement */
2059 #define ALIGN_SKB_FLAG 0x8000
2060 /* bit mask of data length chopped from the previous packet */
2061 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
2062
2063 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus,
2064 struct sk_buff_head *pktq,
2065 struct sk_buff *pkt, u16 total_len)
2066 {
2067 struct brcmf_sdio_dev *sdiodev;
2068 struct sk_buff *pkt_pad;
2069 u16 tail_pad, tail_chop, chain_pad;
2070 unsigned int blksize;
2071 bool lastfrm;
2072 int ntail, ret;
2073
2074 sdiodev = bus->sdiodev;
2075 blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize;
2076 /* sg entry alignment should be a divisor of block size */
2077 WARN_ON(blksize % bus->sgentry_align);
2078
2079 /* Check tail padding */
2080 lastfrm = skb_queue_is_last(pktq, pkt);
2081 tail_pad = 0;
2082 tail_chop = pkt->len % bus->sgentry_align;
2083 if (tail_chop)
2084 tail_pad = bus->sgentry_align - tail_chop;
2085 chain_pad = (total_len + tail_pad) % blksize;
2086 if (lastfrm && chain_pad)
2087 tail_pad += blksize - chain_pad;
2088 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) {
2089 pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop +
2090 bus->head_align);
2091 if (pkt_pad == NULL)
2092 return -ENOMEM;
2093 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad);
2094 if (unlikely(ret < 0)) {
2095 kfree_skb(pkt_pad);
2096 return ret;
2097 }
2098 memcpy(pkt_pad->data,
2099 pkt->data + pkt->len - tail_chop,
2100 tail_chop);
2101 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop;
2102 skb_trim(pkt, pkt->len - tail_chop);
2103 skb_trim(pkt_pad, tail_pad + tail_chop);
2104 __skb_queue_after(pktq, pkt, pkt_pad);
2105 } else {
2106 ntail = pkt->data_len + tail_pad -
2107 (pkt->end - pkt->tail);
2108 if (skb_cloned(pkt) || ntail > 0)
2109 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC))
2110 return -ENOMEM;
2111 if (skb_linearize(pkt))
2112 return -ENOMEM;
2113 __skb_put(pkt, tail_pad);
2114 }
2115
2116 return tail_pad;
2117 }
2118
2119 /**
2120 * brcmf_sdio_txpkt_prep - packet preparation for transmit
2121 * @bus: brcmf_sdio structure pointer
2122 * @pktq: packet list pointer
2123 * @chan: virtual channel to transmit the packet
2124 *
2125 * Processes to be applied to the packet
2126 * - Align data buffer pointer
2127 * - Align data buffer length
2128 * - Prepare header
2129 * Return: negative value if there is error
2130 */
2131 static int
2132 brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2133 uint chan)
2134 {
2135 u16 head_pad, total_len;
2136 struct sk_buff *pkt_next;
2137 u8 txseq;
2138 int ret;
2139 struct brcmf_sdio_hdrinfo hd_info = {0};
2140
2141 txseq = bus->tx_seq;
2142 total_len = 0;
2143 skb_queue_walk(pktq, pkt_next) {
2144 /* alignment packet inserted in previous
2145 * loop cycle can be skipped as it is
2146 * already properly aligned and does not
2147 * need an sdpcm header.
2148 */
2149 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG)
2150 continue;
2151
2152 /* align packet data pointer */
2153 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next);
2154 if (ret < 0)
2155 return ret;
2156 head_pad = (u16)ret;
2157 if (head_pad)
2158 memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad);
2159
2160 total_len += pkt_next->len;
2161
2162 hd_info.len = pkt_next->len;
2163 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next);
2164 if (bus->txglom && pktq->qlen > 1) {
2165 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq,
2166 pkt_next, total_len);
2167 if (ret < 0)
2168 return ret;
2169 hd_info.tail_pad = (u16)ret;
2170 total_len += (u16)ret;
2171 }
2172
2173 hd_info.channel = chan;
2174 hd_info.dat_offset = head_pad + bus->tx_hdrlen;
2175 hd_info.seq_num = txseq++;
2176
2177 /* Now fill the header */
2178 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info);
2179
2180 if (BRCMF_BYTES_ON() &&
2181 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
2182 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)))
2183 brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len,
2184 "Tx Frame:\n");
2185 else if (BRCMF_HDRS_ON())
2186 brcmf_dbg_hex_dump(true, pkt_next->data,
2187 head_pad + bus->tx_hdrlen,
2188 "Tx Header:\n");
2189 }
2190 /* Hardware length tag of the first packet should be total
2191 * length of the chain (including padding)
2192 */
2193 if (bus->txglom)
2194 brcmf_sdio_update_hwhdr(pktq->next->data, total_len);
2195 return 0;
2196 }
2197
2198 /**
2199 * brcmf_sdio_txpkt_postp - packet post processing for transmit
2200 * @bus: brcmf_sdio structure pointer
2201 * @pktq: packet list pointer
2202 *
2203 * Processes to be applied to the packet
2204 * - Remove head padding
2205 * - Remove tail padding
2206 */
2207 static void
2208 brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq)
2209 {
2210 u8 *hdr;
2211 u32 dat_offset;
2212 u16 tail_pad;
2213 u16 dummy_flags, chop_len;
2214 struct sk_buff *pkt_next, *tmp, *pkt_prev;
2215
2216 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2217 dummy_flags = *(u16 *)(pkt_next->cb);
2218 if (dummy_flags & ALIGN_SKB_FLAG) {
2219 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK;
2220 if (chop_len) {
2221 pkt_prev = pkt_next->prev;
2222 skb_put(pkt_prev, chop_len);
2223 }
2224 __skb_unlink(pkt_next, pktq);
2225 brcmu_pkt_buf_free_skb(pkt_next);
2226 } else {
2227 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN;
2228 dat_offset = le32_to_cpu(*(__le32 *)hdr);
2229 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >>
2230 SDPCM_DOFFSET_SHIFT;
2231 skb_pull(pkt_next, dat_offset);
2232 if (bus->txglom) {
2233 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2));
2234 skb_trim(pkt_next, pkt_next->len - tail_pad);
2235 }
2236 }
2237 }
2238 }
2239
2240 /* Writes a HW/SW header into the packet and sends it. */
2241 /* Assumes: (a) header space already there, (b) caller holds lock */
2242 static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2243 uint chan)
2244 {
2245 int ret;
2246 struct sk_buff *pkt_next, *tmp;
2247
2248 brcmf_dbg(TRACE, "Enter\n");
2249
2250 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan);
2251 if (ret)
2252 goto done;
2253
2254 sdio_claim_host(bus->sdiodev->func[1]);
2255 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq);
2256 bus->sdcnt.f2txdata++;
2257
2258 if (ret < 0)
2259 brcmf_sdio_txfail(bus);
2260
2261 sdio_release_host(bus->sdiodev->func[1]);
2262
2263 done:
2264 brcmf_sdio_txpkt_postp(bus, pktq);
2265 if (ret == 0)
2266 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP;
2267 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2268 __skb_unlink(pkt_next, pktq);
2269 brcmf_txcomplete(bus->sdiodev->dev, pkt_next, ret == 0);
2270 }
2271 return ret;
2272 }
2273
2274 static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes)
2275 {
2276 struct sk_buff *pkt;
2277 struct sk_buff_head pktq;
2278 u32 intstatus = 0;
2279 int ret = 0, prec_out, i;
2280 uint cnt = 0;
2281 u8 tx_prec_map, pkt_num;
2282
2283 brcmf_dbg(TRACE, "Enter\n");
2284
2285 tx_prec_map = ~bus->flowcontrol;
2286
2287 /* Send frames until the limit or some other event */
2288 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) {
2289 pkt_num = 1;
2290 if (bus->txglom)
2291 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq,
2292 bus->sdiodev->txglomsz);
2293 pkt_num = min_t(u32, pkt_num,
2294 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol));
2295 __skb_queue_head_init(&pktq);
2296 spin_lock_bh(&bus->txq_lock);
2297 for (i = 0; i < pkt_num; i++) {
2298 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map,
2299 &prec_out);
2300 if (pkt == NULL)
2301 break;
2302 __skb_queue_tail(&pktq, pkt);
2303 }
2304 spin_unlock_bh(&bus->txq_lock);
2305 if (i == 0)
2306 break;
2307
2308 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL);
2309
2310 cnt += i;
2311
2312 /* In poll mode, need to check for other events */
2313 if (!bus->intr) {
2314 /* Check device status, signal pending interrupt */
2315 sdio_claim_host(bus->sdiodev->func[1]);
2316 ret = r_sdreg32(bus, &intstatus,
2317 offsetof(struct sdpcmd_regs,
2318 intstatus));
2319 sdio_release_host(bus->sdiodev->func[1]);
2320 bus->sdcnt.f2txdata++;
2321 if (ret != 0)
2322 break;
2323 if (intstatus & bus->hostintmask)
2324 atomic_set(&bus->ipend, 1);
2325 }
2326 }
2327
2328 /* Deflow-control stack if needed */
2329 if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) &&
2330 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
2331 bus->txoff = false;
2332 brcmf_txflowblock(bus->sdiodev->dev, false);
2333 }
2334
2335 return cnt;
2336 }
2337
2338 static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len)
2339 {
2340 u8 doff;
2341 u16 pad;
2342 uint retries = 0;
2343 struct brcmf_sdio_hdrinfo hd_info = {0};
2344 int ret;
2345
2346 brcmf_dbg(TRACE, "Enter\n");
2347
2348 /* Back the pointer to make room for bus header */
2349 frame -= bus->tx_hdrlen;
2350 len += bus->tx_hdrlen;
2351
2352 /* Add alignment padding (optional for ctl frames) */
2353 doff = ((unsigned long)frame % bus->head_align);
2354 if (doff) {
2355 frame -= doff;
2356 len += doff;
2357 memset(frame + bus->tx_hdrlen, 0, doff);
2358 }
2359
2360 /* Round send length to next SDIO block */
2361 pad = 0;
2362 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2363 pad = bus->blocksize - (len % bus->blocksize);
2364 if ((pad > bus->roundup) || (pad >= bus->blocksize))
2365 pad = 0;
2366 } else if (len % bus->head_align) {
2367 pad = bus->head_align - (len % bus->head_align);
2368 }
2369 len += pad;
2370
2371 hd_info.len = len - pad;
2372 hd_info.channel = SDPCM_CONTROL_CHANNEL;
2373 hd_info.dat_offset = doff + bus->tx_hdrlen;
2374 hd_info.seq_num = bus->tx_seq;
2375 hd_info.lastfrm = true;
2376 hd_info.tail_pad = pad;
2377 brcmf_sdio_hdpack(bus, frame, &hd_info);
2378
2379 if (bus->txglom)
2380 brcmf_sdio_update_hwhdr(frame, len);
2381
2382 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
2383 frame, len, "Tx Frame:\n");
2384 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
2385 BRCMF_HDRS_ON(),
2386 frame, min_t(u16, len, 16), "TxHdr:\n");
2387
2388 do {
2389 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len);
2390
2391 if (ret < 0)
2392 brcmf_sdio_txfail(bus);
2393 else
2394 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
2395 } while (ret < 0 && retries++ < TXRETRIES);
2396
2397 return ret;
2398 }
2399
2400 static void brcmf_sdio_bus_stop(struct device *dev)
2401 {
2402 u32 local_hostintmask;
2403 u8 saveclk;
2404 int err;
2405 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2406 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2407 struct brcmf_sdio *bus = sdiodev->bus;
2408
2409 brcmf_dbg(TRACE, "Enter\n");
2410
2411 if (bus->watchdog_tsk) {
2412 send_sig(SIGTERM, bus->watchdog_tsk, 1);
2413 kthread_stop(bus->watchdog_tsk);
2414 bus->watchdog_tsk = NULL;
2415 }
2416
2417 if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
2418 sdio_claim_host(sdiodev->func[1]);
2419
2420 /* Enable clock for device interrupts */
2421 brcmf_sdio_bus_sleep(bus, false, false);
2422
2423 /* Disable and clear interrupts at the chip level also */
2424 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask));
2425 local_hostintmask = bus->hostintmask;
2426 bus->hostintmask = 0;
2427
2428 /* Force backplane clocks to assure F2 interrupt propagates */
2429 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2430 &err);
2431 if (!err)
2432 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2433 (saveclk | SBSDIO_FORCE_HT), &err);
2434 if (err)
2435 brcmf_err("Failed to force clock for F2: err %d\n",
2436 err);
2437
2438 /* Turn off the bus (F2), free any pending packets */
2439 brcmf_dbg(INTR, "disable SDIO interrupts\n");
2440 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
2441
2442 /* Clear any pending interrupts now that F2 is disabled */
2443 w_sdreg32(bus, local_hostintmask,
2444 offsetof(struct sdpcmd_regs, intstatus));
2445
2446 sdio_release_host(sdiodev->func[1]);
2447 }
2448 /* Clear the data packet queues */
2449 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
2450
2451 /* Clear any held glomming stuff */
2452 brcmu_pkt_buf_free_skb(bus->glomd);
2453 brcmf_sdio_free_glom(bus);
2454
2455 /* Clear rx control and wake any waiters */
2456 spin_lock_bh(&bus->rxctl_lock);
2457 bus->rxlen = 0;
2458 spin_unlock_bh(&bus->rxctl_lock);
2459 brcmf_sdio_dcmd_resp_wake(bus);
2460
2461 /* Reset some F2 state stuff */
2462 bus->rxskip = false;
2463 bus->tx_seq = bus->rx_seq = 0;
2464 }
2465
2466 static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus)
2467 {
2468 struct brcmf_sdio_dev *sdiodev;
2469 unsigned long flags;
2470
2471 sdiodev = bus->sdiodev;
2472 if (sdiodev->oob_irq_requested) {
2473 spin_lock_irqsave(&sdiodev->irq_en_lock, flags);
2474 if (!sdiodev->irq_en && !atomic_read(&bus->ipend)) {
2475 enable_irq(sdiodev->settings->bus.sdio.oob_irq_nr);
2476 sdiodev->irq_en = true;
2477 }
2478 spin_unlock_irqrestore(&sdiodev->irq_en_lock, flags);
2479 }
2480 }
2481
2482 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
2483 {
2484 struct brcmf_core *buscore;
2485 u32 addr;
2486 unsigned long val;
2487 int ret;
2488
2489 buscore = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
2490 addr = buscore->base + offsetof(struct sdpcmd_regs, intstatus);
2491
2492 val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret);
2493 bus->sdcnt.f1regdata++;
2494 if (ret != 0)
2495 return ret;
2496
2497 val &= bus->hostintmask;
2498 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE));
2499
2500 /* Clear interrupts */
2501 if (val) {
2502 brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret);
2503 bus->sdcnt.f1regdata++;
2504 atomic_or(val, &bus->intstatus);
2505 }
2506
2507 return ret;
2508 }
2509
2510 static void brcmf_sdio_dpc(struct brcmf_sdio *bus)
2511 {
2512 u32 newstatus = 0;
2513 unsigned long intstatus;
2514 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2515 uint framecnt; /* Temporary counter of tx/rx frames */
2516 int err = 0;
2517
2518 brcmf_dbg(TRACE, "Enter\n");
2519
2520 sdio_claim_host(bus->sdiodev->func[1]);
2521
2522 /* If waiting for HTAVAIL, check status */
2523 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) {
2524 u8 clkctl, devctl = 0;
2525
2526 #ifdef DEBUG
2527 /* Check for inconsistent device control */
2528 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2529 SBSDIO_DEVICE_CTL, &err);
2530 #endif /* DEBUG */
2531
2532 /* Read CSR, if clock on switch to AVAIL, else ignore */
2533 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
2534 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2535
2536 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2537 devctl, clkctl);
2538
2539 if (SBSDIO_HTAV(clkctl)) {
2540 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2541 SBSDIO_DEVICE_CTL, &err);
2542 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2543 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
2544 devctl, &err);
2545 bus->clkstate = CLK_AVAIL;
2546 }
2547 }
2548
2549 /* Make sure backplane clock is on */
2550 brcmf_sdio_bus_sleep(bus, false, true);
2551
2552 /* Pending interrupt indicates new device status */
2553 if (atomic_read(&bus->ipend) > 0) {
2554 atomic_set(&bus->ipend, 0);
2555 err = brcmf_sdio_intr_rstatus(bus);
2556 }
2557
2558 /* Start with leftover status bits */
2559 intstatus = atomic_xchg(&bus->intstatus, 0);
2560
2561 /* Handle flow-control change: read new state in case our ack
2562 * crossed another change interrupt. If change still set, assume
2563 * FC ON for safety, let next loop through do the debounce.
2564 */
2565 if (intstatus & I_HMB_FC_CHANGE) {
2566 intstatus &= ~I_HMB_FC_CHANGE;
2567 err = w_sdreg32(bus, I_HMB_FC_CHANGE,
2568 offsetof(struct sdpcmd_regs, intstatus));
2569
2570 err = r_sdreg32(bus, &newstatus,
2571 offsetof(struct sdpcmd_regs, intstatus));
2572 bus->sdcnt.f1regdata += 2;
2573 atomic_set(&bus->fcstate,
2574 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)));
2575 intstatus |= (newstatus & bus->hostintmask);
2576 }
2577
2578 /* Handle host mailbox indication */
2579 if (intstatus & I_HMB_HOST_INT) {
2580 intstatus &= ~I_HMB_HOST_INT;
2581 intstatus |= brcmf_sdio_hostmail(bus);
2582 }
2583
2584 sdio_release_host(bus->sdiodev->func[1]);
2585
2586 /* Generally don't ask for these, can get CRC errors... */
2587 if (intstatus & I_WR_OOSYNC) {
2588 brcmf_err("Dongle reports WR_OOSYNC\n");
2589 intstatus &= ~I_WR_OOSYNC;
2590 }
2591
2592 if (intstatus & I_RD_OOSYNC) {
2593 brcmf_err("Dongle reports RD_OOSYNC\n");
2594 intstatus &= ~I_RD_OOSYNC;
2595 }
2596
2597 if (intstatus & I_SBINT) {
2598 brcmf_err("Dongle reports SBINT\n");
2599 intstatus &= ~I_SBINT;
2600 }
2601
2602 /* Would be active due to wake-wlan in gSPI */
2603 if (intstatus & I_CHIPACTIVE) {
2604 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2605 intstatus &= ~I_CHIPACTIVE;
2606 }
2607
2608 /* Ignore frame indications if rxskip is set */
2609 if (bus->rxskip)
2610 intstatus &= ~I_HMB_FRAME_IND;
2611
2612 /* On frame indication, read available frames */
2613 if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) {
2614 brcmf_sdio_readframes(bus, bus->rxbound);
2615 if (!bus->rxpending)
2616 intstatus &= ~I_HMB_FRAME_IND;
2617 }
2618
2619 /* Keep still-pending events for next scheduling */
2620 if (intstatus)
2621 atomic_or(intstatus, &bus->intstatus);
2622
2623 brcmf_sdio_clrintr(bus);
2624
2625 if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) &&
2626 data_ok(bus)) {
2627 sdio_claim_host(bus->sdiodev->func[1]);
2628 if (bus->ctrl_frame_stat) {
2629 err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf,
2630 bus->ctrl_frame_len);
2631 bus->ctrl_frame_err = err;
2632 wmb();
2633 bus->ctrl_frame_stat = false;
2634 }
2635 sdio_release_host(bus->sdiodev->func[1]);
2636 brcmf_sdio_wait_event_wakeup(bus);
2637 }
2638 /* Send queued frames (limit 1 if rx may still be pending) */
2639 if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
2640 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit &&
2641 data_ok(bus)) {
2642 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
2643 txlimit;
2644 brcmf_sdio_sendfromq(bus, framecnt);
2645 }
2646
2647 if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) {
2648 brcmf_err("failed backplane access over SDIO, halting operation\n");
2649 atomic_set(&bus->intstatus, 0);
2650 if (bus->ctrl_frame_stat) {
2651 sdio_claim_host(bus->sdiodev->func[1]);
2652 if (bus->ctrl_frame_stat) {
2653 bus->ctrl_frame_err = -ENODEV;
2654 wmb();
2655 bus->ctrl_frame_stat = false;
2656 brcmf_sdio_wait_event_wakeup(bus);
2657 }
2658 sdio_release_host(bus->sdiodev->func[1]);
2659 }
2660 } else if (atomic_read(&bus->intstatus) ||
2661 atomic_read(&bus->ipend) > 0 ||
2662 (!atomic_read(&bus->fcstate) &&
2663 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
2664 data_ok(bus))) {
2665 bus->dpc_triggered = true;
2666 }
2667 }
2668
2669 static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev)
2670 {
2671 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2672 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2673 struct brcmf_sdio *bus = sdiodev->bus;
2674
2675 return &bus->txq;
2676 }
2677
2678 static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec)
2679 {
2680 struct sk_buff *p;
2681 int eprec = -1; /* precedence to evict from */
2682
2683 /* Fast case, precedence queue is not full and we are also not
2684 * exceeding total queue length
2685 */
2686 if (!pktq_pfull(q, prec) && !pktq_full(q)) {
2687 brcmu_pktq_penq(q, prec, pkt);
2688 return true;
2689 }
2690
2691 /* Determine precedence from which to evict packet, if any */
2692 if (pktq_pfull(q, prec)) {
2693 eprec = prec;
2694 } else if (pktq_full(q)) {
2695 p = brcmu_pktq_peek_tail(q, &eprec);
2696 if (eprec > prec)
2697 return false;
2698 }
2699
2700 /* Evict if needed */
2701 if (eprec >= 0) {
2702 /* Detect queueing to unconfigured precedence */
2703 if (eprec == prec)
2704 return false; /* refuse newer (incoming) packet */
2705 /* Evict packet according to discard policy */
2706 p = brcmu_pktq_pdeq_tail(q, eprec);
2707 if (p == NULL)
2708 brcmf_err("brcmu_pktq_pdeq_tail() failed\n");
2709 brcmu_pkt_buf_free_skb(p);
2710 }
2711
2712 /* Enqueue */
2713 p = brcmu_pktq_penq(q, prec, pkt);
2714 if (p == NULL)
2715 brcmf_err("brcmu_pktq_penq() failed\n");
2716
2717 return p != NULL;
2718 }
2719
2720 static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt)
2721 {
2722 int ret = -EBADE;
2723 uint prec;
2724 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2725 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2726 struct brcmf_sdio *bus = sdiodev->bus;
2727
2728 brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len);
2729 if (sdiodev->state != BRCMF_SDIOD_DATA)
2730 return -EIO;
2731
2732 /* Add space for the header */
2733 skb_push(pkt, bus->tx_hdrlen);
2734 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2735
2736 prec = prio2prec((pkt->priority & PRIOMASK));
2737
2738 /* Check for existing queue, current flow-control,
2739 pending event, or pending clock */
2740 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2741 bus->sdcnt.fcqueued++;
2742
2743 /* Priority based enq */
2744 spin_lock_bh(&bus->txq_lock);
2745 /* reset bus_flags in packet cb */
2746 *(u16 *)(pkt->cb) = 0;
2747 if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) {
2748 skb_pull(pkt, bus->tx_hdrlen);
2749 brcmf_err("out of bus->txq !!!\n");
2750 ret = -ENOSR;
2751 } else {
2752 ret = 0;
2753 }
2754
2755 if (pktq_len(&bus->txq) >= TXHI) {
2756 bus->txoff = true;
2757 brcmf_txflowblock(dev, true);
2758 }
2759 spin_unlock_bh(&bus->txq_lock);
2760
2761 #ifdef DEBUG
2762 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2763 qcount[prec] = pktq_plen(&bus->txq, prec);
2764 #endif
2765
2766 brcmf_sdio_trigger_dpc(bus);
2767 return ret;
2768 }
2769
2770 #ifdef DEBUG
2771 #define CONSOLE_LINE_MAX 192
2772
2773 static int brcmf_sdio_readconsole(struct brcmf_sdio *bus)
2774 {
2775 struct brcmf_console *c = &bus->console;
2776 u8 line[CONSOLE_LINE_MAX], ch;
2777 u32 n, idx, addr;
2778 int rv;
2779
2780 /* Don't do anything until FWREADY updates console address */
2781 if (bus->console_addr == 0)
2782 return 0;
2783
2784 /* Read console log struct */
2785 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2786 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
2787 sizeof(c->log_le));
2788 if (rv < 0)
2789 return rv;
2790
2791 /* Allocate console buffer (one time only) */
2792 if (c->buf == NULL) {
2793 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2794 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2795 if (c->buf == NULL)
2796 return -ENOMEM;
2797 }
2798
2799 idx = le32_to_cpu(c->log_le.idx);
2800
2801 /* Protect against corrupt value */
2802 if (idx > c->bufsize)
2803 return -EBADE;
2804
2805 /* Skip reading the console buffer if the index pointer
2806 has not moved */
2807 if (idx == c->last)
2808 return 0;
2809
2810 /* Read the console buffer */
2811 addr = le32_to_cpu(c->log_le.buf);
2812 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
2813 if (rv < 0)
2814 return rv;
2815
2816 while (c->last != idx) {
2817 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2818 if (c->last == idx) {
2819 /* This would output a partial line.
2820 * Instead, back up
2821 * the buffer pointer and output this
2822 * line next time around.
2823 */
2824 if (c->last >= n)
2825 c->last -= n;
2826 else
2827 c->last = c->bufsize - n;
2828 goto break2;
2829 }
2830 ch = c->buf[c->last];
2831 c->last = (c->last + 1) % c->bufsize;
2832 if (ch == '\n')
2833 break;
2834 line[n] = ch;
2835 }
2836
2837 if (n > 0) {
2838 if (line[n - 1] == '\r')
2839 n--;
2840 line[n] = 0;
2841 pr_debug("CONSOLE: %s\n", line);
2842 }
2843 }
2844 break2:
2845
2846 return 0;
2847 }
2848 #endif /* DEBUG */
2849
2850 static int
2851 brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
2852 {
2853 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2854 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2855 struct brcmf_sdio *bus = sdiodev->bus;
2856 int ret;
2857
2858 brcmf_dbg(TRACE, "Enter\n");
2859 if (sdiodev->state != BRCMF_SDIOD_DATA)
2860 return -EIO;
2861
2862 /* Send from dpc */
2863 bus->ctrl_frame_buf = msg;
2864 bus->ctrl_frame_len = msglen;
2865 wmb();
2866 bus->ctrl_frame_stat = true;
2867
2868 brcmf_sdio_trigger_dpc(bus);
2869 wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat,
2870 CTL_DONE_TIMEOUT);
2871 ret = 0;
2872 if (bus->ctrl_frame_stat) {
2873 sdio_claim_host(bus->sdiodev->func[1]);
2874 if (bus->ctrl_frame_stat) {
2875 brcmf_dbg(SDIO, "ctrl_frame timeout\n");
2876 bus->ctrl_frame_stat = false;
2877 ret = -ETIMEDOUT;
2878 }
2879 sdio_release_host(bus->sdiodev->func[1]);
2880 }
2881 if (!ret) {
2882 brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n",
2883 bus->ctrl_frame_err);
2884 rmb();
2885 ret = bus->ctrl_frame_err;
2886 }
2887
2888 if (ret)
2889 bus->sdcnt.tx_ctlerrs++;
2890 else
2891 bus->sdcnt.tx_ctlpkts++;
2892
2893 return ret;
2894 }
2895
2896 #ifdef DEBUG
2897 static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus,
2898 struct sdpcm_shared *sh)
2899 {
2900 u32 addr, console_ptr, console_size, console_index;
2901 char *conbuf = NULL;
2902 __le32 sh_val;
2903 int rv;
2904
2905 /* obtain console information from device memory */
2906 addr = sh->console_addr + offsetof(struct rte_console, log_le);
2907 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2908 (u8 *)&sh_val, sizeof(u32));
2909 if (rv < 0)
2910 return rv;
2911 console_ptr = le32_to_cpu(sh_val);
2912
2913 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
2914 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2915 (u8 *)&sh_val, sizeof(u32));
2916 if (rv < 0)
2917 return rv;
2918 console_size = le32_to_cpu(sh_val);
2919
2920 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
2921 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2922 (u8 *)&sh_val, sizeof(u32));
2923 if (rv < 0)
2924 return rv;
2925 console_index = le32_to_cpu(sh_val);
2926
2927 /* allocate buffer for console data */
2928 if (console_size <= CONSOLE_BUFFER_MAX)
2929 conbuf = vzalloc(console_size+1);
2930
2931 if (!conbuf)
2932 return -ENOMEM;
2933
2934 /* obtain the console data from device */
2935 conbuf[console_size] = '\0';
2936 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
2937 console_size);
2938 if (rv < 0)
2939 goto done;
2940
2941 rv = seq_write(seq, conbuf + console_index,
2942 console_size - console_index);
2943 if (rv < 0)
2944 goto done;
2945
2946 if (console_index > 0)
2947 rv = seq_write(seq, conbuf, console_index - 1);
2948
2949 done:
2950 vfree(conbuf);
2951 return rv;
2952 }
2953
2954 static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus,
2955 struct sdpcm_shared *sh)
2956 {
2957 int error;
2958 struct brcmf_trap_info tr;
2959
2960 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) {
2961 brcmf_dbg(INFO, "no trap in firmware\n");
2962 return 0;
2963 }
2964
2965 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
2966 sizeof(struct brcmf_trap_info));
2967 if (error < 0)
2968 return error;
2969
2970 seq_printf(seq,
2971 "dongle trap info: type 0x%x @ epc 0x%08x\n"
2972 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
2973 " lr 0x%08x pc 0x%08x offset 0x%x\n"
2974 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
2975 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
2976 le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
2977 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
2978 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
2979 le32_to_cpu(tr.pc), sh->trap_addr,
2980 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
2981 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
2982 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
2983 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
2984
2985 return 0;
2986 }
2987
2988 static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus,
2989 struct sdpcm_shared *sh)
2990 {
2991 int error = 0;
2992 char file[80] = "?";
2993 char expr[80] = "<???>";
2994
2995 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
2996 brcmf_dbg(INFO, "firmware not built with -assert\n");
2997 return 0;
2998 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
2999 brcmf_dbg(INFO, "no assert in dongle\n");
3000 return 0;
3001 }
3002
3003 sdio_claim_host(bus->sdiodev->func[1]);
3004 if (sh->assert_file_addr != 0) {
3005 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3006 sh->assert_file_addr, (u8 *)file, 80);
3007 if (error < 0)
3008 return error;
3009 }
3010 if (sh->assert_exp_addr != 0) {
3011 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3012 sh->assert_exp_addr, (u8 *)expr, 80);
3013 if (error < 0)
3014 return error;
3015 }
3016 sdio_release_host(bus->sdiodev->func[1]);
3017
3018 seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n",
3019 file, sh->assert_line, expr);
3020 return 0;
3021 }
3022
3023 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3024 {
3025 int error;
3026 struct sdpcm_shared sh;
3027
3028 error = brcmf_sdio_readshared(bus, &sh);
3029
3030 if (error < 0)
3031 return error;
3032
3033 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
3034 brcmf_dbg(INFO, "firmware not built with -assert\n");
3035 else if (sh.flags & SDPCM_SHARED_ASSERT)
3036 brcmf_err("assertion in dongle\n");
3037
3038 if (sh.flags & SDPCM_SHARED_TRAP)
3039 brcmf_err("firmware trap in dongle\n");
3040
3041 return 0;
3042 }
3043
3044 static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus)
3045 {
3046 int error = 0;
3047 struct sdpcm_shared sh;
3048
3049 error = brcmf_sdio_readshared(bus, &sh);
3050 if (error < 0)
3051 goto done;
3052
3053 error = brcmf_sdio_assert_info(seq, bus, &sh);
3054 if (error < 0)
3055 goto done;
3056
3057 error = brcmf_sdio_trap_info(seq, bus, &sh);
3058 if (error < 0)
3059 goto done;
3060
3061 error = brcmf_sdio_dump_console(seq, bus, &sh);
3062
3063 done:
3064 return error;
3065 }
3066
3067 static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data)
3068 {
3069 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3070 struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus;
3071
3072 return brcmf_sdio_died_dump(seq, bus);
3073 }
3074
3075 static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data)
3076 {
3077 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3078 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3079 struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt;
3080
3081 seq_printf(seq,
3082 "intrcount: %u\nlastintrs: %u\n"
3083 "pollcnt: %u\nregfails: %u\n"
3084 "tx_sderrs: %u\nfcqueued: %u\n"
3085 "rxrtx: %u\nrx_toolong: %u\n"
3086 "rxc_errors: %u\nrx_hdrfail: %u\n"
3087 "rx_badhdr: %u\nrx_badseq: %u\n"
3088 "fc_rcvd: %u\nfc_xoff: %u\n"
3089 "fc_xon: %u\nrxglomfail: %u\n"
3090 "rxglomframes: %u\nrxglompkts: %u\n"
3091 "f2rxhdrs: %u\nf2rxdata: %u\n"
3092 "f2txdata: %u\nf1regdata: %u\n"
3093 "tickcnt: %u\ntx_ctlerrs: %lu\n"
3094 "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n"
3095 "rx_ctlpkts: %lu\nrx_readahead: %lu\n",
3096 sdcnt->intrcount, sdcnt->lastintrs,
3097 sdcnt->pollcnt, sdcnt->regfails,
3098 sdcnt->tx_sderrs, sdcnt->fcqueued,
3099 sdcnt->rxrtx, sdcnt->rx_toolong,
3100 sdcnt->rxc_errors, sdcnt->rx_hdrfail,
3101 sdcnt->rx_badhdr, sdcnt->rx_badseq,
3102 sdcnt->fc_rcvd, sdcnt->fc_xoff,
3103 sdcnt->fc_xon, sdcnt->rxglomfail,
3104 sdcnt->rxglomframes, sdcnt->rxglompkts,
3105 sdcnt->f2rxhdrs, sdcnt->f2rxdata,
3106 sdcnt->f2txdata, sdcnt->f1regdata,
3107 sdcnt->tickcnt, sdcnt->tx_ctlerrs,
3108 sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs,
3109 sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt);
3110
3111 return 0;
3112 }
3113
3114 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3115 {
3116 struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr;
3117 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
3118
3119 if (IS_ERR_OR_NULL(dentry))
3120 return;
3121
3122 bus->console_interval = BRCMF_CONSOLE;
3123
3124 brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read);
3125 brcmf_debugfs_add_entry(drvr, "counters",
3126 brcmf_debugfs_sdio_count_read);
3127 debugfs_create_u32("console_interval", 0644, dentry,
3128 &bus->console_interval);
3129 }
3130 #else
3131 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3132 {
3133 return 0;
3134 }
3135
3136 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3137 {
3138 }
3139 #endif /* DEBUG */
3140
3141 static int
3142 brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
3143 {
3144 int timeleft;
3145 uint rxlen = 0;
3146 bool pending;
3147 u8 *buf;
3148 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3149 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3150 struct brcmf_sdio *bus = sdiodev->bus;
3151
3152 brcmf_dbg(TRACE, "Enter\n");
3153 if (sdiodev->state != BRCMF_SDIOD_DATA)
3154 return -EIO;
3155
3156 /* Wait until control frame is available */
3157 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3158
3159 spin_lock_bh(&bus->rxctl_lock);
3160 rxlen = bus->rxlen;
3161 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3162 bus->rxctl = NULL;
3163 buf = bus->rxctl_orig;
3164 bus->rxctl_orig = NULL;
3165 bus->rxlen = 0;
3166 spin_unlock_bh(&bus->rxctl_lock);
3167 vfree(buf);
3168
3169 if (rxlen) {
3170 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3171 rxlen, msglen);
3172 } else if (timeleft == 0) {
3173 brcmf_err("resumed on timeout\n");
3174 brcmf_sdio_checkdied(bus);
3175 } else if (pending) {
3176 brcmf_dbg(CTL, "cancelled\n");
3177 return -ERESTARTSYS;
3178 } else {
3179 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3180 brcmf_sdio_checkdied(bus);
3181 }
3182
3183 if (rxlen)
3184 bus->sdcnt.rx_ctlpkts++;
3185 else
3186 bus->sdcnt.rx_ctlerrs++;
3187
3188 return rxlen ? (int)rxlen : -ETIMEDOUT;
3189 }
3190
3191 #ifdef DEBUG
3192 static bool
3193 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3194 u8 *ram_data, uint ram_sz)
3195 {
3196 char *ram_cmp;
3197 int err;
3198 bool ret = true;
3199 int address;
3200 int offset;
3201 int len;
3202
3203 /* read back and verify */
3204 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr,
3205 ram_sz);
3206 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL);
3207 /* do not proceed while no memory but */
3208 if (!ram_cmp)
3209 return true;
3210
3211 address = ram_addr;
3212 offset = 0;
3213 while (offset < ram_sz) {
3214 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK :
3215 ram_sz - offset;
3216 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len);
3217 if (err) {
3218 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3219 err, len, address);
3220 ret = false;
3221 break;
3222 } else if (memcmp(ram_cmp, &ram_data[offset], len)) {
3223 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n",
3224 offset, len);
3225 ret = false;
3226 break;
3227 }
3228 offset += len;
3229 address += len;
3230 }
3231
3232 kfree(ram_cmp);
3233
3234 return ret;
3235 }
3236 #else /* DEBUG */
3237 static bool
3238 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3239 u8 *ram_data, uint ram_sz)
3240 {
3241 return true;
3242 }
3243 #endif /* DEBUG */
3244
3245 static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
3246 const struct firmware *fw)
3247 {
3248 int err;
3249
3250 brcmf_dbg(TRACE, "Enter\n");
3251
3252 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase,
3253 (u8 *)fw->data, fw->size);
3254 if (err)
3255 brcmf_err("error %d on writing %d membytes at 0x%08x\n",
3256 err, (int)fw->size, bus->ci->rambase);
3257 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase,
3258 (u8 *)fw->data, fw->size))
3259 err = -EIO;
3260
3261 return err;
3262 }
3263
3264 static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus,
3265 void *vars, u32 varsz)
3266 {
3267 int address;
3268 int err;
3269
3270 brcmf_dbg(TRACE, "Enter\n");
3271
3272 address = bus->ci->ramsize - varsz + bus->ci->rambase;
3273 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz);
3274 if (err)
3275 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
3276 err, varsz, address);
3277 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz))
3278 err = -EIO;
3279
3280 return err;
3281 }
3282
3283 static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus,
3284 const struct firmware *fw,
3285 void *nvram, u32 nvlen)
3286 {
3287 int bcmerror;
3288 u32 rstvec;
3289
3290 sdio_claim_host(bus->sdiodev->func[1]);
3291 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
3292
3293 rstvec = get_unaligned_le32(fw->data);
3294 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec);
3295
3296 bcmerror = brcmf_sdio_download_code_file(bus, fw);
3297 release_firmware(fw);
3298 if (bcmerror) {
3299 brcmf_err("dongle image file download failed\n");
3300 brcmf_fw_nvram_free(nvram);
3301 goto err;
3302 }
3303
3304 bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen);
3305 brcmf_fw_nvram_free(nvram);
3306 if (bcmerror) {
3307 brcmf_err("dongle nvram file download failed\n");
3308 goto err;
3309 }
3310
3311 /* Take arm out of reset */
3312 if (!brcmf_chip_set_active(bus->ci, rstvec)) {
3313 brcmf_err("error getting out of ARM core reset\n");
3314 goto err;
3315 }
3316
3317 err:
3318 brcmf_sdio_clkctl(bus, CLK_SDONLY, false);
3319 sdio_release_host(bus->sdiodev->func[1]);
3320 return bcmerror;
3321 }
3322
3323 static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
3324 {
3325 int err = 0;
3326 u8 val;
3327
3328 brcmf_dbg(TRACE, "Enter\n");
3329
3330 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
3331 if (err) {
3332 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
3333 return;
3334 }
3335
3336 val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
3337 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
3338 if (err) {
3339 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
3340 return;
3341 }
3342
3343 /* Add CMD14 Support */
3344 brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
3345 (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
3346 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
3347 &err);
3348 if (err) {
3349 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
3350 return;
3351 }
3352
3353 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3354 SBSDIO_FORCE_HT, &err);
3355 if (err) {
3356 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
3357 return;
3358 }
3359
3360 /* set flag */
3361 bus->sr_enabled = true;
3362 brcmf_dbg(INFO, "SR enabled\n");
3363 }
3364
3365 /* enable KSO bit */
3366 static int brcmf_sdio_kso_init(struct brcmf_sdio *bus)
3367 {
3368 u8 val;
3369 int err = 0;
3370
3371 brcmf_dbg(TRACE, "Enter\n");
3372
3373 /* KSO bit added in SDIO core rev 12 */
3374 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12)
3375 return 0;
3376
3377 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
3378 if (err) {
3379 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
3380 return err;
3381 }
3382
3383 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
3384 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
3385 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
3386 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
3387 val, &err);
3388 if (err) {
3389 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
3390 return err;
3391 }
3392 }
3393
3394 return 0;
3395 }
3396
3397
3398 static int brcmf_sdio_bus_preinit(struct device *dev)
3399 {
3400 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3401 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3402 struct brcmf_sdio *bus = sdiodev->bus;
3403 uint pad_size;
3404 u32 value;
3405 int err;
3406
3407 /* the commands below use the terms tx and rx from
3408 * a device perspective, ie. bus:txglom affects the
3409 * bus transfers from device to host.
3410 */
3411 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) {
3412 /* for sdio core rev < 12, disable txgloming */
3413 value = 0;
3414 err = brcmf_iovar_data_set(dev, "bus:txglom", &value,
3415 sizeof(u32));
3416 } else {
3417 /* otherwise, set txglomalign */
3418 value = sdiodev->settings->bus.sdio.sd_sgentry_align;
3419 /* SDIO ADMA requires at least 32 bit alignment */
3420 value = max_t(u32, value, 4);
3421 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value,
3422 sizeof(u32));
3423 }
3424
3425 if (err < 0)
3426 goto done;
3427
3428 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
3429 if (sdiodev->sg_support) {
3430 bus->txglom = false;
3431 value = 1;
3432 pad_size = bus->sdiodev->func[2]->cur_blksize << 1;
3433 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom",
3434 &value, sizeof(u32));
3435 if (err < 0) {
3436 /* bus:rxglom is allowed to fail */
3437 err = 0;
3438 } else {
3439 bus->txglom = true;
3440 bus->tx_hdrlen += SDPCM_HWEXT_LEN;
3441 }
3442 }
3443 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen);
3444
3445 done:
3446 return err;
3447 }
3448
3449 static size_t brcmf_sdio_bus_get_ramsize(struct device *dev)
3450 {
3451 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3452 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3453 struct brcmf_sdio *bus = sdiodev->bus;
3454
3455 return bus->ci->ramsize - bus->ci->srsize;
3456 }
3457
3458 static int brcmf_sdio_bus_get_memdump(struct device *dev, void *data,
3459 size_t mem_size)
3460 {
3461 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3462 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3463 struct brcmf_sdio *bus = sdiodev->bus;
3464 int err;
3465 int address;
3466 int offset;
3467 int len;
3468
3469 brcmf_dbg(INFO, "dump at 0x%08x: size=%zu\n", bus->ci->rambase,
3470 mem_size);
3471
3472 address = bus->ci->rambase;
3473 offset = err = 0;
3474 sdio_claim_host(sdiodev->func[1]);
3475 while (offset < mem_size) {
3476 len = ((offset + MEMBLOCK) < mem_size) ? MEMBLOCK :
3477 mem_size - offset;
3478 err = brcmf_sdiod_ramrw(sdiodev, false, address, data, len);
3479 if (err) {
3480 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3481 err, len, address);
3482 goto done;
3483 }
3484 data += len;
3485 offset += len;
3486 address += len;
3487 }
3488
3489 done:
3490 sdio_release_host(sdiodev->func[1]);
3491 return err;
3492 }
3493
3494 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus)
3495 {
3496 if (!bus->dpc_triggered) {
3497 bus->dpc_triggered = true;
3498 queue_work(bus->brcmf_wq, &bus->datawork);
3499 }
3500 }
3501
3502 void brcmf_sdio_isr(struct brcmf_sdio *bus)
3503 {
3504 brcmf_dbg(TRACE, "Enter\n");
3505
3506 if (!bus) {
3507 brcmf_err("bus is null pointer, exiting\n");
3508 return;
3509 }
3510
3511 /* Count the interrupt call */
3512 bus->sdcnt.intrcount++;
3513 if (in_interrupt())
3514 atomic_set(&bus->ipend, 1);
3515 else
3516 if (brcmf_sdio_intr_rstatus(bus)) {
3517 brcmf_err("failed backplane access\n");
3518 }
3519
3520 /* Disable additional interrupts (is this needed now)? */
3521 if (!bus->intr)
3522 brcmf_err("isr w/o interrupt configured!\n");
3523
3524 bus->dpc_triggered = true;
3525 queue_work(bus->brcmf_wq, &bus->datawork);
3526 }
3527
3528 static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus)
3529 {
3530 brcmf_dbg(TIMER, "Enter\n");
3531
3532 /* Poll period: check device if appropriate. */
3533 if (!bus->sr_enabled &&
3534 bus->poll && (++bus->polltick >= bus->pollrate)) {
3535 u32 intstatus = 0;
3536
3537 /* Reset poll tick */
3538 bus->polltick = 0;
3539
3540 /* Check device if no interrupts */
3541 if (!bus->intr ||
3542 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
3543
3544 if (!bus->dpc_triggered) {
3545 u8 devpend;
3546
3547 sdio_claim_host(bus->sdiodev->func[1]);
3548 devpend = brcmf_sdiod_regrb(bus->sdiodev,
3549 SDIO_CCCR_INTx,
3550 NULL);
3551 sdio_release_host(bus->sdiodev->func[1]);
3552 intstatus = devpend & (INTR_STATUS_FUNC1 |
3553 INTR_STATUS_FUNC2);
3554 }
3555
3556 /* If there is something, make like the ISR and
3557 schedule the DPC */
3558 if (intstatus) {
3559 bus->sdcnt.pollcnt++;
3560 atomic_set(&bus->ipend, 1);
3561
3562 bus->dpc_triggered = true;
3563 queue_work(bus->brcmf_wq, &bus->datawork);
3564 }
3565 }
3566
3567 /* Update interrupt tracking */
3568 bus->sdcnt.lastintrs = bus->sdcnt.intrcount;
3569 }
3570 #ifdef DEBUG
3571 /* Poll for console output periodically */
3572 if (bus->sdiodev->state == BRCMF_SDIOD_DATA && BRCMF_FWCON_ON() &&
3573 bus->console_interval != 0) {
3574 bus->console.count += jiffies_to_msecs(BRCMF_WD_POLL);
3575 if (bus->console.count >= bus->console_interval) {
3576 bus->console.count -= bus->console_interval;
3577 sdio_claim_host(bus->sdiodev->func[1]);
3578 /* Make sure backplane clock is on */
3579 brcmf_sdio_bus_sleep(bus, false, false);
3580 if (brcmf_sdio_readconsole(bus) < 0)
3581 /* stop on error */
3582 bus->console_interval = 0;
3583 sdio_release_host(bus->sdiodev->func[1]);
3584 }
3585 }
3586 #endif /* DEBUG */
3587
3588 /* On idle timeout clear activity flag and/or turn off clock */
3589 if (!bus->dpc_triggered) {
3590 rmb();
3591 if ((!bus->dpc_running) && (bus->idletime > 0) &&
3592 (bus->clkstate == CLK_AVAIL)) {
3593 bus->idlecount++;
3594 if (bus->idlecount > bus->idletime) {
3595 brcmf_dbg(SDIO, "idle\n");
3596 sdio_claim_host(bus->sdiodev->func[1]);
3597 brcmf_sdio_wd_timer(bus, false);
3598 bus->idlecount = 0;
3599 brcmf_sdio_bus_sleep(bus, true, false);
3600 sdio_release_host(bus->sdiodev->func[1]);
3601 }
3602 } else {
3603 bus->idlecount = 0;
3604 }
3605 } else {
3606 bus->idlecount = 0;
3607 }
3608 }
3609
3610 static void brcmf_sdio_dataworker(struct work_struct *work)
3611 {
3612 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
3613 datawork);
3614
3615 bus->dpc_running = true;
3616 wmb();
3617 while (ACCESS_ONCE(bus->dpc_triggered)) {
3618 bus->dpc_triggered = false;
3619 brcmf_sdio_dpc(bus);
3620 bus->idlecount = 0;
3621 }
3622 bus->dpc_running = false;
3623 if (brcmf_sdiod_freezing(bus->sdiodev)) {
3624 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN);
3625 brcmf_sdiod_try_freeze(bus->sdiodev);
3626 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
3627 }
3628 }
3629
3630 static void
3631 brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
3632 struct brcmf_chip *ci, u32 drivestrength)
3633 {
3634 const struct sdiod_drive_str *str_tab = NULL;
3635 u32 str_mask;
3636 u32 str_shift;
3637 u32 i;
3638 u32 drivestrength_sel = 0;
3639 u32 cc_data_temp;
3640 u32 addr;
3641
3642 if (!(ci->cc_caps & CC_CAP_PMU))
3643 return;
3644
3645 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) {
3646 case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12):
3647 str_tab = sdiod_drvstr_tab1_1v8;
3648 str_mask = 0x00003800;
3649 str_shift = 11;
3650 break;
3651 case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17):
3652 str_tab = sdiod_drvstr_tab6_1v8;
3653 str_mask = 0x00001800;
3654 str_shift = 11;
3655 break;
3656 case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17):
3657 /* note: 43143 does not support tristate */
3658 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1;
3659 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) {
3660 str_tab = sdiod_drvstr_tab2_3v3;
3661 str_mask = 0x00000007;
3662 str_shift = 0;
3663 } else
3664 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n",
3665 ci->name, drivestrength);
3666 break;
3667 case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13):
3668 str_tab = sdiod_drive_strength_tab5_1v8;
3669 str_mask = 0x00003800;
3670 str_shift = 11;
3671 break;
3672 default:
3673 brcmf_dbg(INFO, "No SDIO driver strength init needed for chip %s rev %d pmurev %d\n",
3674 ci->name, ci->chiprev, ci->pmurev);
3675 break;
3676 }
3677
3678 if (str_tab != NULL) {
3679 struct brcmf_core *pmu = brcmf_chip_get_pmu(ci);
3680
3681 for (i = 0; str_tab[i].strength != 0; i++) {
3682 if (drivestrength >= str_tab[i].strength) {
3683 drivestrength_sel = str_tab[i].sel;
3684 break;
3685 }
3686 }
3687 addr = CORE_CC_REG(pmu->base, chipcontrol_addr);
3688 brcmf_sdiod_regwl(sdiodev, addr, 1, NULL);
3689 cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3690 cc_data_temp &= ~str_mask;
3691 drivestrength_sel <<= str_shift;
3692 cc_data_temp |= drivestrength_sel;
3693 brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL);
3694
3695 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
3696 str_tab[i].strength, drivestrength, cc_data_temp);
3697 }
3698 }
3699
3700 static int brcmf_sdio_buscoreprep(void *ctx)
3701 {
3702 struct brcmf_sdio_dev *sdiodev = ctx;
3703 int err = 0;
3704 u8 clkval, clkset;
3705
3706 /* Try forcing SDIO core to do ALPAvail request only */
3707 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
3708 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3709 if (err) {
3710 brcmf_err("error writing for HT off\n");
3711 return err;
3712 }
3713
3714 /* If register supported, wait for ALPAvail and then force ALP */
3715 /* This may take up to 15 milliseconds */
3716 clkval = brcmf_sdiod_regrb(sdiodev,
3717 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
3718
3719 if ((clkval & ~SBSDIO_AVBITS) != clkset) {
3720 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
3721 clkset, clkval);
3722 return -EACCES;
3723 }
3724
3725 SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev,
3726 SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
3727 !SBSDIO_ALPAV(clkval)),
3728 PMU_MAX_TRANSITION_DLY);
3729 if (!SBSDIO_ALPAV(clkval)) {
3730 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n",
3731 clkval);
3732 return -EBUSY;
3733 }
3734
3735 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
3736 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3737 udelay(65);
3738
3739 /* Also, disable the extra SDIO pull-ups */
3740 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
3741
3742 return 0;
3743 }
3744
3745 static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip,
3746 u32 rstvec)
3747 {
3748 struct brcmf_sdio_dev *sdiodev = ctx;
3749 struct brcmf_core *core;
3750 u32 reg_addr;
3751
3752 /* clear all interrupts */
3753 core = brcmf_chip_get_core(chip, BCMA_CORE_SDIO_DEV);
3754 reg_addr = core->base + offsetof(struct sdpcmd_regs, intstatus);
3755 brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
3756
3757 if (rstvec)
3758 /* Write reset vector to address 0 */
3759 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec,
3760 sizeof(rstvec));
3761 }
3762
3763 static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr)
3764 {
3765 struct brcmf_sdio_dev *sdiodev = ctx;
3766 u32 val, rev;
3767
3768 val = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3769 if ((sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 ||
3770 sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4339) &&
3771 addr == CORE_CC_REG(SI_ENUM_BASE, chipid)) {
3772 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT;
3773 if (rev >= 2) {
3774 val &= ~CID_ID_MASK;
3775 val |= BRCM_CC_4339_CHIP_ID;
3776 }
3777 }
3778 return val;
3779 }
3780
3781 static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val)
3782 {
3783 struct brcmf_sdio_dev *sdiodev = ctx;
3784
3785 brcmf_sdiod_regwl(sdiodev, addr, val, NULL);
3786 }
3787
3788 static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = {
3789 .prepare = brcmf_sdio_buscoreprep,
3790 .activate = brcmf_sdio_buscore_activate,
3791 .read32 = brcmf_sdio_buscore_read32,
3792 .write32 = brcmf_sdio_buscore_write32,
3793 };
3794
3795 static bool
3796 brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
3797 {
3798 struct brcmf_sdio_dev *sdiodev;
3799 u8 clkctl = 0;
3800 int err = 0;
3801 int reg_addr;
3802 u32 reg_val;
3803 u32 drivestrength;
3804
3805 sdiodev = bus->sdiodev;
3806 sdio_claim_host(sdiodev->func[1]);
3807
3808 pr_debug("F1 signature read @0x18000000=0x%4x\n",
3809 brcmf_sdiod_regrl(sdiodev, SI_ENUM_BASE, NULL));
3810
3811 /*
3812 * Force PLL off until brcmf_chip_attach()
3813 * programs PLL control regs
3814 */
3815
3816 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3817 BRCMF_INIT_CLKCTL1, &err);
3818 if (!err)
3819 clkctl = brcmf_sdiod_regrb(sdiodev,
3820 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3821
3822 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
3823 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
3824 err, BRCMF_INIT_CLKCTL1, clkctl);
3825 goto fail;
3826 }
3827
3828 bus->ci = brcmf_chip_attach(sdiodev, &brcmf_sdio_buscore_ops);
3829 if (IS_ERR(bus->ci)) {
3830 brcmf_err("brcmf_chip_attach failed!\n");
3831 bus->ci = NULL;
3832 goto fail;
3833 }
3834 sdiodev->settings = brcmf_get_module_param(sdiodev->dev,
3835 BRCMF_BUSTYPE_SDIO,
3836 bus->ci->chip,
3837 bus->ci->chiprev);
3838 if (!sdiodev->settings) {
3839 brcmf_err("Failed to get device parameters\n");
3840 goto fail;
3841 }
3842 /* platform specific configuration:
3843 * alignments must be at least 4 bytes for ADMA
3844 */
3845 bus->head_align = ALIGNMENT;
3846 bus->sgentry_align = ALIGNMENT;
3847 if (sdiodev->settings->bus.sdio.sd_head_align > ALIGNMENT)
3848 bus->head_align = sdiodev->settings->bus.sdio.sd_head_align;
3849 if (sdiodev->settings->bus.sdio.sd_sgentry_align > ALIGNMENT)
3850 bus->sgentry_align =
3851 sdiodev->settings->bus.sdio.sd_sgentry_align;
3852
3853 /* allocate scatter-gather table. sg support
3854 * will be disabled upon allocation failure.
3855 */
3856 brcmf_sdiod_sgtable_alloc(sdiodev);
3857
3858 #ifdef CONFIG_PM_SLEEP
3859 /* wowl can be supported when KEEP_POWER is true and (WAKE_SDIO_IRQ
3860 * is true or when platform data OOB irq is true).
3861 */
3862 if ((sdio_get_host_pm_caps(sdiodev->func[1]) & MMC_PM_KEEP_POWER) &&
3863 ((sdio_get_host_pm_caps(sdiodev->func[1]) & MMC_PM_WAKE_SDIO_IRQ) ||
3864 (sdiodev->settings->bus.sdio.oob_irq_supported)))
3865 sdiodev->bus_if->wowl_supported = true;
3866 #endif
3867
3868 if (brcmf_sdio_kso_init(bus)) {
3869 brcmf_err("error enabling KSO\n");
3870 goto fail;
3871 }
3872
3873 if (sdiodev->settings->bus.sdio.drive_strength)
3874 drivestrength = sdiodev->settings->bus.sdio.drive_strength;
3875 else
3876 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH;
3877 brcmf_sdio_drivestrengthinit(sdiodev, bus->ci, drivestrength);
3878
3879 /* Set card control so an SDIO card reset does a WLAN backplane reset */
3880 reg_val = brcmf_sdiod_regrb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err);
3881 if (err)
3882 goto fail;
3883
3884 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
3885
3886 brcmf_sdiod_regwb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
3887 if (err)
3888 goto fail;
3889
3890 /* set PMUControl so a backplane reset does PMU state reload */
3891 reg_addr = CORE_CC_REG(brcmf_chip_get_pmu(bus->ci)->base, pmucontrol);
3892 reg_val = brcmf_sdiod_regrl(sdiodev, reg_addr, &err);
3893 if (err)
3894 goto fail;
3895
3896 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
3897
3898 brcmf_sdiod_regwl(sdiodev, reg_addr, reg_val, &err);
3899 if (err)
3900 goto fail;
3901
3902 sdio_release_host(sdiodev->func[1]);
3903
3904 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
3905
3906 /* allocate header buffer */
3907 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL);
3908 if (!bus->hdrbuf)
3909 return false;
3910 /* Locate an appropriately-aligned portion of hdrbuf */
3911 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
3912 bus->head_align);
3913
3914 /* Set the poll and/or interrupt flags */
3915 bus->intr = true;
3916 bus->poll = false;
3917 if (bus->poll)
3918 bus->pollrate = 1;
3919
3920 return true;
3921
3922 fail:
3923 sdio_release_host(sdiodev->func[1]);
3924 return false;
3925 }
3926
3927 static int
3928 brcmf_sdio_watchdog_thread(void *data)
3929 {
3930 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3931 int wait;
3932
3933 allow_signal(SIGTERM);
3934 /* Run until signal received */
3935 brcmf_sdiod_freezer_count(bus->sdiodev);
3936 while (1) {
3937 if (kthread_should_stop())
3938 break;
3939 brcmf_sdiod_freezer_uncount(bus->sdiodev);
3940 wait = wait_for_completion_interruptible(&bus->watchdog_wait);
3941 brcmf_sdiod_freezer_count(bus->sdiodev);
3942 brcmf_sdiod_try_freeze(bus->sdiodev);
3943 if (!wait) {
3944 brcmf_sdio_bus_watchdog(bus);
3945 /* Count the tick for reference */
3946 bus->sdcnt.tickcnt++;
3947 reinit_completion(&bus->watchdog_wait);
3948 } else
3949 break;
3950 }
3951 return 0;
3952 }
3953
3954 static void
3955 brcmf_sdio_watchdog(unsigned long data)
3956 {
3957 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3958
3959 if (bus->watchdog_tsk) {
3960 complete(&bus->watchdog_wait);
3961 /* Reschedule the watchdog */
3962 if (bus->wd_active)
3963 mod_timer(&bus->timer,
3964 jiffies + BRCMF_WD_POLL);
3965 }
3966 }
3967
3968 static const struct brcmf_bus_ops brcmf_sdio_bus_ops = {
3969 .stop = brcmf_sdio_bus_stop,
3970 .preinit = brcmf_sdio_bus_preinit,
3971 .txdata = brcmf_sdio_bus_txdata,
3972 .txctl = brcmf_sdio_bus_txctl,
3973 .rxctl = brcmf_sdio_bus_rxctl,
3974 .gettxq = brcmf_sdio_bus_gettxq,
3975 .wowl_config = brcmf_sdio_wowl_config,
3976 .get_ramsize = brcmf_sdio_bus_get_ramsize,
3977 .get_memdump = brcmf_sdio_bus_get_memdump,
3978 };
3979
3980 static void brcmf_sdio_firmware_callback(struct device *dev,
3981 const struct firmware *code,
3982 void *nvram, u32 nvram_len)
3983 {
3984 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3985 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3986 struct brcmf_sdio *bus = sdiodev->bus;
3987 int err = 0;
3988 u8 saveclk;
3989
3990 brcmf_dbg(TRACE, "Enter: dev=%s\n", dev_name(dev));
3991
3992 if (!bus_if->drvr)
3993 return;
3994
3995 /* try to download image and nvram to the dongle */
3996 bus->alp_only = true;
3997 err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len);
3998 if (err)
3999 goto fail;
4000 bus->alp_only = false;
4001
4002 /* Start the watchdog timer */
4003 bus->sdcnt.tickcnt = 0;
4004 brcmf_sdio_wd_timer(bus, true);
4005
4006 sdio_claim_host(sdiodev->func[1]);
4007
4008 /* Make sure backplane clock is on, needed to generate F2 interrupt */
4009 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4010 if (bus->clkstate != CLK_AVAIL)
4011 goto release;
4012
4013 /* Force clocks on backplane to be sure F2 interrupt propagates */
4014 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, &err);
4015 if (!err) {
4016 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
4017 (saveclk | SBSDIO_FORCE_HT), &err);
4018 }
4019 if (err) {
4020 brcmf_err("Failed to force clock for F2: err %d\n", err);
4021 goto release;
4022 }
4023
4024 /* Enable function 2 (frame transfers) */
4025 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
4026 offsetof(struct sdpcmd_regs, tosbmailboxdata));
4027 err = sdio_enable_func(sdiodev->func[SDIO_FUNC_2]);
4028
4029
4030 brcmf_dbg(INFO, "enable F2: err=%d\n", err);
4031
4032 /* If F2 successfully enabled, set core and enable interrupts */
4033 if (!err) {
4034 /* Set up the interrupt mask and enable interrupts */
4035 bus->hostintmask = HOSTINTMASK;
4036 w_sdreg32(bus, bus->hostintmask,
4037 offsetof(struct sdpcmd_regs, hostintmask));
4038
4039 brcmf_sdiod_regwb(sdiodev, SBSDIO_WATERMARK, 8, &err);
4040 } else {
4041 /* Disable F2 again */
4042 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
4043 goto release;
4044 }
4045
4046 if (brcmf_chip_sr_capable(bus->ci)) {
4047 brcmf_sdio_sr_init(bus);
4048 } else {
4049 /* Restore previous clock setting */
4050 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
4051 saveclk, &err);
4052 }
4053
4054 if (err == 0) {
4055 /* Allow full data communication using DPC from now on. */
4056 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
4057
4058 err = brcmf_sdiod_intr_register(sdiodev);
4059 if (err != 0)
4060 brcmf_err("intr register failed:%d\n", err);
4061 }
4062
4063 /* If we didn't come up, turn off backplane clock */
4064 if (err != 0)
4065 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4066
4067 sdio_release_host(sdiodev->func[1]);
4068
4069 err = brcmf_bus_start(dev);
4070 if (err != 0) {
4071 brcmf_err("dongle is not responding\n");
4072 goto fail;
4073 }
4074 return;
4075
4076 release:
4077 sdio_release_host(sdiodev->func[1]);
4078 fail:
4079 brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err);
4080 device_release_driver(dev);
4081 }
4082
4083 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
4084 {
4085 int ret;
4086 struct brcmf_sdio *bus;
4087 struct workqueue_struct *wq;
4088
4089 brcmf_dbg(TRACE, "Enter\n");
4090
4091 /* Allocate private bus interface state */
4092 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
4093 if (!bus)
4094 goto fail;
4095
4096 bus->sdiodev = sdiodev;
4097 sdiodev->bus = bus;
4098 skb_queue_head_init(&bus->glom);
4099 bus->txbound = BRCMF_TXBOUND;
4100 bus->rxbound = BRCMF_RXBOUND;
4101 bus->txminmax = BRCMF_TXMINMAX;
4102 bus->tx_seq = SDPCM_SEQ_WRAP - 1;
4103
4104 /* single-threaded workqueue */
4105 wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM,
4106 dev_name(&sdiodev->func[1]->dev));
4107 if (!wq) {
4108 brcmf_err("insufficient memory to create txworkqueue\n");
4109 goto fail;
4110 }
4111 brcmf_sdiod_freezer_count(sdiodev);
4112 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
4113 bus->brcmf_wq = wq;
4114
4115 /* attempt to attach to the dongle */
4116 if (!(brcmf_sdio_probe_attach(bus))) {
4117 brcmf_err("brcmf_sdio_probe_attach failed\n");
4118 goto fail;
4119 }
4120
4121 spin_lock_init(&bus->rxctl_lock);
4122 spin_lock_init(&bus->txq_lock);
4123 init_waitqueue_head(&bus->ctrl_wait);
4124 init_waitqueue_head(&bus->dcmd_resp_wait);
4125
4126 /* Set up the watchdog timer */
4127 init_timer(&bus->timer);
4128 bus->timer.data = (unsigned long)bus;
4129 bus->timer.function = brcmf_sdio_watchdog;
4130
4131 /* Initialize watchdog thread */
4132 init_completion(&bus->watchdog_wait);
4133 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread,
4134 bus, "brcmf_wdog/%s",
4135 dev_name(&sdiodev->func[1]->dev));
4136 if (IS_ERR(bus->watchdog_tsk)) {
4137 pr_warn("brcmf_watchdog thread failed to start\n");
4138 bus->watchdog_tsk = NULL;
4139 }
4140 /* Initialize DPC thread */
4141 bus->dpc_triggered = false;
4142 bus->dpc_running = false;
4143
4144 /* Assign bus interface call back */
4145 bus->sdiodev->bus_if->dev = bus->sdiodev->dev;
4146 bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops;
4147 bus->sdiodev->bus_if->chip = bus->ci->chip;
4148 bus->sdiodev->bus_if->chiprev = bus->ci->chiprev;
4149
4150 /* default sdio bus header length for tx packet */
4151 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
4152
4153 /* Attach to the common layer, reserve hdr space */
4154 ret = brcmf_attach(bus->sdiodev->dev, bus->sdiodev->settings);
4155 if (ret != 0) {
4156 brcmf_err("brcmf_attach failed\n");
4157 goto fail;
4158 }
4159
4160 /* allocate scatter-gather table. sg support
4161 * will be disabled upon allocation failure.
4162 */
4163 brcmf_sdiod_sgtable_alloc(bus->sdiodev);
4164
4165 /* Query the F2 block size, set roundup accordingly */
4166 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
4167 bus->roundup = min(max_roundup, bus->blocksize);
4168
4169 /* Allocate buffers */
4170 if (bus->sdiodev->bus_if->maxctl) {
4171 bus->sdiodev->bus_if->maxctl += bus->roundup;
4172 bus->rxblen =
4173 roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
4174 ALIGNMENT) + bus->head_align;
4175 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
4176 if (!(bus->rxbuf)) {
4177 brcmf_err("rxbuf allocation failed\n");
4178 goto fail;
4179 }
4180 }
4181
4182 sdio_claim_host(bus->sdiodev->func[1]);
4183
4184 /* Disable F2 to clear any intermediate frame state on the dongle */
4185 sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]);
4186
4187 bus->rxflow = false;
4188
4189 /* Done with backplane-dependent accesses, can drop clock... */
4190 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4191
4192 sdio_release_host(bus->sdiodev->func[1]);
4193
4194 /* ...and initialize clock/power states */
4195 bus->clkstate = CLK_SDONLY;
4196 bus->idletime = BRCMF_IDLE_INTERVAL;
4197 bus->idleclock = BRCMF_IDLE_ACTIVE;
4198
4199 /* SR state */
4200 bus->sr_enabled = false;
4201
4202 brcmf_sdio_debugfs_create(bus);
4203 brcmf_dbg(INFO, "completed!!\n");
4204
4205 ret = brcmf_fw_map_chip_to_name(bus->ci->chip, bus->ci->chiprev,
4206 brcmf_sdio_fwnames,
4207 ARRAY_SIZE(brcmf_sdio_fwnames),
4208 sdiodev->fw_name, sdiodev->nvram_name);
4209 if (ret)
4210 goto fail;
4211
4212 ret = brcmf_fw_get_firmwares(sdiodev->dev, BRCMF_FW_REQUEST_NVRAM,
4213 sdiodev->fw_name, sdiodev->nvram_name,
4214 brcmf_sdio_firmware_callback);
4215 if (ret != 0) {
4216 brcmf_err("async firmware request failed: %d\n", ret);
4217 goto fail;
4218 }
4219
4220 return bus;
4221
4222 fail:
4223 brcmf_sdio_remove(bus);
4224 return NULL;
4225 }
4226
4227 /* Detach and free everything */
4228 void brcmf_sdio_remove(struct brcmf_sdio *bus)
4229 {
4230 brcmf_dbg(TRACE, "Enter\n");
4231
4232 if (bus) {
4233 /* De-register interrupt handler */
4234 brcmf_sdiod_intr_unregister(bus->sdiodev);
4235
4236 brcmf_detach(bus->sdiodev->dev);
4237
4238 cancel_work_sync(&bus->datawork);
4239 if (bus->brcmf_wq)
4240 destroy_workqueue(bus->brcmf_wq);
4241
4242 if (bus->ci) {
4243 if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
4244 sdio_claim_host(bus->sdiodev->func[1]);
4245 brcmf_sdio_wd_timer(bus, false);
4246 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4247 /* Leave the device in state where it is
4248 * 'passive'. This is done by resetting all
4249 * necessary cores.
4250 */
4251 msleep(20);
4252 brcmf_chip_set_passive(bus->ci);
4253 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4254 sdio_release_host(bus->sdiodev->func[1]);
4255 }
4256 brcmf_chip_detach(bus->ci);
4257 }
4258 if (bus->sdiodev->settings)
4259 brcmf_release_module_param(bus->sdiodev->settings);
4260
4261 kfree(bus->rxbuf);
4262 kfree(bus->hdrbuf);
4263 kfree(bus);
4264 }
4265
4266 brcmf_dbg(TRACE, "Disconnected\n");
4267 }
4268
4269 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active)
4270 {
4271 /* Totally stop the timer */
4272 if (!active && bus->wd_active) {
4273 del_timer_sync(&bus->timer);
4274 bus->wd_active = false;
4275 return;
4276 }
4277
4278 /* don't start the wd until fw is loaded */
4279 if (bus->sdiodev->state != BRCMF_SDIOD_DATA)
4280 return;
4281
4282 if (active) {
4283 if (!bus->wd_active) {
4284 /* Create timer again when watchdog period is
4285 dynamically changed or in the first instance
4286 */
4287 bus->timer.expires = jiffies + BRCMF_WD_POLL;
4288 add_timer(&bus->timer);
4289 bus->wd_active = true;
4290 } else {
4291 /* Re arm the timer, at last watchdog period */
4292 mod_timer(&bus->timer, jiffies + BRCMF_WD_POLL);
4293 }
4294 }
4295 }
4296
4297 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep)
4298 {
4299 int ret;
4300
4301 sdio_claim_host(bus->sdiodev->func[1]);
4302 ret = brcmf_sdio_bus_sleep(bus, sleep, false);
4303 sdio_release_host(bus->sdiodev->func[1]);
4304
4305 return ret;
4306 }
4307
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