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[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / broadcom / brcm80211 / brcmfmac / sdio.c
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/types.h>
18 #include <linux/atomic.h>
19 #include <linux/kernel.h>
20 #include <linux/kthread.h>
21 #include <linux/printk.h>
22 #include <linux/pci_ids.h>
23 #include <linux/netdevice.h>
24 #include <linux/interrupt.h>
25 #include <linux/sched/signal.h>
26 #include <linux/mmc/sdio.h>
27 #include <linux/mmc/sdio_ids.h>
28 #include <linux/mmc/sdio_func.h>
29 #include <linux/mmc/card.h>
30 #include <linux/semaphore.h>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
33 #include <linux/bcma/bcma.h>
34 #include <linux/debugfs.h>
35 #include <linux/vmalloc.h>
36 #include <asm/unaligned.h>
37 #include <defs.h>
38 #include <brcmu_wifi.h>
39 #include <brcmu_utils.h>
40 #include <brcm_hw_ids.h>
41 #include <soc.h>
42 #include "sdio.h"
43 #include "chip.h"
44 #include "firmware.h"
45 #include "core.h"
46 #include "common.h"
47 #include "bcdc.h"
48
49 #define DCMD_RESP_TIMEOUT msecs_to_jiffies(2500)
50 #define CTL_DONE_TIMEOUT msecs_to_jiffies(2500)
51
52 #ifdef DEBUG
53
54 #define BRCMF_TRAP_INFO_SIZE 80
55
56 #define CBUF_LEN (128)
57
58 /* Device console log buffer state */
59 #define CONSOLE_BUFFER_MAX 2024
60
61 struct rte_log_le {
62 __le32 buf; /* Can't be pointer on (64-bit) hosts */
63 __le32 buf_size;
64 __le32 idx;
65 char *_buf_compat; /* Redundant pointer for backward compat. */
66 };
67
68 struct rte_console {
69 /* Virtual UART
70 * When there is no UART (e.g. Quickturn),
71 * the host should write a complete
72 * input line directly into cbuf and then write
73 * the length into vcons_in.
74 * This may also be used when there is a real UART
75 * (at risk of conflicting with
76 * the real UART). vcons_out is currently unused.
77 */
78 uint vcons_in;
79 uint vcons_out;
80
81 /* Output (logging) buffer
82 * Console output is written to a ring buffer log_buf at index log_idx.
83 * The host may read the output when it sees log_idx advance.
84 * Output will be lost if the output wraps around faster than the host
85 * polls.
86 */
87 struct rte_log_le log_le;
88
89 /* Console input line buffer
90 * Characters are read one at a time into cbuf
91 * until <CR> is received, then
92 * the buffer is processed as a command line.
93 * Also used for virtual UART.
94 */
95 uint cbuf_idx;
96 char cbuf[CBUF_LEN];
97 };
98
99 #endif /* DEBUG */
100 #include <chipcommon.h>
101
102 #include "bus.h"
103 #include "debug.h"
104 #include "tracepoint.h"
105
106 #define TXQLEN 2048 /* bulk tx queue length */
107 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
108 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
109 #define PRIOMASK 7
110
111 #define TXRETRIES 2 /* # of retries for tx frames */
112
113 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
114 one scheduling */
115
116 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
117 one scheduling */
118
119 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
120
121 #define MEMBLOCK 2048 /* Block size used for downloading
122 of dongle image */
123 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
124 biggest possible glom */
125
126 #define BRCMF_FIRSTREAD (1 << 6)
127
128 #define BRCMF_CONSOLE 10 /* watchdog interval to poll console */
129
130 /* SBSDIO_DEVICE_CTL */
131
132 /* 1: device will assert busy signal when receiving CMD53 */
133 #define SBSDIO_DEVCTL_SETBUSY 0x01
134 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
135 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
136 /* 1: mask all interrupts to host except the chipActive (rev 8) */
137 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
138 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
139 * sdio bus power cycle to clear (rev 9) */
140 #define SBSDIO_DEVCTL_PADS_ISO 0x08
141 /* Force SD->SB reset mapping (rev 11) */
142 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
143 /* Determined by CoreControl bit */
144 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
145 /* Force backplane reset */
146 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
147 /* Force no backplane reset */
148 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
149
150 /* direct(mapped) cis space */
151
152 /* MAPPED common CIS address */
153 #define SBSDIO_CIS_BASE_COMMON 0x1000
154 /* maximum bytes in one CIS */
155 #define SBSDIO_CIS_SIZE_LIMIT 0x200
156 /* cis offset addr is < 17 bits */
157 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
158
159 /* manfid tuple length, include tuple, link bytes */
160 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
161
162 #define CORE_BUS_REG(base, field) \
163 (base + offsetof(struct sdpcmd_regs, field))
164
165 /* SDIO function 1 register CHIPCLKCSR */
166 /* Force ALP request to backplane */
167 #define SBSDIO_FORCE_ALP 0x01
168 /* Force HT request to backplane */
169 #define SBSDIO_FORCE_HT 0x02
170 /* Force ILP request to backplane */
171 #define SBSDIO_FORCE_ILP 0x04
172 /* Make ALP ready (power up xtal) */
173 #define SBSDIO_ALP_AVAIL_REQ 0x08
174 /* Make HT ready (power up PLL) */
175 #define SBSDIO_HT_AVAIL_REQ 0x10
176 /* Squelch clock requests from HW */
177 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
178 /* Status: ALP is ready */
179 #define SBSDIO_ALP_AVAIL 0x40
180 /* Status: HT is ready */
181 #define SBSDIO_HT_AVAIL 0x80
182 #define SBSDIO_CSR_MASK 0x1F
183 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
184 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
185 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
186 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
187 #define SBSDIO_CLKAV(regval, alponly) \
188 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
189
190 /* intstatus */
191 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
192 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
193 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
194 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
195 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
196 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
197 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
198 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
199 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
200 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
201 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
202 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
203 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
204 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
205 #define I_PC (1 << 10) /* descriptor error */
206 #define I_PD (1 << 11) /* data error */
207 #define I_DE (1 << 12) /* Descriptor protocol Error */
208 #define I_RU (1 << 13) /* Receive descriptor Underflow */
209 #define I_RO (1 << 14) /* Receive fifo Overflow */
210 #define I_XU (1 << 15) /* Transmit fifo Underflow */
211 #define I_RI (1 << 16) /* Receive Interrupt */
212 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
213 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
214 #define I_XI (1 << 24) /* Transmit Interrupt */
215 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
216 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
217 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
218 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
219 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
220 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
221 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
222 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
223 #define I_DMA (I_RI | I_XI | I_ERRORS)
224
225 /* corecontrol */
226 #define CC_CISRDY (1 << 0) /* CIS Ready */
227 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
228 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
229 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
230 #define CC_XMTDATAAVAIL_MODE (1 << 4)
231 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
232
233 /* SDA_FRAMECTRL */
234 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
235 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
236 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
237 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
238
239 /*
240 * Software allocation of To SB Mailbox resources
241 */
242
243 /* tosbmailbox bits corresponding to intstatus bits */
244 #define SMB_NAK (1 << 0) /* Frame NAK */
245 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
246 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
247 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
248
249 /* tosbmailboxdata */
250 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
251
252 /*
253 * Software allocation of To Host Mailbox resources
254 */
255
256 /* intstatus bits */
257 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
258 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
259 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
260 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
261
262 /* tohostmailboxdata */
263 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
264 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
265 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
266 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
267
268 #define HMB_DATA_FCDATA_MASK 0xff000000
269 #define HMB_DATA_FCDATA_SHIFT 24
270
271 #define HMB_DATA_VERSION_MASK 0x00ff0000
272 #define HMB_DATA_VERSION_SHIFT 16
273
274 /*
275 * Software-defined protocol header
276 */
277
278 /* Current protocol version */
279 #define SDPCM_PROT_VERSION 4
280
281 /*
282 * Shared structure between dongle and the host.
283 * The structure contains pointers to trap or assert information.
284 */
285 #define SDPCM_SHARED_VERSION 0x0003
286 #define SDPCM_SHARED_VERSION_MASK 0x00FF
287 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
288 #define SDPCM_SHARED_ASSERT 0x0200
289 #define SDPCM_SHARED_TRAP 0x0400
290
291 /* Space for header read, limit for data packets */
292 #define MAX_HDR_READ (1 << 6)
293 #define MAX_RX_DATASZ 2048
294
295 /* Bump up limit on waiting for HT to account for first startup;
296 * if the image is doing a CRC calculation before programming the PMU
297 * for HT availability, it could take a couple hundred ms more, so
298 * max out at a 1 second (1000000us).
299 */
300 #undef PMU_MAX_TRANSITION_DLY
301 #define PMU_MAX_TRANSITION_DLY 1000000
302
303 /* Value for ChipClockCSR during initial setup */
304 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
305 SBSDIO_ALP_AVAIL_REQ)
306
307 /* Flags for SDH calls */
308 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
309
310 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
311 * when idle
312 */
313 #define BRCMF_IDLE_INTERVAL 1
314
315 #define KSO_WAIT_US 50
316 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
317 #define BRCMF_SDIO_MAX_ACCESS_ERRORS 5
318
319 /*
320 * Conversion of 802.1D priority to precedence level
321 */
322 static uint prio2prec(u32 prio)
323 {
324 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
325 (prio^2) : prio;
326 }
327
328 #ifdef DEBUG
329 /* Device console log buffer state */
330 struct brcmf_console {
331 uint count; /* Poll interval msec counter */
332 uint log_addr; /* Log struct address (fixed) */
333 struct rte_log_le log_le; /* Log struct (host copy) */
334 uint bufsize; /* Size of log buffer */
335 u8 *buf; /* Log buffer (host copy) */
336 uint last; /* Last buffer read index */
337 };
338
339 struct brcmf_trap_info {
340 __le32 type;
341 __le32 epc;
342 __le32 cpsr;
343 __le32 spsr;
344 __le32 r0; /* a1 */
345 __le32 r1; /* a2 */
346 __le32 r2; /* a3 */
347 __le32 r3; /* a4 */
348 __le32 r4; /* v1 */
349 __le32 r5; /* v2 */
350 __le32 r6; /* v3 */
351 __le32 r7; /* v4 */
352 __le32 r8; /* v5 */
353 __le32 r9; /* sb/v6 */
354 __le32 r10; /* sl/v7 */
355 __le32 r11; /* fp/v8 */
356 __le32 r12; /* ip */
357 __le32 r13; /* sp */
358 __le32 r14; /* lr */
359 __le32 pc; /* r15 */
360 };
361 #endif /* DEBUG */
362
363 struct sdpcm_shared {
364 u32 flags;
365 u32 trap_addr;
366 u32 assert_exp_addr;
367 u32 assert_file_addr;
368 u32 assert_line;
369 u32 console_addr; /* Address of struct rte_console */
370 u32 msgtrace_addr;
371 u8 tag[32];
372 u32 brpt_addr;
373 };
374
375 struct sdpcm_shared_le {
376 __le32 flags;
377 __le32 trap_addr;
378 __le32 assert_exp_addr;
379 __le32 assert_file_addr;
380 __le32 assert_line;
381 __le32 console_addr; /* Address of struct rte_console */
382 __le32 msgtrace_addr;
383 u8 tag[32];
384 __le32 brpt_addr;
385 };
386
387 /* dongle SDIO bus specific header info */
388 struct brcmf_sdio_hdrinfo {
389 u8 seq_num;
390 u8 channel;
391 u16 len;
392 u16 len_left;
393 u16 len_nxtfrm;
394 u8 dat_offset;
395 bool lastfrm;
396 u16 tail_pad;
397 };
398
399 /*
400 * hold counter variables
401 */
402 struct brcmf_sdio_count {
403 uint intrcount; /* Count of device interrupt callbacks */
404 uint lastintrs; /* Count as of last watchdog timer */
405 uint pollcnt; /* Count of active polls */
406 uint regfails; /* Count of R_REG failures */
407 uint tx_sderrs; /* Count of tx attempts with sd errors */
408 uint fcqueued; /* Tx packets that got queued */
409 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
410 uint rx_toolong; /* Receive frames too long to receive */
411 uint rxc_errors; /* SDIO errors when reading control frames */
412 uint rx_hdrfail; /* SDIO errors on header reads */
413 uint rx_badhdr; /* Bad received headers (roosync?) */
414 uint rx_badseq; /* Mismatched rx sequence number */
415 uint fc_rcvd; /* Number of flow-control events received */
416 uint fc_xoff; /* Number which turned on flow-control */
417 uint fc_xon; /* Number which turned off flow-control */
418 uint rxglomfail; /* Failed deglom attempts */
419 uint rxglomframes; /* Number of glom frames (superframes) */
420 uint rxglompkts; /* Number of packets from glom frames */
421 uint f2rxhdrs; /* Number of header reads */
422 uint f2rxdata; /* Number of frame data reads */
423 uint f2txdata; /* Number of f2 frame writes */
424 uint f1regdata; /* Number of f1 register accesses */
425 uint tickcnt; /* Number of watchdog been schedule */
426 ulong tx_ctlerrs; /* Err of sending ctrl frames */
427 ulong tx_ctlpkts; /* Ctrl frames sent to dongle */
428 ulong rx_ctlerrs; /* Err of processing rx ctrl frames */
429 ulong rx_ctlpkts; /* Ctrl frames processed from dongle */
430 ulong rx_readahead_cnt; /* packets where header read-ahead was used */
431 };
432
433 /* misc chip info needed by some of the routines */
434 /* Private data for SDIO bus interaction */
435 struct brcmf_sdio {
436 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
437 struct brcmf_chip *ci; /* Chip info struct */
438
439 u32 hostintmask; /* Copy of Host Interrupt Mask */
440 atomic_t intstatus; /* Intstatus bits (events) pending */
441 atomic_t fcstate; /* State of dongle flow-control */
442
443 uint blocksize; /* Block size of SDIO transfers */
444 uint roundup; /* Max roundup limit */
445
446 struct pktq txq; /* Queue length used for flow-control */
447 u8 flowcontrol; /* per prio flow control bitmask */
448 u8 tx_seq; /* Transmit sequence number (next) */
449 u8 tx_max; /* Maximum transmit sequence allowed */
450
451 u8 *hdrbuf; /* buffer for handling rx frame */
452 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
453 u8 rx_seq; /* Receive sequence number (expected) */
454 struct brcmf_sdio_hdrinfo cur_read;
455 /* info of current read frame */
456 bool rxskip; /* Skip receive (awaiting NAK ACK) */
457 bool rxpending; /* Data frame pending in dongle */
458
459 uint rxbound; /* Rx frames to read before resched */
460 uint txbound; /* Tx frames to send before resched */
461 uint txminmax;
462
463 struct sk_buff *glomd; /* Packet containing glomming descriptor */
464 struct sk_buff_head glom; /* Packet list for glommed superframe */
465
466 u8 *rxbuf; /* Buffer for receiving control packets */
467 uint rxblen; /* Allocated length of rxbuf */
468 u8 *rxctl; /* Aligned pointer into rxbuf */
469 u8 *rxctl_orig; /* pointer for freeing rxctl */
470 uint rxlen; /* Length of valid data in buffer */
471 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */
472
473 u8 sdpcm_ver; /* Bus protocol reported by dongle */
474
475 bool intr; /* Use interrupts */
476 bool poll; /* Use polling */
477 atomic_t ipend; /* Device interrupt is pending */
478 uint spurious; /* Count of spurious interrupts */
479 uint pollrate; /* Ticks between device polls */
480 uint polltick; /* Tick counter */
481
482 #ifdef DEBUG
483 uint console_interval;
484 struct brcmf_console console; /* Console output polling support */
485 uint console_addr; /* Console address from shared struct */
486 #endif /* DEBUG */
487
488 uint clkstate; /* State of sd and backplane clock(s) */
489 s32 idletime; /* Control for activity timeout */
490 s32 idlecount; /* Activity timeout counter */
491 s32 idleclock; /* How to set bus driver when idle */
492 bool rxflow_mode; /* Rx flow control mode */
493 bool rxflow; /* Is rx flow control on */
494 bool alp_only; /* Don't use HT clock (ALP only) */
495
496 u8 *ctrl_frame_buf;
497 u16 ctrl_frame_len;
498 bool ctrl_frame_stat;
499 int ctrl_frame_err;
500
501 spinlock_t txq_lock; /* protect bus->txq */
502 wait_queue_head_t ctrl_wait;
503 wait_queue_head_t dcmd_resp_wait;
504
505 struct timer_list timer;
506 struct completion watchdog_wait;
507 struct task_struct *watchdog_tsk;
508 bool wd_active;
509
510 struct workqueue_struct *brcmf_wq;
511 struct work_struct datawork;
512 bool dpc_triggered;
513 bool dpc_running;
514
515 bool txoff; /* Transmit flow-controlled */
516 struct brcmf_sdio_count sdcnt;
517 bool sr_enabled; /* SaveRestore enabled */
518 bool sleeping;
519
520 u8 tx_hdrlen; /* sdio bus header length for tx packet */
521 bool txglom; /* host tx glomming enable flag */
522 u16 head_align; /* buffer pointer alignment */
523 u16 sgentry_align; /* scatter-gather buffer alignment */
524 };
525
526 /* clkstate */
527 #define CLK_NONE 0
528 #define CLK_SDONLY 1
529 #define CLK_PENDING 2
530 #define CLK_AVAIL 3
531
532 #ifdef DEBUG
533 static int qcount[NUMPRIO];
534 #endif /* DEBUG */
535
536 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
537
538 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
539
540 /* Limit on rounding up frames */
541 static const uint max_roundup = 512;
542
543 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
544 #define ALIGNMENT 8
545 #else
546 #define ALIGNMENT 4
547 #endif
548
549 enum brcmf_sdio_frmtype {
550 BRCMF_SDIO_FT_NORMAL,
551 BRCMF_SDIO_FT_SUPER,
552 BRCMF_SDIO_FT_SUB,
553 };
554
555 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
556
557 /* SDIO Pad drive strength to select value mappings */
558 struct sdiod_drive_str {
559 u8 strength; /* Pad Drive Strength in mA */
560 u8 sel; /* Chip-specific select value */
561 };
562
563 /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */
564 static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
565 {32, 0x6},
566 {26, 0x7},
567 {22, 0x4},
568 {16, 0x5},
569 {12, 0x2},
570 {8, 0x3},
571 {4, 0x0},
572 {0, 0x1}
573 };
574
575 /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
576 static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
577 {6, 0x7},
578 {5, 0x6},
579 {4, 0x5},
580 {3, 0x4},
581 {2, 0x2},
582 {1, 0x1},
583 {0, 0x0}
584 };
585
586 /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
587 static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
588 {3, 0x3},
589 {2, 0x2},
590 {1, 0x1},
591 {0, 0x0} };
592
593 /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
594 static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
595 {16, 0x7},
596 {12, 0x5},
597 {8, 0x3},
598 {4, 0x1}
599 };
600
601 BRCMF_FW_NVRAM_DEF(43143, "brcmfmac43143-sdio.bin", "brcmfmac43143-sdio.txt");
602 BRCMF_FW_NVRAM_DEF(43241B0, "brcmfmac43241b0-sdio.bin",
603 "brcmfmac43241b0-sdio.txt");
604 BRCMF_FW_NVRAM_DEF(43241B4, "brcmfmac43241b4-sdio.bin",
605 "brcmfmac43241b4-sdio.txt");
606 BRCMF_FW_NVRAM_DEF(43241B5, "brcmfmac43241b5-sdio.bin",
607 "brcmfmac43241b5-sdio.txt");
608 BRCMF_FW_NVRAM_DEF(4329, "brcmfmac4329-sdio.bin", "brcmfmac4329-sdio.txt");
609 BRCMF_FW_NVRAM_DEF(4330, "brcmfmac4330-sdio.bin", "brcmfmac4330-sdio.txt");
610 BRCMF_FW_NVRAM_DEF(4334, "brcmfmac4334-sdio.bin", "brcmfmac4334-sdio.txt");
611 BRCMF_FW_NVRAM_DEF(43340, "brcmfmac43340-sdio.bin", "brcmfmac43340-sdio.txt");
612 BRCMF_FW_NVRAM_DEF(4335, "brcmfmac4335-sdio.bin", "brcmfmac4335-sdio.txt");
613 BRCMF_FW_NVRAM_DEF(43362, "brcmfmac43362-sdio.bin", "brcmfmac43362-sdio.txt");
614 BRCMF_FW_NVRAM_DEF(4339, "brcmfmac4339-sdio.bin", "brcmfmac4339-sdio.txt");
615 BRCMF_FW_NVRAM_DEF(43430A0, "brcmfmac43430a0-sdio.bin", "brcmfmac43430a0-sdio.txt");
616 /* Note the names are not postfixed with a1 for backward compatibility */
617 BRCMF_FW_NVRAM_DEF(43430A1, "brcmfmac43430-sdio.bin", "brcmfmac43430-sdio.txt");
618 BRCMF_FW_NVRAM_DEF(43455, "brcmfmac43455-sdio.bin", "brcmfmac43455-sdio.txt");
619 BRCMF_FW_NVRAM_DEF(4354, "brcmfmac4354-sdio.bin", "brcmfmac4354-sdio.txt");
620 BRCMF_FW_NVRAM_DEF(4356, "brcmfmac4356-sdio.bin", "brcmfmac4356-sdio.txt");
621
622 static struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
623 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143),
624 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0),
625 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4),
626 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, 43241B5),
627 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, 4329),
628 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, 4330),
629 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334),
630 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340),
631 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43341_CHIP_ID, 0xFFFFFFFF, 43340),
632 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335),
633 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362),
634 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339),
635 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000001, 43430A0),
636 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFE, 43430A1),
637 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFFC0, 43455),
638 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354),
639 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356)
640 };
641
642 static void pkt_align(struct sk_buff *p, int len, int align)
643 {
644 uint datalign;
645 datalign = (unsigned long)(p->data);
646 datalign = roundup(datalign, (align)) - datalign;
647 if (datalign)
648 skb_pull(p, datalign);
649 __skb_trim(p, len);
650 }
651
652 /* To check if there's window offered */
653 static bool data_ok(struct brcmf_sdio *bus)
654 {
655 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
656 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
657 }
658
659 /*
660 * Reads a register in the SDIO hardware block. This block occupies a series of
661 * adresses on the 32 bit backplane bus.
662 */
663 static int r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset)
664 {
665 struct brcmf_core *core;
666 int ret;
667
668 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
669 *regvar = brcmf_sdiod_regrl(bus->sdiodev, core->base + offset, &ret);
670
671 return ret;
672 }
673
674 static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset)
675 {
676 struct brcmf_core *core;
677 int ret;
678
679 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
680 brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret);
681
682 return ret;
683 }
684
685 static int
686 brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
687 {
688 u8 wr_val = 0, rd_val, cmp_val, bmask;
689 int err = 0;
690 int err_cnt = 0;
691 int try_cnt = 0;
692
693 brcmf_dbg(TRACE, "Enter: on=%d\n", on);
694
695 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
696 /* 1st KSO write goes to AOS wake up core if device is asleep */
697 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
698 wr_val, &err);
699
700 if (on) {
701 /* device WAKEUP through KSO:
702 * write bit 0 & read back until
703 * both bits 0 (kso bit) & 1 (dev on status) are set
704 */
705 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
706 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
707 bmask = cmp_val;
708 usleep_range(2000, 3000);
709 } else {
710 /* Put device to sleep, turn off KSO */
711 cmp_val = 0;
712 /* only check for bit0, bit1(dev on status) may not
713 * get cleared right away
714 */
715 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
716 }
717
718 do {
719 /* reliable KSO bit set/clr:
720 * the sdiod sleep write access is synced to PMU 32khz clk
721 * just one write attempt may fail,
722 * read it back until it matches written value
723 */
724 rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
725 &err);
726 if (!err) {
727 if ((rd_val & bmask) == cmp_val)
728 break;
729 err_cnt = 0;
730 }
731 /* bail out upon subsequent access errors */
732 if (err && (err_cnt++ > BRCMF_SDIO_MAX_ACCESS_ERRORS))
733 break;
734 udelay(KSO_WAIT_US);
735 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
736 wr_val, &err);
737 } while (try_cnt++ < MAX_KSO_ATTEMPTS);
738
739 if (try_cnt > 2)
740 brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt,
741 rd_val, err);
742
743 if (try_cnt > MAX_KSO_ATTEMPTS)
744 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err);
745
746 return err;
747 }
748
749 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
750
751 /* Turn backplane clock on or off */
752 static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
753 {
754 int err;
755 u8 clkctl, clkreq, devctl;
756 unsigned long timeout;
757
758 brcmf_dbg(SDIO, "Enter\n");
759
760 clkctl = 0;
761
762 if (bus->sr_enabled) {
763 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
764 return 0;
765 }
766
767 if (on) {
768 /* Request HT Avail */
769 clkreq =
770 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
771
772 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
773 clkreq, &err);
774 if (err) {
775 brcmf_err("HT Avail request error: %d\n", err);
776 return -EBADE;
777 }
778
779 /* Check current status */
780 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
781 SBSDIO_FUNC1_CHIPCLKCSR, &err);
782 if (err) {
783 brcmf_err("HT Avail read error: %d\n", err);
784 return -EBADE;
785 }
786
787 /* Go to pending and await interrupt if appropriate */
788 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
789 /* Allow only clock-available interrupt */
790 devctl = brcmf_sdiod_regrb(bus->sdiodev,
791 SBSDIO_DEVICE_CTL, &err);
792 if (err) {
793 brcmf_err("Devctl error setting CA: %d\n",
794 err);
795 return -EBADE;
796 }
797
798 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
799 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
800 devctl, &err);
801 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
802 bus->clkstate = CLK_PENDING;
803
804 return 0;
805 } else if (bus->clkstate == CLK_PENDING) {
806 /* Cancel CA-only interrupt filter */
807 devctl = brcmf_sdiod_regrb(bus->sdiodev,
808 SBSDIO_DEVICE_CTL, &err);
809 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
810 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
811 devctl, &err);
812 }
813
814 /* Otherwise, wait here (polling) for HT Avail */
815 timeout = jiffies +
816 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
817 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
818 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
819 SBSDIO_FUNC1_CHIPCLKCSR,
820 &err);
821 if (time_after(jiffies, timeout))
822 break;
823 else
824 usleep_range(5000, 10000);
825 }
826 if (err) {
827 brcmf_err("HT Avail request error: %d\n", err);
828 return -EBADE;
829 }
830 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
831 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
832 PMU_MAX_TRANSITION_DLY, clkctl);
833 return -EBADE;
834 }
835
836 /* Mark clock available */
837 bus->clkstate = CLK_AVAIL;
838 brcmf_dbg(SDIO, "CLKCTL: turned ON\n");
839
840 #if defined(DEBUG)
841 if (!bus->alp_only) {
842 if (SBSDIO_ALPONLY(clkctl))
843 brcmf_err("HT Clock should be on\n");
844 }
845 #endif /* defined (DEBUG) */
846
847 } else {
848 clkreq = 0;
849
850 if (bus->clkstate == CLK_PENDING) {
851 /* Cancel CA-only interrupt filter */
852 devctl = brcmf_sdiod_regrb(bus->sdiodev,
853 SBSDIO_DEVICE_CTL, &err);
854 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
855 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
856 devctl, &err);
857 }
858
859 bus->clkstate = CLK_SDONLY;
860 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
861 clkreq, &err);
862 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
863 if (err) {
864 brcmf_err("Failed access turning clock off: %d\n",
865 err);
866 return -EBADE;
867 }
868 }
869 return 0;
870 }
871
872 /* Change idle/active SD state */
873 static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on)
874 {
875 brcmf_dbg(SDIO, "Enter\n");
876
877 if (on)
878 bus->clkstate = CLK_SDONLY;
879 else
880 bus->clkstate = CLK_NONE;
881
882 return 0;
883 }
884
885 /* Transition SD and backplane clock readiness */
886 static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
887 {
888 #ifdef DEBUG
889 uint oldstate = bus->clkstate;
890 #endif /* DEBUG */
891
892 brcmf_dbg(SDIO, "Enter\n");
893
894 /* Early exit if we're already there */
895 if (bus->clkstate == target)
896 return 0;
897
898 switch (target) {
899 case CLK_AVAIL:
900 /* Make sure SD clock is available */
901 if (bus->clkstate == CLK_NONE)
902 brcmf_sdio_sdclk(bus, true);
903 /* Now request HT Avail on the backplane */
904 brcmf_sdio_htclk(bus, true, pendok);
905 break;
906
907 case CLK_SDONLY:
908 /* Remove HT request, or bring up SD clock */
909 if (bus->clkstate == CLK_NONE)
910 brcmf_sdio_sdclk(bus, true);
911 else if (bus->clkstate == CLK_AVAIL)
912 brcmf_sdio_htclk(bus, false, false);
913 else
914 brcmf_err("request for %d -> %d\n",
915 bus->clkstate, target);
916 break;
917
918 case CLK_NONE:
919 /* Make sure to remove HT request */
920 if (bus->clkstate == CLK_AVAIL)
921 brcmf_sdio_htclk(bus, false, false);
922 /* Now remove the SD clock */
923 brcmf_sdio_sdclk(bus, false);
924 break;
925 }
926 #ifdef DEBUG
927 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate);
928 #endif /* DEBUG */
929
930 return 0;
931 }
932
933 static int
934 brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
935 {
936 int err = 0;
937 u8 clkcsr;
938
939 brcmf_dbg(SDIO, "Enter: request %s currently %s\n",
940 (sleep ? "SLEEP" : "WAKE"),
941 (bus->sleeping ? "SLEEP" : "WAKE"));
942
943 /* If SR is enabled control bus state with KSO */
944 if (bus->sr_enabled) {
945 /* Done if we're already in the requested state */
946 if (sleep == bus->sleeping)
947 goto end;
948
949 /* Going to sleep */
950 if (sleep) {
951 clkcsr = brcmf_sdiod_regrb(bus->sdiodev,
952 SBSDIO_FUNC1_CHIPCLKCSR,
953 &err);
954 if ((clkcsr & SBSDIO_CSR_MASK) == 0) {
955 brcmf_dbg(SDIO, "no clock, set ALP\n");
956 brcmf_sdiod_regwb(bus->sdiodev,
957 SBSDIO_FUNC1_CHIPCLKCSR,
958 SBSDIO_ALP_AVAIL_REQ, &err);
959 }
960 err = brcmf_sdio_kso_control(bus, false);
961 } else {
962 err = brcmf_sdio_kso_control(bus, true);
963 }
964 if (err) {
965 brcmf_err("error while changing bus sleep state %d\n",
966 err);
967 goto done;
968 }
969 }
970
971 end:
972 /* control clocks */
973 if (sleep) {
974 if (!bus->sr_enabled)
975 brcmf_sdio_clkctl(bus, CLK_NONE, pendok);
976 } else {
977 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok);
978 brcmf_sdio_wd_timer(bus, true);
979 }
980 bus->sleeping = sleep;
981 brcmf_dbg(SDIO, "new state %s\n",
982 (sleep ? "SLEEP" : "WAKE"));
983 done:
984 brcmf_dbg(SDIO, "Exit: err=%d\n", err);
985 return err;
986
987 }
988
989 #ifdef DEBUG
990 static inline bool brcmf_sdio_valid_shared_address(u32 addr)
991 {
992 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
993 }
994
995 static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
996 struct sdpcm_shared *sh)
997 {
998 u32 addr = 0;
999 int rv;
1000 u32 shaddr = 0;
1001 struct sdpcm_shared_le sh_le;
1002 __le32 addr_le;
1003
1004 sdio_claim_host(bus->sdiodev->func[1]);
1005 brcmf_sdio_bus_sleep(bus, false, false);
1006
1007 /*
1008 * Read last word in socram to determine
1009 * address of sdpcm_shared structure
1010 */
1011 shaddr = bus->ci->rambase + bus->ci->ramsize - 4;
1012 if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci))
1013 shaddr -= bus->ci->srsize;
1014 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr,
1015 (u8 *)&addr_le, 4);
1016 if (rv < 0)
1017 goto fail;
1018
1019 /*
1020 * Check if addr is valid.
1021 * NVRAM length at the end of memory should have been overwritten.
1022 */
1023 addr = le32_to_cpu(addr_le);
1024 if (!brcmf_sdio_valid_shared_address(addr)) {
1025 brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr);
1026 rv = -EINVAL;
1027 goto fail;
1028 }
1029
1030 brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr);
1031
1032 /* Read hndrte_shared structure */
1033 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
1034 sizeof(struct sdpcm_shared_le));
1035 if (rv < 0)
1036 goto fail;
1037
1038 sdio_release_host(bus->sdiodev->func[1]);
1039
1040 /* Endianness */
1041 sh->flags = le32_to_cpu(sh_le.flags);
1042 sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
1043 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
1044 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
1045 sh->assert_line = le32_to_cpu(sh_le.assert_line);
1046 sh->console_addr = le32_to_cpu(sh_le.console_addr);
1047 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
1048
1049 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) {
1050 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
1051 SDPCM_SHARED_VERSION,
1052 sh->flags & SDPCM_SHARED_VERSION_MASK);
1053 return -EPROTO;
1054 }
1055 return 0;
1056
1057 fail:
1058 brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n",
1059 rv, addr);
1060 sdio_release_host(bus->sdiodev->func[1]);
1061 return rv;
1062 }
1063
1064 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1065 {
1066 struct sdpcm_shared sh;
1067
1068 if (brcmf_sdio_readshared(bus, &sh) == 0)
1069 bus->console_addr = sh.console_addr;
1070 }
1071 #else
1072 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1073 {
1074 }
1075 #endif /* DEBUG */
1076
1077 static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus)
1078 {
1079 u32 intstatus = 0;
1080 u32 hmb_data;
1081 u8 fcbits;
1082 int ret;
1083
1084 brcmf_dbg(SDIO, "Enter\n");
1085
1086 /* Read mailbox data and ack that we did so */
1087 ret = r_sdreg32(bus, &hmb_data,
1088 offsetof(struct sdpcmd_regs, tohostmailboxdata));
1089
1090 if (ret == 0)
1091 w_sdreg32(bus, SMB_INT_ACK,
1092 offsetof(struct sdpcmd_regs, tosbmailbox));
1093 bus->sdcnt.f1regdata += 2;
1094
1095 /* Dongle recomposed rx frames, accept them again */
1096 if (hmb_data & HMB_DATA_NAKHANDLED) {
1097 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n",
1098 bus->rx_seq);
1099 if (!bus->rxskip)
1100 brcmf_err("unexpected NAKHANDLED!\n");
1101
1102 bus->rxskip = false;
1103 intstatus |= I_HMB_FRAME_IND;
1104 }
1105
1106 /*
1107 * DEVREADY does not occur with gSPI.
1108 */
1109 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1110 bus->sdpcm_ver =
1111 (hmb_data & HMB_DATA_VERSION_MASK) >>
1112 HMB_DATA_VERSION_SHIFT;
1113 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1114 brcmf_err("Version mismatch, dongle reports %d, "
1115 "expecting %d\n",
1116 bus->sdpcm_ver, SDPCM_PROT_VERSION);
1117 else
1118 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n",
1119 bus->sdpcm_ver);
1120
1121 /*
1122 * Retrieve console state address now that firmware should have
1123 * updated it.
1124 */
1125 brcmf_sdio_get_console_addr(bus);
1126 }
1127
1128 /*
1129 * Flow Control has been moved into the RX headers and this out of band
1130 * method isn't used any more.
1131 * remaining backward compatible with older dongles.
1132 */
1133 if (hmb_data & HMB_DATA_FC) {
1134 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1135 HMB_DATA_FCDATA_SHIFT;
1136
1137 if (fcbits & ~bus->flowcontrol)
1138 bus->sdcnt.fc_xoff++;
1139
1140 if (bus->flowcontrol & ~fcbits)
1141 bus->sdcnt.fc_xon++;
1142
1143 bus->sdcnt.fc_rcvd++;
1144 bus->flowcontrol = fcbits;
1145 }
1146
1147 /* Shouldn't be any others */
1148 if (hmb_data & ~(HMB_DATA_DEVREADY |
1149 HMB_DATA_NAKHANDLED |
1150 HMB_DATA_FC |
1151 HMB_DATA_FWREADY |
1152 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1153 brcmf_err("Unknown mailbox data content: 0x%02x\n",
1154 hmb_data);
1155
1156 return intstatus;
1157 }
1158
1159 static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
1160 {
1161 uint retries = 0;
1162 u16 lastrbc;
1163 u8 hi, lo;
1164 int err;
1165
1166 brcmf_err("%sterminate frame%s\n",
1167 abort ? "abort command, " : "",
1168 rtx ? ", send NAK" : "");
1169
1170 if (abort)
1171 brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
1172
1173 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
1174 SFC_RF_TERM, &err);
1175 bus->sdcnt.f1regdata++;
1176
1177 /* Wait until the packet has been flushed (device/FIFO stable) */
1178 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1179 hi = brcmf_sdiod_regrb(bus->sdiodev,
1180 SBSDIO_FUNC1_RFRAMEBCHI, &err);
1181 lo = brcmf_sdiod_regrb(bus->sdiodev,
1182 SBSDIO_FUNC1_RFRAMEBCLO, &err);
1183 bus->sdcnt.f1regdata += 2;
1184
1185 if ((hi == 0) && (lo == 0))
1186 break;
1187
1188 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1189 brcmf_err("count growing: last 0x%04x now 0x%04x\n",
1190 lastrbc, (hi << 8) + lo);
1191 }
1192 lastrbc = (hi << 8) + lo;
1193 }
1194
1195 if (!retries)
1196 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc);
1197 else
1198 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries);
1199
1200 if (rtx) {
1201 bus->sdcnt.rxrtx++;
1202 err = w_sdreg32(bus, SMB_NAK,
1203 offsetof(struct sdpcmd_regs, tosbmailbox));
1204
1205 bus->sdcnt.f1regdata++;
1206 if (err == 0)
1207 bus->rxskip = true;
1208 }
1209
1210 /* Clear partial in any case */
1211 bus->cur_read.len = 0;
1212 }
1213
1214 static void brcmf_sdio_txfail(struct brcmf_sdio *bus)
1215 {
1216 struct brcmf_sdio_dev *sdiodev = bus->sdiodev;
1217 u8 i, hi, lo;
1218
1219 /* On failure, abort the command and terminate the frame */
1220 brcmf_err("sdio error, abort command and terminate frame\n");
1221 bus->sdcnt.tx_sderrs++;
1222
1223 brcmf_sdiod_abort(sdiodev, SDIO_FUNC_2);
1224 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL);
1225 bus->sdcnt.f1regdata++;
1226
1227 for (i = 0; i < 3; i++) {
1228 hi = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL);
1229 lo = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL);
1230 bus->sdcnt.f1regdata += 2;
1231 if ((hi == 0) && (lo == 0))
1232 break;
1233 }
1234 }
1235
1236 /* return total length of buffer chain */
1237 static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus)
1238 {
1239 struct sk_buff *p;
1240 uint total;
1241
1242 total = 0;
1243 skb_queue_walk(&bus->glom, p)
1244 total += p->len;
1245 return total;
1246 }
1247
1248 static void brcmf_sdio_free_glom(struct brcmf_sdio *bus)
1249 {
1250 struct sk_buff *cur, *next;
1251
1252 skb_queue_walk_safe(&bus->glom, cur, next) {
1253 skb_unlink(cur, &bus->glom);
1254 brcmu_pkt_buf_free_skb(cur);
1255 }
1256 }
1257
1258 /**
1259 * brcmfmac sdio bus specific header
1260 * This is the lowest layer header wrapped on the packets transmitted between
1261 * host and WiFi dongle which contains information needed for SDIO core and
1262 * firmware
1263 *
1264 * It consists of 3 parts: hardware header, hardware extension header and
1265 * software header
1266 * hardware header (frame tag) - 4 bytes
1267 * Byte 0~1: Frame length
1268 * Byte 2~3: Checksum, bit-wise inverse of frame length
1269 * hardware extension header - 8 bytes
1270 * Tx glom mode only, N/A for Rx or normal Tx
1271 * Byte 0~1: Packet length excluding hw frame tag
1272 * Byte 2: Reserved
1273 * Byte 3: Frame flags, bit 0: last frame indication
1274 * Byte 4~5: Reserved
1275 * Byte 6~7: Tail padding length
1276 * software header - 8 bytes
1277 * Byte 0: Rx/Tx sequence number
1278 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
1279 * Byte 2: Length of next data frame, reserved for Tx
1280 * Byte 3: Data offset
1281 * Byte 4: Flow control bits, reserved for Tx
1282 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
1283 * Byte 6~7: Reserved
1284 */
1285 #define SDPCM_HWHDR_LEN 4
1286 #define SDPCM_HWEXT_LEN 8
1287 #define SDPCM_SWHDR_LEN 8
1288 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
1289 /* software header */
1290 #define SDPCM_SEQ_MASK 0x000000ff
1291 #define SDPCM_SEQ_WRAP 256
1292 #define SDPCM_CHANNEL_MASK 0x00000f00
1293 #define SDPCM_CHANNEL_SHIFT 8
1294 #define SDPCM_CONTROL_CHANNEL 0 /* Control */
1295 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
1296 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
1297 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
1298 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
1299 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
1300 #define SDPCM_NEXTLEN_MASK 0x00ff0000
1301 #define SDPCM_NEXTLEN_SHIFT 16
1302 #define SDPCM_DOFFSET_MASK 0xff000000
1303 #define SDPCM_DOFFSET_SHIFT 24
1304 #define SDPCM_FCMASK_MASK 0x000000ff
1305 #define SDPCM_WINDOW_MASK 0x0000ff00
1306 #define SDPCM_WINDOW_SHIFT 8
1307
1308 static inline u8 brcmf_sdio_getdatoffset(u8 *swheader)
1309 {
1310 u32 hdrvalue;
1311 hdrvalue = *(u32 *)swheader;
1312 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT);
1313 }
1314
1315 static inline bool brcmf_sdio_fromevntchan(u8 *swheader)
1316 {
1317 u32 hdrvalue;
1318 u8 ret;
1319
1320 hdrvalue = *(u32 *)swheader;
1321 ret = (u8)((hdrvalue & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT);
1322
1323 return (ret == SDPCM_EVENT_CHANNEL);
1324 }
1325
1326 static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header,
1327 struct brcmf_sdio_hdrinfo *rd,
1328 enum brcmf_sdio_frmtype type)
1329 {
1330 u16 len, checksum;
1331 u8 rx_seq, fc, tx_seq_max;
1332 u32 swheader;
1333
1334 trace_brcmf_sdpcm_hdr(SDPCM_RX, header);
1335
1336 /* hw header */
1337 len = get_unaligned_le16(header);
1338 checksum = get_unaligned_le16(header + sizeof(u16));
1339 /* All zero means no more to read */
1340 if (!(len | checksum)) {
1341 bus->rxpending = false;
1342 return -ENODATA;
1343 }
1344 if ((u16)(~(len ^ checksum))) {
1345 brcmf_err("HW header checksum error\n");
1346 bus->sdcnt.rx_badhdr++;
1347 brcmf_sdio_rxfail(bus, false, false);
1348 return -EIO;
1349 }
1350 if (len < SDPCM_HDRLEN) {
1351 brcmf_err("HW header length error\n");
1352 return -EPROTO;
1353 }
1354 if (type == BRCMF_SDIO_FT_SUPER &&
1355 (roundup(len, bus->blocksize) != rd->len)) {
1356 brcmf_err("HW superframe header length error\n");
1357 return -EPROTO;
1358 }
1359 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) {
1360 brcmf_err("HW subframe header length error\n");
1361 return -EPROTO;
1362 }
1363 rd->len = len;
1364
1365 /* software header */
1366 header += SDPCM_HWHDR_LEN;
1367 swheader = le32_to_cpu(*(__le32 *)header);
1368 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) {
1369 brcmf_err("Glom descriptor found in superframe head\n");
1370 rd->len = 0;
1371 return -EINVAL;
1372 }
1373 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK);
1374 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT;
1375 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
1376 type != BRCMF_SDIO_FT_SUPER) {
1377 brcmf_err("HW header length too long\n");
1378 bus->sdcnt.rx_toolong++;
1379 brcmf_sdio_rxfail(bus, false, false);
1380 rd->len = 0;
1381 return -EPROTO;
1382 }
1383 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) {
1384 brcmf_err("Wrong channel for superframe\n");
1385 rd->len = 0;
1386 return -EINVAL;
1387 }
1388 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL &&
1389 rd->channel != SDPCM_EVENT_CHANNEL) {
1390 brcmf_err("Wrong channel for subframe\n");
1391 rd->len = 0;
1392 return -EINVAL;
1393 }
1394 rd->dat_offset = brcmf_sdio_getdatoffset(header);
1395 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
1396 brcmf_err("seq %d: bad data offset\n", rx_seq);
1397 bus->sdcnt.rx_badhdr++;
1398 brcmf_sdio_rxfail(bus, false, false);
1399 rd->len = 0;
1400 return -ENXIO;
1401 }
1402 if (rd->seq_num != rx_seq) {
1403 brcmf_dbg(SDIO, "seq %d, expected %d\n", rx_seq, rd->seq_num);
1404 bus->sdcnt.rx_badseq++;
1405 rd->seq_num = rx_seq;
1406 }
1407 /* no need to check the reset for subframe */
1408 if (type == BRCMF_SDIO_FT_SUB)
1409 return 0;
1410 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT;
1411 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
1412 /* only warm for NON glom packet */
1413 if (rd->channel != SDPCM_GLOM_CHANNEL)
1414 brcmf_err("seq %d: next length error\n", rx_seq);
1415 rd->len_nxtfrm = 0;
1416 }
1417 swheader = le32_to_cpu(*(__le32 *)(header + 4));
1418 fc = swheader & SDPCM_FCMASK_MASK;
1419 if (bus->flowcontrol != fc) {
1420 if (~bus->flowcontrol & fc)
1421 bus->sdcnt.fc_xoff++;
1422 if (bus->flowcontrol & ~fc)
1423 bus->sdcnt.fc_xon++;
1424 bus->sdcnt.fc_rcvd++;
1425 bus->flowcontrol = fc;
1426 }
1427 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT;
1428 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
1429 brcmf_err("seq %d: max tx seq number error\n", rx_seq);
1430 tx_seq_max = bus->tx_seq + 2;
1431 }
1432 bus->tx_max = tx_seq_max;
1433
1434 return 0;
1435 }
1436
1437 static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length)
1438 {
1439 *(__le16 *)header = cpu_to_le16(frm_length);
1440 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length);
1441 }
1442
1443 static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header,
1444 struct brcmf_sdio_hdrinfo *hd_info)
1445 {
1446 u32 hdrval;
1447 u8 hdr_offset;
1448
1449 brcmf_sdio_update_hwhdr(header, hd_info->len);
1450 hdr_offset = SDPCM_HWHDR_LEN;
1451
1452 if (bus->txglom) {
1453 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24);
1454 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1455 hdrval = (u16)hd_info->tail_pad << 16;
1456 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval);
1457 hdr_offset += SDPCM_HWEXT_LEN;
1458 }
1459
1460 hdrval = hd_info->seq_num;
1461 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) &
1462 SDPCM_CHANNEL_MASK;
1463 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) &
1464 SDPCM_DOFFSET_MASK;
1465 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1466 *(((__le32 *)(header + hdr_offset)) + 1) = 0;
1467 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header);
1468 }
1469
1470 static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq)
1471 {
1472 u16 dlen, totlen;
1473 u8 *dptr, num = 0;
1474 u16 sublen;
1475 struct sk_buff *pfirst, *pnext;
1476
1477 int errcode;
1478 u8 doff, sfdoff;
1479
1480 struct brcmf_sdio_hdrinfo rd_new;
1481
1482 /* If packets, issue read(s) and send up packet chain */
1483 /* Return sequence numbers consumed? */
1484
1485 brcmf_dbg(SDIO, "start: glomd %p glom %p\n",
1486 bus->glomd, skb_peek(&bus->glom));
1487
1488 /* If there's a descriptor, generate the packet chain */
1489 if (bus->glomd) {
1490 pfirst = pnext = NULL;
1491 dlen = (u16) (bus->glomd->len);
1492 dptr = bus->glomd->data;
1493 if (!dlen || (dlen & 1)) {
1494 brcmf_err("bad glomd len(%d), ignore descriptor\n",
1495 dlen);
1496 dlen = 0;
1497 }
1498
1499 for (totlen = num = 0; dlen; num++) {
1500 /* Get (and move past) next length */
1501 sublen = get_unaligned_le16(dptr);
1502 dlen -= sizeof(u16);
1503 dptr += sizeof(u16);
1504 if ((sublen < SDPCM_HDRLEN) ||
1505 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1506 brcmf_err("descriptor len %d bad: %d\n",
1507 num, sublen);
1508 pnext = NULL;
1509 break;
1510 }
1511 if (sublen % bus->sgentry_align) {
1512 brcmf_err("sublen %d not multiple of %d\n",
1513 sublen, bus->sgentry_align);
1514 }
1515 totlen += sublen;
1516
1517 /* For last frame, adjust read len so total
1518 is a block multiple */
1519 if (!dlen) {
1520 sublen +=
1521 (roundup(totlen, bus->blocksize) - totlen);
1522 totlen = roundup(totlen, bus->blocksize);
1523 }
1524
1525 /* Allocate/chain packet for next subframe */
1526 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align);
1527 if (pnext == NULL) {
1528 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
1529 num, sublen);
1530 break;
1531 }
1532 skb_queue_tail(&bus->glom, pnext);
1533
1534 /* Adhere to start alignment requirements */
1535 pkt_align(pnext, sublen, bus->sgentry_align);
1536 }
1537
1538 /* If all allocations succeeded, save packet chain
1539 in bus structure */
1540 if (pnext) {
1541 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1542 totlen, num);
1543 if (BRCMF_GLOM_ON() && bus->cur_read.len &&
1544 totlen != bus->cur_read.len) {
1545 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1546 bus->cur_read.len, totlen, rxseq);
1547 }
1548 pfirst = pnext = NULL;
1549 } else {
1550 brcmf_sdio_free_glom(bus);
1551 num = 0;
1552 }
1553
1554 /* Done with descriptor packet */
1555 brcmu_pkt_buf_free_skb(bus->glomd);
1556 bus->glomd = NULL;
1557 bus->cur_read.len = 0;
1558 }
1559
1560 /* Ok -- either we just generated a packet chain,
1561 or had one from before */
1562 if (!skb_queue_empty(&bus->glom)) {
1563 if (BRCMF_GLOM_ON()) {
1564 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1565 skb_queue_walk(&bus->glom, pnext) {
1566 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1567 pnext, (u8 *) (pnext->data),
1568 pnext->len, pnext->len);
1569 }
1570 }
1571
1572 pfirst = skb_peek(&bus->glom);
1573 dlen = (u16) brcmf_sdio_glom_len(bus);
1574
1575 /* Do an SDIO read for the superframe. Configurable iovar to
1576 * read directly into the chained packet, or allocate a large
1577 * packet and and copy into the chain.
1578 */
1579 sdio_claim_host(bus->sdiodev->func[1]);
1580 errcode = brcmf_sdiod_recv_chain(bus->sdiodev,
1581 &bus->glom, dlen);
1582 sdio_release_host(bus->sdiodev->func[1]);
1583 bus->sdcnt.f2rxdata++;
1584
1585 /* On failure, kill the superframe */
1586 if (errcode < 0) {
1587 brcmf_err("glom read of %d bytes failed: %d\n",
1588 dlen, errcode);
1589
1590 sdio_claim_host(bus->sdiodev->func[1]);
1591 brcmf_sdio_rxfail(bus, true, false);
1592 bus->sdcnt.rxglomfail++;
1593 brcmf_sdio_free_glom(bus);
1594 sdio_release_host(bus->sdiodev->func[1]);
1595 return 0;
1596 }
1597
1598 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1599 pfirst->data, min_t(int, pfirst->len, 48),
1600 "SUPERFRAME:\n");
1601
1602 rd_new.seq_num = rxseq;
1603 rd_new.len = dlen;
1604 sdio_claim_host(bus->sdiodev->func[1]);
1605 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new,
1606 BRCMF_SDIO_FT_SUPER);
1607 sdio_release_host(bus->sdiodev->func[1]);
1608 bus->cur_read.len = rd_new.len_nxtfrm << 4;
1609
1610 /* Remove superframe header, remember offset */
1611 skb_pull(pfirst, rd_new.dat_offset);
1612 sfdoff = rd_new.dat_offset;
1613 num = 0;
1614
1615 /* Validate all the subframe headers */
1616 skb_queue_walk(&bus->glom, pnext) {
1617 /* leave when invalid subframe is found */
1618 if (errcode)
1619 break;
1620
1621 rd_new.len = pnext->len;
1622 rd_new.seq_num = rxseq++;
1623 sdio_claim_host(bus->sdiodev->func[1]);
1624 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new,
1625 BRCMF_SDIO_FT_SUB);
1626 sdio_release_host(bus->sdiodev->func[1]);
1627 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1628 pnext->data, 32, "subframe:\n");
1629
1630 num++;
1631 }
1632
1633 if (errcode) {
1634 /* Terminate frame on error */
1635 sdio_claim_host(bus->sdiodev->func[1]);
1636 brcmf_sdio_rxfail(bus, true, false);
1637 bus->sdcnt.rxglomfail++;
1638 brcmf_sdio_free_glom(bus);
1639 sdio_release_host(bus->sdiodev->func[1]);
1640 bus->cur_read.len = 0;
1641 return 0;
1642 }
1643
1644 /* Basic SD framing looks ok - process each packet (header) */
1645
1646 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1647 dptr = (u8 *) (pfirst->data);
1648 sublen = get_unaligned_le16(dptr);
1649 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]);
1650
1651 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1652 dptr, pfirst->len,
1653 "Rx Subframe Data:\n");
1654
1655 __skb_trim(pfirst, sublen);
1656 skb_pull(pfirst, doff);
1657
1658 if (pfirst->len == 0) {
1659 skb_unlink(pfirst, &bus->glom);
1660 brcmu_pkt_buf_free_skb(pfirst);
1661 continue;
1662 }
1663
1664 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1665 pfirst->data,
1666 min_t(int, pfirst->len, 32),
1667 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1668 bus->glom.qlen, pfirst, pfirst->data,
1669 pfirst->len, pfirst->next,
1670 pfirst->prev);
1671 skb_unlink(pfirst, &bus->glom);
1672 if (brcmf_sdio_fromevntchan(&dptr[SDPCM_HWHDR_LEN]))
1673 brcmf_rx_event(bus->sdiodev->dev, pfirst);
1674 else
1675 brcmf_rx_frame(bus->sdiodev->dev, pfirst,
1676 false);
1677 bus->sdcnt.rxglompkts++;
1678 }
1679
1680 bus->sdcnt.rxglomframes++;
1681 }
1682 return num;
1683 }
1684
1685 static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
1686 bool *pending)
1687 {
1688 DECLARE_WAITQUEUE(wait, current);
1689 int timeout = DCMD_RESP_TIMEOUT;
1690
1691 /* Wait until control frame is available */
1692 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1693 set_current_state(TASK_INTERRUPTIBLE);
1694
1695 while (!(*condition) && (!signal_pending(current) && timeout))
1696 timeout = schedule_timeout(timeout);
1697
1698 if (signal_pending(current))
1699 *pending = true;
1700
1701 set_current_state(TASK_RUNNING);
1702 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1703
1704 return timeout;
1705 }
1706
1707 static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus)
1708 {
1709 wake_up_interruptible(&bus->dcmd_resp_wait);
1710
1711 return 0;
1712 }
1713 static void
1714 brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
1715 {
1716 uint rdlen, pad;
1717 u8 *buf = NULL, *rbuf;
1718 int sdret;
1719
1720 brcmf_dbg(TRACE, "Enter\n");
1721
1722 if (bus->rxblen)
1723 buf = vzalloc(bus->rxblen);
1724 if (!buf)
1725 goto done;
1726
1727 rbuf = bus->rxbuf;
1728 pad = ((unsigned long)rbuf % bus->head_align);
1729 if (pad)
1730 rbuf += (bus->head_align - pad);
1731
1732 /* Copy the already-read portion over */
1733 memcpy(buf, hdr, BRCMF_FIRSTREAD);
1734 if (len <= BRCMF_FIRSTREAD)
1735 goto gotpkt;
1736
1737 /* Raise rdlen to next SDIO block to avoid tail command */
1738 rdlen = len - BRCMF_FIRSTREAD;
1739 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1740 pad = bus->blocksize - (rdlen % bus->blocksize);
1741 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1742 ((len + pad) < bus->sdiodev->bus_if->maxctl))
1743 rdlen += pad;
1744 } else if (rdlen % bus->head_align) {
1745 rdlen += bus->head_align - (rdlen % bus->head_align);
1746 }
1747
1748 /* Drop if the read is too big or it exceeds our maximum */
1749 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
1750 brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
1751 rdlen, bus->sdiodev->bus_if->maxctl);
1752 brcmf_sdio_rxfail(bus, false, false);
1753 goto done;
1754 }
1755
1756 if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
1757 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1758 len, len - doff, bus->sdiodev->bus_if->maxctl);
1759 bus->sdcnt.rx_toolong++;
1760 brcmf_sdio_rxfail(bus, false, false);
1761 goto done;
1762 }
1763
1764 /* Read remain of frame body */
1765 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen);
1766 bus->sdcnt.f2rxdata++;
1767
1768 /* Control frame failures need retransmission */
1769 if (sdret < 0) {
1770 brcmf_err("read %d control bytes failed: %d\n",
1771 rdlen, sdret);
1772 bus->sdcnt.rxc_errors++;
1773 brcmf_sdio_rxfail(bus, true, true);
1774 goto done;
1775 } else
1776 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen);
1777
1778 gotpkt:
1779
1780 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
1781 buf, len, "RxCtrl:\n");
1782
1783 /* Point to valid data and indicate its length */
1784 spin_lock_bh(&bus->rxctl_lock);
1785 if (bus->rxctl) {
1786 brcmf_err("last control frame is being processed.\n");
1787 spin_unlock_bh(&bus->rxctl_lock);
1788 vfree(buf);
1789 goto done;
1790 }
1791 bus->rxctl = buf + doff;
1792 bus->rxctl_orig = buf;
1793 bus->rxlen = len - doff;
1794 spin_unlock_bh(&bus->rxctl_lock);
1795
1796 done:
1797 /* Awake any waiters */
1798 brcmf_sdio_dcmd_resp_wake(bus);
1799 }
1800
1801 /* Pad read to blocksize for efficiency */
1802 static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
1803 {
1804 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1805 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1806 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1807 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1808 *rdlen += *pad;
1809 } else if (*rdlen % bus->head_align) {
1810 *rdlen += bus->head_align - (*rdlen % bus->head_align);
1811 }
1812 }
1813
1814 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
1815 {
1816 struct sk_buff *pkt; /* Packet for event or data frames */
1817 u16 pad; /* Number of pad bytes to read */
1818 uint rxleft = 0; /* Remaining number of frames allowed */
1819 int ret; /* Return code from calls */
1820 uint rxcount = 0; /* Total frames read */
1821 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new;
1822 u8 head_read = 0;
1823
1824 brcmf_dbg(TRACE, "Enter\n");
1825
1826 /* Not finished unless we encounter no more frames indication */
1827 bus->rxpending = true;
1828
1829 for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
1830 !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA;
1831 rd->seq_num++, rxleft--) {
1832
1833 /* Handle glomming separately */
1834 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
1835 u8 cnt;
1836 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1837 bus->glomd, skb_peek(&bus->glom));
1838 cnt = brcmf_sdio_rxglom(bus, rd->seq_num);
1839 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1840 rd->seq_num += cnt - 1;
1841 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1842 continue;
1843 }
1844
1845 rd->len_left = rd->len;
1846 /* read header first for unknow frame length */
1847 sdio_claim_host(bus->sdiodev->func[1]);
1848 if (!rd->len) {
1849 ret = brcmf_sdiod_recv_buf(bus->sdiodev,
1850 bus->rxhdr, BRCMF_FIRSTREAD);
1851 bus->sdcnt.f2rxhdrs++;
1852 if (ret < 0) {
1853 brcmf_err("RXHEADER FAILED: %d\n",
1854 ret);
1855 bus->sdcnt.rx_hdrfail++;
1856 brcmf_sdio_rxfail(bus, true, true);
1857 sdio_release_host(bus->sdiodev->func[1]);
1858 continue;
1859 }
1860
1861 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
1862 bus->rxhdr, SDPCM_HDRLEN,
1863 "RxHdr:\n");
1864
1865 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd,
1866 BRCMF_SDIO_FT_NORMAL)) {
1867 sdio_release_host(bus->sdiodev->func[1]);
1868 if (!bus->rxpending)
1869 break;
1870 else
1871 continue;
1872 }
1873
1874 if (rd->channel == SDPCM_CONTROL_CHANNEL) {
1875 brcmf_sdio_read_control(bus, bus->rxhdr,
1876 rd->len,
1877 rd->dat_offset);
1878 /* prepare the descriptor for the next read */
1879 rd->len = rd->len_nxtfrm << 4;
1880 rd->len_nxtfrm = 0;
1881 /* treat all packet as event if we don't know */
1882 rd->channel = SDPCM_EVENT_CHANNEL;
1883 sdio_release_host(bus->sdiodev->func[1]);
1884 continue;
1885 }
1886 rd->len_left = rd->len > BRCMF_FIRSTREAD ?
1887 rd->len - BRCMF_FIRSTREAD : 0;
1888 head_read = BRCMF_FIRSTREAD;
1889 }
1890
1891 brcmf_sdio_pad(bus, &pad, &rd->len_left);
1892
1893 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
1894 bus->head_align);
1895 if (!pkt) {
1896 /* Give up on data, request rtx of events */
1897 brcmf_err("brcmu_pkt_buf_get_skb failed\n");
1898 brcmf_sdio_rxfail(bus, false,
1899 RETRYCHAN(rd->channel));
1900 sdio_release_host(bus->sdiodev->func[1]);
1901 continue;
1902 }
1903 skb_pull(pkt, head_read);
1904 pkt_align(pkt, rd->len_left, bus->head_align);
1905
1906 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt);
1907 bus->sdcnt.f2rxdata++;
1908 sdio_release_host(bus->sdiodev->func[1]);
1909
1910 if (ret < 0) {
1911 brcmf_err("read %d bytes from channel %d failed: %d\n",
1912 rd->len, rd->channel, ret);
1913 brcmu_pkt_buf_free_skb(pkt);
1914 sdio_claim_host(bus->sdiodev->func[1]);
1915 brcmf_sdio_rxfail(bus, true,
1916 RETRYCHAN(rd->channel));
1917 sdio_release_host(bus->sdiodev->func[1]);
1918 continue;
1919 }
1920
1921 if (head_read) {
1922 skb_push(pkt, head_read);
1923 memcpy(pkt->data, bus->rxhdr, head_read);
1924 head_read = 0;
1925 } else {
1926 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
1927 rd_new.seq_num = rd->seq_num;
1928 sdio_claim_host(bus->sdiodev->func[1]);
1929 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new,
1930 BRCMF_SDIO_FT_NORMAL)) {
1931 rd->len = 0;
1932 brcmu_pkt_buf_free_skb(pkt);
1933 }
1934 bus->sdcnt.rx_readahead_cnt++;
1935 if (rd->len != roundup(rd_new.len, 16)) {
1936 brcmf_err("frame length mismatch:read %d, should be %d\n",
1937 rd->len,
1938 roundup(rd_new.len, 16) >> 4);
1939 rd->len = 0;
1940 brcmf_sdio_rxfail(bus, true, true);
1941 sdio_release_host(bus->sdiodev->func[1]);
1942 brcmu_pkt_buf_free_skb(pkt);
1943 continue;
1944 }
1945 sdio_release_host(bus->sdiodev->func[1]);
1946 rd->len_nxtfrm = rd_new.len_nxtfrm;
1947 rd->channel = rd_new.channel;
1948 rd->dat_offset = rd_new.dat_offset;
1949
1950 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
1951 BRCMF_DATA_ON()) &&
1952 BRCMF_HDRS_ON(),
1953 bus->rxhdr, SDPCM_HDRLEN,
1954 "RxHdr:\n");
1955
1956 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) {
1957 brcmf_err("readahead on control packet %d?\n",
1958 rd_new.seq_num);
1959 /* Force retry w/normal header read */
1960 rd->len = 0;
1961 sdio_claim_host(bus->sdiodev->func[1]);
1962 brcmf_sdio_rxfail(bus, false, true);
1963 sdio_release_host(bus->sdiodev->func[1]);
1964 brcmu_pkt_buf_free_skb(pkt);
1965 continue;
1966 }
1967 }
1968
1969 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1970 pkt->data, rd->len, "Rx Data:\n");
1971
1972 /* Save superframe descriptor and allocate packet frame */
1973 if (rd->channel == SDPCM_GLOM_CHANNEL) {
1974 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) {
1975 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
1976 rd->len);
1977 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1978 pkt->data, rd->len,
1979 "Glom Data:\n");
1980 __skb_trim(pkt, rd->len);
1981 skb_pull(pkt, SDPCM_HDRLEN);
1982 bus->glomd = pkt;
1983 } else {
1984 brcmf_err("%s: glom superframe w/o "
1985 "descriptor!\n", __func__);
1986 sdio_claim_host(bus->sdiodev->func[1]);
1987 brcmf_sdio_rxfail(bus, false, false);
1988 sdio_release_host(bus->sdiodev->func[1]);
1989 }
1990 /* prepare the descriptor for the next read */
1991 rd->len = rd->len_nxtfrm << 4;
1992 rd->len_nxtfrm = 0;
1993 /* treat all packet as event if we don't know */
1994 rd->channel = SDPCM_EVENT_CHANNEL;
1995 continue;
1996 }
1997
1998 /* Fill in packet len and prio, deliver upward */
1999 __skb_trim(pkt, rd->len);
2000 skb_pull(pkt, rd->dat_offset);
2001
2002 if (pkt->len == 0)
2003 brcmu_pkt_buf_free_skb(pkt);
2004 else if (rd->channel == SDPCM_EVENT_CHANNEL)
2005 brcmf_rx_event(bus->sdiodev->dev, pkt);
2006 else
2007 brcmf_rx_frame(bus->sdiodev->dev, pkt,
2008 false);
2009
2010 /* prepare the descriptor for the next read */
2011 rd->len = rd->len_nxtfrm << 4;
2012 rd->len_nxtfrm = 0;
2013 /* treat all packet as event if we don't know */
2014 rd->channel = SDPCM_EVENT_CHANNEL;
2015 }
2016
2017 rxcount = maxframes - rxleft;
2018 /* Message if we hit the limit */
2019 if (!rxleft)
2020 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes);
2021 else
2022 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2023 /* Back off rxseq if awaiting rtx, update rx_seq */
2024 if (bus->rxskip)
2025 rd->seq_num--;
2026 bus->rx_seq = rd->seq_num;
2027
2028 return rxcount;
2029 }
2030
2031 static void
2032 brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus)
2033 {
2034 wake_up_interruptible(&bus->ctrl_wait);
2035 return;
2036 }
2037
2038 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt)
2039 {
2040 struct brcmf_bus_stats *stats;
2041 u16 head_pad;
2042 u8 *dat_buf;
2043
2044 dat_buf = (u8 *)(pkt->data);
2045
2046 /* Check head padding */
2047 head_pad = ((unsigned long)dat_buf % bus->head_align);
2048 if (head_pad) {
2049 if (skb_headroom(pkt) < head_pad) {
2050 stats = &bus->sdiodev->bus_if->stats;
2051 atomic_inc(&stats->pktcowed);
2052 if (skb_cow_head(pkt, head_pad)) {
2053 atomic_inc(&stats->pktcow_failed);
2054 return -ENOMEM;
2055 }
2056 }
2057 skb_push(pkt, head_pad);
2058 dat_buf = (u8 *)(pkt->data);
2059 }
2060 memset(dat_buf, 0, head_pad + bus->tx_hdrlen);
2061 return 0;
2062 }
2063
2064 /**
2065 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
2066 * bus layer usage.
2067 */
2068 /* flag marking a dummy skb added for DMA alignment requirement */
2069 #define ALIGN_SKB_FLAG 0x8000
2070 /* bit mask of data length chopped from the previous packet */
2071 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
2072
2073 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus,
2074 struct sk_buff_head *pktq,
2075 struct sk_buff *pkt, u16 total_len)
2076 {
2077 struct brcmf_sdio_dev *sdiodev;
2078 struct sk_buff *pkt_pad;
2079 u16 tail_pad, tail_chop, chain_pad;
2080 unsigned int blksize;
2081 bool lastfrm;
2082 int ntail, ret;
2083
2084 sdiodev = bus->sdiodev;
2085 blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize;
2086 /* sg entry alignment should be a divisor of block size */
2087 WARN_ON(blksize % bus->sgentry_align);
2088
2089 /* Check tail padding */
2090 lastfrm = skb_queue_is_last(pktq, pkt);
2091 tail_pad = 0;
2092 tail_chop = pkt->len % bus->sgentry_align;
2093 if (tail_chop)
2094 tail_pad = bus->sgentry_align - tail_chop;
2095 chain_pad = (total_len + tail_pad) % blksize;
2096 if (lastfrm && chain_pad)
2097 tail_pad += blksize - chain_pad;
2098 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) {
2099 pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop +
2100 bus->head_align);
2101 if (pkt_pad == NULL)
2102 return -ENOMEM;
2103 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad);
2104 if (unlikely(ret < 0)) {
2105 kfree_skb(pkt_pad);
2106 return ret;
2107 }
2108 memcpy(pkt_pad->data,
2109 pkt->data + pkt->len - tail_chop,
2110 tail_chop);
2111 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop;
2112 skb_trim(pkt, pkt->len - tail_chop);
2113 skb_trim(pkt_pad, tail_pad + tail_chop);
2114 __skb_queue_after(pktq, pkt, pkt_pad);
2115 } else {
2116 ntail = pkt->data_len + tail_pad -
2117 (pkt->end - pkt->tail);
2118 if (skb_cloned(pkt) || ntail > 0)
2119 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC))
2120 return -ENOMEM;
2121 if (skb_linearize(pkt))
2122 return -ENOMEM;
2123 __skb_put(pkt, tail_pad);
2124 }
2125
2126 return tail_pad;
2127 }
2128
2129 /**
2130 * brcmf_sdio_txpkt_prep - packet preparation for transmit
2131 * @bus: brcmf_sdio structure pointer
2132 * @pktq: packet list pointer
2133 * @chan: virtual channel to transmit the packet
2134 *
2135 * Processes to be applied to the packet
2136 * - Align data buffer pointer
2137 * - Align data buffer length
2138 * - Prepare header
2139 * Return: negative value if there is error
2140 */
2141 static int
2142 brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2143 uint chan)
2144 {
2145 u16 head_pad, total_len;
2146 struct sk_buff *pkt_next;
2147 u8 txseq;
2148 int ret;
2149 struct brcmf_sdio_hdrinfo hd_info = {0};
2150
2151 txseq = bus->tx_seq;
2152 total_len = 0;
2153 skb_queue_walk(pktq, pkt_next) {
2154 /* alignment packet inserted in previous
2155 * loop cycle can be skipped as it is
2156 * already properly aligned and does not
2157 * need an sdpcm header.
2158 */
2159 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG)
2160 continue;
2161
2162 /* align packet data pointer */
2163 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next);
2164 if (ret < 0)
2165 return ret;
2166 head_pad = (u16)ret;
2167 if (head_pad)
2168 memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad);
2169
2170 total_len += pkt_next->len;
2171
2172 hd_info.len = pkt_next->len;
2173 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next);
2174 if (bus->txglom && pktq->qlen > 1) {
2175 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq,
2176 pkt_next, total_len);
2177 if (ret < 0)
2178 return ret;
2179 hd_info.tail_pad = (u16)ret;
2180 total_len += (u16)ret;
2181 }
2182
2183 hd_info.channel = chan;
2184 hd_info.dat_offset = head_pad + bus->tx_hdrlen;
2185 hd_info.seq_num = txseq++;
2186
2187 /* Now fill the header */
2188 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info);
2189
2190 if (BRCMF_BYTES_ON() &&
2191 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
2192 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)))
2193 brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len,
2194 "Tx Frame:\n");
2195 else if (BRCMF_HDRS_ON())
2196 brcmf_dbg_hex_dump(true, pkt_next->data,
2197 head_pad + bus->tx_hdrlen,
2198 "Tx Header:\n");
2199 }
2200 /* Hardware length tag of the first packet should be total
2201 * length of the chain (including padding)
2202 */
2203 if (bus->txglom)
2204 brcmf_sdio_update_hwhdr(pktq->next->data, total_len);
2205 return 0;
2206 }
2207
2208 /**
2209 * brcmf_sdio_txpkt_postp - packet post processing for transmit
2210 * @bus: brcmf_sdio structure pointer
2211 * @pktq: packet list pointer
2212 *
2213 * Processes to be applied to the packet
2214 * - Remove head padding
2215 * - Remove tail padding
2216 */
2217 static void
2218 brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq)
2219 {
2220 u8 *hdr;
2221 u32 dat_offset;
2222 u16 tail_pad;
2223 u16 dummy_flags, chop_len;
2224 struct sk_buff *pkt_next, *tmp, *pkt_prev;
2225
2226 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2227 dummy_flags = *(u16 *)(pkt_next->cb);
2228 if (dummy_flags & ALIGN_SKB_FLAG) {
2229 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK;
2230 if (chop_len) {
2231 pkt_prev = pkt_next->prev;
2232 skb_put(pkt_prev, chop_len);
2233 }
2234 __skb_unlink(pkt_next, pktq);
2235 brcmu_pkt_buf_free_skb(pkt_next);
2236 } else {
2237 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN;
2238 dat_offset = le32_to_cpu(*(__le32 *)hdr);
2239 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >>
2240 SDPCM_DOFFSET_SHIFT;
2241 skb_pull(pkt_next, dat_offset);
2242 if (bus->txglom) {
2243 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2));
2244 skb_trim(pkt_next, pkt_next->len - tail_pad);
2245 }
2246 }
2247 }
2248 }
2249
2250 /* Writes a HW/SW header into the packet and sends it. */
2251 /* Assumes: (a) header space already there, (b) caller holds lock */
2252 static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2253 uint chan)
2254 {
2255 int ret;
2256 struct sk_buff *pkt_next, *tmp;
2257
2258 brcmf_dbg(TRACE, "Enter\n");
2259
2260 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan);
2261 if (ret)
2262 goto done;
2263
2264 sdio_claim_host(bus->sdiodev->func[1]);
2265 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq);
2266 bus->sdcnt.f2txdata++;
2267
2268 if (ret < 0)
2269 brcmf_sdio_txfail(bus);
2270
2271 sdio_release_host(bus->sdiodev->func[1]);
2272
2273 done:
2274 brcmf_sdio_txpkt_postp(bus, pktq);
2275 if (ret == 0)
2276 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP;
2277 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2278 __skb_unlink(pkt_next, pktq);
2279 brcmf_proto_bcdc_txcomplete(bus->sdiodev->dev, pkt_next,
2280 ret == 0);
2281 }
2282 return ret;
2283 }
2284
2285 static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes)
2286 {
2287 struct sk_buff *pkt;
2288 struct sk_buff_head pktq;
2289 u32 intstatus = 0;
2290 int ret = 0, prec_out, i;
2291 uint cnt = 0;
2292 u8 tx_prec_map, pkt_num;
2293
2294 brcmf_dbg(TRACE, "Enter\n");
2295
2296 tx_prec_map = ~bus->flowcontrol;
2297
2298 /* Send frames until the limit or some other event */
2299 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) {
2300 pkt_num = 1;
2301 if (bus->txglom)
2302 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq,
2303 bus->sdiodev->txglomsz);
2304 pkt_num = min_t(u32, pkt_num,
2305 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol));
2306 __skb_queue_head_init(&pktq);
2307 spin_lock_bh(&bus->txq_lock);
2308 for (i = 0; i < pkt_num; i++) {
2309 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map,
2310 &prec_out);
2311 if (pkt == NULL)
2312 break;
2313 __skb_queue_tail(&pktq, pkt);
2314 }
2315 spin_unlock_bh(&bus->txq_lock);
2316 if (i == 0)
2317 break;
2318
2319 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL);
2320
2321 cnt += i;
2322
2323 /* In poll mode, need to check for other events */
2324 if (!bus->intr) {
2325 /* Check device status, signal pending interrupt */
2326 sdio_claim_host(bus->sdiodev->func[1]);
2327 ret = r_sdreg32(bus, &intstatus,
2328 offsetof(struct sdpcmd_regs,
2329 intstatus));
2330 sdio_release_host(bus->sdiodev->func[1]);
2331 bus->sdcnt.f2txdata++;
2332 if (ret != 0)
2333 break;
2334 if (intstatus & bus->hostintmask)
2335 atomic_set(&bus->ipend, 1);
2336 }
2337 }
2338
2339 /* Deflow-control stack if needed */
2340 if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) &&
2341 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
2342 bus->txoff = false;
2343 brcmf_proto_bcdc_txflowblock(bus->sdiodev->dev, false);
2344 }
2345
2346 return cnt;
2347 }
2348
2349 static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len)
2350 {
2351 u8 doff;
2352 u16 pad;
2353 uint retries = 0;
2354 struct brcmf_sdio_hdrinfo hd_info = {0};
2355 int ret;
2356
2357 brcmf_dbg(TRACE, "Enter\n");
2358
2359 /* Back the pointer to make room for bus header */
2360 frame -= bus->tx_hdrlen;
2361 len += bus->tx_hdrlen;
2362
2363 /* Add alignment padding (optional for ctl frames) */
2364 doff = ((unsigned long)frame % bus->head_align);
2365 if (doff) {
2366 frame -= doff;
2367 len += doff;
2368 memset(frame + bus->tx_hdrlen, 0, doff);
2369 }
2370
2371 /* Round send length to next SDIO block */
2372 pad = 0;
2373 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2374 pad = bus->blocksize - (len % bus->blocksize);
2375 if ((pad > bus->roundup) || (pad >= bus->blocksize))
2376 pad = 0;
2377 } else if (len % bus->head_align) {
2378 pad = bus->head_align - (len % bus->head_align);
2379 }
2380 len += pad;
2381
2382 hd_info.len = len - pad;
2383 hd_info.channel = SDPCM_CONTROL_CHANNEL;
2384 hd_info.dat_offset = doff + bus->tx_hdrlen;
2385 hd_info.seq_num = bus->tx_seq;
2386 hd_info.lastfrm = true;
2387 hd_info.tail_pad = pad;
2388 brcmf_sdio_hdpack(bus, frame, &hd_info);
2389
2390 if (bus->txglom)
2391 brcmf_sdio_update_hwhdr(frame, len);
2392
2393 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
2394 frame, len, "Tx Frame:\n");
2395 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
2396 BRCMF_HDRS_ON(),
2397 frame, min_t(u16, len, 16), "TxHdr:\n");
2398
2399 do {
2400 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len);
2401
2402 if (ret < 0)
2403 brcmf_sdio_txfail(bus);
2404 else
2405 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
2406 } while (ret < 0 && retries++ < TXRETRIES);
2407
2408 return ret;
2409 }
2410
2411 static void brcmf_sdio_bus_stop(struct device *dev)
2412 {
2413 u32 local_hostintmask;
2414 u8 saveclk;
2415 int err;
2416 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2417 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2418 struct brcmf_sdio *bus = sdiodev->bus;
2419
2420 brcmf_dbg(TRACE, "Enter\n");
2421
2422 if (bus->watchdog_tsk) {
2423 send_sig(SIGTERM, bus->watchdog_tsk, 1);
2424 kthread_stop(bus->watchdog_tsk);
2425 bus->watchdog_tsk = NULL;
2426 }
2427
2428 if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
2429 sdio_claim_host(sdiodev->func[1]);
2430
2431 /* Enable clock for device interrupts */
2432 brcmf_sdio_bus_sleep(bus, false, false);
2433
2434 /* Disable and clear interrupts at the chip level also */
2435 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask));
2436 local_hostintmask = bus->hostintmask;
2437 bus->hostintmask = 0;
2438
2439 /* Force backplane clocks to assure F2 interrupt propagates */
2440 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2441 &err);
2442 if (!err)
2443 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2444 (saveclk | SBSDIO_FORCE_HT), &err);
2445 if (err)
2446 brcmf_err("Failed to force clock for F2: err %d\n",
2447 err);
2448
2449 /* Turn off the bus (F2), free any pending packets */
2450 brcmf_dbg(INTR, "disable SDIO interrupts\n");
2451 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
2452
2453 /* Clear any pending interrupts now that F2 is disabled */
2454 w_sdreg32(bus, local_hostintmask,
2455 offsetof(struct sdpcmd_regs, intstatus));
2456
2457 sdio_release_host(sdiodev->func[1]);
2458 }
2459 /* Clear the data packet queues */
2460 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
2461
2462 /* Clear any held glomming stuff */
2463 brcmu_pkt_buf_free_skb(bus->glomd);
2464 brcmf_sdio_free_glom(bus);
2465
2466 /* Clear rx control and wake any waiters */
2467 spin_lock_bh(&bus->rxctl_lock);
2468 bus->rxlen = 0;
2469 spin_unlock_bh(&bus->rxctl_lock);
2470 brcmf_sdio_dcmd_resp_wake(bus);
2471
2472 /* Reset some F2 state stuff */
2473 bus->rxskip = false;
2474 bus->tx_seq = bus->rx_seq = 0;
2475 }
2476
2477 static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus)
2478 {
2479 struct brcmf_sdio_dev *sdiodev;
2480 unsigned long flags;
2481
2482 sdiodev = bus->sdiodev;
2483 if (sdiodev->oob_irq_requested) {
2484 spin_lock_irqsave(&sdiodev->irq_en_lock, flags);
2485 if (!sdiodev->irq_en && !atomic_read(&bus->ipend)) {
2486 enable_irq(sdiodev->settings->bus.sdio.oob_irq_nr);
2487 sdiodev->irq_en = true;
2488 }
2489 spin_unlock_irqrestore(&sdiodev->irq_en_lock, flags);
2490 }
2491 }
2492
2493 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
2494 {
2495 struct brcmf_core *buscore;
2496 u32 addr;
2497 unsigned long val;
2498 int ret;
2499
2500 buscore = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
2501 addr = buscore->base + offsetof(struct sdpcmd_regs, intstatus);
2502
2503 val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret);
2504 bus->sdcnt.f1regdata++;
2505 if (ret != 0)
2506 return ret;
2507
2508 val &= bus->hostintmask;
2509 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE));
2510
2511 /* Clear interrupts */
2512 if (val) {
2513 brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret);
2514 bus->sdcnt.f1regdata++;
2515 atomic_or(val, &bus->intstatus);
2516 }
2517
2518 return ret;
2519 }
2520
2521 static void brcmf_sdio_dpc(struct brcmf_sdio *bus)
2522 {
2523 u32 newstatus = 0;
2524 unsigned long intstatus;
2525 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2526 uint framecnt; /* Temporary counter of tx/rx frames */
2527 int err = 0;
2528
2529 brcmf_dbg(TRACE, "Enter\n");
2530
2531 sdio_claim_host(bus->sdiodev->func[1]);
2532
2533 /* If waiting for HTAVAIL, check status */
2534 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) {
2535 u8 clkctl, devctl = 0;
2536
2537 #ifdef DEBUG
2538 /* Check for inconsistent device control */
2539 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2540 SBSDIO_DEVICE_CTL, &err);
2541 #endif /* DEBUG */
2542
2543 /* Read CSR, if clock on switch to AVAIL, else ignore */
2544 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
2545 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2546
2547 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2548 devctl, clkctl);
2549
2550 if (SBSDIO_HTAV(clkctl)) {
2551 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2552 SBSDIO_DEVICE_CTL, &err);
2553 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2554 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
2555 devctl, &err);
2556 bus->clkstate = CLK_AVAIL;
2557 }
2558 }
2559
2560 /* Make sure backplane clock is on */
2561 brcmf_sdio_bus_sleep(bus, false, true);
2562
2563 /* Pending interrupt indicates new device status */
2564 if (atomic_read(&bus->ipend) > 0) {
2565 atomic_set(&bus->ipend, 0);
2566 err = brcmf_sdio_intr_rstatus(bus);
2567 }
2568
2569 /* Start with leftover status bits */
2570 intstatus = atomic_xchg(&bus->intstatus, 0);
2571
2572 /* Handle flow-control change: read new state in case our ack
2573 * crossed another change interrupt. If change still set, assume
2574 * FC ON for safety, let next loop through do the debounce.
2575 */
2576 if (intstatus & I_HMB_FC_CHANGE) {
2577 intstatus &= ~I_HMB_FC_CHANGE;
2578 err = w_sdreg32(bus, I_HMB_FC_CHANGE,
2579 offsetof(struct sdpcmd_regs, intstatus));
2580
2581 err = r_sdreg32(bus, &newstatus,
2582 offsetof(struct sdpcmd_regs, intstatus));
2583 bus->sdcnt.f1regdata += 2;
2584 atomic_set(&bus->fcstate,
2585 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)));
2586 intstatus |= (newstatus & bus->hostintmask);
2587 }
2588
2589 /* Handle host mailbox indication */
2590 if (intstatus & I_HMB_HOST_INT) {
2591 intstatus &= ~I_HMB_HOST_INT;
2592 intstatus |= brcmf_sdio_hostmail(bus);
2593 }
2594
2595 sdio_release_host(bus->sdiodev->func[1]);
2596
2597 /* Generally don't ask for these, can get CRC errors... */
2598 if (intstatus & I_WR_OOSYNC) {
2599 brcmf_err("Dongle reports WR_OOSYNC\n");
2600 intstatus &= ~I_WR_OOSYNC;
2601 }
2602
2603 if (intstatus & I_RD_OOSYNC) {
2604 brcmf_err("Dongle reports RD_OOSYNC\n");
2605 intstatus &= ~I_RD_OOSYNC;
2606 }
2607
2608 if (intstatus & I_SBINT) {
2609 brcmf_err("Dongle reports SBINT\n");
2610 intstatus &= ~I_SBINT;
2611 }
2612
2613 /* Would be active due to wake-wlan in gSPI */
2614 if (intstatus & I_CHIPACTIVE) {
2615 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2616 intstatus &= ~I_CHIPACTIVE;
2617 }
2618
2619 /* Ignore frame indications if rxskip is set */
2620 if (bus->rxskip)
2621 intstatus &= ~I_HMB_FRAME_IND;
2622
2623 /* On frame indication, read available frames */
2624 if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) {
2625 brcmf_sdio_readframes(bus, bus->rxbound);
2626 if (!bus->rxpending)
2627 intstatus &= ~I_HMB_FRAME_IND;
2628 }
2629
2630 /* Keep still-pending events for next scheduling */
2631 if (intstatus)
2632 atomic_or(intstatus, &bus->intstatus);
2633
2634 brcmf_sdio_clrintr(bus);
2635
2636 if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) &&
2637 data_ok(bus)) {
2638 sdio_claim_host(bus->sdiodev->func[1]);
2639 if (bus->ctrl_frame_stat) {
2640 err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf,
2641 bus->ctrl_frame_len);
2642 bus->ctrl_frame_err = err;
2643 wmb();
2644 bus->ctrl_frame_stat = false;
2645 }
2646 sdio_release_host(bus->sdiodev->func[1]);
2647 brcmf_sdio_wait_event_wakeup(bus);
2648 }
2649 /* Send queued frames (limit 1 if rx may still be pending) */
2650 if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
2651 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit &&
2652 data_ok(bus)) {
2653 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
2654 txlimit;
2655 brcmf_sdio_sendfromq(bus, framecnt);
2656 }
2657
2658 if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) {
2659 brcmf_err("failed backplane access over SDIO, halting operation\n");
2660 atomic_set(&bus->intstatus, 0);
2661 if (bus->ctrl_frame_stat) {
2662 sdio_claim_host(bus->sdiodev->func[1]);
2663 if (bus->ctrl_frame_stat) {
2664 bus->ctrl_frame_err = -ENODEV;
2665 wmb();
2666 bus->ctrl_frame_stat = false;
2667 brcmf_sdio_wait_event_wakeup(bus);
2668 }
2669 sdio_release_host(bus->sdiodev->func[1]);
2670 }
2671 } else if (atomic_read(&bus->intstatus) ||
2672 atomic_read(&bus->ipend) > 0 ||
2673 (!atomic_read(&bus->fcstate) &&
2674 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
2675 data_ok(bus))) {
2676 bus->dpc_triggered = true;
2677 }
2678 }
2679
2680 static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev)
2681 {
2682 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2683 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2684 struct brcmf_sdio *bus = sdiodev->bus;
2685
2686 return &bus->txq;
2687 }
2688
2689 static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec)
2690 {
2691 struct sk_buff *p;
2692 int eprec = -1; /* precedence to evict from */
2693
2694 /* Fast case, precedence queue is not full and we are also not
2695 * exceeding total queue length
2696 */
2697 if (!pktq_pfull(q, prec) && !pktq_full(q)) {
2698 brcmu_pktq_penq(q, prec, pkt);
2699 return true;
2700 }
2701
2702 /* Determine precedence from which to evict packet, if any */
2703 if (pktq_pfull(q, prec)) {
2704 eprec = prec;
2705 } else if (pktq_full(q)) {
2706 p = brcmu_pktq_peek_tail(q, &eprec);
2707 if (eprec > prec)
2708 return false;
2709 }
2710
2711 /* Evict if needed */
2712 if (eprec >= 0) {
2713 /* Detect queueing to unconfigured precedence */
2714 if (eprec == prec)
2715 return false; /* refuse newer (incoming) packet */
2716 /* Evict packet according to discard policy */
2717 p = brcmu_pktq_pdeq_tail(q, eprec);
2718 if (p == NULL)
2719 brcmf_err("brcmu_pktq_pdeq_tail() failed\n");
2720 brcmu_pkt_buf_free_skb(p);
2721 }
2722
2723 /* Enqueue */
2724 p = brcmu_pktq_penq(q, prec, pkt);
2725 if (p == NULL)
2726 brcmf_err("brcmu_pktq_penq() failed\n");
2727
2728 return p != NULL;
2729 }
2730
2731 static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt)
2732 {
2733 int ret = -EBADE;
2734 uint prec;
2735 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2736 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2737 struct brcmf_sdio *bus = sdiodev->bus;
2738
2739 brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len);
2740 if (sdiodev->state != BRCMF_SDIOD_DATA)
2741 return -EIO;
2742
2743 /* Add space for the header */
2744 skb_push(pkt, bus->tx_hdrlen);
2745 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2746
2747 prec = prio2prec((pkt->priority & PRIOMASK));
2748
2749 /* Check for existing queue, current flow-control,
2750 pending event, or pending clock */
2751 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2752 bus->sdcnt.fcqueued++;
2753
2754 /* Priority based enq */
2755 spin_lock_bh(&bus->txq_lock);
2756 /* reset bus_flags in packet cb */
2757 *(u16 *)(pkt->cb) = 0;
2758 if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) {
2759 skb_pull(pkt, bus->tx_hdrlen);
2760 brcmf_err("out of bus->txq !!!\n");
2761 ret = -ENOSR;
2762 } else {
2763 ret = 0;
2764 }
2765
2766 if (pktq_len(&bus->txq) >= TXHI) {
2767 bus->txoff = true;
2768 brcmf_proto_bcdc_txflowblock(dev, true);
2769 }
2770 spin_unlock_bh(&bus->txq_lock);
2771
2772 #ifdef DEBUG
2773 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2774 qcount[prec] = pktq_plen(&bus->txq, prec);
2775 #endif
2776
2777 brcmf_sdio_trigger_dpc(bus);
2778 return ret;
2779 }
2780
2781 #ifdef DEBUG
2782 #define CONSOLE_LINE_MAX 192
2783
2784 static int brcmf_sdio_readconsole(struct brcmf_sdio *bus)
2785 {
2786 struct brcmf_console *c = &bus->console;
2787 u8 line[CONSOLE_LINE_MAX], ch;
2788 u32 n, idx, addr;
2789 int rv;
2790
2791 /* Don't do anything until FWREADY updates console address */
2792 if (bus->console_addr == 0)
2793 return 0;
2794
2795 /* Read console log struct */
2796 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2797 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
2798 sizeof(c->log_le));
2799 if (rv < 0)
2800 return rv;
2801
2802 /* Allocate console buffer (one time only) */
2803 if (c->buf == NULL) {
2804 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2805 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2806 if (c->buf == NULL)
2807 return -ENOMEM;
2808 }
2809
2810 idx = le32_to_cpu(c->log_le.idx);
2811
2812 /* Protect against corrupt value */
2813 if (idx > c->bufsize)
2814 return -EBADE;
2815
2816 /* Skip reading the console buffer if the index pointer
2817 has not moved */
2818 if (idx == c->last)
2819 return 0;
2820
2821 /* Read the console buffer */
2822 addr = le32_to_cpu(c->log_le.buf);
2823 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
2824 if (rv < 0)
2825 return rv;
2826
2827 while (c->last != idx) {
2828 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2829 if (c->last == idx) {
2830 /* This would output a partial line.
2831 * Instead, back up
2832 * the buffer pointer and output this
2833 * line next time around.
2834 */
2835 if (c->last >= n)
2836 c->last -= n;
2837 else
2838 c->last = c->bufsize - n;
2839 goto break2;
2840 }
2841 ch = c->buf[c->last];
2842 c->last = (c->last + 1) % c->bufsize;
2843 if (ch == '\n')
2844 break;
2845 line[n] = ch;
2846 }
2847
2848 if (n > 0) {
2849 if (line[n - 1] == '\r')
2850 n--;
2851 line[n] = 0;
2852 pr_debug("CONSOLE: %s\n", line);
2853 }
2854 }
2855 break2:
2856
2857 return 0;
2858 }
2859 #endif /* DEBUG */
2860
2861 static int
2862 brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
2863 {
2864 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2865 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2866 struct brcmf_sdio *bus = sdiodev->bus;
2867 int ret;
2868
2869 brcmf_dbg(TRACE, "Enter\n");
2870 if (sdiodev->state != BRCMF_SDIOD_DATA)
2871 return -EIO;
2872
2873 /* Send from dpc */
2874 bus->ctrl_frame_buf = msg;
2875 bus->ctrl_frame_len = msglen;
2876 wmb();
2877 bus->ctrl_frame_stat = true;
2878
2879 brcmf_sdio_trigger_dpc(bus);
2880 wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat,
2881 CTL_DONE_TIMEOUT);
2882 ret = 0;
2883 if (bus->ctrl_frame_stat) {
2884 sdio_claim_host(bus->sdiodev->func[1]);
2885 if (bus->ctrl_frame_stat) {
2886 brcmf_dbg(SDIO, "ctrl_frame timeout\n");
2887 bus->ctrl_frame_stat = false;
2888 ret = -ETIMEDOUT;
2889 }
2890 sdio_release_host(bus->sdiodev->func[1]);
2891 }
2892 if (!ret) {
2893 brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n",
2894 bus->ctrl_frame_err);
2895 rmb();
2896 ret = bus->ctrl_frame_err;
2897 }
2898
2899 if (ret)
2900 bus->sdcnt.tx_ctlerrs++;
2901 else
2902 bus->sdcnt.tx_ctlpkts++;
2903
2904 return ret;
2905 }
2906
2907 #ifdef DEBUG
2908 static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus,
2909 struct sdpcm_shared *sh)
2910 {
2911 u32 addr, console_ptr, console_size, console_index;
2912 char *conbuf = NULL;
2913 __le32 sh_val;
2914 int rv;
2915
2916 /* obtain console information from device memory */
2917 addr = sh->console_addr + offsetof(struct rte_console, log_le);
2918 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2919 (u8 *)&sh_val, sizeof(u32));
2920 if (rv < 0)
2921 return rv;
2922 console_ptr = le32_to_cpu(sh_val);
2923
2924 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
2925 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2926 (u8 *)&sh_val, sizeof(u32));
2927 if (rv < 0)
2928 return rv;
2929 console_size = le32_to_cpu(sh_val);
2930
2931 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
2932 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2933 (u8 *)&sh_val, sizeof(u32));
2934 if (rv < 0)
2935 return rv;
2936 console_index = le32_to_cpu(sh_val);
2937
2938 /* allocate buffer for console data */
2939 if (console_size <= CONSOLE_BUFFER_MAX)
2940 conbuf = vzalloc(console_size+1);
2941
2942 if (!conbuf)
2943 return -ENOMEM;
2944
2945 /* obtain the console data from device */
2946 conbuf[console_size] = '\0';
2947 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
2948 console_size);
2949 if (rv < 0)
2950 goto done;
2951
2952 rv = seq_write(seq, conbuf + console_index,
2953 console_size - console_index);
2954 if (rv < 0)
2955 goto done;
2956
2957 if (console_index > 0)
2958 rv = seq_write(seq, conbuf, console_index - 1);
2959
2960 done:
2961 vfree(conbuf);
2962 return rv;
2963 }
2964
2965 static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus,
2966 struct sdpcm_shared *sh)
2967 {
2968 int error;
2969 struct brcmf_trap_info tr;
2970
2971 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) {
2972 brcmf_dbg(INFO, "no trap in firmware\n");
2973 return 0;
2974 }
2975
2976 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
2977 sizeof(struct brcmf_trap_info));
2978 if (error < 0)
2979 return error;
2980
2981 seq_printf(seq,
2982 "dongle trap info: type 0x%x @ epc 0x%08x\n"
2983 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
2984 " lr 0x%08x pc 0x%08x offset 0x%x\n"
2985 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
2986 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
2987 le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
2988 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
2989 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
2990 le32_to_cpu(tr.pc), sh->trap_addr,
2991 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
2992 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
2993 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
2994 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
2995
2996 return 0;
2997 }
2998
2999 static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus,
3000 struct sdpcm_shared *sh)
3001 {
3002 int error = 0;
3003 char file[80] = "?";
3004 char expr[80] = "<???>";
3005
3006 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
3007 brcmf_dbg(INFO, "firmware not built with -assert\n");
3008 return 0;
3009 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
3010 brcmf_dbg(INFO, "no assert in dongle\n");
3011 return 0;
3012 }
3013
3014 sdio_claim_host(bus->sdiodev->func[1]);
3015 if (sh->assert_file_addr != 0) {
3016 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3017 sh->assert_file_addr, (u8 *)file, 80);
3018 if (error < 0)
3019 return error;
3020 }
3021 if (sh->assert_exp_addr != 0) {
3022 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3023 sh->assert_exp_addr, (u8 *)expr, 80);
3024 if (error < 0)
3025 return error;
3026 }
3027 sdio_release_host(bus->sdiodev->func[1]);
3028
3029 seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n",
3030 file, sh->assert_line, expr);
3031 return 0;
3032 }
3033
3034 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3035 {
3036 int error;
3037 struct sdpcm_shared sh;
3038
3039 error = brcmf_sdio_readshared(bus, &sh);
3040
3041 if (error < 0)
3042 return error;
3043
3044 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
3045 brcmf_dbg(INFO, "firmware not built with -assert\n");
3046 else if (sh.flags & SDPCM_SHARED_ASSERT)
3047 brcmf_err("assertion in dongle\n");
3048
3049 if (sh.flags & SDPCM_SHARED_TRAP)
3050 brcmf_err("firmware trap in dongle\n");
3051
3052 return 0;
3053 }
3054
3055 static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus)
3056 {
3057 int error = 0;
3058 struct sdpcm_shared sh;
3059
3060 error = brcmf_sdio_readshared(bus, &sh);
3061 if (error < 0)
3062 goto done;
3063
3064 error = brcmf_sdio_assert_info(seq, bus, &sh);
3065 if (error < 0)
3066 goto done;
3067
3068 error = brcmf_sdio_trap_info(seq, bus, &sh);
3069 if (error < 0)
3070 goto done;
3071
3072 error = brcmf_sdio_dump_console(seq, bus, &sh);
3073
3074 done:
3075 return error;
3076 }
3077
3078 static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data)
3079 {
3080 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3081 struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus;
3082
3083 return brcmf_sdio_died_dump(seq, bus);
3084 }
3085
3086 static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data)
3087 {
3088 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3089 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3090 struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt;
3091
3092 seq_printf(seq,
3093 "intrcount: %u\nlastintrs: %u\n"
3094 "pollcnt: %u\nregfails: %u\n"
3095 "tx_sderrs: %u\nfcqueued: %u\n"
3096 "rxrtx: %u\nrx_toolong: %u\n"
3097 "rxc_errors: %u\nrx_hdrfail: %u\n"
3098 "rx_badhdr: %u\nrx_badseq: %u\n"
3099 "fc_rcvd: %u\nfc_xoff: %u\n"
3100 "fc_xon: %u\nrxglomfail: %u\n"
3101 "rxglomframes: %u\nrxglompkts: %u\n"
3102 "f2rxhdrs: %u\nf2rxdata: %u\n"
3103 "f2txdata: %u\nf1regdata: %u\n"
3104 "tickcnt: %u\ntx_ctlerrs: %lu\n"
3105 "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n"
3106 "rx_ctlpkts: %lu\nrx_readahead: %lu\n",
3107 sdcnt->intrcount, sdcnt->lastintrs,
3108 sdcnt->pollcnt, sdcnt->regfails,
3109 sdcnt->tx_sderrs, sdcnt->fcqueued,
3110 sdcnt->rxrtx, sdcnt->rx_toolong,
3111 sdcnt->rxc_errors, sdcnt->rx_hdrfail,
3112 sdcnt->rx_badhdr, sdcnt->rx_badseq,
3113 sdcnt->fc_rcvd, sdcnt->fc_xoff,
3114 sdcnt->fc_xon, sdcnt->rxglomfail,
3115 sdcnt->rxglomframes, sdcnt->rxglompkts,
3116 sdcnt->f2rxhdrs, sdcnt->f2rxdata,
3117 sdcnt->f2txdata, sdcnt->f1regdata,
3118 sdcnt->tickcnt, sdcnt->tx_ctlerrs,
3119 sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs,
3120 sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt);
3121
3122 return 0;
3123 }
3124
3125 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3126 {
3127 struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr;
3128 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
3129
3130 if (IS_ERR_OR_NULL(dentry))
3131 return;
3132
3133 bus->console_interval = BRCMF_CONSOLE;
3134
3135 brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read);
3136 brcmf_debugfs_add_entry(drvr, "counters",
3137 brcmf_debugfs_sdio_count_read);
3138 debugfs_create_u32("console_interval", 0644, dentry,
3139 &bus->console_interval);
3140 }
3141 #else
3142 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3143 {
3144 return 0;
3145 }
3146
3147 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3148 {
3149 }
3150 #endif /* DEBUG */
3151
3152 static int
3153 brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
3154 {
3155 int timeleft;
3156 uint rxlen = 0;
3157 bool pending;
3158 u8 *buf;
3159 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3160 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3161 struct brcmf_sdio *bus = sdiodev->bus;
3162
3163 brcmf_dbg(TRACE, "Enter\n");
3164 if (sdiodev->state != BRCMF_SDIOD_DATA)
3165 return -EIO;
3166
3167 /* Wait until control frame is available */
3168 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3169
3170 spin_lock_bh(&bus->rxctl_lock);
3171 rxlen = bus->rxlen;
3172 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3173 bus->rxctl = NULL;
3174 buf = bus->rxctl_orig;
3175 bus->rxctl_orig = NULL;
3176 bus->rxlen = 0;
3177 spin_unlock_bh(&bus->rxctl_lock);
3178 vfree(buf);
3179
3180 if (rxlen) {
3181 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3182 rxlen, msglen);
3183 } else if (timeleft == 0) {
3184 brcmf_err("resumed on timeout\n");
3185 brcmf_sdio_checkdied(bus);
3186 } else if (pending) {
3187 brcmf_dbg(CTL, "cancelled\n");
3188 return -ERESTARTSYS;
3189 } else {
3190 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3191 brcmf_sdio_checkdied(bus);
3192 }
3193
3194 if (rxlen)
3195 bus->sdcnt.rx_ctlpkts++;
3196 else
3197 bus->sdcnt.rx_ctlerrs++;
3198
3199 return rxlen ? (int)rxlen : -ETIMEDOUT;
3200 }
3201
3202 #ifdef DEBUG
3203 static bool
3204 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3205 u8 *ram_data, uint ram_sz)
3206 {
3207 char *ram_cmp;
3208 int err;
3209 bool ret = true;
3210 int address;
3211 int offset;
3212 int len;
3213
3214 /* read back and verify */
3215 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr,
3216 ram_sz);
3217 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL);
3218 /* do not proceed while no memory but */
3219 if (!ram_cmp)
3220 return true;
3221
3222 address = ram_addr;
3223 offset = 0;
3224 while (offset < ram_sz) {
3225 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK :
3226 ram_sz - offset;
3227 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len);
3228 if (err) {
3229 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3230 err, len, address);
3231 ret = false;
3232 break;
3233 } else if (memcmp(ram_cmp, &ram_data[offset], len)) {
3234 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n",
3235 offset, len);
3236 ret = false;
3237 break;
3238 }
3239 offset += len;
3240 address += len;
3241 }
3242
3243 kfree(ram_cmp);
3244
3245 return ret;
3246 }
3247 #else /* DEBUG */
3248 static bool
3249 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3250 u8 *ram_data, uint ram_sz)
3251 {
3252 return true;
3253 }
3254 #endif /* DEBUG */
3255
3256 static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
3257 const struct firmware *fw)
3258 {
3259 int err;
3260
3261 brcmf_dbg(TRACE, "Enter\n");
3262
3263 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase,
3264 (u8 *)fw->data, fw->size);
3265 if (err)
3266 brcmf_err("error %d on writing %d membytes at 0x%08x\n",
3267 err, (int)fw->size, bus->ci->rambase);
3268 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase,
3269 (u8 *)fw->data, fw->size))
3270 err = -EIO;
3271
3272 return err;
3273 }
3274
3275 static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus,
3276 void *vars, u32 varsz)
3277 {
3278 int address;
3279 int err;
3280
3281 brcmf_dbg(TRACE, "Enter\n");
3282
3283 address = bus->ci->ramsize - varsz + bus->ci->rambase;
3284 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz);
3285 if (err)
3286 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
3287 err, varsz, address);
3288 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz))
3289 err = -EIO;
3290
3291 return err;
3292 }
3293
3294 static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus,
3295 const struct firmware *fw,
3296 void *nvram, u32 nvlen)
3297 {
3298 int bcmerror;
3299 u32 rstvec;
3300
3301 sdio_claim_host(bus->sdiodev->func[1]);
3302 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
3303
3304 rstvec = get_unaligned_le32(fw->data);
3305 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec);
3306
3307 bcmerror = brcmf_sdio_download_code_file(bus, fw);
3308 release_firmware(fw);
3309 if (bcmerror) {
3310 brcmf_err("dongle image file download failed\n");
3311 brcmf_fw_nvram_free(nvram);
3312 goto err;
3313 }
3314
3315 bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen);
3316 brcmf_fw_nvram_free(nvram);
3317 if (bcmerror) {
3318 brcmf_err("dongle nvram file download failed\n");
3319 goto err;
3320 }
3321
3322 /* Take arm out of reset */
3323 if (!brcmf_chip_set_active(bus->ci, rstvec)) {
3324 brcmf_err("error getting out of ARM core reset\n");
3325 goto err;
3326 }
3327
3328 err:
3329 brcmf_sdio_clkctl(bus, CLK_SDONLY, false);
3330 sdio_release_host(bus->sdiodev->func[1]);
3331 return bcmerror;
3332 }
3333
3334 static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
3335 {
3336 int err = 0;
3337 u8 val;
3338
3339 brcmf_dbg(TRACE, "Enter\n");
3340
3341 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
3342 if (err) {
3343 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
3344 return;
3345 }
3346
3347 val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
3348 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
3349 if (err) {
3350 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
3351 return;
3352 }
3353
3354 /* Add CMD14 Support */
3355 brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
3356 (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
3357 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
3358 &err);
3359 if (err) {
3360 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
3361 return;
3362 }
3363
3364 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3365 SBSDIO_FORCE_HT, &err);
3366 if (err) {
3367 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
3368 return;
3369 }
3370
3371 /* set flag */
3372 bus->sr_enabled = true;
3373 brcmf_dbg(INFO, "SR enabled\n");
3374 }
3375
3376 /* enable KSO bit */
3377 static int brcmf_sdio_kso_init(struct brcmf_sdio *bus)
3378 {
3379 u8 val;
3380 int err = 0;
3381
3382 brcmf_dbg(TRACE, "Enter\n");
3383
3384 /* KSO bit added in SDIO core rev 12 */
3385 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12)
3386 return 0;
3387
3388 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
3389 if (err) {
3390 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
3391 return err;
3392 }
3393
3394 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
3395 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
3396 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
3397 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
3398 val, &err);
3399 if (err) {
3400 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
3401 return err;
3402 }
3403 }
3404
3405 return 0;
3406 }
3407
3408
3409 static int brcmf_sdio_bus_preinit(struct device *dev)
3410 {
3411 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3412 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3413 struct brcmf_sdio *bus = sdiodev->bus;
3414 uint pad_size;
3415 u32 value;
3416 int err;
3417
3418 /* the commands below use the terms tx and rx from
3419 * a device perspective, ie. bus:txglom affects the
3420 * bus transfers from device to host.
3421 */
3422 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) {
3423 /* for sdio core rev < 12, disable txgloming */
3424 value = 0;
3425 err = brcmf_iovar_data_set(dev, "bus:txglom", &value,
3426 sizeof(u32));
3427 } else {
3428 /* otherwise, set txglomalign */
3429 value = sdiodev->settings->bus.sdio.sd_sgentry_align;
3430 /* SDIO ADMA requires at least 32 bit alignment */
3431 value = max_t(u32, value, ALIGNMENT);
3432 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value,
3433 sizeof(u32));
3434 }
3435
3436 if (err < 0)
3437 goto done;
3438
3439 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
3440 if (sdiodev->sg_support) {
3441 bus->txglom = false;
3442 value = 1;
3443 pad_size = bus->sdiodev->func[2]->cur_blksize << 1;
3444 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom",
3445 &value, sizeof(u32));
3446 if (err < 0) {
3447 /* bus:rxglom is allowed to fail */
3448 err = 0;
3449 } else {
3450 bus->txglom = true;
3451 bus->tx_hdrlen += SDPCM_HWEXT_LEN;
3452 }
3453 }
3454 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen);
3455
3456 done:
3457 return err;
3458 }
3459
3460 static size_t brcmf_sdio_bus_get_ramsize(struct device *dev)
3461 {
3462 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3463 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3464 struct brcmf_sdio *bus = sdiodev->bus;
3465
3466 return bus->ci->ramsize - bus->ci->srsize;
3467 }
3468
3469 static int brcmf_sdio_bus_get_memdump(struct device *dev, void *data,
3470 size_t mem_size)
3471 {
3472 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3473 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3474 struct brcmf_sdio *bus = sdiodev->bus;
3475 int err;
3476 int address;
3477 int offset;
3478 int len;
3479
3480 brcmf_dbg(INFO, "dump at 0x%08x: size=%zu\n", bus->ci->rambase,
3481 mem_size);
3482
3483 address = bus->ci->rambase;
3484 offset = err = 0;
3485 sdio_claim_host(sdiodev->func[1]);
3486 while (offset < mem_size) {
3487 len = ((offset + MEMBLOCK) < mem_size) ? MEMBLOCK :
3488 mem_size - offset;
3489 err = brcmf_sdiod_ramrw(sdiodev, false, address, data, len);
3490 if (err) {
3491 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3492 err, len, address);
3493 goto done;
3494 }
3495 data += len;
3496 offset += len;
3497 address += len;
3498 }
3499
3500 done:
3501 sdio_release_host(sdiodev->func[1]);
3502 return err;
3503 }
3504
3505 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus)
3506 {
3507 if (!bus->dpc_triggered) {
3508 bus->dpc_triggered = true;
3509 queue_work(bus->brcmf_wq, &bus->datawork);
3510 }
3511 }
3512
3513 void brcmf_sdio_isr(struct brcmf_sdio *bus)
3514 {
3515 brcmf_dbg(TRACE, "Enter\n");
3516
3517 if (!bus) {
3518 brcmf_err("bus is null pointer, exiting\n");
3519 return;
3520 }
3521
3522 /* Count the interrupt call */
3523 bus->sdcnt.intrcount++;
3524 if (in_interrupt())
3525 atomic_set(&bus->ipend, 1);
3526 else
3527 if (brcmf_sdio_intr_rstatus(bus)) {
3528 brcmf_err("failed backplane access\n");
3529 }
3530
3531 /* Disable additional interrupts (is this needed now)? */
3532 if (!bus->intr)
3533 brcmf_err("isr w/o interrupt configured!\n");
3534
3535 bus->dpc_triggered = true;
3536 queue_work(bus->brcmf_wq, &bus->datawork);
3537 }
3538
3539 static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus)
3540 {
3541 brcmf_dbg(TIMER, "Enter\n");
3542
3543 /* Poll period: check device if appropriate. */
3544 if (!bus->sr_enabled &&
3545 bus->poll && (++bus->polltick >= bus->pollrate)) {
3546 u32 intstatus = 0;
3547
3548 /* Reset poll tick */
3549 bus->polltick = 0;
3550
3551 /* Check device if no interrupts */
3552 if (!bus->intr ||
3553 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
3554
3555 if (!bus->dpc_triggered) {
3556 u8 devpend;
3557
3558 sdio_claim_host(bus->sdiodev->func[1]);
3559 devpend = brcmf_sdiod_regrb(bus->sdiodev,
3560 SDIO_CCCR_INTx,
3561 NULL);
3562 sdio_release_host(bus->sdiodev->func[1]);
3563 intstatus = devpend & (INTR_STATUS_FUNC1 |
3564 INTR_STATUS_FUNC2);
3565 }
3566
3567 /* If there is something, make like the ISR and
3568 schedule the DPC */
3569 if (intstatus) {
3570 bus->sdcnt.pollcnt++;
3571 atomic_set(&bus->ipend, 1);
3572
3573 bus->dpc_triggered = true;
3574 queue_work(bus->brcmf_wq, &bus->datawork);
3575 }
3576 }
3577
3578 /* Update interrupt tracking */
3579 bus->sdcnt.lastintrs = bus->sdcnt.intrcount;
3580 }
3581 #ifdef DEBUG
3582 /* Poll for console output periodically */
3583 if (bus->sdiodev->state == BRCMF_SDIOD_DATA && BRCMF_FWCON_ON() &&
3584 bus->console_interval != 0) {
3585 bus->console.count += jiffies_to_msecs(BRCMF_WD_POLL);
3586 if (bus->console.count >= bus->console_interval) {
3587 bus->console.count -= bus->console_interval;
3588 sdio_claim_host(bus->sdiodev->func[1]);
3589 /* Make sure backplane clock is on */
3590 brcmf_sdio_bus_sleep(bus, false, false);
3591 if (brcmf_sdio_readconsole(bus) < 0)
3592 /* stop on error */
3593 bus->console_interval = 0;
3594 sdio_release_host(bus->sdiodev->func[1]);
3595 }
3596 }
3597 #endif /* DEBUG */
3598
3599 /* On idle timeout clear activity flag and/or turn off clock */
3600 if (!bus->dpc_triggered) {
3601 rmb();
3602 if ((!bus->dpc_running) && (bus->idletime > 0) &&
3603 (bus->clkstate == CLK_AVAIL)) {
3604 bus->idlecount++;
3605 if (bus->idlecount > bus->idletime) {
3606 brcmf_dbg(SDIO, "idle\n");
3607 sdio_claim_host(bus->sdiodev->func[1]);
3608 brcmf_sdio_wd_timer(bus, false);
3609 bus->idlecount = 0;
3610 brcmf_sdio_bus_sleep(bus, true, false);
3611 sdio_release_host(bus->sdiodev->func[1]);
3612 }
3613 } else {
3614 bus->idlecount = 0;
3615 }
3616 } else {
3617 bus->idlecount = 0;
3618 }
3619 }
3620
3621 static void brcmf_sdio_dataworker(struct work_struct *work)
3622 {
3623 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
3624 datawork);
3625
3626 bus->dpc_running = true;
3627 wmb();
3628 while (ACCESS_ONCE(bus->dpc_triggered)) {
3629 bus->dpc_triggered = false;
3630 brcmf_sdio_dpc(bus);
3631 bus->idlecount = 0;
3632 }
3633 bus->dpc_running = false;
3634 if (brcmf_sdiod_freezing(bus->sdiodev)) {
3635 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN);
3636 brcmf_sdiod_try_freeze(bus->sdiodev);
3637 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
3638 }
3639 }
3640
3641 static void
3642 brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
3643 struct brcmf_chip *ci, u32 drivestrength)
3644 {
3645 const struct sdiod_drive_str *str_tab = NULL;
3646 u32 str_mask;
3647 u32 str_shift;
3648 u32 i;
3649 u32 drivestrength_sel = 0;
3650 u32 cc_data_temp;
3651 u32 addr;
3652
3653 if (!(ci->cc_caps & CC_CAP_PMU))
3654 return;
3655
3656 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) {
3657 case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12):
3658 str_tab = sdiod_drvstr_tab1_1v8;
3659 str_mask = 0x00003800;
3660 str_shift = 11;
3661 break;
3662 case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17):
3663 str_tab = sdiod_drvstr_tab6_1v8;
3664 str_mask = 0x00001800;
3665 str_shift = 11;
3666 break;
3667 case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17):
3668 /* note: 43143 does not support tristate */
3669 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1;
3670 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) {
3671 str_tab = sdiod_drvstr_tab2_3v3;
3672 str_mask = 0x00000007;
3673 str_shift = 0;
3674 } else
3675 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n",
3676 ci->name, drivestrength);
3677 break;
3678 case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13):
3679 str_tab = sdiod_drive_strength_tab5_1v8;
3680 str_mask = 0x00003800;
3681 str_shift = 11;
3682 break;
3683 default:
3684 brcmf_dbg(INFO, "No SDIO driver strength init needed for chip %s rev %d pmurev %d\n",
3685 ci->name, ci->chiprev, ci->pmurev);
3686 break;
3687 }
3688
3689 if (str_tab != NULL) {
3690 struct brcmf_core *pmu = brcmf_chip_get_pmu(ci);
3691
3692 for (i = 0; str_tab[i].strength != 0; i++) {
3693 if (drivestrength >= str_tab[i].strength) {
3694 drivestrength_sel = str_tab[i].sel;
3695 break;
3696 }
3697 }
3698 addr = CORE_CC_REG(pmu->base, chipcontrol_addr);
3699 brcmf_sdiod_regwl(sdiodev, addr, 1, NULL);
3700 cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3701 cc_data_temp &= ~str_mask;
3702 drivestrength_sel <<= str_shift;
3703 cc_data_temp |= drivestrength_sel;
3704 brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL);
3705
3706 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
3707 str_tab[i].strength, drivestrength, cc_data_temp);
3708 }
3709 }
3710
3711 static int brcmf_sdio_buscoreprep(void *ctx)
3712 {
3713 struct brcmf_sdio_dev *sdiodev = ctx;
3714 int err = 0;
3715 u8 clkval, clkset;
3716
3717 /* Try forcing SDIO core to do ALPAvail request only */
3718 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
3719 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3720 if (err) {
3721 brcmf_err("error writing for HT off\n");
3722 return err;
3723 }
3724
3725 /* If register supported, wait for ALPAvail and then force ALP */
3726 /* This may take up to 15 milliseconds */
3727 clkval = brcmf_sdiod_regrb(sdiodev,
3728 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
3729
3730 if ((clkval & ~SBSDIO_AVBITS) != clkset) {
3731 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
3732 clkset, clkval);
3733 return -EACCES;
3734 }
3735
3736 SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev,
3737 SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
3738 !SBSDIO_ALPAV(clkval)),
3739 PMU_MAX_TRANSITION_DLY);
3740 if (!SBSDIO_ALPAV(clkval)) {
3741 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n",
3742 clkval);
3743 return -EBUSY;
3744 }
3745
3746 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
3747 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3748 udelay(65);
3749
3750 /* Also, disable the extra SDIO pull-ups */
3751 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
3752
3753 return 0;
3754 }
3755
3756 static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip,
3757 u32 rstvec)
3758 {
3759 struct brcmf_sdio_dev *sdiodev = ctx;
3760 struct brcmf_core *core;
3761 u32 reg_addr;
3762
3763 /* clear all interrupts */
3764 core = brcmf_chip_get_core(chip, BCMA_CORE_SDIO_DEV);
3765 reg_addr = core->base + offsetof(struct sdpcmd_regs, intstatus);
3766 brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
3767
3768 if (rstvec)
3769 /* Write reset vector to address 0 */
3770 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec,
3771 sizeof(rstvec));
3772 }
3773
3774 static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr)
3775 {
3776 struct brcmf_sdio_dev *sdiodev = ctx;
3777 u32 val, rev;
3778
3779 val = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3780 if ((sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 ||
3781 sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4339) &&
3782 addr == CORE_CC_REG(SI_ENUM_BASE, chipid)) {
3783 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT;
3784 if (rev >= 2) {
3785 val &= ~CID_ID_MASK;
3786 val |= BRCM_CC_4339_CHIP_ID;
3787 }
3788 }
3789 return val;
3790 }
3791
3792 static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val)
3793 {
3794 struct brcmf_sdio_dev *sdiodev = ctx;
3795
3796 brcmf_sdiod_regwl(sdiodev, addr, val, NULL);
3797 }
3798
3799 static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = {
3800 .prepare = brcmf_sdio_buscoreprep,
3801 .activate = brcmf_sdio_buscore_activate,
3802 .read32 = brcmf_sdio_buscore_read32,
3803 .write32 = brcmf_sdio_buscore_write32,
3804 };
3805
3806 static bool
3807 brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
3808 {
3809 struct brcmf_sdio_dev *sdiodev;
3810 u8 clkctl = 0;
3811 int err = 0;
3812 int reg_addr;
3813 u32 reg_val;
3814 u32 drivestrength;
3815
3816 sdiodev = bus->sdiodev;
3817 sdio_claim_host(sdiodev->func[1]);
3818
3819 pr_debug("F1 signature read @0x18000000=0x%4x\n",
3820 brcmf_sdiod_regrl(sdiodev, SI_ENUM_BASE, NULL));
3821
3822 /*
3823 * Force PLL off until brcmf_chip_attach()
3824 * programs PLL control regs
3825 */
3826
3827 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3828 BRCMF_INIT_CLKCTL1, &err);
3829 if (!err)
3830 clkctl = brcmf_sdiod_regrb(sdiodev,
3831 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3832
3833 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
3834 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
3835 err, BRCMF_INIT_CLKCTL1, clkctl);
3836 goto fail;
3837 }
3838
3839 bus->ci = brcmf_chip_attach(sdiodev, &brcmf_sdio_buscore_ops);
3840 if (IS_ERR(bus->ci)) {
3841 brcmf_err("brcmf_chip_attach failed!\n");
3842 bus->ci = NULL;
3843 goto fail;
3844 }
3845 sdiodev->settings = brcmf_get_module_param(sdiodev->dev,
3846 BRCMF_BUSTYPE_SDIO,
3847 bus->ci->chip,
3848 bus->ci->chiprev);
3849 if (!sdiodev->settings) {
3850 brcmf_err("Failed to get device parameters\n");
3851 goto fail;
3852 }
3853 /* platform specific configuration:
3854 * alignments must be at least 4 bytes for ADMA
3855 */
3856 bus->head_align = ALIGNMENT;
3857 bus->sgentry_align = ALIGNMENT;
3858 if (sdiodev->settings->bus.sdio.sd_head_align > ALIGNMENT)
3859 bus->head_align = sdiodev->settings->bus.sdio.sd_head_align;
3860 if (sdiodev->settings->bus.sdio.sd_sgentry_align > ALIGNMENT)
3861 bus->sgentry_align =
3862 sdiodev->settings->bus.sdio.sd_sgentry_align;
3863
3864 /* allocate scatter-gather table. sg support
3865 * will be disabled upon allocation failure.
3866 */
3867 brcmf_sdiod_sgtable_alloc(sdiodev);
3868
3869 #ifdef CONFIG_PM_SLEEP
3870 /* wowl can be supported when KEEP_POWER is true and (WAKE_SDIO_IRQ
3871 * is true or when platform data OOB irq is true).
3872 */
3873 if ((sdio_get_host_pm_caps(sdiodev->func[1]) & MMC_PM_KEEP_POWER) &&
3874 ((sdio_get_host_pm_caps(sdiodev->func[1]) & MMC_PM_WAKE_SDIO_IRQ) ||
3875 (sdiodev->settings->bus.sdio.oob_irq_supported)))
3876 sdiodev->bus_if->wowl_supported = true;
3877 #endif
3878
3879 if (brcmf_sdio_kso_init(bus)) {
3880 brcmf_err("error enabling KSO\n");
3881 goto fail;
3882 }
3883
3884 if (sdiodev->settings->bus.sdio.drive_strength)
3885 drivestrength = sdiodev->settings->bus.sdio.drive_strength;
3886 else
3887 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH;
3888 brcmf_sdio_drivestrengthinit(sdiodev, bus->ci, drivestrength);
3889
3890 /* Set card control so an SDIO card reset does a WLAN backplane reset */
3891 reg_val = brcmf_sdiod_regrb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err);
3892 if (err)
3893 goto fail;
3894
3895 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
3896
3897 brcmf_sdiod_regwb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
3898 if (err)
3899 goto fail;
3900
3901 /* set PMUControl so a backplane reset does PMU state reload */
3902 reg_addr = CORE_CC_REG(brcmf_chip_get_pmu(bus->ci)->base, pmucontrol);
3903 reg_val = brcmf_sdiod_regrl(sdiodev, reg_addr, &err);
3904 if (err)
3905 goto fail;
3906
3907 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
3908
3909 brcmf_sdiod_regwl(sdiodev, reg_addr, reg_val, &err);
3910 if (err)
3911 goto fail;
3912
3913 sdio_release_host(sdiodev->func[1]);
3914
3915 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
3916
3917 /* allocate header buffer */
3918 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL);
3919 if (!bus->hdrbuf)
3920 return false;
3921 /* Locate an appropriately-aligned portion of hdrbuf */
3922 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
3923 bus->head_align);
3924
3925 /* Set the poll and/or interrupt flags */
3926 bus->intr = true;
3927 bus->poll = false;
3928 if (bus->poll)
3929 bus->pollrate = 1;
3930
3931 return true;
3932
3933 fail:
3934 sdio_release_host(sdiodev->func[1]);
3935 return false;
3936 }
3937
3938 static int
3939 brcmf_sdio_watchdog_thread(void *data)
3940 {
3941 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3942 int wait;
3943
3944 allow_signal(SIGTERM);
3945 /* Run until signal received */
3946 brcmf_sdiod_freezer_count(bus->sdiodev);
3947 while (1) {
3948 if (kthread_should_stop())
3949 break;
3950 brcmf_sdiod_freezer_uncount(bus->sdiodev);
3951 wait = wait_for_completion_interruptible(&bus->watchdog_wait);
3952 brcmf_sdiod_freezer_count(bus->sdiodev);
3953 brcmf_sdiod_try_freeze(bus->sdiodev);
3954 if (!wait) {
3955 brcmf_sdio_bus_watchdog(bus);
3956 /* Count the tick for reference */
3957 bus->sdcnt.tickcnt++;
3958 reinit_completion(&bus->watchdog_wait);
3959 } else
3960 break;
3961 }
3962 return 0;
3963 }
3964
3965 static void
3966 brcmf_sdio_watchdog(unsigned long data)
3967 {
3968 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3969
3970 if (bus->watchdog_tsk) {
3971 complete(&bus->watchdog_wait);
3972 /* Reschedule the watchdog */
3973 if (bus->wd_active)
3974 mod_timer(&bus->timer,
3975 jiffies + BRCMF_WD_POLL);
3976 }
3977 }
3978
3979 static const struct brcmf_bus_ops brcmf_sdio_bus_ops = {
3980 .stop = brcmf_sdio_bus_stop,
3981 .preinit = brcmf_sdio_bus_preinit,
3982 .txdata = brcmf_sdio_bus_txdata,
3983 .txctl = brcmf_sdio_bus_txctl,
3984 .rxctl = brcmf_sdio_bus_rxctl,
3985 .gettxq = brcmf_sdio_bus_gettxq,
3986 .wowl_config = brcmf_sdio_wowl_config,
3987 .get_ramsize = brcmf_sdio_bus_get_ramsize,
3988 .get_memdump = brcmf_sdio_bus_get_memdump,
3989 };
3990
3991 static void brcmf_sdio_firmware_callback(struct device *dev, int err,
3992 const struct firmware *code,
3993 void *nvram, u32 nvram_len)
3994 {
3995 struct brcmf_bus *bus_if;
3996 struct brcmf_sdio_dev *sdiodev;
3997 struct brcmf_sdio *bus;
3998 u8 saveclk;
3999
4000 brcmf_dbg(TRACE, "Enter: dev=%s, err=%d\n", dev_name(dev), err);
4001 bus_if = dev_get_drvdata(dev);
4002 sdiodev = bus_if->bus_priv.sdio;
4003 if (err)
4004 goto fail;
4005
4006 if (!bus_if->drvr)
4007 return;
4008
4009 bus = sdiodev->bus;
4010
4011 /* try to download image and nvram to the dongle */
4012 bus->alp_only = true;
4013 err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len);
4014 if (err)
4015 goto fail;
4016 bus->alp_only = false;
4017
4018 /* Start the watchdog timer */
4019 bus->sdcnt.tickcnt = 0;
4020 brcmf_sdio_wd_timer(bus, true);
4021
4022 sdio_claim_host(sdiodev->func[1]);
4023
4024 /* Make sure backplane clock is on, needed to generate F2 interrupt */
4025 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4026 if (bus->clkstate != CLK_AVAIL)
4027 goto release;
4028
4029 /* Force clocks on backplane to be sure F2 interrupt propagates */
4030 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, &err);
4031 if (!err) {
4032 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
4033 (saveclk | SBSDIO_FORCE_HT), &err);
4034 }
4035 if (err) {
4036 brcmf_err("Failed to force clock for F2: err %d\n", err);
4037 goto release;
4038 }
4039
4040 /* Enable function 2 (frame transfers) */
4041 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
4042 offsetof(struct sdpcmd_regs, tosbmailboxdata));
4043 err = sdio_enable_func(sdiodev->func[SDIO_FUNC_2]);
4044
4045
4046 brcmf_dbg(INFO, "enable F2: err=%d\n", err);
4047
4048 /* If F2 successfully enabled, set core and enable interrupts */
4049 if (!err) {
4050 /* Set up the interrupt mask and enable interrupts */
4051 bus->hostintmask = HOSTINTMASK;
4052 w_sdreg32(bus, bus->hostintmask,
4053 offsetof(struct sdpcmd_regs, hostintmask));
4054
4055 brcmf_sdiod_regwb(sdiodev, SBSDIO_WATERMARK, 8, &err);
4056 } else {
4057 /* Disable F2 again */
4058 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
4059 goto release;
4060 }
4061
4062 if (brcmf_chip_sr_capable(bus->ci)) {
4063 brcmf_sdio_sr_init(bus);
4064 } else {
4065 /* Restore previous clock setting */
4066 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
4067 saveclk, &err);
4068 }
4069
4070 if (err == 0) {
4071 /* Allow full data communication using DPC from now on. */
4072 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
4073
4074 err = brcmf_sdiod_intr_register(sdiodev);
4075 if (err != 0)
4076 brcmf_err("intr register failed:%d\n", err);
4077 }
4078
4079 /* If we didn't come up, turn off backplane clock */
4080 if (err != 0)
4081 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4082
4083 sdio_release_host(sdiodev->func[1]);
4084
4085 err = brcmf_bus_started(dev);
4086 if (err != 0) {
4087 brcmf_err("dongle is not responding\n");
4088 goto fail;
4089 }
4090 return;
4091
4092 release:
4093 sdio_release_host(sdiodev->func[1]);
4094 fail:
4095 brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err);
4096 device_release_driver(dev);
4097 device_release_driver(&sdiodev->func[2]->dev);
4098 }
4099
4100 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
4101 {
4102 int ret;
4103 struct brcmf_sdio *bus;
4104 struct workqueue_struct *wq;
4105
4106 brcmf_dbg(TRACE, "Enter\n");
4107
4108 /* Allocate private bus interface state */
4109 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
4110 if (!bus)
4111 goto fail;
4112
4113 bus->sdiodev = sdiodev;
4114 sdiodev->bus = bus;
4115 skb_queue_head_init(&bus->glom);
4116 bus->txbound = BRCMF_TXBOUND;
4117 bus->rxbound = BRCMF_RXBOUND;
4118 bus->txminmax = BRCMF_TXMINMAX;
4119 bus->tx_seq = SDPCM_SEQ_WRAP - 1;
4120
4121 /* single-threaded workqueue */
4122 wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM,
4123 dev_name(&sdiodev->func[1]->dev));
4124 if (!wq) {
4125 brcmf_err("insufficient memory to create txworkqueue\n");
4126 goto fail;
4127 }
4128 brcmf_sdiod_freezer_count(sdiodev);
4129 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
4130 bus->brcmf_wq = wq;
4131
4132 /* attempt to attach to the dongle */
4133 if (!(brcmf_sdio_probe_attach(bus))) {
4134 brcmf_err("brcmf_sdio_probe_attach failed\n");
4135 goto fail;
4136 }
4137
4138 spin_lock_init(&bus->rxctl_lock);
4139 spin_lock_init(&bus->txq_lock);
4140 init_waitqueue_head(&bus->ctrl_wait);
4141 init_waitqueue_head(&bus->dcmd_resp_wait);
4142
4143 /* Set up the watchdog timer */
4144 init_timer(&bus->timer);
4145 bus->timer.data = (unsigned long)bus;
4146 bus->timer.function = brcmf_sdio_watchdog;
4147
4148 /* Initialize watchdog thread */
4149 init_completion(&bus->watchdog_wait);
4150 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread,
4151 bus, "brcmf_wdog/%s",
4152 dev_name(&sdiodev->func[1]->dev));
4153 if (IS_ERR(bus->watchdog_tsk)) {
4154 pr_warn("brcmf_watchdog thread failed to start\n");
4155 bus->watchdog_tsk = NULL;
4156 }
4157 /* Initialize DPC thread */
4158 bus->dpc_triggered = false;
4159 bus->dpc_running = false;
4160
4161 /* Assign bus interface call back */
4162 bus->sdiodev->bus_if->dev = bus->sdiodev->dev;
4163 bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops;
4164 bus->sdiodev->bus_if->chip = bus->ci->chip;
4165 bus->sdiodev->bus_if->chiprev = bus->ci->chiprev;
4166
4167 /* default sdio bus header length for tx packet */
4168 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
4169
4170 /* Attach to the common layer, reserve hdr space */
4171 ret = brcmf_attach(bus->sdiodev->dev, bus->sdiodev->settings);
4172 if (ret != 0) {
4173 brcmf_err("brcmf_attach failed\n");
4174 goto fail;
4175 }
4176
4177 /* allocate scatter-gather table. sg support
4178 * will be disabled upon allocation failure.
4179 */
4180 brcmf_sdiod_sgtable_alloc(bus->sdiodev);
4181
4182 /* Query the F2 block size, set roundup accordingly */
4183 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
4184 bus->roundup = min(max_roundup, bus->blocksize);
4185
4186 /* Allocate buffers */
4187 if (bus->sdiodev->bus_if->maxctl) {
4188 bus->sdiodev->bus_if->maxctl += bus->roundup;
4189 bus->rxblen =
4190 roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
4191 ALIGNMENT) + bus->head_align;
4192 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
4193 if (!(bus->rxbuf)) {
4194 brcmf_err("rxbuf allocation failed\n");
4195 goto fail;
4196 }
4197 }
4198
4199 sdio_claim_host(bus->sdiodev->func[1]);
4200
4201 /* Disable F2 to clear any intermediate frame state on the dongle */
4202 sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]);
4203
4204 bus->rxflow = false;
4205
4206 /* Done with backplane-dependent accesses, can drop clock... */
4207 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4208
4209 sdio_release_host(bus->sdiodev->func[1]);
4210
4211 /* ...and initialize clock/power states */
4212 bus->clkstate = CLK_SDONLY;
4213 bus->idletime = BRCMF_IDLE_INTERVAL;
4214 bus->idleclock = BRCMF_IDLE_ACTIVE;
4215
4216 /* SR state */
4217 bus->sr_enabled = false;
4218
4219 brcmf_sdio_debugfs_create(bus);
4220 brcmf_dbg(INFO, "completed!!\n");
4221
4222 ret = brcmf_fw_map_chip_to_name(bus->ci->chip, bus->ci->chiprev,
4223 brcmf_sdio_fwnames,
4224 ARRAY_SIZE(brcmf_sdio_fwnames),
4225 sdiodev->fw_name, sdiodev->nvram_name);
4226 if (ret)
4227 goto fail;
4228
4229 ret = brcmf_fw_get_firmwares(sdiodev->dev, BRCMF_FW_REQUEST_NVRAM,
4230 sdiodev->fw_name, sdiodev->nvram_name,
4231 brcmf_sdio_firmware_callback);
4232 if (ret != 0) {
4233 brcmf_err("async firmware request failed: %d\n", ret);
4234 goto fail;
4235 }
4236
4237 return bus;
4238
4239 fail:
4240 brcmf_sdio_remove(bus);
4241 return NULL;
4242 }
4243
4244 /* Detach and free everything */
4245 void brcmf_sdio_remove(struct brcmf_sdio *bus)
4246 {
4247 brcmf_dbg(TRACE, "Enter\n");
4248
4249 if (bus) {
4250 /* De-register interrupt handler */
4251 brcmf_sdiod_intr_unregister(bus->sdiodev);
4252
4253 brcmf_detach(bus->sdiodev->dev);
4254
4255 cancel_work_sync(&bus->datawork);
4256 if (bus->brcmf_wq)
4257 destroy_workqueue(bus->brcmf_wq);
4258
4259 if (bus->ci) {
4260 if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
4261 sdio_claim_host(bus->sdiodev->func[1]);
4262 brcmf_sdio_wd_timer(bus, false);
4263 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4264 /* Leave the device in state where it is
4265 * 'passive'. This is done by resetting all
4266 * necessary cores.
4267 */
4268 msleep(20);
4269 brcmf_chip_set_passive(bus->ci);
4270 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4271 sdio_release_host(bus->sdiodev->func[1]);
4272 }
4273 brcmf_chip_detach(bus->ci);
4274 }
4275 if (bus->sdiodev->settings)
4276 brcmf_release_module_param(bus->sdiodev->settings);
4277
4278 kfree(bus->rxbuf);
4279 kfree(bus->hdrbuf);
4280 kfree(bus);
4281 }
4282
4283 brcmf_dbg(TRACE, "Disconnected\n");
4284 }
4285
4286 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active)
4287 {
4288 /* Totally stop the timer */
4289 if (!active && bus->wd_active) {
4290 del_timer_sync(&bus->timer);
4291 bus->wd_active = false;
4292 return;
4293 }
4294
4295 /* don't start the wd until fw is loaded */
4296 if (bus->sdiodev->state != BRCMF_SDIOD_DATA)
4297 return;
4298
4299 if (active) {
4300 if (!bus->wd_active) {
4301 /* Create timer again when watchdog period is
4302 dynamically changed or in the first instance
4303 */
4304 bus->timer.expires = jiffies + BRCMF_WD_POLL;
4305 add_timer(&bus->timer);
4306 bus->wd_active = true;
4307 } else {
4308 /* Re arm the timer, at last watchdog period */
4309 mod_timer(&bus->timer, jiffies + BRCMF_WD_POLL);
4310 }
4311 }
4312 }
4313
4314 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep)
4315 {
4316 int ret;
4317
4318 sdio_claim_host(bus->sdiodev->func[1]);
4319 ret = brcmf_sdio_bus_sleep(bus, sleep, false);
4320 sdio_release_host(bus->sdiodev->func[1]);
4321
4322 return ret;
4323 }
4324
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