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Merge tag 'omap-for-v4.6/dt-ti81xx-signed' of git://git.kernel.org/pub/scm/linux...
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / broadcom / brcm80211 / brcmfmac / sdio.c
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/types.h>
18 #include <linux/atomic.h>
19 #include <linux/kernel.h>
20 #include <linux/kthread.h>
21 #include <linux/printk.h>
22 #include <linux/pci_ids.h>
23 #include <linux/netdevice.h>
24 #include <linux/interrupt.h>
25 #include <linux/sched.h>
26 #include <linux/mmc/sdio.h>
27 #include <linux/mmc/sdio_ids.h>
28 #include <linux/mmc/sdio_func.h>
29 #include <linux/mmc/card.h>
30 #include <linux/semaphore.h>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
33 #include <linux/bcma/bcma.h>
34 #include <linux/debugfs.h>
35 #include <linux/vmalloc.h>
36 #include <asm/unaligned.h>
37 #include <defs.h>
38 #include <brcmu_wifi.h>
39 #include <brcmu_utils.h>
40 #include <brcm_hw_ids.h>
41 #include <soc.h>
42 #include "sdio.h"
43 #include "chip.h"
44 #include "firmware.h"
45 #include "core.h"
46 #include "common.h"
47
48 #define DCMD_RESP_TIMEOUT msecs_to_jiffies(2500)
49 #define CTL_DONE_TIMEOUT msecs_to_jiffies(2500)
50
51 #ifdef DEBUG
52
53 #define BRCMF_TRAP_INFO_SIZE 80
54
55 #define CBUF_LEN (128)
56
57 /* Device console log buffer state */
58 #define CONSOLE_BUFFER_MAX 2024
59
60 struct rte_log_le {
61 __le32 buf; /* Can't be pointer on (64-bit) hosts */
62 __le32 buf_size;
63 __le32 idx;
64 char *_buf_compat; /* Redundant pointer for backward compat. */
65 };
66
67 struct rte_console {
68 /* Virtual UART
69 * When there is no UART (e.g. Quickturn),
70 * the host should write a complete
71 * input line directly into cbuf and then write
72 * the length into vcons_in.
73 * This may also be used when there is a real UART
74 * (at risk of conflicting with
75 * the real UART). vcons_out is currently unused.
76 */
77 uint vcons_in;
78 uint vcons_out;
79
80 /* Output (logging) buffer
81 * Console output is written to a ring buffer log_buf at index log_idx.
82 * The host may read the output when it sees log_idx advance.
83 * Output will be lost if the output wraps around faster than the host
84 * polls.
85 */
86 struct rte_log_le log_le;
87
88 /* Console input line buffer
89 * Characters are read one at a time into cbuf
90 * until <CR> is received, then
91 * the buffer is processed as a command line.
92 * Also used for virtual UART.
93 */
94 uint cbuf_idx;
95 char cbuf[CBUF_LEN];
96 };
97
98 #endif /* DEBUG */
99 #include <chipcommon.h>
100
101 #include "bus.h"
102 #include "debug.h"
103 #include "tracepoint.h"
104
105 #define TXQLEN 2048 /* bulk tx queue length */
106 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
107 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
108 #define PRIOMASK 7
109
110 #define TXRETRIES 2 /* # of retries for tx frames */
111
112 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
113 one scheduling */
114
115 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
116 one scheduling */
117
118 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
119
120 #define MEMBLOCK 2048 /* Block size used for downloading
121 of dongle image */
122 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
123 biggest possible glom */
124
125 #define BRCMF_FIRSTREAD (1 << 6)
126
127 #define BRCMF_CONSOLE 10 /* watchdog interval to poll console */
128
129 /* SBSDIO_DEVICE_CTL */
130
131 /* 1: device will assert busy signal when receiving CMD53 */
132 #define SBSDIO_DEVCTL_SETBUSY 0x01
133 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
134 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
135 /* 1: mask all interrupts to host except the chipActive (rev 8) */
136 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
137 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
138 * sdio bus power cycle to clear (rev 9) */
139 #define SBSDIO_DEVCTL_PADS_ISO 0x08
140 /* Force SD->SB reset mapping (rev 11) */
141 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
142 /* Determined by CoreControl bit */
143 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
144 /* Force backplane reset */
145 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
146 /* Force no backplane reset */
147 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
148
149 /* direct(mapped) cis space */
150
151 /* MAPPED common CIS address */
152 #define SBSDIO_CIS_BASE_COMMON 0x1000
153 /* maximum bytes in one CIS */
154 #define SBSDIO_CIS_SIZE_LIMIT 0x200
155 /* cis offset addr is < 17 bits */
156 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
157
158 /* manfid tuple length, include tuple, link bytes */
159 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
160
161 #define CORE_BUS_REG(base, field) \
162 (base + offsetof(struct sdpcmd_regs, field))
163
164 /* SDIO function 1 register CHIPCLKCSR */
165 /* Force ALP request to backplane */
166 #define SBSDIO_FORCE_ALP 0x01
167 /* Force HT request to backplane */
168 #define SBSDIO_FORCE_HT 0x02
169 /* Force ILP request to backplane */
170 #define SBSDIO_FORCE_ILP 0x04
171 /* Make ALP ready (power up xtal) */
172 #define SBSDIO_ALP_AVAIL_REQ 0x08
173 /* Make HT ready (power up PLL) */
174 #define SBSDIO_HT_AVAIL_REQ 0x10
175 /* Squelch clock requests from HW */
176 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
177 /* Status: ALP is ready */
178 #define SBSDIO_ALP_AVAIL 0x40
179 /* Status: HT is ready */
180 #define SBSDIO_HT_AVAIL 0x80
181 #define SBSDIO_CSR_MASK 0x1F
182 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
183 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
184 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
185 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
186 #define SBSDIO_CLKAV(regval, alponly) \
187 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
188
189 /* intstatus */
190 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
191 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
192 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
193 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
194 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
195 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
196 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
197 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
198 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
199 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
200 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
201 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
202 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
203 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
204 #define I_PC (1 << 10) /* descriptor error */
205 #define I_PD (1 << 11) /* data error */
206 #define I_DE (1 << 12) /* Descriptor protocol Error */
207 #define I_RU (1 << 13) /* Receive descriptor Underflow */
208 #define I_RO (1 << 14) /* Receive fifo Overflow */
209 #define I_XU (1 << 15) /* Transmit fifo Underflow */
210 #define I_RI (1 << 16) /* Receive Interrupt */
211 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
212 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
213 #define I_XI (1 << 24) /* Transmit Interrupt */
214 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
215 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
216 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
217 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
218 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
219 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
220 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
221 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
222 #define I_DMA (I_RI | I_XI | I_ERRORS)
223
224 /* corecontrol */
225 #define CC_CISRDY (1 << 0) /* CIS Ready */
226 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
227 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
228 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
229 #define CC_XMTDATAAVAIL_MODE (1 << 4)
230 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
231
232 /* SDA_FRAMECTRL */
233 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
234 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
235 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
236 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
237
238 /*
239 * Software allocation of To SB Mailbox resources
240 */
241
242 /* tosbmailbox bits corresponding to intstatus bits */
243 #define SMB_NAK (1 << 0) /* Frame NAK */
244 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
245 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
246 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
247
248 /* tosbmailboxdata */
249 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
250
251 /*
252 * Software allocation of To Host Mailbox resources
253 */
254
255 /* intstatus bits */
256 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
257 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
258 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
259 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
260
261 /* tohostmailboxdata */
262 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
263 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
264 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
265 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
266
267 #define HMB_DATA_FCDATA_MASK 0xff000000
268 #define HMB_DATA_FCDATA_SHIFT 24
269
270 #define HMB_DATA_VERSION_MASK 0x00ff0000
271 #define HMB_DATA_VERSION_SHIFT 16
272
273 /*
274 * Software-defined protocol header
275 */
276
277 /* Current protocol version */
278 #define SDPCM_PROT_VERSION 4
279
280 /*
281 * Shared structure between dongle and the host.
282 * The structure contains pointers to trap or assert information.
283 */
284 #define SDPCM_SHARED_VERSION 0x0003
285 #define SDPCM_SHARED_VERSION_MASK 0x00FF
286 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
287 #define SDPCM_SHARED_ASSERT 0x0200
288 #define SDPCM_SHARED_TRAP 0x0400
289
290 /* Space for header read, limit for data packets */
291 #define MAX_HDR_READ (1 << 6)
292 #define MAX_RX_DATASZ 2048
293
294 /* Bump up limit on waiting for HT to account for first startup;
295 * if the image is doing a CRC calculation before programming the PMU
296 * for HT availability, it could take a couple hundred ms more, so
297 * max out at a 1 second (1000000us).
298 */
299 #undef PMU_MAX_TRANSITION_DLY
300 #define PMU_MAX_TRANSITION_DLY 1000000
301
302 /* Value for ChipClockCSR during initial setup */
303 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
304 SBSDIO_ALP_AVAIL_REQ)
305
306 /* Flags for SDH calls */
307 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
308
309 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
310 * when idle
311 */
312 #define BRCMF_IDLE_INTERVAL 1
313
314 #define KSO_WAIT_US 50
315 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
316
317 /*
318 * Conversion of 802.1D priority to precedence level
319 */
320 static uint prio2prec(u32 prio)
321 {
322 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
323 (prio^2) : prio;
324 }
325
326 #ifdef DEBUG
327 /* Device console log buffer state */
328 struct brcmf_console {
329 uint count; /* Poll interval msec counter */
330 uint log_addr; /* Log struct address (fixed) */
331 struct rte_log_le log_le; /* Log struct (host copy) */
332 uint bufsize; /* Size of log buffer */
333 u8 *buf; /* Log buffer (host copy) */
334 uint last; /* Last buffer read index */
335 };
336
337 struct brcmf_trap_info {
338 __le32 type;
339 __le32 epc;
340 __le32 cpsr;
341 __le32 spsr;
342 __le32 r0; /* a1 */
343 __le32 r1; /* a2 */
344 __le32 r2; /* a3 */
345 __le32 r3; /* a4 */
346 __le32 r4; /* v1 */
347 __le32 r5; /* v2 */
348 __le32 r6; /* v3 */
349 __le32 r7; /* v4 */
350 __le32 r8; /* v5 */
351 __le32 r9; /* sb/v6 */
352 __le32 r10; /* sl/v7 */
353 __le32 r11; /* fp/v8 */
354 __le32 r12; /* ip */
355 __le32 r13; /* sp */
356 __le32 r14; /* lr */
357 __le32 pc; /* r15 */
358 };
359 #endif /* DEBUG */
360
361 struct sdpcm_shared {
362 u32 flags;
363 u32 trap_addr;
364 u32 assert_exp_addr;
365 u32 assert_file_addr;
366 u32 assert_line;
367 u32 console_addr; /* Address of struct rte_console */
368 u32 msgtrace_addr;
369 u8 tag[32];
370 u32 brpt_addr;
371 };
372
373 struct sdpcm_shared_le {
374 __le32 flags;
375 __le32 trap_addr;
376 __le32 assert_exp_addr;
377 __le32 assert_file_addr;
378 __le32 assert_line;
379 __le32 console_addr; /* Address of struct rte_console */
380 __le32 msgtrace_addr;
381 u8 tag[32];
382 __le32 brpt_addr;
383 };
384
385 /* dongle SDIO bus specific header info */
386 struct brcmf_sdio_hdrinfo {
387 u8 seq_num;
388 u8 channel;
389 u16 len;
390 u16 len_left;
391 u16 len_nxtfrm;
392 u8 dat_offset;
393 bool lastfrm;
394 u16 tail_pad;
395 };
396
397 /*
398 * hold counter variables
399 */
400 struct brcmf_sdio_count {
401 uint intrcount; /* Count of device interrupt callbacks */
402 uint lastintrs; /* Count as of last watchdog timer */
403 uint pollcnt; /* Count of active polls */
404 uint regfails; /* Count of R_REG failures */
405 uint tx_sderrs; /* Count of tx attempts with sd errors */
406 uint fcqueued; /* Tx packets that got queued */
407 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
408 uint rx_toolong; /* Receive frames too long to receive */
409 uint rxc_errors; /* SDIO errors when reading control frames */
410 uint rx_hdrfail; /* SDIO errors on header reads */
411 uint rx_badhdr; /* Bad received headers (roosync?) */
412 uint rx_badseq; /* Mismatched rx sequence number */
413 uint fc_rcvd; /* Number of flow-control events received */
414 uint fc_xoff; /* Number which turned on flow-control */
415 uint fc_xon; /* Number which turned off flow-control */
416 uint rxglomfail; /* Failed deglom attempts */
417 uint rxglomframes; /* Number of glom frames (superframes) */
418 uint rxglompkts; /* Number of packets from glom frames */
419 uint f2rxhdrs; /* Number of header reads */
420 uint f2rxdata; /* Number of frame data reads */
421 uint f2txdata; /* Number of f2 frame writes */
422 uint f1regdata; /* Number of f1 register accesses */
423 uint tickcnt; /* Number of watchdog been schedule */
424 ulong tx_ctlerrs; /* Err of sending ctrl frames */
425 ulong tx_ctlpkts; /* Ctrl frames sent to dongle */
426 ulong rx_ctlerrs; /* Err of processing rx ctrl frames */
427 ulong rx_ctlpkts; /* Ctrl frames processed from dongle */
428 ulong rx_readahead_cnt; /* packets where header read-ahead was used */
429 };
430
431 /* misc chip info needed by some of the routines */
432 /* Private data for SDIO bus interaction */
433 struct brcmf_sdio {
434 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
435 struct brcmf_chip *ci; /* Chip info struct */
436
437 u32 hostintmask; /* Copy of Host Interrupt Mask */
438 atomic_t intstatus; /* Intstatus bits (events) pending */
439 atomic_t fcstate; /* State of dongle flow-control */
440
441 uint blocksize; /* Block size of SDIO transfers */
442 uint roundup; /* Max roundup limit */
443
444 struct pktq txq; /* Queue length used for flow-control */
445 u8 flowcontrol; /* per prio flow control bitmask */
446 u8 tx_seq; /* Transmit sequence number (next) */
447 u8 tx_max; /* Maximum transmit sequence allowed */
448
449 u8 *hdrbuf; /* buffer for handling rx frame */
450 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
451 u8 rx_seq; /* Receive sequence number (expected) */
452 struct brcmf_sdio_hdrinfo cur_read;
453 /* info of current read frame */
454 bool rxskip; /* Skip receive (awaiting NAK ACK) */
455 bool rxpending; /* Data frame pending in dongle */
456
457 uint rxbound; /* Rx frames to read before resched */
458 uint txbound; /* Tx frames to send before resched */
459 uint txminmax;
460
461 struct sk_buff *glomd; /* Packet containing glomming descriptor */
462 struct sk_buff_head glom; /* Packet list for glommed superframe */
463
464 u8 *rxbuf; /* Buffer for receiving control packets */
465 uint rxblen; /* Allocated length of rxbuf */
466 u8 *rxctl; /* Aligned pointer into rxbuf */
467 u8 *rxctl_orig; /* pointer for freeing rxctl */
468 uint rxlen; /* Length of valid data in buffer */
469 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */
470
471 u8 sdpcm_ver; /* Bus protocol reported by dongle */
472
473 bool intr; /* Use interrupts */
474 bool poll; /* Use polling */
475 atomic_t ipend; /* Device interrupt is pending */
476 uint spurious; /* Count of spurious interrupts */
477 uint pollrate; /* Ticks between device polls */
478 uint polltick; /* Tick counter */
479
480 #ifdef DEBUG
481 uint console_interval;
482 struct brcmf_console console; /* Console output polling support */
483 uint console_addr; /* Console address from shared struct */
484 #endif /* DEBUG */
485
486 uint clkstate; /* State of sd and backplane clock(s) */
487 s32 idletime; /* Control for activity timeout */
488 s32 idlecount; /* Activity timeout counter */
489 s32 idleclock; /* How to set bus driver when idle */
490 bool rxflow_mode; /* Rx flow control mode */
491 bool rxflow; /* Is rx flow control on */
492 bool alp_only; /* Don't use HT clock (ALP only) */
493
494 u8 *ctrl_frame_buf;
495 u16 ctrl_frame_len;
496 bool ctrl_frame_stat;
497 int ctrl_frame_err;
498
499 spinlock_t txq_lock; /* protect bus->txq */
500 wait_queue_head_t ctrl_wait;
501 wait_queue_head_t dcmd_resp_wait;
502
503 struct timer_list timer;
504 struct completion watchdog_wait;
505 struct task_struct *watchdog_tsk;
506 bool wd_active;
507
508 struct workqueue_struct *brcmf_wq;
509 struct work_struct datawork;
510 bool dpc_triggered;
511 bool dpc_running;
512
513 bool txoff; /* Transmit flow-controlled */
514 struct brcmf_sdio_count sdcnt;
515 bool sr_enabled; /* SaveRestore enabled */
516 bool sleeping;
517
518 u8 tx_hdrlen; /* sdio bus header length for tx packet */
519 bool txglom; /* host tx glomming enable flag */
520 u16 head_align; /* buffer pointer alignment */
521 u16 sgentry_align; /* scatter-gather buffer alignment */
522 };
523
524 /* clkstate */
525 #define CLK_NONE 0
526 #define CLK_SDONLY 1
527 #define CLK_PENDING 2
528 #define CLK_AVAIL 3
529
530 #ifdef DEBUG
531 static int qcount[NUMPRIO];
532 #endif /* DEBUG */
533
534 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
535
536 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
537
538 /* Retry count for register access failures */
539 static const uint retry_limit = 2;
540
541 /* Limit on rounding up frames */
542 static const uint max_roundup = 512;
543
544 #define ALIGNMENT 4
545
546 enum brcmf_sdio_frmtype {
547 BRCMF_SDIO_FT_NORMAL,
548 BRCMF_SDIO_FT_SUPER,
549 BRCMF_SDIO_FT_SUB,
550 };
551
552 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
553
554 /* SDIO Pad drive strength to select value mappings */
555 struct sdiod_drive_str {
556 u8 strength; /* Pad Drive Strength in mA */
557 u8 sel; /* Chip-specific select value */
558 };
559
560 /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */
561 static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
562 {32, 0x6},
563 {26, 0x7},
564 {22, 0x4},
565 {16, 0x5},
566 {12, 0x2},
567 {8, 0x3},
568 {4, 0x0},
569 {0, 0x1}
570 };
571
572 /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
573 static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
574 {6, 0x7},
575 {5, 0x6},
576 {4, 0x5},
577 {3, 0x4},
578 {2, 0x2},
579 {1, 0x1},
580 {0, 0x0}
581 };
582
583 /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
584 static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
585 {3, 0x3},
586 {2, 0x2},
587 {1, 0x1},
588 {0, 0x0} };
589
590 /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
591 static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
592 {16, 0x7},
593 {12, 0x5},
594 {8, 0x3},
595 {4, 0x1}
596 };
597
598 BRCMF_FW_NVRAM_DEF(43143, "brcmfmac43143-sdio.bin", "brcmfmac43143-sdio.txt");
599 BRCMF_FW_NVRAM_DEF(43241B0, "brcmfmac43241b0-sdio.bin",
600 "brcmfmac43241b0-sdio.txt");
601 BRCMF_FW_NVRAM_DEF(43241B4, "brcmfmac43241b4-sdio.bin",
602 "brcmfmac43241b4-sdio.txt");
603 BRCMF_FW_NVRAM_DEF(43241B5, "brcmfmac43241b5-sdio.bin",
604 "brcmfmac43241b5-sdio.txt");
605 BRCMF_FW_NVRAM_DEF(4329, "brcmfmac4329-sdio.bin", "brcmfmac4329-sdio.txt");
606 BRCMF_FW_NVRAM_DEF(4330, "brcmfmac4330-sdio.bin", "brcmfmac4330-sdio.txt");
607 BRCMF_FW_NVRAM_DEF(4334, "brcmfmac4334-sdio.bin", "brcmfmac4334-sdio.txt");
608 BRCMF_FW_NVRAM_DEF(43340, "brcmfmac43340-sdio.bin", "brcmfmac43340-sdio.txt");
609 BRCMF_FW_NVRAM_DEF(4335, "brcmfmac4335-sdio.bin", "brcmfmac4335-sdio.txt");
610 BRCMF_FW_NVRAM_DEF(43362, "brcmfmac43362-sdio.bin", "brcmfmac43362-sdio.txt");
611 BRCMF_FW_NVRAM_DEF(4339, "brcmfmac4339-sdio.bin", "brcmfmac4339-sdio.txt");
612 BRCMF_FW_NVRAM_DEF(43430, "brcmfmac43430-sdio.bin", "brcmfmac43430-sdio.txt");
613 BRCMF_FW_NVRAM_DEF(43455, "brcmfmac43455-sdio.bin", "brcmfmac43455-sdio.txt");
614 BRCMF_FW_NVRAM_DEF(4354, "brcmfmac4354-sdio.bin", "brcmfmac4354-sdio.txt");
615
616 static struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
617 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143),
618 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0),
619 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4),
620 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, 43241B5),
621 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, 4329),
622 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, 4330),
623 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334),
624 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340),
625 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335),
626 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362),
627 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339),
628 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFF, 43430),
629 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFFC0, 43455),
630 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354)
631 };
632
633 static void pkt_align(struct sk_buff *p, int len, int align)
634 {
635 uint datalign;
636 datalign = (unsigned long)(p->data);
637 datalign = roundup(datalign, (align)) - datalign;
638 if (datalign)
639 skb_pull(p, datalign);
640 __skb_trim(p, len);
641 }
642
643 /* To check if there's window offered */
644 static bool data_ok(struct brcmf_sdio *bus)
645 {
646 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
647 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
648 }
649
650 /*
651 * Reads a register in the SDIO hardware block. This block occupies a series of
652 * adresses on the 32 bit backplane bus.
653 */
654 static int r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset)
655 {
656 struct brcmf_core *core;
657 int ret;
658
659 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
660 *regvar = brcmf_sdiod_regrl(bus->sdiodev, core->base + offset, &ret);
661
662 return ret;
663 }
664
665 static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset)
666 {
667 struct brcmf_core *core;
668 int ret;
669
670 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
671 brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret);
672
673 return ret;
674 }
675
676 static int
677 brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
678 {
679 u8 wr_val = 0, rd_val, cmp_val, bmask;
680 int err = 0;
681 int try_cnt = 0;
682
683 brcmf_dbg(TRACE, "Enter: on=%d\n", on);
684
685 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
686 /* 1st KSO write goes to AOS wake up core if device is asleep */
687 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
688 wr_val, &err);
689
690 if (on) {
691 /* device WAKEUP through KSO:
692 * write bit 0 & read back until
693 * both bits 0 (kso bit) & 1 (dev on status) are set
694 */
695 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
696 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
697 bmask = cmp_val;
698 usleep_range(2000, 3000);
699 } else {
700 /* Put device to sleep, turn off KSO */
701 cmp_val = 0;
702 /* only check for bit0, bit1(dev on status) may not
703 * get cleared right away
704 */
705 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
706 }
707
708 do {
709 /* reliable KSO bit set/clr:
710 * the sdiod sleep write access is synced to PMU 32khz clk
711 * just one write attempt may fail,
712 * read it back until it matches written value
713 */
714 rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
715 &err);
716 if (((rd_val & bmask) == cmp_val) && !err)
717 break;
718
719 udelay(KSO_WAIT_US);
720 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
721 wr_val, &err);
722 } while (try_cnt++ < MAX_KSO_ATTEMPTS);
723
724 if (try_cnt > 2)
725 brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt,
726 rd_val, err);
727
728 if (try_cnt > MAX_KSO_ATTEMPTS)
729 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err);
730
731 return err;
732 }
733
734 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
735
736 /* Turn backplane clock on or off */
737 static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
738 {
739 int err;
740 u8 clkctl, clkreq, devctl;
741 unsigned long timeout;
742
743 brcmf_dbg(SDIO, "Enter\n");
744
745 clkctl = 0;
746
747 if (bus->sr_enabled) {
748 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
749 return 0;
750 }
751
752 if (on) {
753 /* Request HT Avail */
754 clkreq =
755 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
756
757 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
758 clkreq, &err);
759 if (err) {
760 brcmf_err("HT Avail request error: %d\n", err);
761 return -EBADE;
762 }
763
764 /* Check current status */
765 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
766 SBSDIO_FUNC1_CHIPCLKCSR, &err);
767 if (err) {
768 brcmf_err("HT Avail read error: %d\n", err);
769 return -EBADE;
770 }
771
772 /* Go to pending and await interrupt if appropriate */
773 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
774 /* Allow only clock-available interrupt */
775 devctl = brcmf_sdiod_regrb(bus->sdiodev,
776 SBSDIO_DEVICE_CTL, &err);
777 if (err) {
778 brcmf_err("Devctl error setting CA: %d\n",
779 err);
780 return -EBADE;
781 }
782
783 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
784 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
785 devctl, &err);
786 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
787 bus->clkstate = CLK_PENDING;
788
789 return 0;
790 } else if (bus->clkstate == CLK_PENDING) {
791 /* Cancel CA-only interrupt filter */
792 devctl = brcmf_sdiod_regrb(bus->sdiodev,
793 SBSDIO_DEVICE_CTL, &err);
794 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
795 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
796 devctl, &err);
797 }
798
799 /* Otherwise, wait here (polling) for HT Avail */
800 timeout = jiffies +
801 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
802 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
803 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
804 SBSDIO_FUNC1_CHIPCLKCSR,
805 &err);
806 if (time_after(jiffies, timeout))
807 break;
808 else
809 usleep_range(5000, 10000);
810 }
811 if (err) {
812 brcmf_err("HT Avail request error: %d\n", err);
813 return -EBADE;
814 }
815 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
816 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
817 PMU_MAX_TRANSITION_DLY, clkctl);
818 return -EBADE;
819 }
820
821 /* Mark clock available */
822 bus->clkstate = CLK_AVAIL;
823 brcmf_dbg(SDIO, "CLKCTL: turned ON\n");
824
825 #if defined(DEBUG)
826 if (!bus->alp_only) {
827 if (SBSDIO_ALPONLY(clkctl))
828 brcmf_err("HT Clock should be on\n");
829 }
830 #endif /* defined (DEBUG) */
831
832 } else {
833 clkreq = 0;
834
835 if (bus->clkstate == CLK_PENDING) {
836 /* Cancel CA-only interrupt filter */
837 devctl = brcmf_sdiod_regrb(bus->sdiodev,
838 SBSDIO_DEVICE_CTL, &err);
839 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
840 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
841 devctl, &err);
842 }
843
844 bus->clkstate = CLK_SDONLY;
845 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
846 clkreq, &err);
847 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
848 if (err) {
849 brcmf_err("Failed access turning clock off: %d\n",
850 err);
851 return -EBADE;
852 }
853 }
854 return 0;
855 }
856
857 /* Change idle/active SD state */
858 static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on)
859 {
860 brcmf_dbg(SDIO, "Enter\n");
861
862 if (on)
863 bus->clkstate = CLK_SDONLY;
864 else
865 bus->clkstate = CLK_NONE;
866
867 return 0;
868 }
869
870 /* Transition SD and backplane clock readiness */
871 static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
872 {
873 #ifdef DEBUG
874 uint oldstate = bus->clkstate;
875 #endif /* DEBUG */
876
877 brcmf_dbg(SDIO, "Enter\n");
878
879 /* Early exit if we're already there */
880 if (bus->clkstate == target)
881 return 0;
882
883 switch (target) {
884 case CLK_AVAIL:
885 /* Make sure SD clock is available */
886 if (bus->clkstate == CLK_NONE)
887 brcmf_sdio_sdclk(bus, true);
888 /* Now request HT Avail on the backplane */
889 brcmf_sdio_htclk(bus, true, pendok);
890 break;
891
892 case CLK_SDONLY:
893 /* Remove HT request, or bring up SD clock */
894 if (bus->clkstate == CLK_NONE)
895 brcmf_sdio_sdclk(bus, true);
896 else if (bus->clkstate == CLK_AVAIL)
897 brcmf_sdio_htclk(bus, false, false);
898 else
899 brcmf_err("request for %d -> %d\n",
900 bus->clkstate, target);
901 break;
902
903 case CLK_NONE:
904 /* Make sure to remove HT request */
905 if (bus->clkstate == CLK_AVAIL)
906 brcmf_sdio_htclk(bus, false, false);
907 /* Now remove the SD clock */
908 brcmf_sdio_sdclk(bus, false);
909 break;
910 }
911 #ifdef DEBUG
912 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate);
913 #endif /* DEBUG */
914
915 return 0;
916 }
917
918 static int
919 brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
920 {
921 int err = 0;
922 u8 clkcsr;
923
924 brcmf_dbg(SDIO, "Enter: request %s currently %s\n",
925 (sleep ? "SLEEP" : "WAKE"),
926 (bus->sleeping ? "SLEEP" : "WAKE"));
927
928 /* If SR is enabled control bus state with KSO */
929 if (bus->sr_enabled) {
930 /* Done if we're already in the requested state */
931 if (sleep == bus->sleeping)
932 goto end;
933
934 /* Going to sleep */
935 if (sleep) {
936 clkcsr = brcmf_sdiod_regrb(bus->sdiodev,
937 SBSDIO_FUNC1_CHIPCLKCSR,
938 &err);
939 if ((clkcsr & SBSDIO_CSR_MASK) == 0) {
940 brcmf_dbg(SDIO, "no clock, set ALP\n");
941 brcmf_sdiod_regwb(bus->sdiodev,
942 SBSDIO_FUNC1_CHIPCLKCSR,
943 SBSDIO_ALP_AVAIL_REQ, &err);
944 }
945 err = brcmf_sdio_kso_control(bus, false);
946 } else {
947 err = brcmf_sdio_kso_control(bus, true);
948 }
949 if (err) {
950 brcmf_err("error while changing bus sleep state %d\n",
951 err);
952 goto done;
953 }
954 }
955
956 end:
957 /* control clocks */
958 if (sleep) {
959 if (!bus->sr_enabled)
960 brcmf_sdio_clkctl(bus, CLK_NONE, pendok);
961 } else {
962 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok);
963 brcmf_sdio_wd_timer(bus, true);
964 }
965 bus->sleeping = sleep;
966 brcmf_dbg(SDIO, "new state %s\n",
967 (sleep ? "SLEEP" : "WAKE"));
968 done:
969 brcmf_dbg(SDIO, "Exit: err=%d\n", err);
970 return err;
971
972 }
973
974 #ifdef DEBUG
975 static inline bool brcmf_sdio_valid_shared_address(u32 addr)
976 {
977 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
978 }
979
980 static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
981 struct sdpcm_shared *sh)
982 {
983 u32 addr = 0;
984 int rv;
985 u32 shaddr = 0;
986 struct sdpcm_shared_le sh_le;
987 __le32 addr_le;
988
989 sdio_claim_host(bus->sdiodev->func[1]);
990 brcmf_sdio_bus_sleep(bus, false, false);
991
992 /*
993 * Read last word in socram to determine
994 * address of sdpcm_shared structure
995 */
996 shaddr = bus->ci->rambase + bus->ci->ramsize - 4;
997 if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci))
998 shaddr -= bus->ci->srsize;
999 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr,
1000 (u8 *)&addr_le, 4);
1001 if (rv < 0)
1002 goto fail;
1003
1004 /*
1005 * Check if addr is valid.
1006 * NVRAM length at the end of memory should have been overwritten.
1007 */
1008 addr = le32_to_cpu(addr_le);
1009 if (!brcmf_sdio_valid_shared_address(addr)) {
1010 brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr);
1011 rv = -EINVAL;
1012 goto fail;
1013 }
1014
1015 brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr);
1016
1017 /* Read hndrte_shared structure */
1018 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
1019 sizeof(struct sdpcm_shared_le));
1020 if (rv < 0)
1021 goto fail;
1022
1023 sdio_release_host(bus->sdiodev->func[1]);
1024
1025 /* Endianness */
1026 sh->flags = le32_to_cpu(sh_le.flags);
1027 sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
1028 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
1029 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
1030 sh->assert_line = le32_to_cpu(sh_le.assert_line);
1031 sh->console_addr = le32_to_cpu(sh_le.console_addr);
1032 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
1033
1034 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) {
1035 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
1036 SDPCM_SHARED_VERSION,
1037 sh->flags & SDPCM_SHARED_VERSION_MASK);
1038 return -EPROTO;
1039 }
1040 return 0;
1041
1042 fail:
1043 brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n",
1044 rv, addr);
1045 sdio_release_host(bus->sdiodev->func[1]);
1046 return rv;
1047 }
1048
1049 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1050 {
1051 struct sdpcm_shared sh;
1052
1053 if (brcmf_sdio_readshared(bus, &sh) == 0)
1054 bus->console_addr = sh.console_addr;
1055 }
1056 #else
1057 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1058 {
1059 }
1060 #endif /* DEBUG */
1061
1062 static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus)
1063 {
1064 u32 intstatus = 0;
1065 u32 hmb_data;
1066 u8 fcbits;
1067 int ret;
1068
1069 brcmf_dbg(SDIO, "Enter\n");
1070
1071 /* Read mailbox data and ack that we did so */
1072 ret = r_sdreg32(bus, &hmb_data,
1073 offsetof(struct sdpcmd_regs, tohostmailboxdata));
1074
1075 if (ret == 0)
1076 w_sdreg32(bus, SMB_INT_ACK,
1077 offsetof(struct sdpcmd_regs, tosbmailbox));
1078 bus->sdcnt.f1regdata += 2;
1079
1080 /* Dongle recomposed rx frames, accept them again */
1081 if (hmb_data & HMB_DATA_NAKHANDLED) {
1082 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n",
1083 bus->rx_seq);
1084 if (!bus->rxskip)
1085 brcmf_err("unexpected NAKHANDLED!\n");
1086
1087 bus->rxskip = false;
1088 intstatus |= I_HMB_FRAME_IND;
1089 }
1090
1091 /*
1092 * DEVREADY does not occur with gSPI.
1093 */
1094 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1095 bus->sdpcm_ver =
1096 (hmb_data & HMB_DATA_VERSION_MASK) >>
1097 HMB_DATA_VERSION_SHIFT;
1098 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1099 brcmf_err("Version mismatch, dongle reports %d, "
1100 "expecting %d\n",
1101 bus->sdpcm_ver, SDPCM_PROT_VERSION);
1102 else
1103 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n",
1104 bus->sdpcm_ver);
1105
1106 /*
1107 * Retrieve console state address now that firmware should have
1108 * updated it.
1109 */
1110 brcmf_sdio_get_console_addr(bus);
1111 }
1112
1113 /*
1114 * Flow Control has been moved into the RX headers and this out of band
1115 * method isn't used any more.
1116 * remaining backward compatible with older dongles.
1117 */
1118 if (hmb_data & HMB_DATA_FC) {
1119 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1120 HMB_DATA_FCDATA_SHIFT;
1121
1122 if (fcbits & ~bus->flowcontrol)
1123 bus->sdcnt.fc_xoff++;
1124
1125 if (bus->flowcontrol & ~fcbits)
1126 bus->sdcnt.fc_xon++;
1127
1128 bus->sdcnt.fc_rcvd++;
1129 bus->flowcontrol = fcbits;
1130 }
1131
1132 /* Shouldn't be any others */
1133 if (hmb_data & ~(HMB_DATA_DEVREADY |
1134 HMB_DATA_NAKHANDLED |
1135 HMB_DATA_FC |
1136 HMB_DATA_FWREADY |
1137 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1138 brcmf_err("Unknown mailbox data content: 0x%02x\n",
1139 hmb_data);
1140
1141 return intstatus;
1142 }
1143
1144 static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
1145 {
1146 uint retries = 0;
1147 u16 lastrbc;
1148 u8 hi, lo;
1149 int err;
1150
1151 brcmf_err("%sterminate frame%s\n",
1152 abort ? "abort command, " : "",
1153 rtx ? ", send NAK" : "");
1154
1155 if (abort)
1156 brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
1157
1158 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
1159 SFC_RF_TERM, &err);
1160 bus->sdcnt.f1regdata++;
1161
1162 /* Wait until the packet has been flushed (device/FIFO stable) */
1163 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1164 hi = brcmf_sdiod_regrb(bus->sdiodev,
1165 SBSDIO_FUNC1_RFRAMEBCHI, &err);
1166 lo = brcmf_sdiod_regrb(bus->sdiodev,
1167 SBSDIO_FUNC1_RFRAMEBCLO, &err);
1168 bus->sdcnt.f1regdata += 2;
1169
1170 if ((hi == 0) && (lo == 0))
1171 break;
1172
1173 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1174 brcmf_err("count growing: last 0x%04x now 0x%04x\n",
1175 lastrbc, (hi << 8) + lo);
1176 }
1177 lastrbc = (hi << 8) + lo;
1178 }
1179
1180 if (!retries)
1181 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc);
1182 else
1183 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries);
1184
1185 if (rtx) {
1186 bus->sdcnt.rxrtx++;
1187 err = w_sdreg32(bus, SMB_NAK,
1188 offsetof(struct sdpcmd_regs, tosbmailbox));
1189
1190 bus->sdcnt.f1regdata++;
1191 if (err == 0)
1192 bus->rxskip = true;
1193 }
1194
1195 /* Clear partial in any case */
1196 bus->cur_read.len = 0;
1197 }
1198
1199 static void brcmf_sdio_txfail(struct brcmf_sdio *bus)
1200 {
1201 struct brcmf_sdio_dev *sdiodev = bus->sdiodev;
1202 u8 i, hi, lo;
1203
1204 /* On failure, abort the command and terminate the frame */
1205 brcmf_err("sdio error, abort command and terminate frame\n");
1206 bus->sdcnt.tx_sderrs++;
1207
1208 brcmf_sdiod_abort(sdiodev, SDIO_FUNC_2);
1209 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL);
1210 bus->sdcnt.f1regdata++;
1211
1212 for (i = 0; i < 3; i++) {
1213 hi = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL);
1214 lo = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL);
1215 bus->sdcnt.f1regdata += 2;
1216 if ((hi == 0) && (lo == 0))
1217 break;
1218 }
1219 }
1220
1221 /* return total length of buffer chain */
1222 static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus)
1223 {
1224 struct sk_buff *p;
1225 uint total;
1226
1227 total = 0;
1228 skb_queue_walk(&bus->glom, p)
1229 total += p->len;
1230 return total;
1231 }
1232
1233 static void brcmf_sdio_free_glom(struct brcmf_sdio *bus)
1234 {
1235 struct sk_buff *cur, *next;
1236
1237 skb_queue_walk_safe(&bus->glom, cur, next) {
1238 skb_unlink(cur, &bus->glom);
1239 brcmu_pkt_buf_free_skb(cur);
1240 }
1241 }
1242
1243 /**
1244 * brcmfmac sdio bus specific header
1245 * This is the lowest layer header wrapped on the packets transmitted between
1246 * host and WiFi dongle which contains information needed for SDIO core and
1247 * firmware
1248 *
1249 * It consists of 3 parts: hardware header, hardware extension header and
1250 * software header
1251 * hardware header (frame tag) - 4 bytes
1252 * Byte 0~1: Frame length
1253 * Byte 2~3: Checksum, bit-wise inverse of frame length
1254 * hardware extension header - 8 bytes
1255 * Tx glom mode only, N/A for Rx or normal Tx
1256 * Byte 0~1: Packet length excluding hw frame tag
1257 * Byte 2: Reserved
1258 * Byte 3: Frame flags, bit 0: last frame indication
1259 * Byte 4~5: Reserved
1260 * Byte 6~7: Tail padding length
1261 * software header - 8 bytes
1262 * Byte 0: Rx/Tx sequence number
1263 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
1264 * Byte 2: Length of next data frame, reserved for Tx
1265 * Byte 3: Data offset
1266 * Byte 4: Flow control bits, reserved for Tx
1267 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
1268 * Byte 6~7: Reserved
1269 */
1270 #define SDPCM_HWHDR_LEN 4
1271 #define SDPCM_HWEXT_LEN 8
1272 #define SDPCM_SWHDR_LEN 8
1273 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
1274 /* software header */
1275 #define SDPCM_SEQ_MASK 0x000000ff
1276 #define SDPCM_SEQ_WRAP 256
1277 #define SDPCM_CHANNEL_MASK 0x00000f00
1278 #define SDPCM_CHANNEL_SHIFT 8
1279 #define SDPCM_CONTROL_CHANNEL 0 /* Control */
1280 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
1281 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
1282 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
1283 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
1284 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
1285 #define SDPCM_NEXTLEN_MASK 0x00ff0000
1286 #define SDPCM_NEXTLEN_SHIFT 16
1287 #define SDPCM_DOFFSET_MASK 0xff000000
1288 #define SDPCM_DOFFSET_SHIFT 24
1289 #define SDPCM_FCMASK_MASK 0x000000ff
1290 #define SDPCM_WINDOW_MASK 0x0000ff00
1291 #define SDPCM_WINDOW_SHIFT 8
1292
1293 static inline u8 brcmf_sdio_getdatoffset(u8 *swheader)
1294 {
1295 u32 hdrvalue;
1296 hdrvalue = *(u32 *)swheader;
1297 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT);
1298 }
1299
1300 static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header,
1301 struct brcmf_sdio_hdrinfo *rd,
1302 enum brcmf_sdio_frmtype type)
1303 {
1304 u16 len, checksum;
1305 u8 rx_seq, fc, tx_seq_max;
1306 u32 swheader;
1307
1308 trace_brcmf_sdpcm_hdr(SDPCM_RX, header);
1309
1310 /* hw header */
1311 len = get_unaligned_le16(header);
1312 checksum = get_unaligned_le16(header + sizeof(u16));
1313 /* All zero means no more to read */
1314 if (!(len | checksum)) {
1315 bus->rxpending = false;
1316 return -ENODATA;
1317 }
1318 if ((u16)(~(len ^ checksum))) {
1319 brcmf_err("HW header checksum error\n");
1320 bus->sdcnt.rx_badhdr++;
1321 brcmf_sdio_rxfail(bus, false, false);
1322 return -EIO;
1323 }
1324 if (len < SDPCM_HDRLEN) {
1325 brcmf_err("HW header length error\n");
1326 return -EPROTO;
1327 }
1328 if (type == BRCMF_SDIO_FT_SUPER &&
1329 (roundup(len, bus->blocksize) != rd->len)) {
1330 brcmf_err("HW superframe header length error\n");
1331 return -EPROTO;
1332 }
1333 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) {
1334 brcmf_err("HW subframe header length error\n");
1335 return -EPROTO;
1336 }
1337 rd->len = len;
1338
1339 /* software header */
1340 header += SDPCM_HWHDR_LEN;
1341 swheader = le32_to_cpu(*(__le32 *)header);
1342 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) {
1343 brcmf_err("Glom descriptor found in superframe head\n");
1344 rd->len = 0;
1345 return -EINVAL;
1346 }
1347 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK);
1348 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT;
1349 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
1350 type != BRCMF_SDIO_FT_SUPER) {
1351 brcmf_err("HW header length too long\n");
1352 bus->sdcnt.rx_toolong++;
1353 brcmf_sdio_rxfail(bus, false, false);
1354 rd->len = 0;
1355 return -EPROTO;
1356 }
1357 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) {
1358 brcmf_err("Wrong channel for superframe\n");
1359 rd->len = 0;
1360 return -EINVAL;
1361 }
1362 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL &&
1363 rd->channel != SDPCM_EVENT_CHANNEL) {
1364 brcmf_err("Wrong channel for subframe\n");
1365 rd->len = 0;
1366 return -EINVAL;
1367 }
1368 rd->dat_offset = brcmf_sdio_getdatoffset(header);
1369 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
1370 brcmf_err("seq %d: bad data offset\n", rx_seq);
1371 bus->sdcnt.rx_badhdr++;
1372 brcmf_sdio_rxfail(bus, false, false);
1373 rd->len = 0;
1374 return -ENXIO;
1375 }
1376 if (rd->seq_num != rx_seq) {
1377 brcmf_err("seq %d: sequence number error, expect %d\n",
1378 rx_seq, rd->seq_num);
1379 bus->sdcnt.rx_badseq++;
1380 rd->seq_num = rx_seq;
1381 }
1382 /* no need to check the reset for subframe */
1383 if (type == BRCMF_SDIO_FT_SUB)
1384 return 0;
1385 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT;
1386 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
1387 /* only warm for NON glom packet */
1388 if (rd->channel != SDPCM_GLOM_CHANNEL)
1389 brcmf_err("seq %d: next length error\n", rx_seq);
1390 rd->len_nxtfrm = 0;
1391 }
1392 swheader = le32_to_cpu(*(__le32 *)(header + 4));
1393 fc = swheader & SDPCM_FCMASK_MASK;
1394 if (bus->flowcontrol != fc) {
1395 if (~bus->flowcontrol & fc)
1396 bus->sdcnt.fc_xoff++;
1397 if (bus->flowcontrol & ~fc)
1398 bus->sdcnt.fc_xon++;
1399 bus->sdcnt.fc_rcvd++;
1400 bus->flowcontrol = fc;
1401 }
1402 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT;
1403 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
1404 brcmf_err("seq %d: max tx seq number error\n", rx_seq);
1405 tx_seq_max = bus->tx_seq + 2;
1406 }
1407 bus->tx_max = tx_seq_max;
1408
1409 return 0;
1410 }
1411
1412 static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length)
1413 {
1414 *(__le16 *)header = cpu_to_le16(frm_length);
1415 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length);
1416 }
1417
1418 static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header,
1419 struct brcmf_sdio_hdrinfo *hd_info)
1420 {
1421 u32 hdrval;
1422 u8 hdr_offset;
1423
1424 brcmf_sdio_update_hwhdr(header, hd_info->len);
1425 hdr_offset = SDPCM_HWHDR_LEN;
1426
1427 if (bus->txglom) {
1428 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24);
1429 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1430 hdrval = (u16)hd_info->tail_pad << 16;
1431 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval);
1432 hdr_offset += SDPCM_HWEXT_LEN;
1433 }
1434
1435 hdrval = hd_info->seq_num;
1436 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) &
1437 SDPCM_CHANNEL_MASK;
1438 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) &
1439 SDPCM_DOFFSET_MASK;
1440 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1441 *(((__le32 *)(header + hdr_offset)) + 1) = 0;
1442 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header);
1443 }
1444
1445 static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq)
1446 {
1447 u16 dlen, totlen;
1448 u8 *dptr, num = 0;
1449 u16 sublen;
1450 struct sk_buff *pfirst, *pnext;
1451
1452 int errcode;
1453 u8 doff, sfdoff;
1454
1455 struct brcmf_sdio_hdrinfo rd_new;
1456
1457 /* If packets, issue read(s) and send up packet chain */
1458 /* Return sequence numbers consumed? */
1459
1460 brcmf_dbg(SDIO, "start: glomd %p glom %p\n",
1461 bus->glomd, skb_peek(&bus->glom));
1462
1463 /* If there's a descriptor, generate the packet chain */
1464 if (bus->glomd) {
1465 pfirst = pnext = NULL;
1466 dlen = (u16) (bus->glomd->len);
1467 dptr = bus->glomd->data;
1468 if (!dlen || (dlen & 1)) {
1469 brcmf_err("bad glomd len(%d), ignore descriptor\n",
1470 dlen);
1471 dlen = 0;
1472 }
1473
1474 for (totlen = num = 0; dlen; num++) {
1475 /* Get (and move past) next length */
1476 sublen = get_unaligned_le16(dptr);
1477 dlen -= sizeof(u16);
1478 dptr += sizeof(u16);
1479 if ((sublen < SDPCM_HDRLEN) ||
1480 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1481 brcmf_err("descriptor len %d bad: %d\n",
1482 num, sublen);
1483 pnext = NULL;
1484 break;
1485 }
1486 if (sublen % bus->sgentry_align) {
1487 brcmf_err("sublen %d not multiple of %d\n",
1488 sublen, bus->sgentry_align);
1489 }
1490 totlen += sublen;
1491
1492 /* For last frame, adjust read len so total
1493 is a block multiple */
1494 if (!dlen) {
1495 sublen +=
1496 (roundup(totlen, bus->blocksize) - totlen);
1497 totlen = roundup(totlen, bus->blocksize);
1498 }
1499
1500 /* Allocate/chain packet for next subframe */
1501 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align);
1502 if (pnext == NULL) {
1503 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
1504 num, sublen);
1505 break;
1506 }
1507 skb_queue_tail(&bus->glom, pnext);
1508
1509 /* Adhere to start alignment requirements */
1510 pkt_align(pnext, sublen, bus->sgentry_align);
1511 }
1512
1513 /* If all allocations succeeded, save packet chain
1514 in bus structure */
1515 if (pnext) {
1516 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1517 totlen, num);
1518 if (BRCMF_GLOM_ON() && bus->cur_read.len &&
1519 totlen != bus->cur_read.len) {
1520 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1521 bus->cur_read.len, totlen, rxseq);
1522 }
1523 pfirst = pnext = NULL;
1524 } else {
1525 brcmf_sdio_free_glom(bus);
1526 num = 0;
1527 }
1528
1529 /* Done with descriptor packet */
1530 brcmu_pkt_buf_free_skb(bus->glomd);
1531 bus->glomd = NULL;
1532 bus->cur_read.len = 0;
1533 }
1534
1535 /* Ok -- either we just generated a packet chain,
1536 or had one from before */
1537 if (!skb_queue_empty(&bus->glom)) {
1538 if (BRCMF_GLOM_ON()) {
1539 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1540 skb_queue_walk(&bus->glom, pnext) {
1541 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1542 pnext, (u8 *) (pnext->data),
1543 pnext->len, pnext->len);
1544 }
1545 }
1546
1547 pfirst = skb_peek(&bus->glom);
1548 dlen = (u16) brcmf_sdio_glom_len(bus);
1549
1550 /* Do an SDIO read for the superframe. Configurable iovar to
1551 * read directly into the chained packet, or allocate a large
1552 * packet and and copy into the chain.
1553 */
1554 sdio_claim_host(bus->sdiodev->func[1]);
1555 errcode = brcmf_sdiod_recv_chain(bus->sdiodev,
1556 &bus->glom, dlen);
1557 sdio_release_host(bus->sdiodev->func[1]);
1558 bus->sdcnt.f2rxdata++;
1559
1560 /* On failure, kill the superframe */
1561 if (errcode < 0) {
1562 brcmf_err("glom read of %d bytes failed: %d\n",
1563 dlen, errcode);
1564
1565 sdio_claim_host(bus->sdiodev->func[1]);
1566 brcmf_sdio_rxfail(bus, true, false);
1567 bus->sdcnt.rxglomfail++;
1568 brcmf_sdio_free_glom(bus);
1569 sdio_release_host(bus->sdiodev->func[1]);
1570 return 0;
1571 }
1572
1573 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1574 pfirst->data, min_t(int, pfirst->len, 48),
1575 "SUPERFRAME:\n");
1576
1577 rd_new.seq_num = rxseq;
1578 rd_new.len = dlen;
1579 sdio_claim_host(bus->sdiodev->func[1]);
1580 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new,
1581 BRCMF_SDIO_FT_SUPER);
1582 sdio_release_host(bus->sdiodev->func[1]);
1583 bus->cur_read.len = rd_new.len_nxtfrm << 4;
1584
1585 /* Remove superframe header, remember offset */
1586 skb_pull(pfirst, rd_new.dat_offset);
1587 sfdoff = rd_new.dat_offset;
1588 num = 0;
1589
1590 /* Validate all the subframe headers */
1591 skb_queue_walk(&bus->glom, pnext) {
1592 /* leave when invalid subframe is found */
1593 if (errcode)
1594 break;
1595
1596 rd_new.len = pnext->len;
1597 rd_new.seq_num = rxseq++;
1598 sdio_claim_host(bus->sdiodev->func[1]);
1599 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new,
1600 BRCMF_SDIO_FT_SUB);
1601 sdio_release_host(bus->sdiodev->func[1]);
1602 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1603 pnext->data, 32, "subframe:\n");
1604
1605 num++;
1606 }
1607
1608 if (errcode) {
1609 /* Terminate frame on error */
1610 sdio_claim_host(bus->sdiodev->func[1]);
1611 brcmf_sdio_rxfail(bus, true, false);
1612 bus->sdcnt.rxglomfail++;
1613 brcmf_sdio_free_glom(bus);
1614 sdio_release_host(bus->sdiodev->func[1]);
1615 bus->cur_read.len = 0;
1616 return 0;
1617 }
1618
1619 /* Basic SD framing looks ok - process each packet (header) */
1620
1621 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1622 dptr = (u8 *) (pfirst->data);
1623 sublen = get_unaligned_le16(dptr);
1624 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]);
1625
1626 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1627 dptr, pfirst->len,
1628 "Rx Subframe Data:\n");
1629
1630 __skb_trim(pfirst, sublen);
1631 skb_pull(pfirst, doff);
1632
1633 if (pfirst->len == 0) {
1634 skb_unlink(pfirst, &bus->glom);
1635 brcmu_pkt_buf_free_skb(pfirst);
1636 continue;
1637 }
1638
1639 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1640 pfirst->data,
1641 min_t(int, pfirst->len, 32),
1642 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1643 bus->glom.qlen, pfirst, pfirst->data,
1644 pfirst->len, pfirst->next,
1645 pfirst->prev);
1646 skb_unlink(pfirst, &bus->glom);
1647 brcmf_rx_frame(bus->sdiodev->dev, pfirst);
1648 bus->sdcnt.rxglompkts++;
1649 }
1650
1651 bus->sdcnt.rxglomframes++;
1652 }
1653 return num;
1654 }
1655
1656 static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
1657 bool *pending)
1658 {
1659 DECLARE_WAITQUEUE(wait, current);
1660 int timeout = DCMD_RESP_TIMEOUT;
1661
1662 /* Wait until control frame is available */
1663 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1664 set_current_state(TASK_INTERRUPTIBLE);
1665
1666 while (!(*condition) && (!signal_pending(current) && timeout))
1667 timeout = schedule_timeout(timeout);
1668
1669 if (signal_pending(current))
1670 *pending = true;
1671
1672 set_current_state(TASK_RUNNING);
1673 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1674
1675 return timeout;
1676 }
1677
1678 static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus)
1679 {
1680 wake_up_interruptible(&bus->dcmd_resp_wait);
1681
1682 return 0;
1683 }
1684 static void
1685 brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
1686 {
1687 uint rdlen, pad;
1688 u8 *buf = NULL, *rbuf;
1689 int sdret;
1690
1691 brcmf_dbg(TRACE, "Enter\n");
1692
1693 if (bus->rxblen)
1694 buf = vzalloc(bus->rxblen);
1695 if (!buf)
1696 goto done;
1697
1698 rbuf = bus->rxbuf;
1699 pad = ((unsigned long)rbuf % bus->head_align);
1700 if (pad)
1701 rbuf += (bus->head_align - pad);
1702
1703 /* Copy the already-read portion over */
1704 memcpy(buf, hdr, BRCMF_FIRSTREAD);
1705 if (len <= BRCMF_FIRSTREAD)
1706 goto gotpkt;
1707
1708 /* Raise rdlen to next SDIO block to avoid tail command */
1709 rdlen = len - BRCMF_FIRSTREAD;
1710 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1711 pad = bus->blocksize - (rdlen % bus->blocksize);
1712 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1713 ((len + pad) < bus->sdiodev->bus_if->maxctl))
1714 rdlen += pad;
1715 } else if (rdlen % bus->head_align) {
1716 rdlen += bus->head_align - (rdlen % bus->head_align);
1717 }
1718
1719 /* Drop if the read is too big or it exceeds our maximum */
1720 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
1721 brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
1722 rdlen, bus->sdiodev->bus_if->maxctl);
1723 brcmf_sdio_rxfail(bus, false, false);
1724 goto done;
1725 }
1726
1727 if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
1728 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1729 len, len - doff, bus->sdiodev->bus_if->maxctl);
1730 bus->sdcnt.rx_toolong++;
1731 brcmf_sdio_rxfail(bus, false, false);
1732 goto done;
1733 }
1734
1735 /* Read remain of frame body */
1736 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen);
1737 bus->sdcnt.f2rxdata++;
1738
1739 /* Control frame failures need retransmission */
1740 if (sdret < 0) {
1741 brcmf_err("read %d control bytes failed: %d\n",
1742 rdlen, sdret);
1743 bus->sdcnt.rxc_errors++;
1744 brcmf_sdio_rxfail(bus, true, true);
1745 goto done;
1746 } else
1747 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen);
1748
1749 gotpkt:
1750
1751 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
1752 buf, len, "RxCtrl:\n");
1753
1754 /* Point to valid data and indicate its length */
1755 spin_lock_bh(&bus->rxctl_lock);
1756 if (bus->rxctl) {
1757 brcmf_err("last control frame is being processed.\n");
1758 spin_unlock_bh(&bus->rxctl_lock);
1759 vfree(buf);
1760 goto done;
1761 }
1762 bus->rxctl = buf + doff;
1763 bus->rxctl_orig = buf;
1764 bus->rxlen = len - doff;
1765 spin_unlock_bh(&bus->rxctl_lock);
1766
1767 done:
1768 /* Awake any waiters */
1769 brcmf_sdio_dcmd_resp_wake(bus);
1770 }
1771
1772 /* Pad read to blocksize for efficiency */
1773 static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
1774 {
1775 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1776 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1777 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1778 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1779 *rdlen += *pad;
1780 } else if (*rdlen % bus->head_align) {
1781 *rdlen += bus->head_align - (*rdlen % bus->head_align);
1782 }
1783 }
1784
1785 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
1786 {
1787 struct sk_buff *pkt; /* Packet for event or data frames */
1788 u16 pad; /* Number of pad bytes to read */
1789 uint rxleft = 0; /* Remaining number of frames allowed */
1790 int ret; /* Return code from calls */
1791 uint rxcount = 0; /* Total frames read */
1792 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new;
1793 u8 head_read = 0;
1794
1795 brcmf_dbg(TRACE, "Enter\n");
1796
1797 /* Not finished unless we encounter no more frames indication */
1798 bus->rxpending = true;
1799
1800 for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
1801 !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA;
1802 rd->seq_num++, rxleft--) {
1803
1804 /* Handle glomming separately */
1805 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
1806 u8 cnt;
1807 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1808 bus->glomd, skb_peek(&bus->glom));
1809 cnt = brcmf_sdio_rxglom(bus, rd->seq_num);
1810 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1811 rd->seq_num += cnt - 1;
1812 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1813 continue;
1814 }
1815
1816 rd->len_left = rd->len;
1817 /* read header first for unknow frame length */
1818 sdio_claim_host(bus->sdiodev->func[1]);
1819 if (!rd->len) {
1820 ret = brcmf_sdiod_recv_buf(bus->sdiodev,
1821 bus->rxhdr, BRCMF_FIRSTREAD);
1822 bus->sdcnt.f2rxhdrs++;
1823 if (ret < 0) {
1824 brcmf_err("RXHEADER FAILED: %d\n",
1825 ret);
1826 bus->sdcnt.rx_hdrfail++;
1827 brcmf_sdio_rxfail(bus, true, true);
1828 sdio_release_host(bus->sdiodev->func[1]);
1829 continue;
1830 }
1831
1832 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
1833 bus->rxhdr, SDPCM_HDRLEN,
1834 "RxHdr:\n");
1835
1836 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd,
1837 BRCMF_SDIO_FT_NORMAL)) {
1838 sdio_release_host(bus->sdiodev->func[1]);
1839 if (!bus->rxpending)
1840 break;
1841 else
1842 continue;
1843 }
1844
1845 if (rd->channel == SDPCM_CONTROL_CHANNEL) {
1846 brcmf_sdio_read_control(bus, bus->rxhdr,
1847 rd->len,
1848 rd->dat_offset);
1849 /* prepare the descriptor for the next read */
1850 rd->len = rd->len_nxtfrm << 4;
1851 rd->len_nxtfrm = 0;
1852 /* treat all packet as event if we don't know */
1853 rd->channel = SDPCM_EVENT_CHANNEL;
1854 sdio_release_host(bus->sdiodev->func[1]);
1855 continue;
1856 }
1857 rd->len_left = rd->len > BRCMF_FIRSTREAD ?
1858 rd->len - BRCMF_FIRSTREAD : 0;
1859 head_read = BRCMF_FIRSTREAD;
1860 }
1861
1862 brcmf_sdio_pad(bus, &pad, &rd->len_left);
1863
1864 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
1865 bus->head_align);
1866 if (!pkt) {
1867 /* Give up on data, request rtx of events */
1868 brcmf_err("brcmu_pkt_buf_get_skb failed\n");
1869 brcmf_sdio_rxfail(bus, false,
1870 RETRYCHAN(rd->channel));
1871 sdio_release_host(bus->sdiodev->func[1]);
1872 continue;
1873 }
1874 skb_pull(pkt, head_read);
1875 pkt_align(pkt, rd->len_left, bus->head_align);
1876
1877 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt);
1878 bus->sdcnt.f2rxdata++;
1879 sdio_release_host(bus->sdiodev->func[1]);
1880
1881 if (ret < 0) {
1882 brcmf_err("read %d bytes from channel %d failed: %d\n",
1883 rd->len, rd->channel, ret);
1884 brcmu_pkt_buf_free_skb(pkt);
1885 sdio_claim_host(bus->sdiodev->func[1]);
1886 brcmf_sdio_rxfail(bus, true,
1887 RETRYCHAN(rd->channel));
1888 sdio_release_host(bus->sdiodev->func[1]);
1889 continue;
1890 }
1891
1892 if (head_read) {
1893 skb_push(pkt, head_read);
1894 memcpy(pkt->data, bus->rxhdr, head_read);
1895 head_read = 0;
1896 } else {
1897 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
1898 rd_new.seq_num = rd->seq_num;
1899 sdio_claim_host(bus->sdiodev->func[1]);
1900 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new,
1901 BRCMF_SDIO_FT_NORMAL)) {
1902 rd->len = 0;
1903 brcmu_pkt_buf_free_skb(pkt);
1904 }
1905 bus->sdcnt.rx_readahead_cnt++;
1906 if (rd->len != roundup(rd_new.len, 16)) {
1907 brcmf_err("frame length mismatch:read %d, should be %d\n",
1908 rd->len,
1909 roundup(rd_new.len, 16) >> 4);
1910 rd->len = 0;
1911 brcmf_sdio_rxfail(bus, true, true);
1912 sdio_release_host(bus->sdiodev->func[1]);
1913 brcmu_pkt_buf_free_skb(pkt);
1914 continue;
1915 }
1916 sdio_release_host(bus->sdiodev->func[1]);
1917 rd->len_nxtfrm = rd_new.len_nxtfrm;
1918 rd->channel = rd_new.channel;
1919 rd->dat_offset = rd_new.dat_offset;
1920
1921 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
1922 BRCMF_DATA_ON()) &&
1923 BRCMF_HDRS_ON(),
1924 bus->rxhdr, SDPCM_HDRLEN,
1925 "RxHdr:\n");
1926
1927 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) {
1928 brcmf_err("readahead on control packet %d?\n",
1929 rd_new.seq_num);
1930 /* Force retry w/normal header read */
1931 rd->len = 0;
1932 sdio_claim_host(bus->sdiodev->func[1]);
1933 brcmf_sdio_rxfail(bus, false, true);
1934 sdio_release_host(bus->sdiodev->func[1]);
1935 brcmu_pkt_buf_free_skb(pkt);
1936 continue;
1937 }
1938 }
1939
1940 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1941 pkt->data, rd->len, "Rx Data:\n");
1942
1943 /* Save superframe descriptor and allocate packet frame */
1944 if (rd->channel == SDPCM_GLOM_CHANNEL) {
1945 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) {
1946 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
1947 rd->len);
1948 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1949 pkt->data, rd->len,
1950 "Glom Data:\n");
1951 __skb_trim(pkt, rd->len);
1952 skb_pull(pkt, SDPCM_HDRLEN);
1953 bus->glomd = pkt;
1954 } else {
1955 brcmf_err("%s: glom superframe w/o "
1956 "descriptor!\n", __func__);
1957 sdio_claim_host(bus->sdiodev->func[1]);
1958 brcmf_sdio_rxfail(bus, false, false);
1959 sdio_release_host(bus->sdiodev->func[1]);
1960 }
1961 /* prepare the descriptor for the next read */
1962 rd->len = rd->len_nxtfrm << 4;
1963 rd->len_nxtfrm = 0;
1964 /* treat all packet as event if we don't know */
1965 rd->channel = SDPCM_EVENT_CHANNEL;
1966 continue;
1967 }
1968
1969 /* Fill in packet len and prio, deliver upward */
1970 __skb_trim(pkt, rd->len);
1971 skb_pull(pkt, rd->dat_offset);
1972
1973 /* prepare the descriptor for the next read */
1974 rd->len = rd->len_nxtfrm << 4;
1975 rd->len_nxtfrm = 0;
1976 /* treat all packet as event if we don't know */
1977 rd->channel = SDPCM_EVENT_CHANNEL;
1978
1979 if (pkt->len == 0) {
1980 brcmu_pkt_buf_free_skb(pkt);
1981 continue;
1982 }
1983
1984 brcmf_rx_frame(bus->sdiodev->dev, pkt);
1985 }
1986
1987 rxcount = maxframes - rxleft;
1988 /* Message if we hit the limit */
1989 if (!rxleft)
1990 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes);
1991 else
1992 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
1993 /* Back off rxseq if awaiting rtx, update rx_seq */
1994 if (bus->rxskip)
1995 rd->seq_num--;
1996 bus->rx_seq = rd->seq_num;
1997
1998 return rxcount;
1999 }
2000
2001 static void
2002 brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus)
2003 {
2004 wake_up_interruptible(&bus->ctrl_wait);
2005 return;
2006 }
2007
2008 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt)
2009 {
2010 u16 head_pad;
2011 u8 *dat_buf;
2012
2013 dat_buf = (u8 *)(pkt->data);
2014
2015 /* Check head padding */
2016 head_pad = ((unsigned long)dat_buf % bus->head_align);
2017 if (head_pad) {
2018 if (skb_headroom(pkt) < head_pad) {
2019 bus->sdiodev->bus_if->tx_realloc++;
2020 head_pad = 0;
2021 if (skb_cow(pkt, head_pad))
2022 return -ENOMEM;
2023 }
2024 skb_push(pkt, head_pad);
2025 dat_buf = (u8 *)(pkt->data);
2026 memset(dat_buf, 0, head_pad + bus->tx_hdrlen);
2027 }
2028 return head_pad;
2029 }
2030
2031 /**
2032 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
2033 * bus layer usage.
2034 */
2035 /* flag marking a dummy skb added for DMA alignment requirement */
2036 #define ALIGN_SKB_FLAG 0x8000
2037 /* bit mask of data length chopped from the previous packet */
2038 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
2039
2040 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus,
2041 struct sk_buff_head *pktq,
2042 struct sk_buff *pkt, u16 total_len)
2043 {
2044 struct brcmf_sdio_dev *sdiodev;
2045 struct sk_buff *pkt_pad;
2046 u16 tail_pad, tail_chop, chain_pad;
2047 unsigned int blksize;
2048 bool lastfrm;
2049 int ntail, ret;
2050
2051 sdiodev = bus->sdiodev;
2052 blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize;
2053 /* sg entry alignment should be a divisor of block size */
2054 WARN_ON(blksize % bus->sgentry_align);
2055
2056 /* Check tail padding */
2057 lastfrm = skb_queue_is_last(pktq, pkt);
2058 tail_pad = 0;
2059 tail_chop = pkt->len % bus->sgentry_align;
2060 if (tail_chop)
2061 tail_pad = bus->sgentry_align - tail_chop;
2062 chain_pad = (total_len + tail_pad) % blksize;
2063 if (lastfrm && chain_pad)
2064 tail_pad += blksize - chain_pad;
2065 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) {
2066 pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop +
2067 bus->head_align);
2068 if (pkt_pad == NULL)
2069 return -ENOMEM;
2070 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad);
2071 if (unlikely(ret < 0)) {
2072 kfree_skb(pkt_pad);
2073 return ret;
2074 }
2075 memcpy(pkt_pad->data,
2076 pkt->data + pkt->len - tail_chop,
2077 tail_chop);
2078 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop;
2079 skb_trim(pkt, pkt->len - tail_chop);
2080 skb_trim(pkt_pad, tail_pad + tail_chop);
2081 __skb_queue_after(pktq, pkt, pkt_pad);
2082 } else {
2083 ntail = pkt->data_len + tail_pad -
2084 (pkt->end - pkt->tail);
2085 if (skb_cloned(pkt) || ntail > 0)
2086 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC))
2087 return -ENOMEM;
2088 if (skb_linearize(pkt))
2089 return -ENOMEM;
2090 __skb_put(pkt, tail_pad);
2091 }
2092
2093 return tail_pad;
2094 }
2095
2096 /**
2097 * brcmf_sdio_txpkt_prep - packet preparation for transmit
2098 * @bus: brcmf_sdio structure pointer
2099 * @pktq: packet list pointer
2100 * @chan: virtual channel to transmit the packet
2101 *
2102 * Processes to be applied to the packet
2103 * - Align data buffer pointer
2104 * - Align data buffer length
2105 * - Prepare header
2106 * Return: negative value if there is error
2107 */
2108 static int
2109 brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2110 uint chan)
2111 {
2112 u16 head_pad, total_len;
2113 struct sk_buff *pkt_next;
2114 u8 txseq;
2115 int ret;
2116 struct brcmf_sdio_hdrinfo hd_info = {0};
2117
2118 txseq = bus->tx_seq;
2119 total_len = 0;
2120 skb_queue_walk(pktq, pkt_next) {
2121 /* alignment packet inserted in previous
2122 * loop cycle can be skipped as it is
2123 * already properly aligned and does not
2124 * need an sdpcm header.
2125 */
2126 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG)
2127 continue;
2128
2129 /* align packet data pointer */
2130 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next);
2131 if (ret < 0)
2132 return ret;
2133 head_pad = (u16)ret;
2134 if (head_pad)
2135 memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad);
2136
2137 total_len += pkt_next->len;
2138
2139 hd_info.len = pkt_next->len;
2140 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next);
2141 if (bus->txglom && pktq->qlen > 1) {
2142 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq,
2143 pkt_next, total_len);
2144 if (ret < 0)
2145 return ret;
2146 hd_info.tail_pad = (u16)ret;
2147 total_len += (u16)ret;
2148 }
2149
2150 hd_info.channel = chan;
2151 hd_info.dat_offset = head_pad + bus->tx_hdrlen;
2152 hd_info.seq_num = txseq++;
2153
2154 /* Now fill the header */
2155 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info);
2156
2157 if (BRCMF_BYTES_ON() &&
2158 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
2159 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)))
2160 brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len,
2161 "Tx Frame:\n");
2162 else if (BRCMF_HDRS_ON())
2163 brcmf_dbg_hex_dump(true, pkt_next->data,
2164 head_pad + bus->tx_hdrlen,
2165 "Tx Header:\n");
2166 }
2167 /* Hardware length tag of the first packet should be total
2168 * length of the chain (including padding)
2169 */
2170 if (bus->txglom)
2171 brcmf_sdio_update_hwhdr(pktq->next->data, total_len);
2172 return 0;
2173 }
2174
2175 /**
2176 * brcmf_sdio_txpkt_postp - packet post processing for transmit
2177 * @bus: brcmf_sdio structure pointer
2178 * @pktq: packet list pointer
2179 *
2180 * Processes to be applied to the packet
2181 * - Remove head padding
2182 * - Remove tail padding
2183 */
2184 static void
2185 brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq)
2186 {
2187 u8 *hdr;
2188 u32 dat_offset;
2189 u16 tail_pad;
2190 u16 dummy_flags, chop_len;
2191 struct sk_buff *pkt_next, *tmp, *pkt_prev;
2192
2193 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2194 dummy_flags = *(u16 *)(pkt_next->cb);
2195 if (dummy_flags & ALIGN_SKB_FLAG) {
2196 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK;
2197 if (chop_len) {
2198 pkt_prev = pkt_next->prev;
2199 skb_put(pkt_prev, chop_len);
2200 }
2201 __skb_unlink(pkt_next, pktq);
2202 brcmu_pkt_buf_free_skb(pkt_next);
2203 } else {
2204 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN;
2205 dat_offset = le32_to_cpu(*(__le32 *)hdr);
2206 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >>
2207 SDPCM_DOFFSET_SHIFT;
2208 skb_pull(pkt_next, dat_offset);
2209 if (bus->txglom) {
2210 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2));
2211 skb_trim(pkt_next, pkt_next->len - tail_pad);
2212 }
2213 }
2214 }
2215 }
2216
2217 /* Writes a HW/SW header into the packet and sends it. */
2218 /* Assumes: (a) header space already there, (b) caller holds lock */
2219 static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2220 uint chan)
2221 {
2222 int ret;
2223 struct sk_buff *pkt_next, *tmp;
2224
2225 brcmf_dbg(TRACE, "Enter\n");
2226
2227 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan);
2228 if (ret)
2229 goto done;
2230
2231 sdio_claim_host(bus->sdiodev->func[1]);
2232 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq);
2233 bus->sdcnt.f2txdata++;
2234
2235 if (ret < 0)
2236 brcmf_sdio_txfail(bus);
2237
2238 sdio_release_host(bus->sdiodev->func[1]);
2239
2240 done:
2241 brcmf_sdio_txpkt_postp(bus, pktq);
2242 if (ret == 0)
2243 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP;
2244 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2245 __skb_unlink(pkt_next, pktq);
2246 brcmf_txcomplete(bus->sdiodev->dev, pkt_next, ret == 0);
2247 }
2248 return ret;
2249 }
2250
2251 static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes)
2252 {
2253 struct sk_buff *pkt;
2254 struct sk_buff_head pktq;
2255 u32 intstatus = 0;
2256 int ret = 0, prec_out, i;
2257 uint cnt = 0;
2258 u8 tx_prec_map, pkt_num;
2259
2260 brcmf_dbg(TRACE, "Enter\n");
2261
2262 tx_prec_map = ~bus->flowcontrol;
2263
2264 /* Send frames until the limit or some other event */
2265 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) {
2266 pkt_num = 1;
2267 if (bus->txglom)
2268 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq,
2269 bus->sdiodev->txglomsz);
2270 pkt_num = min_t(u32, pkt_num,
2271 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol));
2272 __skb_queue_head_init(&pktq);
2273 spin_lock_bh(&bus->txq_lock);
2274 for (i = 0; i < pkt_num; i++) {
2275 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map,
2276 &prec_out);
2277 if (pkt == NULL)
2278 break;
2279 __skb_queue_tail(&pktq, pkt);
2280 }
2281 spin_unlock_bh(&bus->txq_lock);
2282 if (i == 0)
2283 break;
2284
2285 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL);
2286
2287 cnt += i;
2288
2289 /* In poll mode, need to check for other events */
2290 if (!bus->intr) {
2291 /* Check device status, signal pending interrupt */
2292 sdio_claim_host(bus->sdiodev->func[1]);
2293 ret = r_sdreg32(bus, &intstatus,
2294 offsetof(struct sdpcmd_regs,
2295 intstatus));
2296 sdio_release_host(bus->sdiodev->func[1]);
2297 bus->sdcnt.f2txdata++;
2298 if (ret != 0)
2299 break;
2300 if (intstatus & bus->hostintmask)
2301 atomic_set(&bus->ipend, 1);
2302 }
2303 }
2304
2305 /* Deflow-control stack if needed */
2306 if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) &&
2307 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
2308 bus->txoff = false;
2309 brcmf_txflowblock(bus->sdiodev->dev, false);
2310 }
2311
2312 return cnt;
2313 }
2314
2315 static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len)
2316 {
2317 u8 doff;
2318 u16 pad;
2319 uint retries = 0;
2320 struct brcmf_sdio_hdrinfo hd_info = {0};
2321 int ret;
2322
2323 brcmf_dbg(TRACE, "Enter\n");
2324
2325 /* Back the pointer to make room for bus header */
2326 frame -= bus->tx_hdrlen;
2327 len += bus->tx_hdrlen;
2328
2329 /* Add alignment padding (optional for ctl frames) */
2330 doff = ((unsigned long)frame % bus->head_align);
2331 if (doff) {
2332 frame -= doff;
2333 len += doff;
2334 memset(frame + bus->tx_hdrlen, 0, doff);
2335 }
2336
2337 /* Round send length to next SDIO block */
2338 pad = 0;
2339 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2340 pad = bus->blocksize - (len % bus->blocksize);
2341 if ((pad > bus->roundup) || (pad >= bus->blocksize))
2342 pad = 0;
2343 } else if (len % bus->head_align) {
2344 pad = bus->head_align - (len % bus->head_align);
2345 }
2346 len += pad;
2347
2348 hd_info.len = len - pad;
2349 hd_info.channel = SDPCM_CONTROL_CHANNEL;
2350 hd_info.dat_offset = doff + bus->tx_hdrlen;
2351 hd_info.seq_num = bus->tx_seq;
2352 hd_info.lastfrm = true;
2353 hd_info.tail_pad = pad;
2354 brcmf_sdio_hdpack(bus, frame, &hd_info);
2355
2356 if (bus->txglom)
2357 brcmf_sdio_update_hwhdr(frame, len);
2358
2359 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
2360 frame, len, "Tx Frame:\n");
2361 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
2362 BRCMF_HDRS_ON(),
2363 frame, min_t(u16, len, 16), "TxHdr:\n");
2364
2365 do {
2366 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len);
2367
2368 if (ret < 0)
2369 brcmf_sdio_txfail(bus);
2370 else
2371 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
2372 } while (ret < 0 && retries++ < TXRETRIES);
2373
2374 return ret;
2375 }
2376
2377 static void brcmf_sdio_bus_stop(struct device *dev)
2378 {
2379 u32 local_hostintmask;
2380 u8 saveclk;
2381 int err;
2382 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2383 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2384 struct brcmf_sdio *bus = sdiodev->bus;
2385
2386 brcmf_dbg(TRACE, "Enter\n");
2387
2388 if (bus->watchdog_tsk) {
2389 send_sig(SIGTERM, bus->watchdog_tsk, 1);
2390 kthread_stop(bus->watchdog_tsk);
2391 bus->watchdog_tsk = NULL;
2392 }
2393
2394 if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
2395 sdio_claim_host(sdiodev->func[1]);
2396
2397 /* Enable clock for device interrupts */
2398 brcmf_sdio_bus_sleep(bus, false, false);
2399
2400 /* Disable and clear interrupts at the chip level also */
2401 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask));
2402 local_hostintmask = bus->hostintmask;
2403 bus->hostintmask = 0;
2404
2405 /* Force backplane clocks to assure F2 interrupt propagates */
2406 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2407 &err);
2408 if (!err)
2409 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2410 (saveclk | SBSDIO_FORCE_HT), &err);
2411 if (err)
2412 brcmf_err("Failed to force clock for F2: err %d\n",
2413 err);
2414
2415 /* Turn off the bus (F2), free any pending packets */
2416 brcmf_dbg(INTR, "disable SDIO interrupts\n");
2417 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
2418
2419 /* Clear any pending interrupts now that F2 is disabled */
2420 w_sdreg32(bus, local_hostintmask,
2421 offsetof(struct sdpcmd_regs, intstatus));
2422
2423 sdio_release_host(sdiodev->func[1]);
2424 }
2425 /* Clear the data packet queues */
2426 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
2427
2428 /* Clear any held glomming stuff */
2429 brcmu_pkt_buf_free_skb(bus->glomd);
2430 brcmf_sdio_free_glom(bus);
2431
2432 /* Clear rx control and wake any waiters */
2433 spin_lock_bh(&bus->rxctl_lock);
2434 bus->rxlen = 0;
2435 spin_unlock_bh(&bus->rxctl_lock);
2436 brcmf_sdio_dcmd_resp_wake(bus);
2437
2438 /* Reset some F2 state stuff */
2439 bus->rxskip = false;
2440 bus->tx_seq = bus->rx_seq = 0;
2441 }
2442
2443 static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus)
2444 {
2445 struct brcmf_sdio_dev *sdiodev;
2446 unsigned long flags;
2447
2448 sdiodev = bus->sdiodev;
2449 if (sdiodev->oob_irq_requested) {
2450 spin_lock_irqsave(&sdiodev->irq_en_lock, flags);
2451 if (!sdiodev->irq_en && !atomic_read(&bus->ipend)) {
2452 enable_irq(sdiodev->settings->bus.sdio.oob_irq_nr);
2453 sdiodev->irq_en = true;
2454 }
2455 spin_unlock_irqrestore(&sdiodev->irq_en_lock, flags);
2456 }
2457 }
2458
2459 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
2460 {
2461 struct brcmf_core *buscore;
2462 u32 addr;
2463 unsigned long val;
2464 int ret;
2465
2466 buscore = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
2467 addr = buscore->base + offsetof(struct sdpcmd_regs, intstatus);
2468
2469 val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret);
2470 bus->sdcnt.f1regdata++;
2471 if (ret != 0)
2472 return ret;
2473
2474 val &= bus->hostintmask;
2475 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE));
2476
2477 /* Clear interrupts */
2478 if (val) {
2479 brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret);
2480 bus->sdcnt.f1regdata++;
2481 atomic_or(val, &bus->intstatus);
2482 }
2483
2484 return ret;
2485 }
2486
2487 static void brcmf_sdio_dpc(struct brcmf_sdio *bus)
2488 {
2489 u32 newstatus = 0;
2490 unsigned long intstatus;
2491 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2492 uint framecnt; /* Temporary counter of tx/rx frames */
2493 int err = 0;
2494
2495 brcmf_dbg(TRACE, "Enter\n");
2496
2497 sdio_claim_host(bus->sdiodev->func[1]);
2498
2499 /* If waiting for HTAVAIL, check status */
2500 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) {
2501 u8 clkctl, devctl = 0;
2502
2503 #ifdef DEBUG
2504 /* Check for inconsistent device control */
2505 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2506 SBSDIO_DEVICE_CTL, &err);
2507 #endif /* DEBUG */
2508
2509 /* Read CSR, if clock on switch to AVAIL, else ignore */
2510 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
2511 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2512
2513 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2514 devctl, clkctl);
2515
2516 if (SBSDIO_HTAV(clkctl)) {
2517 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2518 SBSDIO_DEVICE_CTL, &err);
2519 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2520 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
2521 devctl, &err);
2522 bus->clkstate = CLK_AVAIL;
2523 }
2524 }
2525
2526 /* Make sure backplane clock is on */
2527 brcmf_sdio_bus_sleep(bus, false, true);
2528
2529 /* Pending interrupt indicates new device status */
2530 if (atomic_read(&bus->ipend) > 0) {
2531 atomic_set(&bus->ipend, 0);
2532 err = brcmf_sdio_intr_rstatus(bus);
2533 }
2534
2535 /* Start with leftover status bits */
2536 intstatus = atomic_xchg(&bus->intstatus, 0);
2537
2538 /* Handle flow-control change: read new state in case our ack
2539 * crossed another change interrupt. If change still set, assume
2540 * FC ON for safety, let next loop through do the debounce.
2541 */
2542 if (intstatus & I_HMB_FC_CHANGE) {
2543 intstatus &= ~I_HMB_FC_CHANGE;
2544 err = w_sdreg32(bus, I_HMB_FC_CHANGE,
2545 offsetof(struct sdpcmd_regs, intstatus));
2546
2547 err = r_sdreg32(bus, &newstatus,
2548 offsetof(struct sdpcmd_regs, intstatus));
2549 bus->sdcnt.f1regdata += 2;
2550 atomic_set(&bus->fcstate,
2551 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)));
2552 intstatus |= (newstatus & bus->hostintmask);
2553 }
2554
2555 /* Handle host mailbox indication */
2556 if (intstatus & I_HMB_HOST_INT) {
2557 intstatus &= ~I_HMB_HOST_INT;
2558 intstatus |= brcmf_sdio_hostmail(bus);
2559 }
2560
2561 sdio_release_host(bus->sdiodev->func[1]);
2562
2563 /* Generally don't ask for these, can get CRC errors... */
2564 if (intstatus & I_WR_OOSYNC) {
2565 brcmf_err("Dongle reports WR_OOSYNC\n");
2566 intstatus &= ~I_WR_OOSYNC;
2567 }
2568
2569 if (intstatus & I_RD_OOSYNC) {
2570 brcmf_err("Dongle reports RD_OOSYNC\n");
2571 intstatus &= ~I_RD_OOSYNC;
2572 }
2573
2574 if (intstatus & I_SBINT) {
2575 brcmf_err("Dongle reports SBINT\n");
2576 intstatus &= ~I_SBINT;
2577 }
2578
2579 /* Would be active due to wake-wlan in gSPI */
2580 if (intstatus & I_CHIPACTIVE) {
2581 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2582 intstatus &= ~I_CHIPACTIVE;
2583 }
2584
2585 /* Ignore frame indications if rxskip is set */
2586 if (bus->rxskip)
2587 intstatus &= ~I_HMB_FRAME_IND;
2588
2589 /* On frame indication, read available frames */
2590 if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) {
2591 brcmf_sdio_readframes(bus, bus->rxbound);
2592 if (!bus->rxpending)
2593 intstatus &= ~I_HMB_FRAME_IND;
2594 }
2595
2596 /* Keep still-pending events for next scheduling */
2597 if (intstatus)
2598 atomic_or(intstatus, &bus->intstatus);
2599
2600 brcmf_sdio_clrintr(bus);
2601
2602 if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) &&
2603 data_ok(bus)) {
2604 sdio_claim_host(bus->sdiodev->func[1]);
2605 if (bus->ctrl_frame_stat) {
2606 err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf,
2607 bus->ctrl_frame_len);
2608 bus->ctrl_frame_err = err;
2609 wmb();
2610 bus->ctrl_frame_stat = false;
2611 }
2612 sdio_release_host(bus->sdiodev->func[1]);
2613 brcmf_sdio_wait_event_wakeup(bus);
2614 }
2615 /* Send queued frames (limit 1 if rx may still be pending) */
2616 if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
2617 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit &&
2618 data_ok(bus)) {
2619 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
2620 txlimit;
2621 brcmf_sdio_sendfromq(bus, framecnt);
2622 }
2623
2624 if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) {
2625 brcmf_err("failed backplane access over SDIO, halting operation\n");
2626 atomic_set(&bus->intstatus, 0);
2627 if (bus->ctrl_frame_stat) {
2628 sdio_claim_host(bus->sdiodev->func[1]);
2629 if (bus->ctrl_frame_stat) {
2630 bus->ctrl_frame_err = -ENODEV;
2631 wmb();
2632 bus->ctrl_frame_stat = false;
2633 brcmf_sdio_wait_event_wakeup(bus);
2634 }
2635 sdio_release_host(bus->sdiodev->func[1]);
2636 }
2637 } else if (atomic_read(&bus->intstatus) ||
2638 atomic_read(&bus->ipend) > 0 ||
2639 (!atomic_read(&bus->fcstate) &&
2640 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
2641 data_ok(bus))) {
2642 bus->dpc_triggered = true;
2643 }
2644 }
2645
2646 static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev)
2647 {
2648 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2649 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2650 struct brcmf_sdio *bus = sdiodev->bus;
2651
2652 return &bus->txq;
2653 }
2654
2655 static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec)
2656 {
2657 struct sk_buff *p;
2658 int eprec = -1; /* precedence to evict from */
2659
2660 /* Fast case, precedence queue is not full and we are also not
2661 * exceeding total queue length
2662 */
2663 if (!pktq_pfull(q, prec) && !pktq_full(q)) {
2664 brcmu_pktq_penq(q, prec, pkt);
2665 return true;
2666 }
2667
2668 /* Determine precedence from which to evict packet, if any */
2669 if (pktq_pfull(q, prec)) {
2670 eprec = prec;
2671 } else if (pktq_full(q)) {
2672 p = brcmu_pktq_peek_tail(q, &eprec);
2673 if (eprec > prec)
2674 return false;
2675 }
2676
2677 /* Evict if needed */
2678 if (eprec >= 0) {
2679 /* Detect queueing to unconfigured precedence */
2680 if (eprec == prec)
2681 return false; /* refuse newer (incoming) packet */
2682 /* Evict packet according to discard policy */
2683 p = brcmu_pktq_pdeq_tail(q, eprec);
2684 if (p == NULL)
2685 brcmf_err("brcmu_pktq_pdeq_tail() failed\n");
2686 brcmu_pkt_buf_free_skb(p);
2687 }
2688
2689 /* Enqueue */
2690 p = brcmu_pktq_penq(q, prec, pkt);
2691 if (p == NULL)
2692 brcmf_err("brcmu_pktq_penq() failed\n");
2693
2694 return p != NULL;
2695 }
2696
2697 static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt)
2698 {
2699 int ret = -EBADE;
2700 uint prec;
2701 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2702 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2703 struct brcmf_sdio *bus = sdiodev->bus;
2704
2705 brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len);
2706 if (sdiodev->state != BRCMF_SDIOD_DATA)
2707 return -EIO;
2708
2709 /* Add space for the header */
2710 skb_push(pkt, bus->tx_hdrlen);
2711 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2712
2713 prec = prio2prec((pkt->priority & PRIOMASK));
2714
2715 /* Check for existing queue, current flow-control,
2716 pending event, or pending clock */
2717 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2718 bus->sdcnt.fcqueued++;
2719
2720 /* Priority based enq */
2721 spin_lock_bh(&bus->txq_lock);
2722 /* reset bus_flags in packet cb */
2723 *(u16 *)(pkt->cb) = 0;
2724 if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) {
2725 skb_pull(pkt, bus->tx_hdrlen);
2726 brcmf_err("out of bus->txq !!!\n");
2727 ret = -ENOSR;
2728 } else {
2729 ret = 0;
2730 }
2731
2732 if (pktq_len(&bus->txq) >= TXHI) {
2733 bus->txoff = true;
2734 brcmf_txflowblock(dev, true);
2735 }
2736 spin_unlock_bh(&bus->txq_lock);
2737
2738 #ifdef DEBUG
2739 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2740 qcount[prec] = pktq_plen(&bus->txq, prec);
2741 #endif
2742
2743 brcmf_sdio_trigger_dpc(bus);
2744 return ret;
2745 }
2746
2747 #ifdef DEBUG
2748 #define CONSOLE_LINE_MAX 192
2749
2750 static int brcmf_sdio_readconsole(struct brcmf_sdio *bus)
2751 {
2752 struct brcmf_console *c = &bus->console;
2753 u8 line[CONSOLE_LINE_MAX], ch;
2754 u32 n, idx, addr;
2755 int rv;
2756
2757 /* Don't do anything until FWREADY updates console address */
2758 if (bus->console_addr == 0)
2759 return 0;
2760
2761 /* Read console log struct */
2762 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2763 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
2764 sizeof(c->log_le));
2765 if (rv < 0)
2766 return rv;
2767
2768 /* Allocate console buffer (one time only) */
2769 if (c->buf == NULL) {
2770 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2771 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2772 if (c->buf == NULL)
2773 return -ENOMEM;
2774 }
2775
2776 idx = le32_to_cpu(c->log_le.idx);
2777
2778 /* Protect against corrupt value */
2779 if (idx > c->bufsize)
2780 return -EBADE;
2781
2782 /* Skip reading the console buffer if the index pointer
2783 has not moved */
2784 if (idx == c->last)
2785 return 0;
2786
2787 /* Read the console buffer */
2788 addr = le32_to_cpu(c->log_le.buf);
2789 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
2790 if (rv < 0)
2791 return rv;
2792
2793 while (c->last != idx) {
2794 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2795 if (c->last == idx) {
2796 /* This would output a partial line.
2797 * Instead, back up
2798 * the buffer pointer and output this
2799 * line next time around.
2800 */
2801 if (c->last >= n)
2802 c->last -= n;
2803 else
2804 c->last = c->bufsize - n;
2805 goto break2;
2806 }
2807 ch = c->buf[c->last];
2808 c->last = (c->last + 1) % c->bufsize;
2809 if (ch == '\n')
2810 break;
2811 line[n] = ch;
2812 }
2813
2814 if (n > 0) {
2815 if (line[n - 1] == '\r')
2816 n--;
2817 line[n] = 0;
2818 pr_debug("CONSOLE: %s\n", line);
2819 }
2820 }
2821 break2:
2822
2823 return 0;
2824 }
2825 #endif /* DEBUG */
2826
2827 static int
2828 brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
2829 {
2830 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2831 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2832 struct brcmf_sdio *bus = sdiodev->bus;
2833 int ret;
2834
2835 brcmf_dbg(TRACE, "Enter\n");
2836 if (sdiodev->state != BRCMF_SDIOD_DATA)
2837 return -EIO;
2838
2839 /* Send from dpc */
2840 bus->ctrl_frame_buf = msg;
2841 bus->ctrl_frame_len = msglen;
2842 wmb();
2843 bus->ctrl_frame_stat = true;
2844
2845 brcmf_sdio_trigger_dpc(bus);
2846 wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat,
2847 CTL_DONE_TIMEOUT);
2848 ret = 0;
2849 if (bus->ctrl_frame_stat) {
2850 sdio_claim_host(bus->sdiodev->func[1]);
2851 if (bus->ctrl_frame_stat) {
2852 brcmf_dbg(SDIO, "ctrl_frame timeout\n");
2853 bus->ctrl_frame_stat = false;
2854 ret = -ETIMEDOUT;
2855 }
2856 sdio_release_host(bus->sdiodev->func[1]);
2857 }
2858 if (!ret) {
2859 brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n",
2860 bus->ctrl_frame_err);
2861 rmb();
2862 ret = bus->ctrl_frame_err;
2863 }
2864
2865 if (ret)
2866 bus->sdcnt.tx_ctlerrs++;
2867 else
2868 bus->sdcnt.tx_ctlpkts++;
2869
2870 return ret;
2871 }
2872
2873 #ifdef DEBUG
2874 static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus,
2875 struct sdpcm_shared *sh)
2876 {
2877 u32 addr, console_ptr, console_size, console_index;
2878 char *conbuf = NULL;
2879 __le32 sh_val;
2880 int rv;
2881
2882 /* obtain console information from device memory */
2883 addr = sh->console_addr + offsetof(struct rte_console, log_le);
2884 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2885 (u8 *)&sh_val, sizeof(u32));
2886 if (rv < 0)
2887 return rv;
2888 console_ptr = le32_to_cpu(sh_val);
2889
2890 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
2891 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2892 (u8 *)&sh_val, sizeof(u32));
2893 if (rv < 0)
2894 return rv;
2895 console_size = le32_to_cpu(sh_val);
2896
2897 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
2898 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2899 (u8 *)&sh_val, sizeof(u32));
2900 if (rv < 0)
2901 return rv;
2902 console_index = le32_to_cpu(sh_val);
2903
2904 /* allocate buffer for console data */
2905 if (console_size <= CONSOLE_BUFFER_MAX)
2906 conbuf = vzalloc(console_size+1);
2907
2908 if (!conbuf)
2909 return -ENOMEM;
2910
2911 /* obtain the console data from device */
2912 conbuf[console_size] = '\0';
2913 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
2914 console_size);
2915 if (rv < 0)
2916 goto done;
2917
2918 rv = seq_write(seq, conbuf + console_index,
2919 console_size - console_index);
2920 if (rv < 0)
2921 goto done;
2922
2923 if (console_index > 0)
2924 rv = seq_write(seq, conbuf, console_index - 1);
2925
2926 done:
2927 vfree(conbuf);
2928 return rv;
2929 }
2930
2931 static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus,
2932 struct sdpcm_shared *sh)
2933 {
2934 int error;
2935 struct brcmf_trap_info tr;
2936
2937 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) {
2938 brcmf_dbg(INFO, "no trap in firmware\n");
2939 return 0;
2940 }
2941
2942 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
2943 sizeof(struct brcmf_trap_info));
2944 if (error < 0)
2945 return error;
2946
2947 seq_printf(seq,
2948 "dongle trap info: type 0x%x @ epc 0x%08x\n"
2949 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
2950 " lr 0x%08x pc 0x%08x offset 0x%x\n"
2951 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
2952 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
2953 le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
2954 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
2955 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
2956 le32_to_cpu(tr.pc), sh->trap_addr,
2957 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
2958 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
2959 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
2960 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
2961
2962 return 0;
2963 }
2964
2965 static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus,
2966 struct sdpcm_shared *sh)
2967 {
2968 int error = 0;
2969 char file[80] = "?";
2970 char expr[80] = "<???>";
2971
2972 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
2973 brcmf_dbg(INFO, "firmware not built with -assert\n");
2974 return 0;
2975 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
2976 brcmf_dbg(INFO, "no assert in dongle\n");
2977 return 0;
2978 }
2979
2980 sdio_claim_host(bus->sdiodev->func[1]);
2981 if (sh->assert_file_addr != 0) {
2982 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
2983 sh->assert_file_addr, (u8 *)file, 80);
2984 if (error < 0)
2985 return error;
2986 }
2987 if (sh->assert_exp_addr != 0) {
2988 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
2989 sh->assert_exp_addr, (u8 *)expr, 80);
2990 if (error < 0)
2991 return error;
2992 }
2993 sdio_release_host(bus->sdiodev->func[1]);
2994
2995 seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n",
2996 file, sh->assert_line, expr);
2997 return 0;
2998 }
2999
3000 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3001 {
3002 int error;
3003 struct sdpcm_shared sh;
3004
3005 error = brcmf_sdio_readshared(bus, &sh);
3006
3007 if (error < 0)
3008 return error;
3009
3010 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
3011 brcmf_dbg(INFO, "firmware not built with -assert\n");
3012 else if (sh.flags & SDPCM_SHARED_ASSERT)
3013 brcmf_err("assertion in dongle\n");
3014
3015 if (sh.flags & SDPCM_SHARED_TRAP)
3016 brcmf_err("firmware trap in dongle\n");
3017
3018 return 0;
3019 }
3020
3021 static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus)
3022 {
3023 int error = 0;
3024 struct sdpcm_shared sh;
3025
3026 error = brcmf_sdio_readshared(bus, &sh);
3027 if (error < 0)
3028 goto done;
3029
3030 error = brcmf_sdio_assert_info(seq, bus, &sh);
3031 if (error < 0)
3032 goto done;
3033
3034 error = brcmf_sdio_trap_info(seq, bus, &sh);
3035 if (error < 0)
3036 goto done;
3037
3038 error = brcmf_sdio_dump_console(seq, bus, &sh);
3039
3040 done:
3041 return error;
3042 }
3043
3044 static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data)
3045 {
3046 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3047 struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus;
3048
3049 return brcmf_sdio_died_dump(seq, bus);
3050 }
3051
3052 static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data)
3053 {
3054 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3055 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3056 struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt;
3057
3058 seq_printf(seq,
3059 "intrcount: %u\nlastintrs: %u\n"
3060 "pollcnt: %u\nregfails: %u\n"
3061 "tx_sderrs: %u\nfcqueued: %u\n"
3062 "rxrtx: %u\nrx_toolong: %u\n"
3063 "rxc_errors: %u\nrx_hdrfail: %u\n"
3064 "rx_badhdr: %u\nrx_badseq: %u\n"
3065 "fc_rcvd: %u\nfc_xoff: %u\n"
3066 "fc_xon: %u\nrxglomfail: %u\n"
3067 "rxglomframes: %u\nrxglompkts: %u\n"
3068 "f2rxhdrs: %u\nf2rxdata: %u\n"
3069 "f2txdata: %u\nf1regdata: %u\n"
3070 "tickcnt: %u\ntx_ctlerrs: %lu\n"
3071 "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n"
3072 "rx_ctlpkts: %lu\nrx_readahead: %lu\n",
3073 sdcnt->intrcount, sdcnt->lastintrs,
3074 sdcnt->pollcnt, sdcnt->regfails,
3075 sdcnt->tx_sderrs, sdcnt->fcqueued,
3076 sdcnt->rxrtx, sdcnt->rx_toolong,
3077 sdcnt->rxc_errors, sdcnt->rx_hdrfail,
3078 sdcnt->rx_badhdr, sdcnt->rx_badseq,
3079 sdcnt->fc_rcvd, sdcnt->fc_xoff,
3080 sdcnt->fc_xon, sdcnt->rxglomfail,
3081 sdcnt->rxglomframes, sdcnt->rxglompkts,
3082 sdcnt->f2rxhdrs, sdcnt->f2rxdata,
3083 sdcnt->f2txdata, sdcnt->f1regdata,
3084 sdcnt->tickcnt, sdcnt->tx_ctlerrs,
3085 sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs,
3086 sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt);
3087
3088 return 0;
3089 }
3090
3091 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3092 {
3093 struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr;
3094 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
3095
3096 if (IS_ERR_OR_NULL(dentry))
3097 return;
3098
3099 bus->console_interval = BRCMF_CONSOLE;
3100
3101 brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read);
3102 brcmf_debugfs_add_entry(drvr, "counters",
3103 brcmf_debugfs_sdio_count_read);
3104 debugfs_create_u32("console_interval", 0644, dentry,
3105 &bus->console_interval);
3106 }
3107 #else
3108 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3109 {
3110 return 0;
3111 }
3112
3113 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3114 {
3115 }
3116 #endif /* DEBUG */
3117
3118 static int
3119 brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
3120 {
3121 int timeleft;
3122 uint rxlen = 0;
3123 bool pending;
3124 u8 *buf;
3125 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3126 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3127 struct brcmf_sdio *bus = sdiodev->bus;
3128
3129 brcmf_dbg(TRACE, "Enter\n");
3130 if (sdiodev->state != BRCMF_SDIOD_DATA)
3131 return -EIO;
3132
3133 /* Wait until control frame is available */
3134 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3135
3136 spin_lock_bh(&bus->rxctl_lock);
3137 rxlen = bus->rxlen;
3138 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3139 bus->rxctl = NULL;
3140 buf = bus->rxctl_orig;
3141 bus->rxctl_orig = NULL;
3142 bus->rxlen = 0;
3143 spin_unlock_bh(&bus->rxctl_lock);
3144 vfree(buf);
3145
3146 if (rxlen) {
3147 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3148 rxlen, msglen);
3149 } else if (timeleft == 0) {
3150 brcmf_err("resumed on timeout\n");
3151 brcmf_sdio_checkdied(bus);
3152 } else if (pending) {
3153 brcmf_dbg(CTL, "cancelled\n");
3154 return -ERESTARTSYS;
3155 } else {
3156 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3157 brcmf_sdio_checkdied(bus);
3158 }
3159
3160 if (rxlen)
3161 bus->sdcnt.rx_ctlpkts++;
3162 else
3163 bus->sdcnt.rx_ctlerrs++;
3164
3165 return rxlen ? (int)rxlen : -ETIMEDOUT;
3166 }
3167
3168 #ifdef DEBUG
3169 static bool
3170 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3171 u8 *ram_data, uint ram_sz)
3172 {
3173 char *ram_cmp;
3174 int err;
3175 bool ret = true;
3176 int address;
3177 int offset;
3178 int len;
3179
3180 /* read back and verify */
3181 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr,
3182 ram_sz);
3183 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL);
3184 /* do not proceed while no memory but */
3185 if (!ram_cmp)
3186 return true;
3187
3188 address = ram_addr;
3189 offset = 0;
3190 while (offset < ram_sz) {
3191 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK :
3192 ram_sz - offset;
3193 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len);
3194 if (err) {
3195 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3196 err, len, address);
3197 ret = false;
3198 break;
3199 } else if (memcmp(ram_cmp, &ram_data[offset], len)) {
3200 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n",
3201 offset, len);
3202 ret = false;
3203 break;
3204 }
3205 offset += len;
3206 address += len;
3207 }
3208
3209 kfree(ram_cmp);
3210
3211 return ret;
3212 }
3213 #else /* DEBUG */
3214 static bool
3215 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3216 u8 *ram_data, uint ram_sz)
3217 {
3218 return true;
3219 }
3220 #endif /* DEBUG */
3221
3222 static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
3223 const struct firmware *fw)
3224 {
3225 int err;
3226
3227 brcmf_dbg(TRACE, "Enter\n");
3228
3229 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase,
3230 (u8 *)fw->data, fw->size);
3231 if (err)
3232 brcmf_err("error %d on writing %d membytes at 0x%08x\n",
3233 err, (int)fw->size, bus->ci->rambase);
3234 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase,
3235 (u8 *)fw->data, fw->size))
3236 err = -EIO;
3237
3238 return err;
3239 }
3240
3241 static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus,
3242 void *vars, u32 varsz)
3243 {
3244 int address;
3245 int err;
3246
3247 brcmf_dbg(TRACE, "Enter\n");
3248
3249 address = bus->ci->ramsize - varsz + bus->ci->rambase;
3250 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz);
3251 if (err)
3252 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
3253 err, varsz, address);
3254 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz))
3255 err = -EIO;
3256
3257 return err;
3258 }
3259
3260 static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus,
3261 const struct firmware *fw,
3262 void *nvram, u32 nvlen)
3263 {
3264 int bcmerror = -EFAULT;
3265 u32 rstvec;
3266
3267 sdio_claim_host(bus->sdiodev->func[1]);
3268 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
3269
3270 rstvec = get_unaligned_le32(fw->data);
3271 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec);
3272
3273 bcmerror = brcmf_sdio_download_code_file(bus, fw);
3274 release_firmware(fw);
3275 if (bcmerror) {
3276 brcmf_err("dongle image file download failed\n");
3277 brcmf_fw_nvram_free(nvram);
3278 goto err;
3279 }
3280
3281 bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen);
3282 brcmf_fw_nvram_free(nvram);
3283 if (bcmerror) {
3284 brcmf_err("dongle nvram file download failed\n");
3285 goto err;
3286 }
3287
3288 /* Take arm out of reset */
3289 if (!brcmf_chip_set_active(bus->ci, rstvec)) {
3290 brcmf_err("error getting out of ARM core reset\n");
3291 goto err;
3292 }
3293
3294 /* Allow full data communication using DPC from now on. */
3295 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
3296 bcmerror = 0;
3297
3298 err:
3299 brcmf_sdio_clkctl(bus, CLK_SDONLY, false);
3300 sdio_release_host(bus->sdiodev->func[1]);
3301 return bcmerror;
3302 }
3303
3304 static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
3305 {
3306 int err = 0;
3307 u8 val;
3308
3309 brcmf_dbg(TRACE, "Enter\n");
3310
3311 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
3312 if (err) {
3313 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
3314 return;
3315 }
3316
3317 val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
3318 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
3319 if (err) {
3320 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
3321 return;
3322 }
3323
3324 /* Add CMD14 Support */
3325 brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
3326 (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
3327 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
3328 &err);
3329 if (err) {
3330 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
3331 return;
3332 }
3333
3334 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3335 SBSDIO_FORCE_HT, &err);
3336 if (err) {
3337 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
3338 return;
3339 }
3340
3341 /* set flag */
3342 bus->sr_enabled = true;
3343 brcmf_dbg(INFO, "SR enabled\n");
3344 }
3345
3346 /* enable KSO bit */
3347 static int brcmf_sdio_kso_init(struct brcmf_sdio *bus)
3348 {
3349 u8 val;
3350 int err = 0;
3351
3352 brcmf_dbg(TRACE, "Enter\n");
3353
3354 /* KSO bit added in SDIO core rev 12 */
3355 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12)
3356 return 0;
3357
3358 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
3359 if (err) {
3360 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
3361 return err;
3362 }
3363
3364 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
3365 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
3366 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
3367 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
3368 val, &err);
3369 if (err) {
3370 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
3371 return err;
3372 }
3373 }
3374
3375 return 0;
3376 }
3377
3378
3379 static int brcmf_sdio_bus_preinit(struct device *dev)
3380 {
3381 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3382 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3383 struct brcmf_sdio *bus = sdiodev->bus;
3384 uint pad_size;
3385 u32 value;
3386 int err;
3387
3388 /* the commands below use the terms tx and rx from
3389 * a device perspective, ie. bus:txglom affects the
3390 * bus transfers from device to host.
3391 */
3392 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) {
3393 /* for sdio core rev < 12, disable txgloming */
3394 value = 0;
3395 err = brcmf_iovar_data_set(dev, "bus:txglom", &value,
3396 sizeof(u32));
3397 } else {
3398 /* otherwise, set txglomalign */
3399 value = sdiodev->settings->bus.sdio.sd_sgentry_align;
3400 /* SDIO ADMA requires at least 32 bit alignment */
3401 value = max_t(u32, value, 4);
3402 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value,
3403 sizeof(u32));
3404 }
3405
3406 if (err < 0)
3407 goto done;
3408
3409 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
3410 if (sdiodev->sg_support) {
3411 bus->txglom = false;
3412 value = 1;
3413 pad_size = bus->sdiodev->func[2]->cur_blksize << 1;
3414 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom",
3415 &value, sizeof(u32));
3416 if (err < 0) {
3417 /* bus:rxglom is allowed to fail */
3418 err = 0;
3419 } else {
3420 bus->txglom = true;
3421 bus->tx_hdrlen += SDPCM_HWEXT_LEN;
3422 }
3423 }
3424 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen);
3425
3426 done:
3427 return err;
3428 }
3429
3430 static size_t brcmf_sdio_bus_get_ramsize(struct device *dev)
3431 {
3432 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3433 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3434 struct brcmf_sdio *bus = sdiodev->bus;
3435
3436 return bus->ci->ramsize - bus->ci->srsize;
3437 }
3438
3439 static int brcmf_sdio_bus_get_memdump(struct device *dev, void *data,
3440 size_t mem_size)
3441 {
3442 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3443 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3444 struct brcmf_sdio *bus = sdiodev->bus;
3445 int err;
3446 int address;
3447 int offset;
3448 int len;
3449
3450 brcmf_dbg(INFO, "dump at 0x%08x: size=%zu\n", bus->ci->rambase,
3451 mem_size);
3452
3453 address = bus->ci->rambase;
3454 offset = err = 0;
3455 sdio_claim_host(sdiodev->func[1]);
3456 while (offset < mem_size) {
3457 len = ((offset + MEMBLOCK) < mem_size) ? MEMBLOCK :
3458 mem_size - offset;
3459 err = brcmf_sdiod_ramrw(sdiodev, false, address, data, len);
3460 if (err) {
3461 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3462 err, len, address);
3463 goto done;
3464 }
3465 data += len;
3466 offset += len;
3467 address += len;
3468 }
3469
3470 done:
3471 sdio_release_host(sdiodev->func[1]);
3472 return err;
3473 }
3474
3475 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus)
3476 {
3477 if (!bus->dpc_triggered) {
3478 bus->dpc_triggered = true;
3479 queue_work(bus->brcmf_wq, &bus->datawork);
3480 }
3481 }
3482
3483 void brcmf_sdio_isr(struct brcmf_sdio *bus)
3484 {
3485 brcmf_dbg(TRACE, "Enter\n");
3486
3487 if (!bus) {
3488 brcmf_err("bus is null pointer, exiting\n");
3489 return;
3490 }
3491
3492 /* Count the interrupt call */
3493 bus->sdcnt.intrcount++;
3494 if (in_interrupt())
3495 atomic_set(&bus->ipend, 1);
3496 else
3497 if (brcmf_sdio_intr_rstatus(bus)) {
3498 brcmf_err("failed backplane access\n");
3499 }
3500
3501 /* Disable additional interrupts (is this needed now)? */
3502 if (!bus->intr)
3503 brcmf_err("isr w/o interrupt configured!\n");
3504
3505 bus->dpc_triggered = true;
3506 queue_work(bus->brcmf_wq, &bus->datawork);
3507 }
3508
3509 static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus)
3510 {
3511 brcmf_dbg(TIMER, "Enter\n");
3512
3513 /* Poll period: check device if appropriate. */
3514 if (!bus->sr_enabled &&
3515 bus->poll && (++bus->polltick >= bus->pollrate)) {
3516 u32 intstatus = 0;
3517
3518 /* Reset poll tick */
3519 bus->polltick = 0;
3520
3521 /* Check device if no interrupts */
3522 if (!bus->intr ||
3523 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
3524
3525 if (!bus->dpc_triggered) {
3526 u8 devpend;
3527
3528 sdio_claim_host(bus->sdiodev->func[1]);
3529 devpend = brcmf_sdiod_regrb(bus->sdiodev,
3530 SDIO_CCCR_INTx,
3531 NULL);
3532 sdio_release_host(bus->sdiodev->func[1]);
3533 intstatus = devpend & (INTR_STATUS_FUNC1 |
3534 INTR_STATUS_FUNC2);
3535 }
3536
3537 /* If there is something, make like the ISR and
3538 schedule the DPC */
3539 if (intstatus) {
3540 bus->sdcnt.pollcnt++;
3541 atomic_set(&bus->ipend, 1);
3542
3543 bus->dpc_triggered = true;
3544 queue_work(bus->brcmf_wq, &bus->datawork);
3545 }
3546 }
3547
3548 /* Update interrupt tracking */
3549 bus->sdcnt.lastintrs = bus->sdcnt.intrcount;
3550 }
3551 #ifdef DEBUG
3552 /* Poll for console output periodically */
3553 if (bus->sdiodev->state == BRCMF_SDIOD_DATA && BRCMF_FWCON_ON() &&
3554 bus->console_interval != 0) {
3555 bus->console.count += jiffies_to_msecs(BRCMF_WD_POLL);
3556 if (bus->console.count >= bus->console_interval) {
3557 bus->console.count -= bus->console_interval;
3558 sdio_claim_host(bus->sdiodev->func[1]);
3559 /* Make sure backplane clock is on */
3560 brcmf_sdio_bus_sleep(bus, false, false);
3561 if (brcmf_sdio_readconsole(bus) < 0)
3562 /* stop on error */
3563 bus->console_interval = 0;
3564 sdio_release_host(bus->sdiodev->func[1]);
3565 }
3566 }
3567 #endif /* DEBUG */
3568
3569 /* On idle timeout clear activity flag and/or turn off clock */
3570 if (!bus->dpc_triggered) {
3571 rmb();
3572 if ((!bus->dpc_running) && (bus->idletime > 0) &&
3573 (bus->clkstate == CLK_AVAIL)) {
3574 bus->idlecount++;
3575 if (bus->idlecount > bus->idletime) {
3576 brcmf_dbg(SDIO, "idle\n");
3577 sdio_claim_host(bus->sdiodev->func[1]);
3578 brcmf_sdio_wd_timer(bus, false);
3579 bus->idlecount = 0;
3580 brcmf_sdio_bus_sleep(bus, true, false);
3581 sdio_release_host(bus->sdiodev->func[1]);
3582 }
3583 } else {
3584 bus->idlecount = 0;
3585 }
3586 } else {
3587 bus->idlecount = 0;
3588 }
3589 }
3590
3591 static void brcmf_sdio_dataworker(struct work_struct *work)
3592 {
3593 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
3594 datawork);
3595
3596 bus->dpc_running = true;
3597 wmb();
3598 while (ACCESS_ONCE(bus->dpc_triggered)) {
3599 bus->dpc_triggered = false;
3600 brcmf_sdio_dpc(bus);
3601 bus->idlecount = 0;
3602 }
3603 bus->dpc_running = false;
3604 if (brcmf_sdiod_freezing(bus->sdiodev)) {
3605 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN);
3606 brcmf_sdiod_try_freeze(bus->sdiodev);
3607 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
3608 }
3609 }
3610
3611 static void
3612 brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
3613 struct brcmf_chip *ci, u32 drivestrength)
3614 {
3615 const struct sdiod_drive_str *str_tab = NULL;
3616 u32 str_mask;
3617 u32 str_shift;
3618 u32 i;
3619 u32 drivestrength_sel = 0;
3620 u32 cc_data_temp;
3621 u32 addr;
3622
3623 if (!(ci->cc_caps & CC_CAP_PMU))
3624 return;
3625
3626 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) {
3627 case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12):
3628 str_tab = sdiod_drvstr_tab1_1v8;
3629 str_mask = 0x00003800;
3630 str_shift = 11;
3631 break;
3632 case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17):
3633 str_tab = sdiod_drvstr_tab6_1v8;
3634 str_mask = 0x00001800;
3635 str_shift = 11;
3636 break;
3637 case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17):
3638 /* note: 43143 does not support tristate */
3639 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1;
3640 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) {
3641 str_tab = sdiod_drvstr_tab2_3v3;
3642 str_mask = 0x00000007;
3643 str_shift = 0;
3644 } else
3645 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n",
3646 ci->name, drivestrength);
3647 break;
3648 case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13):
3649 str_tab = sdiod_drive_strength_tab5_1v8;
3650 str_mask = 0x00003800;
3651 str_shift = 11;
3652 break;
3653 default:
3654 brcmf_err("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
3655 ci->name, ci->chiprev, ci->pmurev);
3656 break;
3657 }
3658
3659 if (str_tab != NULL) {
3660 struct brcmf_core *pmu = brcmf_chip_get_pmu(ci);
3661
3662 for (i = 0; str_tab[i].strength != 0; i++) {
3663 if (drivestrength >= str_tab[i].strength) {
3664 drivestrength_sel = str_tab[i].sel;
3665 break;
3666 }
3667 }
3668 addr = CORE_CC_REG(pmu->base, chipcontrol_addr);
3669 brcmf_sdiod_regwl(sdiodev, addr, 1, NULL);
3670 cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3671 cc_data_temp &= ~str_mask;
3672 drivestrength_sel <<= str_shift;
3673 cc_data_temp |= drivestrength_sel;
3674 brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL);
3675
3676 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
3677 str_tab[i].strength, drivestrength, cc_data_temp);
3678 }
3679 }
3680
3681 static int brcmf_sdio_buscoreprep(void *ctx)
3682 {
3683 struct brcmf_sdio_dev *sdiodev = ctx;
3684 int err = 0;
3685 u8 clkval, clkset;
3686
3687 /* Try forcing SDIO core to do ALPAvail request only */
3688 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
3689 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3690 if (err) {
3691 brcmf_err("error writing for HT off\n");
3692 return err;
3693 }
3694
3695 /* If register supported, wait for ALPAvail and then force ALP */
3696 /* This may take up to 15 milliseconds */
3697 clkval = brcmf_sdiod_regrb(sdiodev,
3698 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
3699
3700 if ((clkval & ~SBSDIO_AVBITS) != clkset) {
3701 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
3702 clkset, clkval);
3703 return -EACCES;
3704 }
3705
3706 SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev,
3707 SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
3708 !SBSDIO_ALPAV(clkval)),
3709 PMU_MAX_TRANSITION_DLY);
3710 if (!SBSDIO_ALPAV(clkval)) {
3711 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n",
3712 clkval);
3713 return -EBUSY;
3714 }
3715
3716 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
3717 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3718 udelay(65);
3719
3720 /* Also, disable the extra SDIO pull-ups */
3721 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
3722
3723 return 0;
3724 }
3725
3726 static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip,
3727 u32 rstvec)
3728 {
3729 struct brcmf_sdio_dev *sdiodev = ctx;
3730 struct brcmf_core *core;
3731 u32 reg_addr;
3732
3733 /* clear all interrupts */
3734 core = brcmf_chip_get_core(chip, BCMA_CORE_SDIO_DEV);
3735 reg_addr = core->base + offsetof(struct sdpcmd_regs, intstatus);
3736 brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
3737
3738 if (rstvec)
3739 /* Write reset vector to address 0 */
3740 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec,
3741 sizeof(rstvec));
3742 }
3743
3744 static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr)
3745 {
3746 struct brcmf_sdio_dev *sdiodev = ctx;
3747 u32 val, rev;
3748
3749 val = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3750 if (sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 &&
3751 addr == CORE_CC_REG(SI_ENUM_BASE, chipid)) {
3752 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT;
3753 if (rev >= 2) {
3754 val &= ~CID_ID_MASK;
3755 val |= BRCM_CC_4339_CHIP_ID;
3756 }
3757 }
3758 return val;
3759 }
3760
3761 static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val)
3762 {
3763 struct brcmf_sdio_dev *sdiodev = ctx;
3764
3765 brcmf_sdiod_regwl(sdiodev, addr, val, NULL);
3766 }
3767
3768 static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = {
3769 .prepare = brcmf_sdio_buscoreprep,
3770 .activate = brcmf_sdio_buscore_activate,
3771 .read32 = brcmf_sdio_buscore_read32,
3772 .write32 = brcmf_sdio_buscore_write32,
3773 };
3774
3775 static bool
3776 brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
3777 {
3778 struct brcmf_sdio_dev *sdiodev;
3779 u8 clkctl = 0;
3780 int err = 0;
3781 int reg_addr;
3782 u32 reg_val;
3783 u32 drivestrength;
3784
3785 sdiodev = bus->sdiodev;
3786 sdio_claim_host(sdiodev->func[1]);
3787
3788 pr_debug("F1 signature read @0x18000000=0x%4x\n",
3789 brcmf_sdiod_regrl(sdiodev, SI_ENUM_BASE, NULL));
3790
3791 /*
3792 * Force PLL off until brcmf_chip_attach()
3793 * programs PLL control regs
3794 */
3795
3796 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3797 BRCMF_INIT_CLKCTL1, &err);
3798 if (!err)
3799 clkctl = brcmf_sdiod_regrb(sdiodev,
3800 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3801
3802 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
3803 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
3804 err, BRCMF_INIT_CLKCTL1, clkctl);
3805 goto fail;
3806 }
3807
3808 bus->ci = brcmf_chip_attach(sdiodev, &brcmf_sdio_buscore_ops);
3809 if (IS_ERR(bus->ci)) {
3810 brcmf_err("brcmf_chip_attach failed!\n");
3811 bus->ci = NULL;
3812 goto fail;
3813 }
3814 sdiodev->settings = brcmf_get_module_param(sdiodev->dev,
3815 BRCMF_BUSTYPE_SDIO,
3816 bus->ci->chip,
3817 bus->ci->chiprev);
3818 if (!sdiodev->settings) {
3819 brcmf_err("Failed to get device parameters\n");
3820 goto fail;
3821 }
3822 /* platform specific configuration:
3823 * alignments must be at least 4 bytes for ADMA
3824 */
3825 bus->head_align = ALIGNMENT;
3826 bus->sgentry_align = ALIGNMENT;
3827 if (sdiodev->settings->bus.sdio.sd_head_align > ALIGNMENT)
3828 bus->head_align = sdiodev->settings->bus.sdio.sd_head_align;
3829 if (sdiodev->settings->bus.sdio.sd_sgentry_align > ALIGNMENT)
3830 bus->sgentry_align =
3831 sdiodev->settings->bus.sdio.sd_sgentry_align;
3832
3833 /* allocate scatter-gather table. sg support
3834 * will be disabled upon allocation failure.
3835 */
3836 brcmf_sdiod_sgtable_alloc(sdiodev);
3837
3838 #ifdef CONFIG_PM_SLEEP
3839 /* wowl can be supported when KEEP_POWER is true and (WAKE_SDIO_IRQ
3840 * is true or when platform data OOB irq is true).
3841 */
3842 if ((sdio_get_host_pm_caps(sdiodev->func[1]) & MMC_PM_KEEP_POWER) &&
3843 ((sdio_get_host_pm_caps(sdiodev->func[1]) & MMC_PM_WAKE_SDIO_IRQ) ||
3844 (sdiodev->settings->bus.sdio.oob_irq_supported)))
3845 sdiodev->bus_if->wowl_supported = true;
3846 #endif
3847
3848 if (brcmf_sdio_kso_init(bus)) {
3849 brcmf_err("error enabling KSO\n");
3850 goto fail;
3851 }
3852
3853 if (sdiodev->settings->bus.sdio.drive_strength)
3854 drivestrength = sdiodev->settings->bus.sdio.drive_strength;
3855 else
3856 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH;
3857 brcmf_sdio_drivestrengthinit(sdiodev, bus->ci, drivestrength);
3858
3859 /* Set card control so an SDIO card reset does a WLAN backplane reset */
3860 reg_val = brcmf_sdiod_regrb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err);
3861 if (err)
3862 goto fail;
3863
3864 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
3865
3866 brcmf_sdiod_regwb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
3867 if (err)
3868 goto fail;
3869
3870 /* set PMUControl so a backplane reset does PMU state reload */
3871 reg_addr = CORE_CC_REG(brcmf_chip_get_pmu(bus->ci)->base, pmucontrol);
3872 reg_val = brcmf_sdiod_regrl(sdiodev, reg_addr, &err);
3873 if (err)
3874 goto fail;
3875
3876 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
3877
3878 brcmf_sdiod_regwl(sdiodev, reg_addr, reg_val, &err);
3879 if (err)
3880 goto fail;
3881
3882 sdio_release_host(sdiodev->func[1]);
3883
3884 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
3885
3886 /* allocate header buffer */
3887 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL);
3888 if (!bus->hdrbuf)
3889 return false;
3890 /* Locate an appropriately-aligned portion of hdrbuf */
3891 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
3892 bus->head_align);
3893
3894 /* Set the poll and/or interrupt flags */
3895 bus->intr = true;
3896 bus->poll = false;
3897 if (bus->poll)
3898 bus->pollrate = 1;
3899
3900 return true;
3901
3902 fail:
3903 sdio_release_host(sdiodev->func[1]);
3904 return false;
3905 }
3906
3907 static int
3908 brcmf_sdio_watchdog_thread(void *data)
3909 {
3910 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3911 int wait;
3912
3913 allow_signal(SIGTERM);
3914 /* Run until signal received */
3915 brcmf_sdiod_freezer_count(bus->sdiodev);
3916 while (1) {
3917 if (kthread_should_stop())
3918 break;
3919 brcmf_sdiod_freezer_uncount(bus->sdiodev);
3920 wait = wait_for_completion_interruptible(&bus->watchdog_wait);
3921 brcmf_sdiod_freezer_count(bus->sdiodev);
3922 brcmf_sdiod_try_freeze(bus->sdiodev);
3923 if (!wait) {
3924 brcmf_sdio_bus_watchdog(bus);
3925 /* Count the tick for reference */
3926 bus->sdcnt.tickcnt++;
3927 reinit_completion(&bus->watchdog_wait);
3928 } else
3929 break;
3930 }
3931 return 0;
3932 }
3933
3934 static void
3935 brcmf_sdio_watchdog(unsigned long data)
3936 {
3937 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3938
3939 if (bus->watchdog_tsk) {
3940 complete(&bus->watchdog_wait);
3941 /* Reschedule the watchdog */
3942 if (bus->wd_active)
3943 mod_timer(&bus->timer,
3944 jiffies + BRCMF_WD_POLL);
3945 }
3946 }
3947
3948 static const struct brcmf_bus_ops brcmf_sdio_bus_ops = {
3949 .stop = brcmf_sdio_bus_stop,
3950 .preinit = brcmf_sdio_bus_preinit,
3951 .txdata = brcmf_sdio_bus_txdata,
3952 .txctl = brcmf_sdio_bus_txctl,
3953 .rxctl = brcmf_sdio_bus_rxctl,
3954 .gettxq = brcmf_sdio_bus_gettxq,
3955 .wowl_config = brcmf_sdio_wowl_config,
3956 .get_ramsize = brcmf_sdio_bus_get_ramsize,
3957 .get_memdump = brcmf_sdio_bus_get_memdump,
3958 };
3959
3960 static void brcmf_sdio_firmware_callback(struct device *dev,
3961 const struct firmware *code,
3962 void *nvram, u32 nvram_len)
3963 {
3964 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3965 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3966 struct brcmf_sdio *bus = sdiodev->bus;
3967 int err = 0;
3968 u8 saveclk;
3969
3970 brcmf_dbg(TRACE, "Enter: dev=%s\n", dev_name(dev));
3971
3972 if (!bus_if->drvr)
3973 return;
3974
3975 /* try to download image and nvram to the dongle */
3976 bus->alp_only = true;
3977 err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len);
3978 if (err)
3979 goto fail;
3980 bus->alp_only = false;
3981
3982 /* Start the watchdog timer */
3983 bus->sdcnt.tickcnt = 0;
3984 brcmf_sdio_wd_timer(bus, true);
3985
3986 sdio_claim_host(sdiodev->func[1]);
3987
3988 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3989 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
3990 if (bus->clkstate != CLK_AVAIL)
3991 goto release;
3992
3993 /* Force clocks on backplane to be sure F2 interrupt propagates */
3994 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, &err);
3995 if (!err) {
3996 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3997 (saveclk | SBSDIO_FORCE_HT), &err);
3998 }
3999 if (err) {
4000 brcmf_err("Failed to force clock for F2: err %d\n", err);
4001 goto release;
4002 }
4003
4004 /* Enable function 2 (frame transfers) */
4005 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
4006 offsetof(struct sdpcmd_regs, tosbmailboxdata));
4007 err = sdio_enable_func(sdiodev->func[SDIO_FUNC_2]);
4008
4009
4010 brcmf_dbg(INFO, "enable F2: err=%d\n", err);
4011
4012 /* If F2 successfully enabled, set core and enable interrupts */
4013 if (!err) {
4014 /* Set up the interrupt mask and enable interrupts */
4015 bus->hostintmask = HOSTINTMASK;
4016 w_sdreg32(bus, bus->hostintmask,
4017 offsetof(struct sdpcmd_regs, hostintmask));
4018
4019 brcmf_sdiod_regwb(sdiodev, SBSDIO_WATERMARK, 8, &err);
4020 } else {
4021 /* Disable F2 again */
4022 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
4023 goto release;
4024 }
4025
4026 if (brcmf_chip_sr_capable(bus->ci)) {
4027 brcmf_sdio_sr_init(bus);
4028 } else {
4029 /* Restore previous clock setting */
4030 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
4031 saveclk, &err);
4032 }
4033
4034 if (err == 0) {
4035 err = brcmf_sdiod_intr_register(sdiodev);
4036 if (err != 0)
4037 brcmf_err("intr register failed:%d\n", err);
4038 }
4039
4040 /* If we didn't come up, turn off backplane clock */
4041 if (err != 0)
4042 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4043
4044 sdio_release_host(sdiodev->func[1]);
4045
4046 err = brcmf_bus_start(dev);
4047 if (err != 0) {
4048 brcmf_err("dongle is not responding\n");
4049 goto fail;
4050 }
4051 return;
4052
4053 release:
4054 sdio_release_host(sdiodev->func[1]);
4055 fail:
4056 brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err);
4057 device_release_driver(dev);
4058 }
4059
4060 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
4061 {
4062 int ret;
4063 struct brcmf_sdio *bus;
4064 struct workqueue_struct *wq;
4065
4066 brcmf_dbg(TRACE, "Enter\n");
4067
4068 /* Allocate private bus interface state */
4069 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
4070 if (!bus)
4071 goto fail;
4072
4073 bus->sdiodev = sdiodev;
4074 sdiodev->bus = bus;
4075 skb_queue_head_init(&bus->glom);
4076 bus->txbound = BRCMF_TXBOUND;
4077 bus->rxbound = BRCMF_RXBOUND;
4078 bus->txminmax = BRCMF_TXMINMAX;
4079 bus->tx_seq = SDPCM_SEQ_WRAP - 1;
4080
4081 /* single-threaded workqueue */
4082 wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM,
4083 dev_name(&sdiodev->func[1]->dev));
4084 if (!wq) {
4085 brcmf_err("insufficient memory to create txworkqueue\n");
4086 goto fail;
4087 }
4088 brcmf_sdiod_freezer_count(sdiodev);
4089 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
4090 bus->brcmf_wq = wq;
4091
4092 /* attempt to attach to the dongle */
4093 if (!(brcmf_sdio_probe_attach(bus))) {
4094 brcmf_err("brcmf_sdio_probe_attach failed\n");
4095 goto fail;
4096 }
4097
4098 spin_lock_init(&bus->rxctl_lock);
4099 spin_lock_init(&bus->txq_lock);
4100 init_waitqueue_head(&bus->ctrl_wait);
4101 init_waitqueue_head(&bus->dcmd_resp_wait);
4102
4103 /* Set up the watchdog timer */
4104 init_timer(&bus->timer);
4105 bus->timer.data = (unsigned long)bus;
4106 bus->timer.function = brcmf_sdio_watchdog;
4107
4108 /* Initialize watchdog thread */
4109 init_completion(&bus->watchdog_wait);
4110 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread,
4111 bus, "brcmf_wdog/%s",
4112 dev_name(&sdiodev->func[1]->dev));
4113 if (IS_ERR(bus->watchdog_tsk)) {
4114 pr_warn("brcmf_watchdog thread failed to start\n");
4115 bus->watchdog_tsk = NULL;
4116 }
4117 /* Initialize DPC thread */
4118 bus->dpc_triggered = false;
4119 bus->dpc_running = false;
4120
4121 /* Assign bus interface call back */
4122 bus->sdiodev->bus_if->dev = bus->sdiodev->dev;
4123 bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops;
4124 bus->sdiodev->bus_if->chip = bus->ci->chip;
4125 bus->sdiodev->bus_if->chiprev = bus->ci->chiprev;
4126
4127 /* default sdio bus header length for tx packet */
4128 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
4129
4130 /* Attach to the common layer, reserve hdr space */
4131 ret = brcmf_attach(bus->sdiodev->dev, bus->sdiodev->settings);
4132 if (ret != 0) {
4133 brcmf_err("brcmf_attach failed\n");
4134 goto fail;
4135 }
4136
4137 /* allocate scatter-gather table. sg support
4138 * will be disabled upon allocation failure.
4139 */
4140 brcmf_sdiod_sgtable_alloc(bus->sdiodev);
4141
4142 /* Query the F2 block size, set roundup accordingly */
4143 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
4144 bus->roundup = min(max_roundup, bus->blocksize);
4145
4146 /* Allocate buffers */
4147 if (bus->sdiodev->bus_if->maxctl) {
4148 bus->sdiodev->bus_if->maxctl += bus->roundup;
4149 bus->rxblen =
4150 roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
4151 ALIGNMENT) + bus->head_align;
4152 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
4153 if (!(bus->rxbuf)) {
4154 brcmf_err("rxbuf allocation failed\n");
4155 goto fail;
4156 }
4157 }
4158
4159 sdio_claim_host(bus->sdiodev->func[1]);
4160
4161 /* Disable F2 to clear any intermediate frame state on the dongle */
4162 sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]);
4163
4164 bus->rxflow = false;
4165
4166 /* Done with backplane-dependent accesses, can drop clock... */
4167 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4168
4169 sdio_release_host(bus->sdiodev->func[1]);
4170
4171 /* ...and initialize clock/power states */
4172 bus->clkstate = CLK_SDONLY;
4173 bus->idletime = BRCMF_IDLE_INTERVAL;
4174 bus->idleclock = BRCMF_IDLE_ACTIVE;
4175
4176 /* SR state */
4177 bus->sr_enabled = false;
4178
4179 brcmf_sdio_debugfs_create(bus);
4180 brcmf_dbg(INFO, "completed!!\n");
4181
4182 ret = brcmf_fw_map_chip_to_name(bus->ci->chip, bus->ci->chiprev,
4183 brcmf_sdio_fwnames,
4184 ARRAY_SIZE(brcmf_sdio_fwnames),
4185 sdiodev->fw_name, sdiodev->nvram_name);
4186 if (ret)
4187 goto fail;
4188
4189 ret = brcmf_fw_get_firmwares(sdiodev->dev, BRCMF_FW_REQUEST_NVRAM,
4190 sdiodev->fw_name, sdiodev->nvram_name,
4191 brcmf_sdio_firmware_callback);
4192 if (ret != 0) {
4193 brcmf_err("async firmware request failed: %d\n", ret);
4194 goto fail;
4195 }
4196
4197 return bus;
4198
4199 fail:
4200 brcmf_sdio_remove(bus);
4201 return NULL;
4202 }
4203
4204 /* Detach and free everything */
4205 void brcmf_sdio_remove(struct brcmf_sdio *bus)
4206 {
4207 brcmf_dbg(TRACE, "Enter\n");
4208
4209 if (bus) {
4210 /* De-register interrupt handler */
4211 brcmf_sdiod_intr_unregister(bus->sdiodev);
4212
4213 brcmf_detach(bus->sdiodev->dev);
4214
4215 cancel_work_sync(&bus->datawork);
4216 if (bus->brcmf_wq)
4217 destroy_workqueue(bus->brcmf_wq);
4218
4219 if (bus->ci) {
4220 if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
4221 sdio_claim_host(bus->sdiodev->func[1]);
4222 brcmf_sdio_wd_timer(bus, false);
4223 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4224 /* Leave the device in state where it is
4225 * 'passive'. This is done by resetting all
4226 * necessary cores.
4227 */
4228 msleep(20);
4229 brcmf_chip_set_passive(bus->ci);
4230 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4231 sdio_release_host(bus->sdiodev->func[1]);
4232 }
4233 brcmf_chip_detach(bus->ci);
4234 }
4235 if (bus->sdiodev->settings)
4236 brcmf_release_module_param(bus->sdiodev->settings);
4237
4238 kfree(bus->rxbuf);
4239 kfree(bus->hdrbuf);
4240 kfree(bus);
4241 }
4242
4243 brcmf_dbg(TRACE, "Disconnected\n");
4244 }
4245
4246 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active)
4247 {
4248 /* Totally stop the timer */
4249 if (!active && bus->wd_active) {
4250 del_timer_sync(&bus->timer);
4251 bus->wd_active = false;
4252 return;
4253 }
4254
4255 /* don't start the wd until fw is loaded */
4256 if (bus->sdiodev->state != BRCMF_SDIOD_DATA)
4257 return;
4258
4259 if (active) {
4260 if (!bus->wd_active) {
4261 /* Create timer again when watchdog period is
4262 dynamically changed or in the first instance
4263 */
4264 bus->timer.expires = jiffies + BRCMF_WD_POLL;
4265 add_timer(&bus->timer);
4266 bus->wd_active = true;
4267 } else {
4268 /* Re arm the timer, at last watchdog period */
4269 mod_timer(&bus->timer, jiffies + BRCMF_WD_POLL);
4270 }
4271 }
4272 }
4273
4274 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep)
4275 {
4276 int ret;
4277
4278 sdio_claim_host(bus->sdiodev->func[1]);
4279 ret = brcmf_sdio_bus_sleep(bus, sleep, false);
4280 sdio_release_host(bus->sdiodev->func[1]);
4281
4282 return ret;
4283 }
4284
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