drivers/net/wireless/cw1200/hwio.c

   1 /*
   2  * Low-level device IO routines for ST-Ericsson CW1200 drivers
   3  *
   4  * Copyright (c) 2010, ST-Ericsson
   5  * Author: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
   6  *
   7  * Based on:
   8  * ST-Ericsson UMAC CW1200 driver, which is
   9  * Copyright (c) 2010, ST-Ericsson
  10  * Author: Ajitpal Singh <ajitpal.singh@lockless.no>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include <linux/types.h>
  18
  19 #include "cw1200.h"
  20 #include "hwio.h"
  21 #include "sbus.h"
  22
  23  /* Sdio addr is 4*spi_addr */
  24 #define SPI_REG_ADDR_TO_SDIO(spi_reg_addr) ((spi_reg_addr) << 2)
  25 #define SDIO_ADDR17BIT(buf_id, mpf, rfu, reg_id_ofs) \
  26                                 ((((buf_id)    & 0x1F) << 7) \
  27                                 | (((mpf)        & 1) << 6) \
  28                                 | (((rfu)        & 1) << 5) \
  29                                 | (((reg_id_ofs) & 0x1F) << 0))
  30 #define MAX_RETRY               3
  31
  32
  33 static int __cw1200_reg_read(struct cw1200_common *priv, u16 addr,
  34                              void *buf, size_t buf_len, int buf_id)
  35 {
  36         u16 addr_sdio;
  37         u32 sdio_reg_addr_17bit;
  38
  39         /* Check if buffer is aligned to 4 byte boundary */
  40         if (WARN_ON(((unsigned long)buf & 3) && (buf_len > 4))) {
  41                 pr_err("buffer is not aligned.\n");
  42                 return -EINVAL;
  43         }
  44
  45         /* Convert to SDIO Register Address */
  46         addr_sdio = SPI_REG_ADDR_TO_SDIO(addr);
  47         sdio_reg_addr_17bit = SDIO_ADDR17BIT(buf_id, 0, 0, addr_sdio);
  48
  49         return priv->sbus_ops->sbus_memcpy_fromio(priv->sbus_priv,
  50                                                   sdio_reg_addr_17bit,
  51                                                   buf, buf_len);
  52 }
  53
  54 static int __cw1200_reg_write(struct cw1200_common *priv, u16 addr,
  55                                 const void *buf, size_t buf_len, int buf_id)
  56 {
  57         u16 addr_sdio;
  58         u32 sdio_reg_addr_17bit;
  59
  60         /* Convert to SDIO Register Address */
  61         addr_sdio = SPI_REG_ADDR_TO_SDIO(addr);
  62         sdio_reg_addr_17bit = SDIO_ADDR17BIT(buf_id, 0, 0, addr_sdio);
  63
  64         return priv->sbus_ops->sbus_memcpy_toio(priv->sbus_priv,
  65                                                 sdio_reg_addr_17bit,
  66                                                 buf, buf_len);
  67 }
  68
  69 static inline int __cw1200_reg_read_32(struct cw1200_common *priv,
  70                                         u16 addr, u32 *val)
  71 {
  72         int i = __cw1200_reg_read(priv, addr, val, sizeof(*val), 0);
  73         *val = le32_to_cpu(*val);
  74         return i;
  75 }
  76
  77 static inline int __cw1200_reg_write_32(struct cw1200_common *priv,
  78                                         u16 addr, u32 val)
  79 {
  80         val = cpu_to_le32(val);
  81         return __cw1200_reg_write(priv, addr, &val, sizeof(val), 0);
  82 }
  83
  84 static inline int __cw1200_reg_read_16(struct cw1200_common *priv,
  85                                         u16 addr, u16 *val)
  86 {
  87         int i = __cw1200_reg_read(priv, addr, val, sizeof(*val), 0);
  88         *val = le16_to_cpu(*val);
  89         return i;
  90 }
  91
  92 static inline int __cw1200_reg_write_16(struct cw1200_common *priv,
  93                                         u16 addr, u16 val)
  94 {
  95         val = cpu_to_le16(val);
  96         return __cw1200_reg_write(priv, addr, &val, sizeof(val), 0);
  97 }
  98
  99 int cw1200_reg_read(struct cw1200_common *priv, u16 addr, void *buf,
 100                         size_t buf_len)
 101 {
 102         int ret;
 103         priv->sbus_ops->lock(priv->sbus_priv);
 104         ret = __cw1200_reg_read(priv, addr, buf, buf_len, 0);
 105         priv->sbus_ops->unlock(priv->sbus_priv);
 106         return ret;
 107 }
 108
 109 int cw1200_reg_write(struct cw1200_common *priv, u16 addr, const void *buf,
 110                         size_t buf_len)
 111 {
 112         int ret;
 113         priv->sbus_ops->lock(priv->sbus_priv);
 114         ret = __cw1200_reg_write(priv, addr, buf, buf_len, 0);
 115         priv->sbus_ops->unlock(priv->sbus_priv);
 116         return ret;
 117 }
 118
 119 int cw1200_data_read(struct cw1200_common *priv, void *buf, size_t buf_len)
 120 {
 121         int ret, retry = 1;
 122         int buf_id_rx = priv->buf_id_rx;
 123
 124         priv->sbus_ops->lock(priv->sbus_priv);
 125
 126         while (retry <= MAX_RETRY) {
 127                 ret = __cw1200_reg_read(priv,
 128                                         ST90TDS_IN_OUT_QUEUE_REG_ID, buf,
 129                                         buf_len, buf_id_rx + 1);
 130                 if (!ret) {
 131                         buf_id_rx = (buf_id_rx + 1) & 3;
 132                         priv->buf_id_rx = buf_id_rx;
 133                         break;
 134                 } else {
 135                         retry++;
 136                         mdelay(1);
 137                         pr_err("error :[%d]\n", ret);
 138                 }
 139         }
 140
 141         priv->sbus_ops->unlock(priv->sbus_priv);
 142         return ret;
 143 }
 144
 145 int cw1200_data_write(struct cw1200_common *priv, const void *buf,
 146                         size_t buf_len)
 147 {
 148         int ret, retry = 1;
 149         int buf_id_tx = priv->buf_id_tx;
 150
 151         priv->sbus_ops->lock(priv->sbus_priv);
 152
 153         while (retry <= MAX_RETRY) {
 154                 ret = __cw1200_reg_write(priv,
 155                                          ST90TDS_IN_OUT_QUEUE_REG_ID, buf,
 156                                          buf_len, buf_id_tx);
 157                 if (!ret) {
 158                         buf_id_tx = (buf_id_tx + 1) & 31;
 159                         priv->buf_id_tx = buf_id_tx;
 160                         break;
 161                 } else {
 162                         retry++;
 163                         mdelay(1);
 164                         pr_err("error :[%d]\n", ret);
 165                 }
 166         }
 167
 168         priv->sbus_ops->unlock(priv->sbus_priv);
 169         return ret;
 170 }
 171
 172 int cw1200_indirect_read(struct cw1200_common *priv, u32 addr, void *buf,
 173                          size_t buf_len, u32 prefetch, u16 port_addr)
 174 {
 175         u32 val32 = 0;
 176         int i, ret;
 177
 178         if ((buf_len / 2) >= 0x1000) {
 179                 pr_err("Can't read more than 0xfff words.\n");
 180                 return -EINVAL;
 181                 goto out;
 182         }
 183
 184         priv->sbus_ops->lock(priv->sbus_priv);
 185         /* Write address */
 186         ret = __cw1200_reg_write_32(priv, ST90TDS_SRAM_BASE_ADDR_REG_ID, addr);
 187         if (ret < 0) {
 188                 pr_err("Can't write address register.\n");
 189                 goto out;
 190         }
 191
 192         /* Read CONFIG Register Value - We will read 32 bits */
 193         ret = __cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32);
 194         if (ret < 0) {
 195                 pr_err("Can't read config register.\n");
 196                 goto out;
 197         }
 198
 199         /* Set PREFETCH bit */
 200         ret = __cw1200_reg_write_32(priv, ST90TDS_CONFIG_REG_ID,
 201                                         val32 | prefetch);
 202         if (ret < 0) {
 203                 pr_err("Can't write prefetch bit.\n");
 204                 goto out;
 205         }
 206
 207         /* Check for PRE-FETCH bit to be cleared */
 208         for (i = 0; i < 20; i++) {
 209                 ret = __cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32);
 210                 if (ret < 0) {
 211                         pr_err("Can't check prefetch bit.\n");
 212                         goto out;
 213                 }
 214                 if (!(val32 & prefetch))
 215                         break;
 216
 217                 mdelay(i);
 218         }
 219
 220         if (val32 & prefetch) {
 221                 pr_err("Prefetch bit is not cleared.\n");
 222                 goto out;
 223         }
 224
 225         /* Read data port */
 226         ret = __cw1200_reg_read(priv, port_addr, buf, buf_len, 0);
 227         if (ret < 0) {
 228                 pr_err("Can't read data port.\n");
 229                 goto out;
 230         }
 231
 232 out:
 233         priv->sbus_ops->unlock(priv->sbus_priv);
 234         return ret;
 235 }
 236
 237 int cw1200_apb_write(struct cw1200_common *priv, u32 addr, const void *buf,
 238                         size_t buf_len)
 239 {
 240         int ret;
 241
 242         if ((buf_len / 2) >= 0x1000) {
 243                 pr_err("Can't write more than 0xfff words.\n");
 244                 return -EINVAL;
 245         }
 246
 247         priv->sbus_ops->lock(priv->sbus_priv);
 248
 249         /* Write address */
 250         ret = __cw1200_reg_write_32(priv, ST90TDS_SRAM_BASE_ADDR_REG_ID, addr);
 251         if (ret < 0) {
 252                 pr_err("Can't write address register.\n");
 253                 goto out;
 254         }
 255
 256         /* Write data port */
 257         ret = __cw1200_reg_write(priv, ST90TDS_SRAM_DPORT_REG_ID,
 258                                         buf, buf_len, 0);
 259         if (ret < 0) {
 260                 pr_err("Can't write data port.\n");
 261                 goto out;
 262         }
 263
 264 out:
 265         priv->sbus_ops->unlock(priv->sbus_priv);
 266         return ret;
 267 }
 268
 269 int __cw1200_irq_enable(struct cw1200_common *priv, int enable)
 270 {
 271         u32 val32;
 272         u16 val16;
 273         int ret;
 274
 275         if (HIF_8601_SILICON == priv->hw_type) {
 276                 ret = __cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32);
 277                 if (ret < 0) {
 278                         pr_err("Can't read config register.\n");
 279                         return ret;
 280                 }
 281
 282                 if (enable)
 283                         val32 |= ST90TDS_CONF_IRQ_RDY_ENABLE;
 284                 else
 285                         val32 &= ~ST90TDS_CONF_IRQ_RDY_ENABLE;
 286
 287                 ret = __cw1200_reg_write_32(priv, ST90TDS_CONFIG_REG_ID, val32);
 288                 if (ret < 0) {
 289                         pr_err("Can't write config register.\n");
 290                         return ret;
 291                 }
 292         } else {
 293                 ret = __cw1200_reg_read_16(priv, ST90TDS_CONFIG_REG_ID, &val16);
 294                 if (ret < 0) {
 295                         pr_err("Can't read control register.\n");
 296                         return ret;
 297                 }
 298
 299                 if (enable)
 300                         val16 |= ST90TDS_CONT_IRQ_RDY_ENABLE;
 301                 else
 302                         val16 &= ~ST90TDS_CONT_IRQ_RDY_ENABLE;
 303
 304                 ret = __cw1200_reg_write_16(priv, ST90TDS_CONFIG_REG_ID, val16);
 305                 if (ret < 0) {
 306                         pr_err("Can't write control register.\n");
 307                         return ret;
 308                 }
 309         }
 310         return 0;
 311 }