]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blob - drivers/net/wireless/intel/iwlwifi/fw/dbg.c
projects / mirror_ubuntu-jammy-kernel.git / blob
? search:


4d3687cc83a4dc71e3b6d4cc959a822d5bb88141
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / intel / iwlwifi / fw / dbg.c
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
11 * Copyright(c) 2018 - 2020 Intel Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * The full GNU General Public License is included in this distribution
23 * in the file called COPYING.
24 *
25 * Contact Information:
26 * Intel Linux Wireless <linuxwifi@intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *
29 * BSD LICENSE
30 *
31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
33 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
34 * Copyright(c) 2018 - 2020 Intel Corporation
35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 *
41 * * Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * * Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in
45 * the documentation and/or other materials provided with the
46 * distribution.
47 * * Neither the name Intel Corporation nor the names of its
48 * contributors may be used to endorse or promote products derived
49 * from this software without specific prior written permission.
50 *
51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *
63 *****************************************************************************/
64 #include <linux/devcoredump.h>
65 #include "iwl-drv.h"
66 #include "runtime.h"
67 #include "dbg.h"
68 #include "debugfs.h"
69 #include "iwl-io.h"
70 #include "iwl-prph.h"
71 #include "iwl-csr.h"
72
73 /**
74 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump
75 *
76 * @fwrt_ptr: pointer to the buffer coming from fwrt
77 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the
78 * transport's data.
79 * @trans_len: length of the valid data in trans_ptr
80 * @fwrt_len: length of the valid data in fwrt_ptr
81 */
82 struct iwl_fw_dump_ptrs {
83 struct iwl_trans_dump_data *trans_ptr;
84 void *fwrt_ptr;
85 u32 fwrt_len;
86 };
87
88 #define RADIO_REG_MAX_READ 0x2ad
89 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt,
90 struct iwl_fw_error_dump_data **dump_data)
91 {
92 u8 *pos = (void *)(*dump_data)->data;
93 unsigned long flags;
94 int i;
95
96 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n");
97
98 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
99 return;
100
101 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG);
102 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ);
103
104 for (i = 0; i < RADIO_REG_MAX_READ; i++) {
105 u32 rd_cmd = RADIO_RSP_RD_CMD;
106
107 rd_cmd |= i << RADIO_RSP_ADDR_POS;
108 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd);
109 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT);
110
111 pos++;
112 }
113
114 *dump_data = iwl_fw_error_next_data(*dump_data);
115
116 iwl_trans_release_nic_access(fwrt->trans, &flags);
117 }
118
119 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt,
120 struct iwl_fw_error_dump_data **dump_data,
121 int size, u32 offset, int fifo_num)
122 {
123 struct iwl_fw_error_dump_fifo *fifo_hdr;
124 u32 *fifo_data;
125 u32 fifo_len;
126 int i;
127
128 fifo_hdr = (void *)(*dump_data)->data;
129 fifo_data = (void *)fifo_hdr->data;
130 fifo_len = size;
131
132 /* No need to try to read the data if the length is 0 */
133 if (fifo_len == 0)
134 return;
135
136 /* Add a TLV for the RXF */
137 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF);
138 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
139
140 fifo_hdr->fifo_num = cpu_to_le32(fifo_num);
141 fifo_hdr->available_bytes =
142 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
143 RXF_RD_D_SPACE + offset));
144 fifo_hdr->wr_ptr =
145 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
146 RXF_RD_WR_PTR + offset));
147 fifo_hdr->rd_ptr =
148 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
149 RXF_RD_RD_PTR + offset));
150 fifo_hdr->fence_ptr =
151 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
152 RXF_RD_FENCE_PTR + offset));
153 fifo_hdr->fence_mode =
154 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
155 RXF_SET_FENCE_MODE + offset));
156
157 /* Lock fence */
158 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1);
159 /* Set fence pointer to the same place like WR pointer */
160 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1);
161 /* Set fence offset */
162 iwl_trans_write_prph(fwrt->trans,
163 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0);
164
165 /* Read FIFO */
166 fifo_len /= sizeof(u32); /* Size in DWORDS */
167 for (i = 0; i < fifo_len; i++)
168 fifo_data[i] = iwl_trans_read_prph(fwrt->trans,
169 RXF_FIFO_RD_FENCE_INC +
170 offset);
171 *dump_data = iwl_fw_error_next_data(*dump_data);
172 }
173
174 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt,
175 struct iwl_fw_error_dump_data **dump_data,
176 int size, u32 offset, int fifo_num)
177 {
178 struct iwl_fw_error_dump_fifo *fifo_hdr;
179 u32 *fifo_data;
180 u32 fifo_len;
181 int i;
182
183 fifo_hdr = (void *)(*dump_data)->data;
184 fifo_data = (void *)fifo_hdr->data;
185 fifo_len = size;
186
187 /* No need to try to read the data if the length is 0 */
188 if (fifo_len == 0)
189 return;
190
191 /* Add a TLV for the FIFO */
192 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF);
193 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
194
195 fifo_hdr->fifo_num = cpu_to_le32(fifo_num);
196 fifo_hdr->available_bytes =
197 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
198 TXF_FIFO_ITEM_CNT + offset));
199 fifo_hdr->wr_ptr =
200 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
201 TXF_WR_PTR + offset));
202 fifo_hdr->rd_ptr =
203 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
204 TXF_RD_PTR + offset));
205 fifo_hdr->fence_ptr =
206 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
207 TXF_FENCE_PTR + offset));
208 fifo_hdr->fence_mode =
209 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
210 TXF_LOCK_FENCE + offset));
211
212 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */
213 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset,
214 TXF_WR_PTR + offset);
215
216 /* Dummy-read to advance the read pointer to the head */
217 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset);
218
219 /* Read FIFO */
220 fifo_len /= sizeof(u32); /* Size in DWORDS */
221 for (i = 0; i < fifo_len; i++)
222 fifo_data[i] = iwl_trans_read_prph(fwrt->trans,
223 TXF_READ_MODIFY_DATA +
224 offset);
225 *dump_data = iwl_fw_error_next_data(*dump_data);
226 }
227
228 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt,
229 struct iwl_fw_error_dump_data **dump_data)
230 {
231 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
232 unsigned long flags;
233
234 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n");
235
236 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
237 return;
238
239 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) {
240 /* Pull RXF1 */
241 iwl_fwrt_dump_rxf(fwrt, dump_data,
242 cfg->lmac[0].rxfifo1_size, 0, 0);
243 /* Pull RXF2 */
244 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size,
245 RXF_DIFF_FROM_PREV +
246 fwrt->trans->trans_cfg->umac_prph_offset, 1);
247 /* Pull LMAC2 RXF1 */
248 if (fwrt->smem_cfg.num_lmacs > 1)
249 iwl_fwrt_dump_rxf(fwrt, dump_data,
250 cfg->lmac[1].rxfifo1_size,
251 LMAC2_PRPH_OFFSET, 2);
252 }
253
254 iwl_trans_release_nic_access(fwrt->trans, &flags);
255 }
256
257 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt,
258 struct iwl_fw_error_dump_data **dump_data)
259 {
260 struct iwl_fw_error_dump_fifo *fifo_hdr;
261 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
262 u32 *fifo_data;
263 u32 fifo_len;
264 unsigned long flags;
265 int i, j;
266
267 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n");
268
269 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
270 return;
271
272 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) {
273 /* Pull TXF data from LMAC1 */
274 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) {
275 /* Mark the number of TXF we're pulling now */
276 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i);
277 iwl_fwrt_dump_txf(fwrt, dump_data,
278 cfg->lmac[0].txfifo_size[i], 0, i);
279 }
280
281 /* Pull TXF data from LMAC2 */
282 if (fwrt->smem_cfg.num_lmacs > 1) {
283 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries;
284 i++) {
285 /* Mark the number of TXF we're pulling now */
286 iwl_trans_write_prph(fwrt->trans,
287 TXF_LARC_NUM +
288 LMAC2_PRPH_OFFSET, i);
289 iwl_fwrt_dump_txf(fwrt, dump_data,
290 cfg->lmac[1].txfifo_size[i],
291 LMAC2_PRPH_OFFSET,
292 i + cfg->num_txfifo_entries);
293 }
294 }
295 }
296
297 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) &&
298 fw_has_capa(&fwrt->fw->ucode_capa,
299 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) {
300 /* Pull UMAC internal TXF data from all TXFs */
301 for (i = 0;
302 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size);
303 i++) {
304 fifo_hdr = (void *)(*dump_data)->data;
305 fifo_data = (void *)fifo_hdr->data;
306 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i];
307
308 /* No need to try to read the data if the length is 0 */
309 if (fifo_len == 0)
310 continue;
311
312 /* Add a TLV for the internal FIFOs */
313 (*dump_data)->type =
314 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF);
315 (*dump_data)->len =
316 cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
317
318 fifo_hdr->fifo_num = cpu_to_le32(i);
319
320 /* Mark the number of TXF we're pulling now */
321 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i +
322 fwrt->smem_cfg.num_txfifo_entries);
323
324 fifo_hdr->available_bytes =
325 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
326 TXF_CPU2_FIFO_ITEM_CNT));
327 fifo_hdr->wr_ptr =
328 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
329 TXF_CPU2_WR_PTR));
330 fifo_hdr->rd_ptr =
331 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
332 TXF_CPU2_RD_PTR));
333 fifo_hdr->fence_ptr =
334 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
335 TXF_CPU2_FENCE_PTR));
336 fifo_hdr->fence_mode =
337 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
338 TXF_CPU2_LOCK_FENCE));
339
340 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */
341 iwl_trans_write_prph(fwrt->trans,
342 TXF_CPU2_READ_MODIFY_ADDR,
343 TXF_CPU2_WR_PTR);
344
345 /* Dummy-read to advance the read pointer to head */
346 iwl_trans_read_prph(fwrt->trans,
347 TXF_CPU2_READ_MODIFY_DATA);
348
349 /* Read FIFO */
350 fifo_len /= sizeof(u32); /* Size in DWORDS */
351 for (j = 0; j < fifo_len; j++)
352 fifo_data[j] =
353 iwl_trans_read_prph(fwrt->trans,
354 TXF_CPU2_READ_MODIFY_DATA);
355 *dump_data = iwl_fw_error_next_data(*dump_data);
356 }
357 }
358
359 iwl_trans_release_nic_access(fwrt->trans, &flags);
360 }
361
362 #define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */
363 #define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */
364
365 struct iwl_prph_range {
366 u32 start, end;
367 };
368
369 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = {
370 { .start = 0x00a00000, .end = 0x00a00000 },
371 { .start = 0x00a0000c, .end = 0x00a00024 },
372 { .start = 0x00a0002c, .end = 0x00a0003c },
373 { .start = 0x00a00410, .end = 0x00a00418 },
374 { .start = 0x00a00420, .end = 0x00a00420 },
375 { .start = 0x00a00428, .end = 0x00a00428 },
376 { .start = 0x00a00430, .end = 0x00a0043c },
377 { .start = 0x00a00444, .end = 0x00a00444 },
378 { .start = 0x00a004c0, .end = 0x00a004cc },
379 { .start = 0x00a004d8, .end = 0x00a004d8 },
380 { .start = 0x00a004e0, .end = 0x00a004f0 },
381 { .start = 0x00a00840, .end = 0x00a00840 },
382 { .start = 0x00a00850, .end = 0x00a00858 },
383 { .start = 0x00a01004, .end = 0x00a01008 },
384 { .start = 0x00a01010, .end = 0x00a01010 },
385 { .start = 0x00a01018, .end = 0x00a01018 },
386 { .start = 0x00a01024, .end = 0x00a01024 },
387 { .start = 0x00a0102c, .end = 0x00a01034 },
388 { .start = 0x00a0103c, .end = 0x00a01040 },
389 { .start = 0x00a01048, .end = 0x00a01094 },
390 { .start = 0x00a01c00, .end = 0x00a01c20 },
391 { .start = 0x00a01c58, .end = 0x00a01c58 },
392 { .start = 0x00a01c7c, .end = 0x00a01c7c },
393 { .start = 0x00a01c28, .end = 0x00a01c54 },
394 { .start = 0x00a01c5c, .end = 0x00a01c5c },
395 { .start = 0x00a01c60, .end = 0x00a01cdc },
396 { .start = 0x00a01ce0, .end = 0x00a01d0c },
397 { .start = 0x00a01d18, .end = 0x00a01d20 },
398 { .start = 0x00a01d2c, .end = 0x00a01d30 },
399 { .start = 0x00a01d40, .end = 0x00a01d5c },
400 { .start = 0x00a01d80, .end = 0x00a01d80 },
401 { .start = 0x00a01d98, .end = 0x00a01d9c },
402 { .start = 0x00a01da8, .end = 0x00a01da8 },
403 { .start = 0x00a01db8, .end = 0x00a01df4 },
404 { .start = 0x00a01dc0, .end = 0x00a01dfc },
405 { .start = 0x00a01e00, .end = 0x00a01e2c },
406 { .start = 0x00a01e40, .end = 0x00a01e60 },
407 { .start = 0x00a01e68, .end = 0x00a01e6c },
408 { .start = 0x00a01e74, .end = 0x00a01e74 },
409 { .start = 0x00a01e84, .end = 0x00a01e90 },
410 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
411 { .start = 0x00a01ed0, .end = 0x00a01ee0 },
412 { .start = 0x00a01f00, .end = 0x00a01f1c },
413 { .start = 0x00a01f44, .end = 0x00a01ffc },
414 { .start = 0x00a02000, .end = 0x00a02048 },
415 { .start = 0x00a02068, .end = 0x00a020f0 },
416 { .start = 0x00a02100, .end = 0x00a02118 },
417 { .start = 0x00a02140, .end = 0x00a0214c },
418 { .start = 0x00a02168, .end = 0x00a0218c },
419 { .start = 0x00a021c0, .end = 0x00a021c0 },
420 { .start = 0x00a02400, .end = 0x00a02410 },
421 { .start = 0x00a02418, .end = 0x00a02420 },
422 { .start = 0x00a02428, .end = 0x00a0242c },
423 { .start = 0x00a02434, .end = 0x00a02434 },
424 { .start = 0x00a02440, .end = 0x00a02460 },
425 { .start = 0x00a02468, .end = 0x00a024b0 },
426 { .start = 0x00a024c8, .end = 0x00a024cc },
427 { .start = 0x00a02500, .end = 0x00a02504 },
428 { .start = 0x00a0250c, .end = 0x00a02510 },
429 { .start = 0x00a02540, .end = 0x00a02554 },
430 { .start = 0x00a02580, .end = 0x00a025f4 },
431 { .start = 0x00a02600, .end = 0x00a0260c },
432 { .start = 0x00a02648, .end = 0x00a02650 },
433 { .start = 0x00a02680, .end = 0x00a02680 },
434 { .start = 0x00a026c0, .end = 0x00a026d0 },
435 { .start = 0x00a02700, .end = 0x00a0270c },
436 { .start = 0x00a02804, .end = 0x00a02804 },
437 { .start = 0x00a02818, .end = 0x00a0281c },
438 { .start = 0x00a02c00, .end = 0x00a02db4 },
439 { .start = 0x00a02df4, .end = 0x00a02fb0 },
440 { .start = 0x00a03000, .end = 0x00a03014 },
441 { .start = 0x00a0301c, .end = 0x00a0302c },
442 { .start = 0x00a03034, .end = 0x00a03038 },
443 { .start = 0x00a03040, .end = 0x00a03048 },
444 { .start = 0x00a03060, .end = 0x00a03068 },
445 { .start = 0x00a03070, .end = 0x00a03074 },
446 { .start = 0x00a0307c, .end = 0x00a0307c },
447 { .start = 0x00a03080, .end = 0x00a03084 },
448 { .start = 0x00a0308c, .end = 0x00a03090 },
449 { .start = 0x00a03098, .end = 0x00a03098 },
450 { .start = 0x00a030a0, .end = 0x00a030a0 },
451 { .start = 0x00a030a8, .end = 0x00a030b4 },
452 { .start = 0x00a030bc, .end = 0x00a030bc },
453 { .start = 0x00a030c0, .end = 0x00a0312c },
454 { .start = 0x00a03c00, .end = 0x00a03c5c },
455 { .start = 0x00a04400, .end = 0x00a04454 },
456 { .start = 0x00a04460, .end = 0x00a04474 },
457 { .start = 0x00a044c0, .end = 0x00a044ec },
458 { .start = 0x00a04500, .end = 0x00a04504 },
459 { .start = 0x00a04510, .end = 0x00a04538 },
460 { .start = 0x00a04540, .end = 0x00a04548 },
461 { .start = 0x00a04560, .end = 0x00a0457c },
462 { .start = 0x00a04590, .end = 0x00a04598 },
463 { .start = 0x00a045c0, .end = 0x00a045f4 },
464 };
465
466 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = {
467 { .start = 0x00a05c00, .end = 0x00a05c18 },
468 { .start = 0x00a05400, .end = 0x00a056e8 },
469 { .start = 0x00a08000, .end = 0x00a098bc },
470 { .start = 0x00a02400, .end = 0x00a02758 },
471 { .start = 0x00a04764, .end = 0x00a0476c },
472 { .start = 0x00a04770, .end = 0x00a04774 },
473 { .start = 0x00a04620, .end = 0x00a04624 },
474 };
475
476 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = {
477 { .start = 0x00a00000, .end = 0x00a00000 },
478 { .start = 0x00a0000c, .end = 0x00a00024 },
479 { .start = 0x00a0002c, .end = 0x00a00034 },
480 { .start = 0x00a0003c, .end = 0x00a0003c },
481 { .start = 0x00a00410, .end = 0x00a00418 },
482 { .start = 0x00a00420, .end = 0x00a00420 },
483 { .start = 0x00a00428, .end = 0x00a00428 },
484 { .start = 0x00a00430, .end = 0x00a0043c },
485 { .start = 0x00a00444, .end = 0x00a00444 },
486 { .start = 0x00a00840, .end = 0x00a00840 },
487 { .start = 0x00a00850, .end = 0x00a00858 },
488 { .start = 0x00a01004, .end = 0x00a01008 },
489 { .start = 0x00a01010, .end = 0x00a01010 },
490 { .start = 0x00a01018, .end = 0x00a01018 },
491 { .start = 0x00a01024, .end = 0x00a01024 },
492 { .start = 0x00a0102c, .end = 0x00a01034 },
493 { .start = 0x00a0103c, .end = 0x00a01040 },
494 { .start = 0x00a01048, .end = 0x00a01050 },
495 { .start = 0x00a01058, .end = 0x00a01058 },
496 { .start = 0x00a01060, .end = 0x00a01070 },
497 { .start = 0x00a0108c, .end = 0x00a0108c },
498 { .start = 0x00a01c20, .end = 0x00a01c28 },
499 { .start = 0x00a01d10, .end = 0x00a01d10 },
500 { .start = 0x00a01e28, .end = 0x00a01e2c },
501 { .start = 0x00a01e60, .end = 0x00a01e60 },
502 { .start = 0x00a01e80, .end = 0x00a01e80 },
503 { .start = 0x00a01ea0, .end = 0x00a01ea0 },
504 { .start = 0x00a02000, .end = 0x00a0201c },
505 { .start = 0x00a02024, .end = 0x00a02024 },
506 { .start = 0x00a02040, .end = 0x00a02048 },
507 { .start = 0x00a020c0, .end = 0x00a020e0 },
508 { .start = 0x00a02400, .end = 0x00a02404 },
509 { .start = 0x00a0240c, .end = 0x00a02414 },
510 { .start = 0x00a0241c, .end = 0x00a0243c },
511 { .start = 0x00a02448, .end = 0x00a024bc },
512 { .start = 0x00a024c4, .end = 0x00a024cc },
513 { .start = 0x00a02508, .end = 0x00a02508 },
514 { .start = 0x00a02510, .end = 0x00a02514 },
515 { .start = 0x00a0251c, .end = 0x00a0251c },
516 { .start = 0x00a0252c, .end = 0x00a0255c },
517 { .start = 0x00a02564, .end = 0x00a025a0 },
518 { .start = 0x00a025a8, .end = 0x00a025b4 },
519 { .start = 0x00a025c0, .end = 0x00a025c0 },
520 { .start = 0x00a025e8, .end = 0x00a025f4 },
521 { .start = 0x00a02c08, .end = 0x00a02c18 },
522 { .start = 0x00a02c2c, .end = 0x00a02c38 },
523 { .start = 0x00a02c68, .end = 0x00a02c78 },
524 { .start = 0x00a03000, .end = 0x00a03000 },
525 { .start = 0x00a03010, .end = 0x00a03014 },
526 { .start = 0x00a0301c, .end = 0x00a0302c },
527 { .start = 0x00a03034, .end = 0x00a03038 },
528 { .start = 0x00a03040, .end = 0x00a03044 },
529 { .start = 0x00a03060, .end = 0x00a03068 },
530 { .start = 0x00a03070, .end = 0x00a03070 },
531 { .start = 0x00a0307c, .end = 0x00a03084 },
532 { .start = 0x00a0308c, .end = 0x00a03090 },
533 { .start = 0x00a03098, .end = 0x00a03098 },
534 { .start = 0x00a030a0, .end = 0x00a030a0 },
535 { .start = 0x00a030a8, .end = 0x00a030b4 },
536 { .start = 0x00a030bc, .end = 0x00a030c0 },
537 { .start = 0x00a030c8, .end = 0x00a030f4 },
538 { .start = 0x00a03100, .end = 0x00a0312c },
539 { .start = 0x00a03c00, .end = 0x00a03c5c },
540 { .start = 0x00a04400, .end = 0x00a04454 },
541 { .start = 0x00a04460, .end = 0x00a04474 },
542 { .start = 0x00a044c0, .end = 0x00a044ec },
543 { .start = 0x00a04500, .end = 0x00a04504 },
544 { .start = 0x00a04510, .end = 0x00a04538 },
545 { .start = 0x00a04540, .end = 0x00a04548 },
546 { .start = 0x00a04560, .end = 0x00a04560 },
547 { .start = 0x00a04570, .end = 0x00a0457c },
548 { .start = 0x00a04590, .end = 0x00a04590 },
549 { .start = 0x00a04598, .end = 0x00a04598 },
550 { .start = 0x00a045c0, .end = 0x00a045f4 },
551 { .start = 0x00a05c18, .end = 0x00a05c1c },
552 { .start = 0x00a0c000, .end = 0x00a0c018 },
553 { .start = 0x00a0c020, .end = 0x00a0c028 },
554 { .start = 0x00a0c038, .end = 0x00a0c094 },
555 { .start = 0x00a0c0c0, .end = 0x00a0c104 },
556 { .start = 0x00a0c10c, .end = 0x00a0c118 },
557 { .start = 0x00a0c150, .end = 0x00a0c174 },
558 { .start = 0x00a0c17c, .end = 0x00a0c188 },
559 { .start = 0x00a0c190, .end = 0x00a0c198 },
560 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 },
561 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 },
562 };
563
564 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = {
565 { .start = 0x00d03c00, .end = 0x00d03c64 },
566 { .start = 0x00d05c18, .end = 0x00d05c1c },
567 { .start = 0x00d0c000, .end = 0x00d0c174 },
568 };
569
570 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start,
571 u32 len_bytes, __le32 *data)
572 {
573 u32 i;
574
575 for (i = 0; i < len_bytes; i += 4)
576 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i));
577 }
578
579 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt,
580 const struct iwl_prph_range *iwl_prph_dump_addr,
581 u32 range_len, void *ptr)
582 {
583 struct iwl_fw_error_dump_prph *prph;
584 struct iwl_trans *trans = fwrt->trans;
585 struct iwl_fw_error_dump_data **data =
586 (struct iwl_fw_error_dump_data **)ptr;
587 unsigned long flags;
588 u32 i;
589
590 if (!data)
591 return;
592
593 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n");
594
595 if (!iwl_trans_grab_nic_access(trans, &flags))
596 return;
597
598 for (i = 0; i < range_len; i++) {
599 /* The range includes both boundaries */
600 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
601 iwl_prph_dump_addr[i].start + 4;
602
603 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
604 (*data)->len = cpu_to_le32(sizeof(*prph) +
605 num_bytes_in_chunk);
606 prph = (void *)(*data)->data;
607 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
608
609 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start,
610 /* our range is inclusive, hence + 4 */
611 iwl_prph_dump_addr[i].end -
612 iwl_prph_dump_addr[i].start + 4,
613 (void *)prph->data);
614
615 *data = iwl_fw_error_next_data(*data);
616 }
617
618 iwl_trans_release_nic_access(trans, &flags);
619 }
620
621 /*
622 * alloc_sgtable - allocates scallerlist table in the given size,
623 * fills it with pages and returns it
624 * @size: the size (in bytes) of the table
625 */
626 static struct scatterlist *alloc_sgtable(int size)
627 {
628 int alloc_size, nents, i;
629 struct page *new_page;
630 struct scatterlist *iter;
631 struct scatterlist *table;
632
633 nents = DIV_ROUND_UP(size, PAGE_SIZE);
634 table = kcalloc(nents, sizeof(*table), GFP_KERNEL);
635 if (!table)
636 return NULL;
637 sg_init_table(table, nents);
638 iter = table;
639 for_each_sg(table, iter, sg_nents(table), i) {
640 new_page = alloc_page(GFP_KERNEL);
641 if (!new_page) {
642 /* release all previous allocated pages in the table */
643 iter = table;
644 for_each_sg(table, iter, sg_nents(table), i) {
645 new_page = sg_page(iter);
646 if (new_page)
647 __free_page(new_page);
648 }
649 kfree(table);
650 return NULL;
651 }
652 alloc_size = min_t(int, size, PAGE_SIZE);
653 size -= PAGE_SIZE;
654 sg_set_page(iter, new_page, alloc_size, 0);
655 }
656 return table;
657 }
658
659 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt,
660 const struct iwl_prph_range *iwl_prph_dump_addr,
661 u32 range_len, void *ptr)
662 {
663 u32 *prph_len = (u32 *)ptr;
664 int i, num_bytes_in_chunk;
665
666 if (!prph_len)
667 return;
668
669 for (i = 0; i < range_len; i++) {
670 /* The range includes both boundaries */
671 num_bytes_in_chunk =
672 iwl_prph_dump_addr[i].end -
673 iwl_prph_dump_addr[i].start + 4;
674
675 *prph_len += sizeof(struct iwl_fw_error_dump_data) +
676 sizeof(struct iwl_fw_error_dump_prph) +
677 num_bytes_in_chunk;
678 }
679 }
680
681 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr,
682 void (*handler)(struct iwl_fw_runtime *,
683 const struct iwl_prph_range *,
684 u32, void *))
685 {
686 u32 range_len;
687
688 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
689 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210);
690 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr);
691 } else if (fwrt->trans->trans_cfg->device_family >=
692 IWL_DEVICE_FAMILY_22000) {
693 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000);
694 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr);
695 } else {
696 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm);
697 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr);
698
699 if (fwrt->trans->trans_cfg->mq_rx_supported) {
700 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000);
701 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr);
702 }
703 }
704 }
705
706 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt,
707 struct iwl_fw_error_dump_data **dump_data,
708 u32 len, u32 ofs, u32 type)
709 {
710 struct iwl_fw_error_dump_mem *dump_mem;
711
712 if (!len)
713 return;
714
715 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
716 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem));
717 dump_mem = (void *)(*dump_data)->data;
718 dump_mem->type = cpu_to_le32(type);
719 dump_mem->offset = cpu_to_le32(ofs);
720 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len);
721 *dump_data = iwl_fw_error_next_data(*dump_data);
722
723 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type);
724 }
725
726 #define ADD_LEN(len, item_len, const_len) \
727 do {size_t item = item_len; len += (!!item) * const_len + item; } \
728 while (0)
729
730 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt,
731 struct iwl_fwrt_shared_mem_cfg *mem_cfg)
732 {
733 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) +
734 sizeof(struct iwl_fw_error_dump_fifo);
735 u32 fifo_len = 0;
736 int i;
737
738 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF))
739 return 0;
740
741 /* Count RXF2 size */
742 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len);
743
744 /* Count RXF1 sizes */
745 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC))
746 mem_cfg->num_lmacs = MAX_NUM_LMAC;
747
748 for (i = 0; i < mem_cfg->num_lmacs; i++)
749 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len);
750
751 return fifo_len;
752 }
753
754 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt,
755 struct iwl_fwrt_shared_mem_cfg *mem_cfg)
756 {
757 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) +
758 sizeof(struct iwl_fw_error_dump_fifo);
759 u32 fifo_len = 0;
760 int i;
761
762 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF))
763 goto dump_internal_txf;
764
765 /* Count TXF sizes */
766 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC))
767 mem_cfg->num_lmacs = MAX_NUM_LMAC;
768
769 for (i = 0; i < mem_cfg->num_lmacs; i++) {
770 int j;
771
772 for (j = 0; j < mem_cfg->num_txfifo_entries; j++)
773 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j],
774 hdr_len);
775 }
776
777 dump_internal_txf:
778 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) &&
779 fw_has_capa(&fwrt->fw->ucode_capa,
780 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)))
781 goto out;
782
783 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++)
784 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len);
785
786 out:
787 return fifo_len;
788 }
789
790 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt,
791 struct iwl_fw_error_dump_data **data)
792 {
793 int i;
794
795 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n");
796 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) {
797 struct iwl_fw_error_dump_paging *paging;
798 struct page *pages =
799 fwrt->fw_paging_db[i].fw_paging_block;
800 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys;
801
802 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
803 (*data)->len = cpu_to_le32(sizeof(*paging) +
804 PAGING_BLOCK_SIZE);
805 paging = (void *)(*data)->data;
806 paging->index = cpu_to_le32(i);
807 dma_sync_single_for_cpu(fwrt->trans->dev, addr,
808 PAGING_BLOCK_SIZE,
809 DMA_BIDIRECTIONAL);
810 memcpy(paging->data, page_address(pages),
811 PAGING_BLOCK_SIZE);
812 dma_sync_single_for_device(fwrt->trans->dev, addr,
813 PAGING_BLOCK_SIZE,
814 DMA_BIDIRECTIONAL);
815 (*data) = iwl_fw_error_next_data(*data);
816 }
817 }
818
819 static struct iwl_fw_error_dump_file *
820 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt,
821 struct iwl_fw_dump_ptrs *fw_error_dump,
822 struct iwl_fwrt_dump_data *data)
823 {
824 struct iwl_fw_error_dump_file *dump_file;
825 struct iwl_fw_error_dump_data *dump_data;
826 struct iwl_fw_error_dump_info *dump_info;
827 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg;
828 struct iwl_fw_error_dump_trigger_desc *dump_trig;
829 u32 sram_len, sram_ofs;
830 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv;
831 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg;
832 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0;
833 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len;
834 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ?
835 0 : fwrt->trans->cfg->dccm2_len;
836 int i;
837
838 /* SRAM - include stack CCM if driver knows the values for it */
839 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) {
840 const struct fw_img *img;
841
842 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX)
843 return NULL;
844 img = &fwrt->fw->img[fwrt->cur_fw_img];
845 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset;
846 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len;
847 } else {
848 sram_ofs = fwrt->trans->cfg->dccm_offset;
849 sram_len = fwrt->trans->cfg->dccm_len;
850 }
851
852 /* reading RXF/TXF sizes */
853 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) {
854 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg);
855 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg);
856
857 /* Make room for PRPH registers */
858 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH))
859 iwl_fw_prph_handler(fwrt, &prph_len,
860 iwl_fw_get_prph_len);
861
862 if (fwrt->trans->trans_cfg->device_family ==
863 IWL_DEVICE_FAMILY_7000 &&
864 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG))
865 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ;
866 }
867
868 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len;
869
870 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO))
871 file_len += sizeof(*dump_data) + sizeof(*dump_info);
872 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG))
873 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg);
874
875 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) {
876 size_t hdr_len = sizeof(*dump_data) +
877 sizeof(struct iwl_fw_error_dump_mem);
878
879 /* Dump SRAM only if no mem_tlvs */
880 if (!fwrt->fw->dbg.n_mem_tlv)
881 ADD_LEN(file_len, sram_len, hdr_len);
882
883 /* Make room for all mem types that exist */
884 ADD_LEN(file_len, smem_len, hdr_len);
885 ADD_LEN(file_len, sram2_len, hdr_len);
886
887 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++)
888 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len);
889 }
890
891 /* Make room for fw's virtual image pages, if it exists */
892 if (iwl_fw_dbg_is_paging_enabled(fwrt))
893 file_len += fwrt->num_of_paging_blk *
894 (sizeof(*dump_data) +
895 sizeof(struct iwl_fw_error_dump_paging) +
896 PAGING_BLOCK_SIZE);
897
898 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) {
899 file_len += sizeof(*dump_data) +
900 fwrt->trans->cfg->d3_debug_data_length * 2;
901 }
902
903 /* If we only want a monitor dump, reset the file length */
904 if (data->monitor_only) {
905 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 +
906 sizeof(*dump_info) + sizeof(*dump_smem_cfg);
907 }
908
909 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) &&
910 data->desc)
911 file_len += sizeof(*dump_data) + sizeof(*dump_trig) +
912 data->desc->len;
913
914 dump_file = vzalloc(file_len);
915 if (!dump_file)
916 return NULL;
917
918 fw_error_dump->fwrt_ptr = dump_file;
919
920 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER);
921 dump_data = (void *)dump_file->data;
922
923 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) {
924 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO);
925 dump_data->len = cpu_to_le32(sizeof(*dump_info));
926 dump_info = (void *)dump_data->data;
927 dump_info->hw_type =
928 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev));
929 dump_info->hw_step =
930 cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev));
931 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable,
932 sizeof(dump_info->fw_human_readable));
933 strncpy(dump_info->dev_human_readable, fwrt->trans->name,
934 sizeof(dump_info->dev_human_readable) - 1);
935 strncpy(dump_info->bus_human_readable, fwrt->dev->bus->name,
936 sizeof(dump_info->bus_human_readable) - 1);
937 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs;
938 dump_info->lmac_err_id[0] =
939 cpu_to_le32(fwrt->dump.lmac_err_id[0]);
940 if (fwrt->smem_cfg.num_lmacs > 1)
941 dump_info->lmac_err_id[1] =
942 cpu_to_le32(fwrt->dump.lmac_err_id[1]);
943 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id);
944
945 dump_data = iwl_fw_error_next_data(dump_data);
946 }
947
948 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) {
949 /* Dump shared memory configuration */
950 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG);
951 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg));
952 dump_smem_cfg = (void *)dump_data->data;
953 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs);
954 dump_smem_cfg->num_txfifo_entries =
955 cpu_to_le32(mem_cfg->num_txfifo_entries);
956 for (i = 0; i < MAX_NUM_LMAC; i++) {
957 int j;
958 u32 *txf_size = mem_cfg->lmac[i].txfifo_size;
959
960 for (j = 0; j < TX_FIFO_MAX_NUM; j++)
961 dump_smem_cfg->lmac[i].txfifo_size[j] =
962 cpu_to_le32(txf_size[j]);
963 dump_smem_cfg->lmac[i].rxfifo1_size =
964 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size);
965 }
966 dump_smem_cfg->rxfifo2_size =
967 cpu_to_le32(mem_cfg->rxfifo2_size);
968 dump_smem_cfg->internal_txfifo_addr =
969 cpu_to_le32(mem_cfg->internal_txfifo_addr);
970 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) {
971 dump_smem_cfg->internal_txfifo_size[i] =
972 cpu_to_le32(mem_cfg->internal_txfifo_size[i]);
973 }
974
975 dump_data = iwl_fw_error_next_data(dump_data);
976 }
977
978 /* We only dump the FIFOs if the FW is in error state */
979 if (fifo_len) {
980 iwl_fw_dump_rxf(fwrt, &dump_data);
981 iwl_fw_dump_txf(fwrt, &dump_data);
982 }
983
984 if (radio_len)
985 iwl_read_radio_regs(fwrt, &dump_data);
986
987 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) &&
988 data->desc) {
989 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO);
990 dump_data->len = cpu_to_le32(sizeof(*dump_trig) +
991 data->desc->len);
992 dump_trig = (void *)dump_data->data;
993 memcpy(dump_trig, &data->desc->trig_desc,
994 sizeof(*dump_trig) + data->desc->len);
995
996 dump_data = iwl_fw_error_next_data(dump_data);
997 }
998
999 /* In case we only want monitor dump, skip to dump trasport data */
1000 if (data->monitor_only)
1001 goto out;
1002
1003 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) {
1004 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem =
1005 fwrt->fw->dbg.mem_tlv;
1006
1007 if (!fwrt->fw->dbg.n_mem_tlv)
1008 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs,
1009 IWL_FW_ERROR_DUMP_MEM_SRAM);
1010
1011 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) {
1012 u32 len = le32_to_cpu(fw_dbg_mem[i].len);
1013 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs);
1014
1015 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs,
1016 le32_to_cpu(fw_dbg_mem[i].data_type));
1017 }
1018
1019 iwl_fw_dump_mem(fwrt, &dump_data, smem_len,
1020 fwrt->trans->cfg->smem_offset,
1021 IWL_FW_ERROR_DUMP_MEM_SMEM);
1022
1023 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len,
1024 fwrt->trans->cfg->dccm2_offset,
1025 IWL_FW_ERROR_DUMP_MEM_SRAM);
1026 }
1027
1028 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) {
1029 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr;
1030 size_t data_size = fwrt->trans->cfg->d3_debug_data_length;
1031
1032 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA);
1033 dump_data->len = cpu_to_le32(data_size * 2);
1034
1035 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size);
1036
1037 kfree(fwrt->dump.d3_debug_data);
1038 fwrt->dump.d3_debug_data = NULL;
1039
1040 iwl_trans_read_mem_bytes(fwrt->trans, addr,
1041 dump_data->data + data_size,
1042 data_size);
1043
1044 dump_data = iwl_fw_error_next_data(dump_data);
1045 }
1046
1047 /* Dump fw's virtual image */
1048 if (iwl_fw_dbg_is_paging_enabled(fwrt))
1049 iwl_dump_paging(fwrt, &dump_data);
1050
1051 if (prph_len)
1052 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph);
1053
1054 out:
1055 dump_file->file_len = cpu_to_le32(file_len);
1056 return dump_file;
1057 }
1058
1059 /**
1060 * struct iwl_dump_ini_region_data - region data
1061 * @reg_tlv: region TLV
1062 * @dump_data: dump data
1063 */
1064 struct iwl_dump_ini_region_data {
1065 struct iwl_ucode_tlv *reg_tlv;
1066 struct iwl_fwrt_dump_data *dump_data;
1067 };
1068
1069 static int iwl_dump_ini_prph_iter(struct iwl_fw_runtime *fwrt,
1070 struct iwl_dump_ini_region_data *reg_data,
1071 void *range_ptr, int idx)
1072 {
1073 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1074 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1075 __le32 *val = range->data;
1076 u32 prph_val;
1077 u32 addr = le32_to_cpu(reg->addrs[idx]) +
1078 le32_to_cpu(reg->dev_addr.offset);
1079 int i;
1080
1081 range->internal_base_addr = cpu_to_le32(addr);
1082 range->range_data_size = reg->dev_addr.size;
1083 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {
1084 prph_val = iwl_read_prph(fwrt->trans, addr + i);
1085 if (prph_val == 0x5a5a5a5a)
1086 return -EBUSY;
1087 *val++ = cpu_to_le32(prph_val);
1088 }
1089
1090 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1091 }
1092
1093 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt,
1094 struct iwl_dump_ini_region_data *reg_data,
1095 void *range_ptr, int idx)
1096 {
1097 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1098 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1099 __le32 *val = range->data;
1100 u32 addr = le32_to_cpu(reg->addrs[idx]) +
1101 le32_to_cpu(reg->dev_addr.offset);
1102 int i;
1103
1104 range->internal_base_addr = cpu_to_le32(addr);
1105 range->range_data_size = reg->dev_addr.size;
1106 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4)
1107 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i));
1108
1109 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1110 }
1111
1112 static int iwl_dump_ini_config_iter(struct iwl_fw_runtime *fwrt,
1113 struct iwl_dump_ini_region_data *reg_data,
1114 void *range_ptr, int idx)
1115 {
1116 struct iwl_trans *trans = fwrt->trans;
1117 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1118 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1119 __le32 *val = range->data;
1120 u32 addr = le32_to_cpu(reg->addrs[idx]) +
1121 le32_to_cpu(reg->dev_addr.offset);
1122 int i;
1123
1124 /* we shouldn't get here if the trans doesn't have read_config32 */
1125 if (WARN_ON_ONCE(!trans->ops->read_config32))
1126 return -EOPNOTSUPP;
1127
1128 range->internal_base_addr = cpu_to_le32(addr);
1129 range->range_data_size = reg->dev_addr.size;
1130 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {
1131 int ret;
1132 u32 tmp;
1133
1134 ret = trans->ops->read_config32(trans, addr + i, &tmp);
1135 if (ret < 0)
1136 return ret;
1137
1138 *val++ = cpu_to_le32(tmp);
1139 }
1140
1141 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1142 }
1143
1144 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt,
1145 struct iwl_dump_ini_region_data *reg_data,
1146 void *range_ptr, int idx)
1147 {
1148 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1149 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1150 u32 addr = le32_to_cpu(reg->addrs[idx]) +
1151 le32_to_cpu(reg->dev_addr.offset);
1152
1153 range->internal_base_addr = cpu_to_le32(addr);
1154 range->range_data_size = reg->dev_addr.size;
1155 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1156 le32_to_cpu(reg->dev_addr.size));
1157
1158 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1159 }
1160
1161 static int _iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt,
1162 void *range_ptr, int idx)
1163 {
1164 /* increase idx by 1 since the pages are from 1 to
1165 * fwrt->num_of_paging_blk + 1
1166 */
1167 struct page *page = fwrt->fw_paging_db[++idx].fw_paging_block;
1168 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1169 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys;
1170 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size;
1171
1172 range->page_num = cpu_to_le32(idx);
1173 range->range_data_size = cpu_to_le32(page_size);
1174 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size,
1175 DMA_BIDIRECTIONAL);
1176 memcpy(range->data, page_address(page), page_size);
1177 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size,
1178 DMA_BIDIRECTIONAL);
1179
1180 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1181 }
1182
1183 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt,
1184 struct iwl_dump_ini_region_data *reg_data,
1185 void *range_ptr, int idx)
1186 {
1187 struct iwl_fw_ini_error_dump_range *range;
1188 u32 page_size;
1189
1190 if (!fwrt->trans->trans_cfg->gen2)
1191 return _iwl_dump_ini_paging_iter(fwrt, range_ptr, idx);
1192
1193 range = range_ptr;
1194 page_size = fwrt->trans->init_dram.paging[idx].size;
1195
1196 range->page_num = cpu_to_le32(idx);
1197 range->range_data_size = cpu_to_le32(page_size);
1198 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block,
1199 page_size);
1200
1201 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1202 }
1203
1204 static int
1205 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt,
1206 struct iwl_dump_ini_region_data *reg_data,
1207 void *range_ptr, int idx)
1208 {
1209 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1210 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1211 struct iwl_dram_data *frag;
1212 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id);
1213
1214 frag = &fwrt->trans->dbg.fw_mon_ini[alloc_id].frags[idx];
1215
1216 range->dram_base_addr = cpu_to_le64(frag->physical);
1217 range->range_data_size = cpu_to_le32(frag->size);
1218
1219 memcpy(range->data, frag->block, frag->size);
1220
1221 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1222 }
1223
1224 static int iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime *fwrt,
1225 struct iwl_dump_ini_region_data *reg_data,
1226 void *range_ptr, int idx)
1227 {
1228 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1229 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1230 u32 addr = le32_to_cpu(reg->internal_buffer.base_addr);
1231
1232 range->internal_base_addr = cpu_to_le32(addr);
1233 range->range_data_size = reg->internal_buffer.size;
1234 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1235 le32_to_cpu(reg->internal_buffer.size));
1236
1237 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1238 }
1239
1240 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt,
1241 struct iwl_dump_ini_region_data *reg_data, int idx)
1242 {
1243 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1244 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data;
1245 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
1246 int txf_num = cfg->num_txfifo_entries;
1247 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size);
1248 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid[0]);
1249
1250 if (!idx) {
1251 if (le32_to_cpu(reg->fifos.offset) && cfg->num_lmacs == 1) {
1252 IWL_ERR(fwrt, "WRT: Invalid lmac offset 0x%x\n",
1253 le32_to_cpu(reg->fifos.offset));
1254 return false;
1255 }
1256
1257 iter->internal_txf = 0;
1258 iter->fifo_size = 0;
1259 iter->fifo = -1;
1260 if (le32_to_cpu(reg->fifos.offset))
1261 iter->lmac = 1;
1262 else
1263 iter->lmac = 0;
1264 }
1265
1266 if (!iter->internal_txf) {
1267 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) {
1268 iter->fifo_size =
1269 cfg->lmac[iter->lmac].txfifo_size[iter->fifo];
1270 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo)))
1271 return true;
1272 }
1273 iter->fifo--;
1274 }
1275
1276 iter->internal_txf = 1;
1277
1278 if (!fw_has_capa(&fwrt->fw->ucode_capa,
1279 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))
1280 return false;
1281
1282 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) {
1283 iter->fifo_size =
1284 cfg->internal_txfifo_size[iter->fifo - txf_num];
1285 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo)))
1286 return true;
1287 }
1288
1289 return false;
1290 }
1291
1292 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt,
1293 struct iwl_dump_ini_region_data *reg_data,
1294 void *range_ptr, int idx)
1295 {
1296 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1297 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1298 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data;
1299 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data;
1300 u32 offs = le32_to_cpu(reg->fifos.offset), addr;
1301 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1302 u32 registers_size = registers_num * sizeof(*reg_dump);
1303 __le32 *data;
1304 unsigned long flags;
1305 int i;
1306
1307 if (!iwl_ini_txf_iter(fwrt, reg_data, idx))
1308 return -EIO;
1309
1310 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
1311 return -EBUSY;
1312
1313 range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo);
1314 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num);
1315 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size);
1316
1317 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo);
1318
1319 /*
1320 * read txf registers. for each register, write to the dump the
1321 * register address and its value
1322 */
1323 for (i = 0; i < registers_num; i++) {
1324 addr = le32_to_cpu(reg->addrs[i]) + offs;
1325
1326 reg_dump->addr = cpu_to_le32(addr);
1327 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans,
1328 addr));
1329
1330 reg_dump++;
1331 }
1332
1333 if (reg->fifos.hdr_only) {
1334 range->range_data_size = cpu_to_le32(registers_size);
1335 goto out;
1336 }
1337
1338 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */
1339 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs,
1340 TXF_WR_PTR + offs);
1341
1342 /* Dummy-read to advance the read pointer to the head */
1343 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs);
1344
1345 /* Read FIFO */
1346 addr = TXF_READ_MODIFY_DATA + offs;
1347 data = (void *)reg_dump;
1348 for (i = 0; i < iter->fifo_size; i += sizeof(*data))
1349 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr));
1350
1351 out:
1352 iwl_trans_release_nic_access(fwrt->trans, &flags);
1353
1354 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1355 }
1356
1357 struct iwl_ini_rxf_data {
1358 u32 fifo_num;
1359 u32 size;
1360 u32 offset;
1361 };
1362
1363 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt,
1364 struct iwl_dump_ini_region_data *reg_data,
1365 struct iwl_ini_rxf_data *data)
1366 {
1367 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1368 u32 fid1 = le32_to_cpu(reg->fifos.fid[0]);
1369 u32 fid2 = le32_to_cpu(reg->fifos.fid[1]);
1370 u8 fifo_idx;
1371
1372 if (!data)
1373 return;
1374
1375 /* make sure only one bit is set in only one fid */
1376 if (WARN_ONCE(hweight_long(fid1) + hweight_long(fid2) != 1,
1377 "fid1=%x, fid2=%x\n", fid1, fid2))
1378 return;
1379
1380 memset(data, 0, sizeof(*data));
1381
1382 if (fid1) {
1383 fifo_idx = ffs(fid1) - 1;
1384 if (WARN_ONCE(fifo_idx >= MAX_NUM_LMAC, "fifo_idx=%d\n",
1385 fifo_idx))
1386 return;
1387
1388 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size;
1389 data->fifo_num = fifo_idx;
1390 } else {
1391 u8 max_idx;
1392
1393 fifo_idx = ffs(fid2) - 1;
1394 if (iwl_fw_lookup_notif_ver(fwrt->fw, SYSTEM_GROUP,
1395 SHARED_MEM_CFG_CMD, 0) <= 3)
1396 max_idx = 0;
1397 else
1398 max_idx = 1;
1399
1400 if (WARN_ONCE(fifo_idx > max_idx,
1401 "invalid umac fifo idx %d", fifo_idx))
1402 return;
1403
1404 /* use bit 31 to distinguish between umac and lmac rxf while
1405 * parsing the dump
1406 */
1407 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT;
1408
1409 switch (fifo_idx) {
1410 case 0:
1411 data->size = fwrt->smem_cfg.rxfifo2_size;
1412 data->offset = iwl_umac_prph(fwrt->trans,
1413 RXF_DIFF_FROM_PREV);
1414 break;
1415 case 1:
1416 data->size = fwrt->smem_cfg.rxfifo2_control_size;
1417 data->offset = iwl_umac_prph(fwrt->trans,
1418 RXF2C_DIFF_FROM_PREV);
1419 break;
1420 }
1421 }
1422 }
1423
1424 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt,
1425 struct iwl_dump_ini_region_data *reg_data,
1426 void *range_ptr, int idx)
1427 {
1428 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1429 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1430 struct iwl_ini_rxf_data rxf_data;
1431 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data;
1432 u32 offs = le32_to_cpu(reg->fifos.offset), addr;
1433 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1434 u32 registers_size = registers_num * sizeof(*reg_dump);
1435 __le32 *data;
1436 unsigned long flags;
1437 int i;
1438
1439 iwl_ini_get_rxf_data(fwrt, reg_data, &rxf_data);
1440 if (!rxf_data.size)
1441 return -EIO;
1442
1443 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
1444 return -EBUSY;
1445
1446 range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num);
1447 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num);
1448 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size);
1449
1450 /*
1451 * read rxf registers. for each register, write to the dump the
1452 * register address and its value
1453 */
1454 for (i = 0; i < registers_num; i++) {
1455 addr = le32_to_cpu(reg->addrs[i]) + offs;
1456
1457 reg_dump->addr = cpu_to_le32(addr);
1458 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans,
1459 addr));
1460
1461 reg_dump++;
1462 }
1463
1464 if (reg->fifos.hdr_only) {
1465 range->range_data_size = cpu_to_le32(registers_size);
1466 goto out;
1467 }
1468
1469 offs = rxf_data.offset;
1470
1471 /* Lock fence */
1472 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1);
1473 /* Set fence pointer to the same place like WR pointer */
1474 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1);
1475 /* Set fence offset */
1476 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs,
1477 0x0);
1478
1479 /* Read FIFO */
1480 addr = RXF_FIFO_RD_FENCE_INC + offs;
1481 data = (void *)reg_dump;
1482 for (i = 0; i < rxf_data.size; i += sizeof(*data))
1483 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr));
1484
1485 out:
1486 iwl_trans_release_nic_access(fwrt->trans, &flags);
1487
1488 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1489 }
1490
1491 static int
1492 iwl_dump_ini_err_table_iter(struct iwl_fw_runtime *fwrt,
1493 struct iwl_dump_ini_region_data *reg_data,
1494 void *range_ptr, int idx)
1495 {
1496 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1497 struct iwl_fw_ini_region_err_table *err_table = &reg->err_table;
1498 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1499 u32 addr = le32_to_cpu(err_table->base_addr) +
1500 le32_to_cpu(err_table->offset);
1501
1502 range->internal_base_addr = cpu_to_le32(addr);
1503 range->range_data_size = err_table->size;
1504 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1505 le32_to_cpu(err_table->size));
1506
1507 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1508 }
1509
1510 static int iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime *fwrt,
1511 struct iwl_dump_ini_region_data *reg_data,
1512 void *range_ptr, int idx)
1513 {
1514 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1515 struct iwl_rx_packet *pkt = reg_data->dump_data->fw_pkt;
1516 u32 pkt_len;
1517
1518 if (!pkt)
1519 return -EIO;
1520
1521 pkt_len = iwl_rx_packet_payload_len(pkt);
1522
1523 memcpy(&range->fw_pkt_hdr, &pkt->hdr, sizeof(range->fw_pkt_hdr));
1524 range->range_data_size = cpu_to_le32(pkt_len);
1525
1526 memcpy(range->data, pkt->data, pkt_len);
1527
1528 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1529 }
1530
1531 static void *
1532 iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt,
1533 struct iwl_dump_ini_region_data *reg_data,
1534 void *data)
1535 {
1536 struct iwl_fw_ini_error_dump *dump = data;
1537
1538 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1539
1540 return dump->ranges;
1541 }
1542
1543 /**
1544 * mask_apply_and_normalize - applies mask on val and normalize the result
1545 *
1546 * The normalization is based on the first set bit in the mask
1547 *
1548 * @val: value
1549 * @mask: mask to apply and to normalize with
1550 */
1551 static u32 mask_apply_and_normalize(u32 val, u32 mask)
1552 {
1553 return (val & mask) >> (ffs(mask) - 1);
1554 }
1555
1556 static __le32 iwl_get_mon_reg(struct iwl_fw_runtime *fwrt, u32 alloc_id,
1557 const struct iwl_fw_mon_reg *reg_info)
1558 {
1559 u32 val, offs;
1560
1561 /* The header addresses of DBGCi is calculate as follows:
1562 * DBGC1 address + (0x100 * i)
1563 */
1564 offs = (alloc_id - IWL_FW_INI_ALLOCATION_ID_DBGC1) * 0x100;
1565
1566 if (!reg_info || !reg_info->addr || !reg_info->mask)
1567 return 0;
1568
1569 val = iwl_read_prph_no_grab(fwrt->trans, reg_info->addr + offs);
1570
1571 return cpu_to_le32(mask_apply_and_normalize(val, reg_info->mask));
1572 }
1573
1574 static void *
1575 iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt,
1576 struct iwl_dump_ini_region_data *reg_data,
1577 struct iwl_fw_ini_monitor_dump *data,
1578 const struct iwl_fw_mon_regs *addrs)
1579 {
1580 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1581 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id);
1582 unsigned long flags;
1583
1584 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) {
1585 IWL_ERR(fwrt, "Failed to get monitor header\n");
1586 return NULL;
1587 }
1588
1589 data->write_ptr = iwl_get_mon_reg(fwrt, alloc_id,
1590 &addrs->write_ptr);
1591 data->cycle_cnt = iwl_get_mon_reg(fwrt, alloc_id,
1592 &addrs->cycle_cnt);
1593 data->cur_frag = iwl_get_mon_reg(fwrt, alloc_id,
1594 &addrs->cur_frag);
1595
1596 iwl_trans_release_nic_access(fwrt->trans, &flags);
1597
1598 data->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1599
1600 return data->ranges;
1601 }
1602
1603 static void *
1604 iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt,
1605 struct iwl_dump_ini_region_data *reg_data,
1606 void *data)
1607 {
1608 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data;
1609
1610 return iwl_dump_ini_mon_fill_header(fwrt, reg_data, mon_dump,
1611 &fwrt->trans->cfg->mon_dram_regs);
1612 }
1613
1614 static void *
1615 iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt,
1616 struct iwl_dump_ini_region_data *reg_data,
1617 void *data)
1618 {
1619 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data;
1620
1621 return iwl_dump_ini_mon_fill_header(fwrt, reg_data, mon_dump,
1622 &fwrt->trans->cfg->mon_smem_regs);
1623 }
1624
1625 static void *
1626 iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime *fwrt,
1627 struct iwl_dump_ini_region_data *reg_data,
1628 void *data)
1629 {
1630 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1631 struct iwl_fw_ini_err_table_dump *dump = data;
1632
1633 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1634 dump->version = reg->err_table.version;
1635
1636 return dump->ranges;
1637 }
1638
1639 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt,
1640 struct iwl_dump_ini_region_data *reg_data)
1641 {
1642 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1643
1644 return iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1645 }
1646
1647 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt,
1648 struct iwl_dump_ini_region_data *reg_data)
1649 {
1650 if (fwrt->trans->trans_cfg->gen2)
1651 return fwrt->trans->init_dram.paging_cnt;
1652
1653 return fwrt->num_of_paging_blk;
1654 }
1655
1656 static u32
1657 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt,
1658 struct iwl_dump_ini_region_data *reg_data)
1659 {
1660 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1661 struct iwl_fw_mon *fw_mon;
1662 u32 ranges = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id);
1663 int i;
1664
1665 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
1666
1667 for (i = 0; i < fw_mon->num_frags; i++) {
1668 if (!fw_mon->frags[i].size)
1669 break;
1670
1671 ranges++;
1672 }
1673
1674 return ranges;
1675 }
1676
1677 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt,
1678 struct iwl_dump_ini_region_data *reg_data)
1679 {
1680 u32 num_of_fifos = 0;
1681
1682 while (iwl_ini_txf_iter(fwrt, reg_data, num_of_fifos))
1683 num_of_fifos++;
1684
1685 return num_of_fifos;
1686 }
1687
1688 static u32 iwl_dump_ini_single_range(struct iwl_fw_runtime *fwrt,
1689 struct iwl_dump_ini_region_data *reg_data)
1690 {
1691 return 1;
1692 }
1693
1694 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt,
1695 struct iwl_dump_ini_region_data *reg_data)
1696 {
1697 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1698 u32 size = le32_to_cpu(reg->dev_addr.size);
1699 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data);
1700
1701 if (!size || !ranges)
1702 return 0;
1703
1704 return sizeof(struct iwl_fw_ini_error_dump) + ranges *
1705 (size + sizeof(struct iwl_fw_ini_error_dump_range));
1706 }
1707
1708 static u32
1709 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt,
1710 struct iwl_dump_ini_region_data *reg_data)
1711 {
1712 int i;
1713 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range);
1714 u32 size = sizeof(struct iwl_fw_ini_error_dump);
1715
1716 if (fwrt->trans->trans_cfg->gen2) {
1717 for (i = 0; i < iwl_dump_ini_paging_ranges(fwrt, reg_data); i++)
1718 size += range_header_len +
1719 fwrt->trans->init_dram.paging[i].size;
1720 } else {
1721 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg_data);
1722 i++)
1723 size += range_header_len +
1724 fwrt->fw_paging_db[i].fw_paging_size;
1725 }
1726
1727 return size;
1728 }
1729
1730 static u32
1731 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt,
1732 struct iwl_dump_ini_region_data *reg_data)
1733 {
1734 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1735 struct iwl_fw_mon *fw_mon;
1736 u32 size = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id);
1737 int i;
1738
1739 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
1740
1741 for (i = 0; i < fw_mon->num_frags; i++) {
1742 struct iwl_dram_data *frag = &fw_mon->frags[i];
1743
1744 if (!frag->size)
1745 break;
1746
1747 size += sizeof(struct iwl_fw_ini_error_dump_range) + frag->size;
1748 }
1749
1750 if (size)
1751 size += sizeof(struct iwl_fw_ini_monitor_dump);
1752
1753 return size;
1754 }
1755
1756 static u32
1757 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt,
1758 struct iwl_dump_ini_region_data *reg_data)
1759 {
1760 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1761 u32 size;
1762
1763 size = le32_to_cpu(reg->internal_buffer.size);
1764 if (!size)
1765 return 0;
1766
1767 size += sizeof(struct iwl_fw_ini_monitor_dump) +
1768 sizeof(struct iwl_fw_ini_error_dump_range);
1769
1770 return size;
1771 }
1772
1773 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt,
1774 struct iwl_dump_ini_region_data *reg_data)
1775 {
1776 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1777 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data;
1778 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1779 u32 size = 0;
1780 u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) +
1781 registers_num *
1782 sizeof(struct iwl_fw_ini_error_dump_register);
1783
1784 while (iwl_ini_txf_iter(fwrt, reg_data, size)) {
1785 size += fifo_hdr;
1786 if (!reg->fifos.hdr_only)
1787 size += iter->fifo_size;
1788 }
1789
1790 if (!size)
1791 return 0;
1792
1793 return size + sizeof(struct iwl_fw_ini_error_dump);
1794 }
1795
1796 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt,
1797 struct iwl_dump_ini_region_data *reg_data)
1798 {
1799 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1800 struct iwl_ini_rxf_data rx_data;
1801 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1802 u32 size = sizeof(struct iwl_fw_ini_error_dump) +
1803 sizeof(struct iwl_fw_ini_error_dump_range) +
1804 registers_num * sizeof(struct iwl_fw_ini_error_dump_register);
1805
1806 if (reg->fifos.hdr_only)
1807 return size;
1808
1809 iwl_ini_get_rxf_data(fwrt, reg_data, &rx_data);
1810 size += rx_data.size;
1811
1812 return size;
1813 }
1814
1815 static u32
1816 iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime *fwrt,
1817 struct iwl_dump_ini_region_data *reg_data)
1818 {
1819 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1820 u32 size = le32_to_cpu(reg->err_table.size);
1821
1822 if (size)
1823 size += sizeof(struct iwl_fw_ini_err_table_dump) +
1824 sizeof(struct iwl_fw_ini_error_dump_range);
1825
1826 return size;
1827 }
1828
1829 static u32
1830 iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime *fwrt,
1831 struct iwl_dump_ini_region_data *reg_data)
1832 {
1833 u32 size = 0;
1834
1835 if (!reg_data->dump_data->fw_pkt)
1836 return 0;
1837
1838 size += iwl_rx_packet_payload_len(reg_data->dump_data->fw_pkt);
1839 if (size)
1840 size += sizeof(struct iwl_fw_ini_error_dump) +
1841 sizeof(struct iwl_fw_ini_error_dump_range);
1842
1843 return size;
1844 }
1845
1846 /**
1847 * struct iwl_dump_ini_mem_ops - ini memory dump operations
1848 * @get_num_of_ranges: returns the number of memory ranges in the region.
1849 * @get_size: returns the total size of the region.
1850 * @fill_mem_hdr: fills region type specific headers and returns pointer to
1851 * the first range or NULL if failed to fill headers.
1852 * @fill_range: copies a given memory range into the dump.
1853 * Returns the size of the range or negative error value otherwise.
1854 */
1855 struct iwl_dump_ini_mem_ops {
1856 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt,
1857 struct iwl_dump_ini_region_data *reg_data);
1858 u32 (*get_size)(struct iwl_fw_runtime *fwrt,
1859 struct iwl_dump_ini_region_data *reg_data);
1860 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt,
1861 struct iwl_dump_ini_region_data *reg_data,
1862 void *data);
1863 int (*fill_range)(struct iwl_fw_runtime *fwrt,
1864 struct iwl_dump_ini_region_data *reg_data,
1865 void *range, int idx);
1866 };
1867
1868 /**
1869 * iwl_dump_ini_mem
1870 *
1871 * Creates a dump tlv and copy a memory region into it.
1872 * Returns the size of the current dump tlv or 0 if failed
1873 *
1874 * @fwrt: fw runtime struct
1875 * @list: list to add the dump tlv to
1876 * @reg: memory region
1877 * @ops: memory dump operations
1878 */
1879 static u32 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, struct list_head *list,
1880 struct iwl_dump_ini_region_data *reg_data,
1881 const struct iwl_dump_ini_mem_ops *ops)
1882 {
1883 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1884 struct iwl_fw_ini_dump_entry *entry;
1885 struct iwl_fw_error_dump_data *tlv;
1886 struct iwl_fw_ini_error_dump_header *header;
1887 u32 type = le32_to_cpu(reg->type), id = le32_to_cpu(reg->id);
1888 u32 num_of_ranges, i, size;
1889 void *range;
1890
1891 if (!ops->get_num_of_ranges || !ops->get_size || !ops->fill_mem_hdr ||
1892 !ops->fill_range)
1893 return 0;
1894
1895 size = ops->get_size(fwrt, reg_data);
1896 if (!size)
1897 return 0;
1898
1899 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + size);
1900 if (!entry)
1901 return 0;
1902
1903 entry->size = sizeof(*tlv) + size;
1904
1905 tlv = (void *)entry->data;
1906 tlv->type = reg->type;
1907 tlv->len = cpu_to_le32(size);
1908
1909 IWL_DEBUG_FW(fwrt, "WRT: Collecting region: id=%d, type=%d\n", id,
1910 type);
1911
1912 num_of_ranges = ops->get_num_of_ranges(fwrt, reg_data);
1913
1914 header = (void *)tlv->data;
1915 header->region_id = reg->id;
1916 header->num_of_ranges = cpu_to_le32(num_of_ranges);
1917 header->name_len = cpu_to_le32(IWL_FW_INI_MAX_NAME);
1918 memcpy(header->name, reg->name, IWL_FW_INI_MAX_NAME);
1919
1920 range = ops->fill_mem_hdr(fwrt, reg_data, header);
1921 if (!range) {
1922 IWL_ERR(fwrt,
1923 "WRT: Failed to fill region header: id=%d, type=%d\n",
1924 id, type);
1925 goto out_err;
1926 }
1927
1928 for (i = 0; i < num_of_ranges; i++) {
1929 int range_size = ops->fill_range(fwrt, reg_data, range, i);
1930
1931 if (range_size < 0) {
1932 IWL_ERR(fwrt,
1933 "WRT: Failed to dump region: id=%d, type=%d\n",
1934 id, type);
1935 goto out_err;
1936 }
1937 range = range + range_size;
1938 }
1939
1940 list_add_tail(&entry->list, list);
1941
1942 return entry->size;
1943
1944 out_err:
1945 vfree(entry);
1946
1947 return 0;
1948 }
1949
1950 static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt,
1951 struct iwl_fw_ini_trigger_tlv *trigger,
1952 struct list_head *list)
1953 {
1954 struct iwl_fw_ini_dump_entry *entry;
1955 struct iwl_fw_error_dump_data *tlv;
1956 struct iwl_fw_ini_dump_info *dump;
1957 struct iwl_dbg_tlv_node *node;
1958 struct iwl_fw_ini_dump_cfg_name *cfg_name;
1959 u32 size = sizeof(*tlv) + sizeof(*dump);
1960 u32 num_of_cfg_names = 0;
1961 u32 hw_type;
1962
1963 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) {
1964 size += sizeof(*cfg_name);
1965 num_of_cfg_names++;
1966 }
1967
1968 entry = vzalloc(sizeof(*entry) + size);
1969 if (!entry)
1970 return 0;
1971
1972 entry->size = size;
1973
1974 tlv = (void *)entry->data;
1975 tlv->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE);
1976 tlv->len = cpu_to_le32(size - sizeof(*tlv));
1977
1978 dump = (void *)tlv->data;
1979
1980 dump->version = cpu_to_le32(IWL_INI_DUMP_VER);
1981 dump->time_point = trigger->time_point;
1982 dump->trigger_reason = trigger->trigger_reason;
1983 dump->external_cfg_state =
1984 cpu_to_le32(fwrt->trans->dbg.external_ini_cfg);
1985
1986 dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type);
1987 dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype);
1988
1989 dump->hw_step = cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev));
1990
1991 /*
1992 * Several HWs all have type == 0x42, so we'll override this value
1993 * according to the detected HW
1994 */
1995 hw_type = CSR_HW_REV_TYPE(fwrt->trans->hw_rev);
1996 if (hw_type == IWL_AX210_HW_TYPE) {
1997 u32 prph_val = iwl_read_prph(fwrt->trans, WFPM_OTP_CFG1_ADDR);
1998 u32 is_jacket = !!(prph_val & WFPM_OTP_CFG1_IS_JACKET_BIT);
1999 u32 is_cdb = !!(prph_val & WFPM_OTP_CFG1_IS_CDB_BIT);
2000 u32 masked_bits = is_jacket | (is_cdb << 1);
2001
2002 /*
2003 * The HW type depends on certain bits in this case, so add
2004 * these bits to the HW type. We won't have collisions since we
2005 * add these bits after the highest possible bit in the mask.
2006 */
2007 hw_type |= masked_bits << IWL_AX210_HW_TYPE_ADDITION_SHIFT;
2008 }
2009 dump->hw_type = cpu_to_le32(hw_type);
2010
2011 dump->rf_id_flavor =
2012 cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->hw_rf_id));
2013 dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->hw_rf_id));
2014 dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->hw_rf_id));
2015 dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->hw_rf_id));
2016
2017 dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major);
2018 dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor);
2019 dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major);
2020 dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor);
2021
2022 dump->fw_mon_mode = cpu_to_le32(fwrt->trans->dbg.ini_dest);
2023 dump->regions_mask = trigger->regions_mask;
2024
2025 dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag));
2026 memcpy(dump->build_tag, fwrt->fw->human_readable,
2027 sizeof(dump->build_tag));
2028
2029 cfg_name = dump->cfg_names;
2030 dump->num_of_cfg_names = cpu_to_le32(num_of_cfg_names);
2031 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) {
2032 struct iwl_fw_ini_debug_info_tlv *debug_info =
2033 (void *)node->tlv.data;
2034
2035 cfg_name->image_type = debug_info->image_type;
2036 cfg_name->cfg_name_len =
2037 cpu_to_le32(IWL_FW_INI_MAX_CFG_NAME);
2038 memcpy(cfg_name->cfg_name, debug_info->debug_cfg_name,
2039 sizeof(cfg_name->cfg_name));
2040 cfg_name++;
2041 }
2042
2043 /* add dump info TLV to the beginning of the list since it needs to be
2044 * the first TLV in the dump
2045 */
2046 list_add(&entry->list, list);
2047
2048 return entry->size;
2049 }
2050
2051 static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = {
2052 [IWL_FW_INI_REGION_INVALID] = {},
2053 [IWL_FW_INI_REGION_INTERNAL_BUFFER] = {
2054 .get_num_of_ranges = iwl_dump_ini_single_range,
2055 .get_size = iwl_dump_ini_mon_smem_get_size,
2056 .fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header,
2057 .fill_range = iwl_dump_ini_mon_smem_iter,
2058 },
2059 [IWL_FW_INI_REGION_DRAM_BUFFER] = {
2060 .get_num_of_ranges = iwl_dump_ini_mon_dram_ranges,
2061 .get_size = iwl_dump_ini_mon_dram_get_size,
2062 .fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header,
2063 .fill_range = iwl_dump_ini_mon_dram_iter,
2064 },
2065 [IWL_FW_INI_REGION_TXF] = {
2066 .get_num_of_ranges = iwl_dump_ini_txf_ranges,
2067 .get_size = iwl_dump_ini_txf_get_size,
2068 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2069 .fill_range = iwl_dump_ini_txf_iter,
2070 },
2071 [IWL_FW_INI_REGION_RXF] = {
2072 .get_num_of_ranges = iwl_dump_ini_single_range,
2073 .get_size = iwl_dump_ini_rxf_get_size,
2074 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2075 .fill_range = iwl_dump_ini_rxf_iter,
2076 },
2077 [IWL_FW_INI_REGION_LMAC_ERROR_TABLE] = {
2078 .get_num_of_ranges = iwl_dump_ini_single_range,
2079 .get_size = iwl_dump_ini_err_table_get_size,
2080 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header,
2081 .fill_range = iwl_dump_ini_err_table_iter,
2082 },
2083 [IWL_FW_INI_REGION_UMAC_ERROR_TABLE] = {
2084 .get_num_of_ranges = iwl_dump_ini_single_range,
2085 .get_size = iwl_dump_ini_err_table_get_size,
2086 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header,
2087 .fill_range = iwl_dump_ini_err_table_iter,
2088 },
2089 [IWL_FW_INI_REGION_RSP_OR_NOTIF] = {
2090 .get_num_of_ranges = iwl_dump_ini_single_range,
2091 .get_size = iwl_dump_ini_fw_pkt_get_size,
2092 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2093 .fill_range = iwl_dump_ini_fw_pkt_iter,
2094 },
2095 [IWL_FW_INI_REGION_DEVICE_MEMORY] = {
2096 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2097 .get_size = iwl_dump_ini_mem_get_size,
2098 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2099 .fill_range = iwl_dump_ini_dev_mem_iter,
2100 },
2101 [IWL_FW_INI_REGION_PERIPHERY_MAC] = {
2102 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2103 .get_size = iwl_dump_ini_mem_get_size,
2104 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2105 .fill_range = iwl_dump_ini_prph_iter,
2106 },
2107 [IWL_FW_INI_REGION_PERIPHERY_PHY] = {},
2108 [IWL_FW_INI_REGION_PERIPHERY_AUX] = {},
2109 [IWL_FW_INI_REGION_PAGING] = {
2110 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2111 .get_num_of_ranges = iwl_dump_ini_paging_ranges,
2112 .get_size = iwl_dump_ini_paging_get_size,
2113 .fill_range = iwl_dump_ini_paging_iter,
2114 },
2115 [IWL_FW_INI_REGION_CSR] = {
2116 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2117 .get_size = iwl_dump_ini_mem_get_size,
2118 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2119 .fill_range = iwl_dump_ini_csr_iter,
2120 },
2121 [IWL_FW_INI_REGION_DRAM_IMR] = {},
2122 [IWL_FW_INI_REGION_PCI_IOSF_CONFIG] = {
2123 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2124 .get_size = iwl_dump_ini_mem_get_size,
2125 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2126 .fill_range = iwl_dump_ini_config_iter,
2127 },
2128 };
2129
2130 static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt,
2131 struct iwl_fwrt_dump_data *dump_data,
2132 struct list_head *list)
2133 {
2134 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig;
2135 struct iwl_dump_ini_region_data reg_data = {
2136 .dump_data = dump_data,
2137 };
2138 int i;
2139 u32 size = 0;
2140 u64 regions_mask = le64_to_cpu(trigger->regions_mask);
2141
2142 BUILD_BUG_ON(sizeof(trigger->regions_mask) != sizeof(regions_mask));
2143 BUILD_BUG_ON((sizeof(trigger->regions_mask) * BITS_PER_BYTE) <
2144 ARRAY_SIZE(fwrt->trans->dbg.active_regions));
2145
2146 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions); i++) {
2147 u32 reg_type;
2148 struct iwl_fw_ini_region_tlv *reg;
2149
2150 if (!(BIT_ULL(i) & regions_mask))
2151 continue;
2152
2153 reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i];
2154 if (!reg_data.reg_tlv) {
2155 IWL_WARN(fwrt,
2156 "WRT: Unassigned region id %d, skipping\n", i);
2157 continue;
2158 }
2159
2160 reg = (void *)reg_data.reg_tlv->data;
2161 reg_type = le32_to_cpu(reg->type);
2162 if (reg_type >= ARRAY_SIZE(iwl_dump_ini_region_ops))
2163 continue;
2164
2165 size += iwl_dump_ini_mem(fwrt, list, &reg_data,
2166 &iwl_dump_ini_region_ops[reg_type]);
2167 }
2168
2169 if (size)
2170 size += iwl_dump_ini_info(fwrt, trigger, list);
2171
2172 return size;
2173 }
2174
2175 static bool iwl_fw_ini_trigger_on(struct iwl_fw_runtime *fwrt,
2176 struct iwl_fw_ini_trigger_tlv *trig)
2177 {
2178 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point);
2179 u32 usec = le32_to_cpu(trig->ignore_consec);
2180
2181 if (!iwl_trans_dbg_ini_valid(fwrt->trans) ||
2182 tp_id == IWL_FW_INI_TIME_POINT_INVALID ||
2183 tp_id >= IWL_FW_INI_TIME_POINT_NUM ||
2184 iwl_fw_dbg_no_trig_window(fwrt, tp_id, usec))
2185 return false;
2186
2187 return true;
2188 }
2189
2190 static u32 iwl_dump_ini_file_gen(struct iwl_fw_runtime *fwrt,
2191 struct iwl_fwrt_dump_data *dump_data,
2192 struct list_head *list)
2193 {
2194 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig;
2195 struct iwl_fw_ini_dump_entry *entry;
2196 struct iwl_fw_ini_dump_file_hdr *hdr;
2197 u32 size;
2198
2199 if (!trigger || !iwl_fw_ini_trigger_on(fwrt, trigger) ||
2200 !le64_to_cpu(trigger->regions_mask))
2201 return 0;
2202
2203 entry = vzalloc(sizeof(*entry) + sizeof(*hdr));
2204 if (!entry)
2205 return 0;
2206
2207 entry->size = sizeof(*hdr);
2208
2209 size = iwl_dump_ini_trigger(fwrt, dump_data, list);
2210 if (!size) {
2211 vfree(entry);
2212 return 0;
2213 }
2214
2215 hdr = (void *)entry->data;
2216 hdr->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER);
2217 hdr->file_len = cpu_to_le32(size + entry->size);
2218
2219 list_add(&entry->list, list);
2220
2221 return le32_to_cpu(hdr->file_len);
2222 }
2223
2224 static inline void iwl_fw_free_dump_desc(struct iwl_fw_runtime *fwrt,
2225 const struct iwl_fw_dump_desc *desc)
2226 {
2227 if (desc && desc != &iwl_dump_desc_assert)
2228 kfree(desc);
2229
2230 fwrt->dump.lmac_err_id[0] = 0;
2231 if (fwrt->smem_cfg.num_lmacs > 1)
2232 fwrt->dump.lmac_err_id[1] = 0;
2233 fwrt->dump.umac_err_id = 0;
2234 }
2235
2236 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt,
2237 struct iwl_fwrt_dump_data *dump_data)
2238 {
2239 struct iwl_fw_dump_ptrs fw_error_dump = {};
2240 struct iwl_fw_error_dump_file *dump_file;
2241 struct scatterlist *sg_dump_data;
2242 u32 file_len;
2243 u32 dump_mask = fwrt->fw->dbg.dump_mask;
2244
2245 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump, dump_data);
2246 if (!dump_file)
2247 return;
2248
2249 if (dump_data->monitor_only)
2250 dump_mask &= IWL_FW_ERROR_DUMP_FW_MONITOR;
2251
2252 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask);
2253 file_len = le32_to_cpu(dump_file->file_len);
2254 fw_error_dump.fwrt_len = file_len;
2255
2256 if (fw_error_dump.trans_ptr) {
2257 file_len += fw_error_dump.trans_ptr->len;
2258 dump_file->file_len = cpu_to_le32(file_len);
2259 }
2260
2261 sg_dump_data = alloc_sgtable(file_len);
2262 if (sg_dump_data) {
2263 sg_pcopy_from_buffer(sg_dump_data,
2264 sg_nents(sg_dump_data),
2265 fw_error_dump.fwrt_ptr,
2266 fw_error_dump.fwrt_len, 0);
2267 if (fw_error_dump.trans_ptr)
2268 sg_pcopy_from_buffer(sg_dump_data,
2269 sg_nents(sg_dump_data),
2270 fw_error_dump.trans_ptr->data,
2271 fw_error_dump.trans_ptr->len,
2272 fw_error_dump.fwrt_len);
2273 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len,
2274 GFP_KERNEL);
2275 }
2276 vfree(fw_error_dump.fwrt_ptr);
2277 vfree(fw_error_dump.trans_ptr);
2278 }
2279
2280 static void iwl_dump_ini_list_free(struct list_head *list)
2281 {
2282 while (!list_empty(list)) {
2283 struct iwl_fw_ini_dump_entry *entry =
2284 list_entry(list->next, typeof(*entry), list);
2285
2286 list_del(&entry->list);
2287 vfree(entry);
2288 }
2289 }
2290
2291 static void iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data *dump_data)
2292 {
2293 dump_data->trig = NULL;
2294 kfree(dump_data->fw_pkt);
2295 dump_data->fw_pkt = NULL;
2296 }
2297
2298 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt,
2299 struct iwl_fwrt_dump_data *dump_data)
2300 {
2301 struct list_head dump_list = LIST_HEAD_INIT(dump_list);
2302 struct scatterlist *sg_dump_data;
2303 u32 file_len = iwl_dump_ini_file_gen(fwrt, dump_data, &dump_list);
2304
2305 if (!file_len)
2306 return;
2307
2308 sg_dump_data = alloc_sgtable(file_len);
2309 if (sg_dump_data) {
2310 struct iwl_fw_ini_dump_entry *entry;
2311 int sg_entries = sg_nents(sg_dump_data);
2312 u32 offs = 0;
2313
2314 list_for_each_entry(entry, &dump_list, list) {
2315 sg_pcopy_from_buffer(sg_dump_data, sg_entries,
2316 entry->data, entry->size, offs);
2317 offs += entry->size;
2318 }
2319 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len,
2320 GFP_KERNEL);
2321 }
2322 iwl_dump_ini_list_free(&dump_list);
2323 }
2324
2325 const struct iwl_fw_dump_desc iwl_dump_desc_assert = {
2326 .trig_desc = {
2327 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT),
2328 },
2329 };
2330 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert);
2331
2332 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt,
2333 const struct iwl_fw_dump_desc *desc,
2334 bool monitor_only,
2335 unsigned int delay)
2336 {
2337 struct iwl_fwrt_wk_data *wk_data;
2338 unsigned long idx;
2339
2340 if (iwl_trans_dbg_ini_valid(fwrt->trans)) {
2341 iwl_fw_free_dump_desc(fwrt, desc);
2342 return 0;
2343 }
2344
2345 /*
2346 * Check there is an available worker.
2347 * ffz return value is undefined if no zero exists,
2348 * so check against ~0UL first.
2349 */
2350 if (fwrt->dump.active_wks == ~0UL)
2351 return -EBUSY;
2352
2353 idx = ffz(fwrt->dump.active_wks);
2354
2355 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM ||
2356 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks))
2357 return -EBUSY;
2358
2359 wk_data = &fwrt->dump.wks[idx];
2360
2361 if (WARN_ON(wk_data->dump_data.desc))
2362 iwl_fw_free_dump_desc(fwrt, wk_data->dump_data.desc);
2363
2364 wk_data->dump_data.desc = desc;
2365 wk_data->dump_data.monitor_only = monitor_only;
2366
2367 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n",
2368 le32_to_cpu(desc->trig_desc.type));
2369
2370 schedule_delayed_work(&wk_data->wk, usecs_to_jiffies(delay));
2371
2372 return 0;
2373 }
2374 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc);
2375
2376 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt,
2377 enum iwl_fw_dbg_trigger trig_type)
2378 {
2379 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status))
2380 return -EIO;
2381
2382 if (iwl_trans_dbg_ini_valid(fwrt->trans)) {
2383 if (trig_type != FW_DBG_TRIGGER_ALIVE_TIMEOUT)
2384 return -EIO;
2385
2386 iwl_dbg_tlv_time_point(fwrt,
2387 IWL_FW_INI_TIME_POINT_HOST_ALIVE_TIMEOUT,
2388 NULL);
2389 } else {
2390 struct iwl_fw_dump_desc *iwl_dump_error_desc;
2391 int ret;
2392
2393 iwl_dump_error_desc =
2394 kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL);
2395
2396 if (!iwl_dump_error_desc)
2397 return -ENOMEM;
2398
2399 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type);
2400 iwl_dump_error_desc->len = 0;
2401
2402 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc,
2403 false, 0);
2404 if (ret) {
2405 kfree(iwl_dump_error_desc);
2406 return ret;
2407 }
2408 }
2409
2410 iwl_trans_sync_nmi(fwrt->trans);
2411
2412 return 0;
2413 }
2414 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect);
2415
2416 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt,
2417 enum iwl_fw_dbg_trigger trig,
2418 const char *str, size_t len,
2419 struct iwl_fw_dbg_trigger_tlv *trigger)
2420 {
2421 struct iwl_fw_dump_desc *desc;
2422 unsigned int delay = 0;
2423 bool monitor_only = false;
2424
2425 if (trigger) {
2426 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1;
2427
2428 if (!le16_to_cpu(trigger->occurrences))
2429 return 0;
2430
2431 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) {
2432 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n",
2433 trig);
2434 iwl_force_nmi(fwrt->trans);
2435 return 0;
2436 }
2437
2438 trigger->occurrences = cpu_to_le16(occurrences);
2439 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY;
2440
2441 /* convert msec to usec */
2442 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC;
2443 }
2444
2445 desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC);
2446 if (!desc)
2447 return -ENOMEM;
2448
2449
2450 desc->len = len;
2451 desc->trig_desc.type = cpu_to_le32(trig);
2452 memcpy(desc->trig_desc.data, str, len);
2453
2454 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay);
2455 }
2456 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect);
2457
2458 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt,
2459 struct iwl_fwrt_dump_data *dump_data)
2460 {
2461 struct iwl_fw_ini_trigger_tlv *trig = dump_data->trig;
2462 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point);
2463 u32 occur, delay;
2464 unsigned long idx;
2465
2466 if (!iwl_fw_ini_trigger_on(fwrt, trig)) {
2467 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n",
2468 tp_id);
2469 return -EINVAL;
2470 }
2471
2472 delay = le32_to_cpu(trig->dump_delay);
2473 occur = le32_to_cpu(trig->occurrences);
2474 if (!occur)
2475 return 0;
2476
2477 trig->occurrences = cpu_to_le32(--occur);
2478
2479 /* Check there is an available worker.
2480 * ffz return value is undefined if no zero exists,
2481 * so check against ~0UL first.
2482 */
2483 if (fwrt->dump.active_wks == ~0UL)
2484 return -EBUSY;
2485
2486 idx = ffz(fwrt->dump.active_wks);
2487
2488 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM ||
2489 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks))
2490 return -EBUSY;
2491
2492 fwrt->dump.wks[idx].dump_data = *dump_data;
2493
2494 IWL_WARN(fwrt, "WRT: Collecting data: ini trigger %d fired.\n", tp_id);
2495
2496 schedule_delayed_work(&fwrt->dump.wks[idx].wk, usecs_to_jiffies(delay));
2497
2498 return 0;
2499 }
2500
2501 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt,
2502 struct iwl_fw_dbg_trigger_tlv *trigger,
2503 const char *fmt, ...)
2504 {
2505 int ret, len = 0;
2506 char buf[64];
2507
2508 if (iwl_trans_dbg_ini_valid(fwrt->trans))
2509 return 0;
2510
2511 if (fmt) {
2512 va_list ap;
2513
2514 buf[sizeof(buf) - 1] = '\0';
2515
2516 va_start(ap, fmt);
2517 vsnprintf(buf, sizeof(buf), fmt, ap);
2518 va_end(ap);
2519
2520 /* check for truncation */
2521 if (WARN_ON_ONCE(buf[sizeof(buf) - 1]))
2522 buf[sizeof(buf) - 1] = '\0';
2523
2524 len = strlen(buf) + 1;
2525 }
2526
2527 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len,
2528 trigger);
2529
2530 if (ret)
2531 return ret;
2532
2533 return 0;
2534 }
2535 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig);
2536
2537 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id)
2538 {
2539 u8 *ptr;
2540 int ret;
2541 int i;
2542
2543 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv),
2544 "Invalid configuration %d\n", conf_id))
2545 return -EINVAL;
2546
2547 /* EARLY START - firmware's configuration is hard coded */
2548 if ((!fwrt->fw->dbg.conf_tlv[conf_id] ||
2549 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) &&
2550 conf_id == FW_DBG_START_FROM_ALIVE)
2551 return 0;
2552
2553 if (!fwrt->fw->dbg.conf_tlv[conf_id])
2554 return -EINVAL;
2555
2556 if (fwrt->dump.conf != FW_DBG_INVALID)
2557 IWL_WARN(fwrt, "FW already configured (%d) - re-configuring\n",
2558 fwrt->dump.conf);
2559
2560 /* Send all HCMDs for configuring the FW debug */
2561 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd;
2562 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) {
2563 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr;
2564 struct iwl_host_cmd hcmd = {
2565 .id = cmd->id,
2566 .len = { le16_to_cpu(cmd->len), },
2567 .data = { cmd->data, },
2568 };
2569
2570 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
2571 if (ret)
2572 return ret;
2573
2574 ptr += sizeof(*cmd);
2575 ptr += le16_to_cpu(cmd->len);
2576 }
2577
2578 fwrt->dump.conf = conf_id;
2579
2580 return 0;
2581 }
2582 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf);
2583
2584 /* this function assumes dump_start was called beforehand and dump_end will be
2585 * called afterwards
2586 */
2587 static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx)
2588 {
2589 struct iwl_fw_dbg_params params = {0};
2590 struct iwl_fwrt_dump_data *dump_data =
2591 &fwrt->dump.wks[wk_idx].dump_data;
2592
2593 if (!test_bit(wk_idx, &fwrt->dump.active_wks))
2594 return;
2595
2596 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) {
2597 IWL_ERR(fwrt, "Device is not enabled - cannot dump error\n");
2598 goto out;
2599 }
2600
2601 /* there's no point in fw dump if the bus is dead */
2602 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) {
2603 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n");
2604 goto out;
2605 }
2606
2607 iwl_fw_dbg_stop_restart_recording(fwrt, &params, true);
2608
2609 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection start\n");
2610 if (iwl_trans_dbg_ini_valid(fwrt->trans))
2611 iwl_fw_error_ini_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data);
2612 else
2613 iwl_fw_error_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data);
2614 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection done\n");
2615
2616 iwl_fw_dbg_stop_restart_recording(fwrt, &params, false);
2617
2618 out:
2619 if (iwl_trans_dbg_ini_valid(fwrt->trans)) {
2620 iwl_fw_error_dump_data_free(dump_data);
2621 } else {
2622 iwl_fw_free_dump_desc(fwrt, dump_data->desc);
2623 dump_data->desc = NULL;
2624 }
2625
2626 clear_bit(wk_idx, &fwrt->dump.active_wks);
2627 }
2628
2629 void iwl_fw_error_dump_wk(struct work_struct *work)
2630 {
2631 struct iwl_fwrt_wk_data *wks =
2632 container_of(work, typeof(*wks), wk.work);
2633 struct iwl_fw_runtime *fwrt =
2634 container_of(wks, typeof(*fwrt), dump.wks[wks->idx]);
2635
2636 /* assumes the op mode mutex is locked in dump_start since
2637 * iwl_fw_dbg_collect_sync can't run in parallel
2638 */
2639 if (fwrt->ops && fwrt->ops->dump_start &&
2640 fwrt->ops->dump_start(fwrt->ops_ctx))
2641 return;
2642
2643 iwl_fw_dbg_collect_sync(fwrt, wks->idx);
2644
2645 if (fwrt->ops && fwrt->ops->dump_end)
2646 fwrt->ops->dump_end(fwrt->ops_ctx);
2647 }
2648
2649 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt)
2650 {
2651 const struct iwl_cfg *cfg = fwrt->trans->cfg;
2652
2653 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt))
2654 return;
2655
2656 if (!fwrt->dump.d3_debug_data) {
2657 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length,
2658 GFP_KERNEL);
2659 if (!fwrt->dump.d3_debug_data) {
2660 IWL_ERR(fwrt,
2661 "failed to allocate memory for D3 debug data\n");
2662 return;
2663 }
2664 }
2665
2666 /* if the buffer holds previous debug data it is overwritten */
2667 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr,
2668 fwrt->dump.d3_debug_data,
2669 cfg->d3_debug_data_length);
2670 }
2671 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data);
2672
2673 void iwl_fw_dbg_stop_sync(struct iwl_fw_runtime *fwrt)
2674 {
2675 int i;
2676
2677 iwl_dbg_tlv_del_timers(fwrt->trans);
2678 for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++)
2679 iwl_fw_dbg_collect_sync(fwrt, i);
2680
2681 iwl_fw_dbg_stop_restart_recording(fwrt, NULL, true);
2682 }
2683 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync);
2684
2685 #define FSEQ_REG(x) { .addr = (x), .str = #x, }
2686
2687 void iwl_fw_error_print_fseq_regs(struct iwl_fw_runtime *fwrt)
2688 {
2689 struct iwl_trans *trans = fwrt->trans;
2690 unsigned long flags;
2691 int i;
2692 struct {
2693 u32 addr;
2694 const char *str;
2695 } fseq_regs[] = {
2696 FSEQ_REG(FSEQ_ERROR_CODE),
2697 FSEQ_REG(FSEQ_TOP_INIT_VERSION),
2698 FSEQ_REG(FSEQ_CNVIO_INIT_VERSION),
2699 FSEQ_REG(FSEQ_OTP_VERSION),
2700 FSEQ_REG(FSEQ_TOP_CONTENT_VERSION),
2701 FSEQ_REG(FSEQ_ALIVE_TOKEN),
2702 FSEQ_REG(FSEQ_CNVI_ID),
2703 FSEQ_REG(FSEQ_CNVR_ID),
2704 FSEQ_REG(CNVI_AUX_MISC_CHIP),
2705 FSEQ_REG(CNVR_AUX_MISC_CHIP),
2706 FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_DIG_DCDC_VTRIM),
2707 FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR),
2708 };
2709
2710 if (!iwl_trans_grab_nic_access(trans, &flags))
2711 return;
2712
2713 IWL_ERR(fwrt, "Fseq Registers:\n");
2714
2715 for (i = 0; i < ARRAY_SIZE(fseq_regs); i++)
2716 IWL_ERR(fwrt, "0x%08X | %s\n",
2717 iwl_read_prph_no_grab(trans, fseq_regs[i].addr),
2718 fseq_regs[i].str);
2719
2720 iwl_trans_release_nic_access(trans, &flags);
2721 }
2722 IWL_EXPORT_SYMBOL(iwl_fw_error_print_fseq_regs);
2723
2724 static int iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans *trans, bool suspend)
2725 {
2726 struct iwl_dbg_suspend_resume_cmd cmd = {
2727 .operation = suspend ?
2728 cpu_to_le32(DBGC_SUSPEND_CMD) :
2729 cpu_to_le32(DBGC_RESUME_CMD),
2730 };
2731 struct iwl_host_cmd hcmd = {
2732 .id = WIDE_ID(DEBUG_GROUP, DBGC_SUSPEND_RESUME),
2733 .data[0] = &cmd,
2734 .len[0] = sizeof(cmd),
2735 };
2736
2737 return iwl_trans_send_cmd(trans, &hcmd);
2738 }
2739
2740 static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans,
2741 struct iwl_fw_dbg_params *params)
2742 {
2743 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
2744 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
2745 return;
2746 }
2747
2748 if (params) {
2749 params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE);
2750 params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL);
2751 }
2752
2753 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0);
2754 /* wait for the DBGC to finish writing the internal buffer to DRAM to
2755 * avoid halting the HW while writing
2756 */
2757 usleep_range(700, 1000);
2758 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0);
2759 }
2760
2761 static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans,
2762 struct iwl_fw_dbg_params *params)
2763 {
2764 if (!params)
2765 return -EIO;
2766
2767 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
2768 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
2769 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);
2770 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);
2771 } else {
2772 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample);
2773 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl);
2774 }
2775
2776 return 0;
2777 }
2778
2779 void iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt,
2780 struct iwl_fw_dbg_params *params,
2781 bool stop)
2782 {
2783 int ret __maybe_unused = 0;
2784
2785 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status))
2786 return;
2787
2788 if (fw_has_capa(&fwrt->fw->ucode_capa,
2789 IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP))
2790 ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop);
2791 else if (stop)
2792 iwl_fw_dbg_stop_recording(fwrt->trans, params);
2793 else
2794 ret = iwl_fw_dbg_restart_recording(fwrt->trans, params);
2795 #ifdef CONFIG_IWLWIFI_DEBUGFS
2796 if (!ret) {
2797 if (stop)
2798 fwrt->trans->dbg.rec_on = false;
2799 else
2800 iwl_fw_set_dbg_rec_on(fwrt);
2801 }
2802 #endif
2803 }
2804 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_restart_recording);
Ubuntu Jammy Linux kernel mirror