1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11 * Copyright(c) 2018 - 2019 Intel Corporation
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 * The full GNU General Public License is included in this distribution in the
23 * file called COPYING.
25 * Contact Information:
26 * Intel Linux Wireless <linuxwifi@intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
34 * Copyright(c) 2018 - 2019 Intel Corporation
35 * All rights reserved.
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
41 * * Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * * Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in
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47 * * Neither the name Intel Corporation nor the names of its
48 * contributors may be used to endorse or promote products derived
49 * from this software without specific prior written permission.
51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *****************************************************************************/
64 #include <linux/sched.h>
65 #include <linux/wait.h>
66 #include <linux/gfp.h>
71 #include "iwl-op-mode.h"
72 #include "iwl-context-info-gen3.h"
74 /******************************************************************************
78 ******************************************************************************/
81 * Rx theory of operation
83 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
84 * each of which point to Receive Buffers to be filled by the NIC. These get
85 * used not only for Rx frames, but for any command response or notification
86 * from the NIC. The driver and NIC manage the Rx buffers by means
87 * of indexes into the circular buffer.
90 * The host/firmware share two index registers for managing the Rx buffers.
92 * The READ index maps to the first position that the firmware may be writing
93 * to -- the driver can read up to (but not including) this position and get
95 * The READ index is managed by the firmware once the card is enabled.
97 * The WRITE index maps to the last position the driver has read from -- the
98 * position preceding WRITE is the last slot the firmware can place a packet.
100 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
103 * During initialization, the host sets up the READ queue position to the first
104 * INDEX position, and WRITE to the last (READ - 1 wrapped)
106 * When the firmware places a packet in a buffer, it will advance the READ index
107 * and fire the RX interrupt. The driver can then query the READ index and
108 * process as many packets as possible, moving the WRITE index forward as it
109 * resets the Rx queue buffers with new memory.
111 * The management in the driver is as follows:
112 * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free.
113 * When the interrupt handler is called, the request is processed.
114 * The page is either stolen - transferred to the upper layer
115 * or reused - added immediately to the iwl->rxq->rx_free list.
116 * + When the page is stolen - the driver updates the matching queue's used
117 * count, detaches the RBD and transfers it to the queue used list.
118 * When there are two used RBDs - they are transferred to the allocator empty
119 * list. Work is then scheduled for the allocator to start allocating
121 * When there are another 6 used RBDs - they are transferred to the allocator
122 * empty list and the driver tries to claim the pre-allocated buffers and
123 * add them to iwl->rxq->rx_free. If it fails - it continues to claim them
125 * When there are 8+ buffers in the free list - either from allocation or from
126 * 8 reused unstolen pages - restock is called to update the FW and indexes.
127 * + In order to make sure the allocator always has RBDs to use for allocation
128 * the allocator has initial pool in the size of num_queues*(8-2) - the
129 * maximum missing RBDs per allocation request (request posted with 2
130 * empty RBDs, there is no guarantee when the other 6 RBDs are supplied).
131 * The queues supplies the recycle of the rest of the RBDs.
132 * + A received packet is processed and handed to the kernel network stack,
133 * detached from the iwl->rxq. The driver 'processed' index is updated.
134 * + If there are no allocated buffers in iwl->rxq->rx_free,
135 * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.
136 * If there were enough free buffers and RX_STALLED is set it is cleared.
141 * iwl_rxq_alloc() Allocates rx_free
142 * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls
143 * iwl_pcie_rxq_restock.
144 * Used only during initialization.
145 * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx
146 * queue, updates firmware pointers, and updates
148 * iwl_pcie_rx_allocator() Background work for allocating pages.
150 * -- enable interrupts --
151 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
152 * READ INDEX, detaching the SKB from the pool.
153 * Moves the packet buffer from queue to rx_used.
154 * Posts and claims requests to the allocator.
155 * Calls iwl_pcie_rxq_restock to refill any empty
161 * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue
163 * Regular Receive interrupt:
165 * rxq.queue -> rxq.rx_used -> allocator.rbd_empty ->
166 * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue
168 * rxq.queue -> rxq.rx_free -> rxq.queue
174 * iwl_rxq_space - Return number of free slots available in queue.
176 static int iwl_rxq_space(const struct iwl_rxq
*rxq
)
178 /* Make sure rx queue size is a power of 2 */
179 WARN_ON(rxq
->queue_size
& (rxq
->queue_size
- 1));
182 * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity
183 * between empty and completely full queues.
184 * The following is equivalent to modulo by RX_QUEUE_SIZE and is well
185 * defined for negative dividends.
187 return (rxq
->read
- rxq
->write
- 1) & (rxq
->queue_size
- 1);
191 * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
193 static inline __le32
iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr
)
195 return cpu_to_le32((u32
)(dma_addr
>> 8));
199 * iwl_pcie_rx_stop - stops the Rx DMA
201 int iwl_pcie_rx_stop(struct iwl_trans
*trans
)
203 if (trans
->trans_cfg
->device_family
>= IWL_DEVICE_FAMILY_AX210
) {
204 /* TODO: remove this once fw does it */
205 iwl_write_umac_prph(trans
, RFH_RXF_DMA_CFG_GEN3
, 0);
206 return iwl_poll_umac_prph_bit(trans
, RFH_GEN_STATUS_GEN3
,
207 RXF_DMA_IDLE
, RXF_DMA_IDLE
, 1000);
208 } else if (trans
->trans_cfg
->mq_rx_supported
) {
209 iwl_write_prph(trans
, RFH_RXF_DMA_CFG
, 0);
210 return iwl_poll_prph_bit(trans
, RFH_GEN_STATUS
,
211 RXF_DMA_IDLE
, RXF_DMA_IDLE
, 1000);
213 iwl_write_direct32(trans
, FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
214 return iwl_poll_direct_bit(trans
, FH_MEM_RSSR_RX_STATUS_REG
,
215 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE
,
221 * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
223 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans
*trans
,
228 lockdep_assert_held(&rxq
->lock
);
231 * explicitly wake up the NIC if:
232 * 1. shadow registers aren't enabled
233 * 2. there is a chance that the NIC is asleep
235 if (!trans
->trans_cfg
->base_params
->shadow_reg_enable
&&
236 test_bit(STATUS_TPOWER_PMI
, &trans
->status
)) {
237 reg
= iwl_read32(trans
, CSR_UCODE_DRV_GP1
);
239 if (reg
& CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP
) {
240 IWL_DEBUG_INFO(trans
, "Rx queue requesting wakeup, GP1 = 0x%x\n",
242 iwl_set_bit(trans
, CSR_GP_CNTRL
,
243 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
244 rxq
->need_update
= true;
249 rxq
->write_actual
= round_down(rxq
->write
, 8);
250 if (trans
->trans_cfg
->mq_rx_supported
)
251 iwl_write32(trans
, RFH_Q_FRBDCB_WIDX_TRG(rxq
->id
),
254 iwl_write32(trans
, FH_RSCSR_CHNL0_WPTR
, rxq
->write_actual
);
257 static void iwl_pcie_rxq_check_wrptr(struct iwl_trans
*trans
)
259 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
262 for (i
= 0; i
< trans
->num_rx_queues
; i
++) {
263 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
[i
];
265 if (!rxq
->need_update
)
267 spin_lock(&rxq
->lock
);
268 iwl_pcie_rxq_inc_wr_ptr(trans
, rxq
);
269 rxq
->need_update
= false;
270 spin_unlock(&rxq
->lock
);
274 static void iwl_pcie_restock_bd(struct iwl_trans
*trans
,
276 struct iwl_rx_mem_buffer
*rxb
)
278 if (trans
->trans_cfg
->device_family
>= IWL_DEVICE_FAMILY_AX210
) {
279 struct iwl_rx_transfer_desc
*bd
= rxq
->bd
;
281 BUILD_BUG_ON(sizeof(*bd
) != 2 * sizeof(u64
));
283 bd
[rxq
->write
].addr
= cpu_to_le64(rxb
->page_dma
);
284 bd
[rxq
->write
].rbid
= cpu_to_le16(rxb
->vid
);
286 __le64
*bd
= rxq
->bd
;
288 bd
[rxq
->write
] = cpu_to_le64(rxb
->page_dma
| rxb
->vid
);
291 IWL_DEBUG_RX(trans
, "Assigned virtual RB ID %u to queue %d index %d\n",
292 (u32
)rxb
->vid
, rxq
->id
, rxq
->write
);
296 * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx
298 static void iwl_pcie_rxmq_restock(struct iwl_trans
*trans
,
301 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
302 struct iwl_rx_mem_buffer
*rxb
;
305 * If the device isn't enabled - no need to try to add buffers...
306 * This can happen when we stop the device and still have an interrupt
307 * pending. We stop the APM before we sync the interrupts because we
308 * have to (see comment there). On the other hand, since the APM is
309 * stopped, we cannot access the HW (in particular not prph).
310 * So don't try to restock if the APM has been already stopped.
312 if (!test_bit(STATUS_DEVICE_ENABLED
, &trans
->status
))
315 spin_lock(&rxq
->lock
);
316 while (rxq
->free_count
) {
317 /* Get next free Rx buffer, remove from free list */
318 rxb
= list_first_entry(&rxq
->rx_free
, struct iwl_rx_mem_buffer
,
320 list_del(&rxb
->list
);
321 rxb
->invalid
= false;
322 /* some low bits are expected to be unset (depending on hw) */
323 WARN_ON(rxb
->page_dma
& trans_pcie
->supported_dma_mask
);
324 /* Point to Rx buffer via next RBD in circular buffer */
325 iwl_pcie_restock_bd(trans
, rxq
, rxb
);
326 rxq
->write
= (rxq
->write
+ 1) & (rxq
->queue_size
- 1);
329 spin_unlock(&rxq
->lock
);
332 * If we've added more space for the firmware to place data, tell it.
333 * Increment device's write pointer in multiples of 8.
335 if (rxq
->write_actual
!= (rxq
->write
& ~0x7)) {
336 spin_lock(&rxq
->lock
);
337 iwl_pcie_rxq_inc_wr_ptr(trans
, rxq
);
338 spin_unlock(&rxq
->lock
);
343 * iwl_pcie_rxsq_restock - restock implementation for single queue rx
345 static void iwl_pcie_rxsq_restock(struct iwl_trans
*trans
,
348 struct iwl_rx_mem_buffer
*rxb
;
351 * If the device isn't enabled - not need to try to add buffers...
352 * This can happen when we stop the device and still have an interrupt
353 * pending. We stop the APM before we sync the interrupts because we
354 * have to (see comment there). On the other hand, since the APM is
355 * stopped, we cannot access the HW (in particular not prph).
356 * So don't try to restock if the APM has been already stopped.
358 if (!test_bit(STATUS_DEVICE_ENABLED
, &trans
->status
))
361 spin_lock(&rxq
->lock
);
362 while ((iwl_rxq_space(rxq
) > 0) && (rxq
->free_count
)) {
363 __le32
*bd
= (__le32
*)rxq
->bd
;
364 /* The overwritten rxb must be a used one */
365 rxb
= rxq
->queue
[rxq
->write
];
366 BUG_ON(rxb
&& rxb
->page
);
368 /* Get next free Rx buffer, remove from free list */
369 rxb
= list_first_entry(&rxq
->rx_free
, struct iwl_rx_mem_buffer
,
371 list_del(&rxb
->list
);
372 rxb
->invalid
= false;
374 /* Point to Rx buffer via next RBD in circular buffer */
375 bd
[rxq
->write
] = iwl_pcie_dma_addr2rbd_ptr(rxb
->page_dma
);
376 rxq
->queue
[rxq
->write
] = rxb
;
377 rxq
->write
= (rxq
->write
+ 1) & RX_QUEUE_MASK
;
380 spin_unlock(&rxq
->lock
);
382 /* If we've added more space for the firmware to place data, tell it.
383 * Increment device's write pointer in multiples of 8. */
384 if (rxq
->write_actual
!= (rxq
->write
& ~0x7)) {
385 spin_lock(&rxq
->lock
);
386 iwl_pcie_rxq_inc_wr_ptr(trans
, rxq
);
387 spin_unlock(&rxq
->lock
);
392 * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
394 * If there are slots in the RX queue that need to be restocked,
395 * and we have free pre-allocated buffers, fill the ranks as much
396 * as we can, pulling from rx_free.
398 * This moves the 'write' index forward to catch up with 'processed', and
399 * also updates the memory address in the firmware to reference the new
403 void iwl_pcie_rxq_restock(struct iwl_trans
*trans
, struct iwl_rxq
*rxq
)
405 if (trans
->trans_cfg
->mq_rx_supported
)
406 iwl_pcie_rxmq_restock(trans
, rxq
);
408 iwl_pcie_rxsq_restock(trans
, rxq
);
412 * iwl_pcie_rx_alloc_page - allocates and returns a page.
415 static struct page
*iwl_pcie_rx_alloc_page(struct iwl_trans
*trans
,
416 u32
*offset
, gfp_t priority
)
418 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
419 unsigned int rbsize
= iwl_trans_get_rb_size(trans_pcie
->rx_buf_size
);
420 unsigned int allocsize
= PAGE_SIZE
<< trans_pcie
->rx_page_order
;
422 gfp_t gfp_mask
= priority
;
424 if (trans_pcie
->rx_page_order
> 0)
425 gfp_mask
|= __GFP_COMP
;
427 if (trans_pcie
->alloc_page
) {
428 spin_lock_bh(&trans_pcie
->alloc_page_lock
);
430 if (trans_pcie
->alloc_page
) {
431 *offset
= trans_pcie
->alloc_page_used
;
432 page
= trans_pcie
->alloc_page
;
433 trans_pcie
->alloc_page_used
+= rbsize
;
434 if (trans_pcie
->alloc_page_used
>= allocsize
)
435 trans_pcie
->alloc_page
= NULL
;
438 spin_unlock_bh(&trans_pcie
->alloc_page_lock
);
441 spin_unlock_bh(&trans_pcie
->alloc_page_lock
);
444 /* Alloc a new receive buffer */
445 page
= alloc_pages(gfp_mask
, trans_pcie
->rx_page_order
);
448 IWL_DEBUG_INFO(trans
, "alloc_pages failed, order: %d\n",
449 trans_pcie
->rx_page_order
);
451 * Issue an error if we don't have enough pre-allocated
454 if (!(gfp_mask
& __GFP_NOWARN
) && net_ratelimit())
456 "Failed to alloc_pages\n");
460 if (2 * rbsize
<= allocsize
) {
461 spin_lock_bh(&trans_pcie
->alloc_page_lock
);
462 if (!trans_pcie
->alloc_page
) {
464 trans_pcie
->alloc_page
= page
;
465 trans_pcie
->alloc_page_used
= rbsize
;
467 spin_unlock_bh(&trans_pcie
->alloc_page_lock
);
475 * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
477 * A used RBD is an Rx buffer that has been given to the stack. To use it again
478 * a page must be allocated and the RBD must point to the page. This function
479 * doesn't change the HW pointer but handles the list of pages that is used by
480 * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
483 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans
*trans
, gfp_t priority
,
486 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
487 struct iwl_rx_mem_buffer
*rxb
;
493 spin_lock(&rxq
->lock
);
494 if (list_empty(&rxq
->rx_used
)) {
495 spin_unlock(&rxq
->lock
);
498 spin_unlock(&rxq
->lock
);
500 page
= iwl_pcie_rx_alloc_page(trans
, &offset
, priority
);
504 spin_lock(&rxq
->lock
);
506 if (list_empty(&rxq
->rx_used
)) {
507 spin_unlock(&rxq
->lock
);
508 __free_pages(page
, trans_pcie
->rx_page_order
);
511 rxb
= list_first_entry(&rxq
->rx_used
, struct iwl_rx_mem_buffer
,
513 list_del(&rxb
->list
);
514 spin_unlock(&rxq
->lock
);
518 rxb
->offset
= offset
;
519 /* Get physical address of the RB */
521 dma_map_page(trans
->dev
, page
, rxb
->offset
,
522 trans_pcie
->rx_buf_bytes
,
524 if (dma_mapping_error(trans
->dev
, rxb
->page_dma
)) {
526 spin_lock(&rxq
->lock
);
527 list_add(&rxb
->list
, &rxq
->rx_used
);
528 spin_unlock(&rxq
->lock
);
529 __free_pages(page
, trans_pcie
->rx_page_order
);
533 spin_lock(&rxq
->lock
);
535 list_add_tail(&rxb
->list
, &rxq
->rx_free
);
538 spin_unlock(&rxq
->lock
);
542 void iwl_pcie_free_rbs_pool(struct iwl_trans
*trans
)
544 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
547 for (i
= 0; i
< RX_POOL_SIZE(trans_pcie
->num_rx_bufs
); i
++) {
548 if (!trans_pcie
->rx_pool
[i
].page
)
550 dma_unmap_page(trans
->dev
, trans_pcie
->rx_pool
[i
].page_dma
,
551 trans_pcie
->rx_buf_bytes
, DMA_FROM_DEVICE
);
552 __free_pages(trans_pcie
->rx_pool
[i
].page
,
553 trans_pcie
->rx_page_order
);
554 trans_pcie
->rx_pool
[i
].page
= NULL
;
559 * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues
561 * Allocates for each received request 8 pages
562 * Called as a scheduled work item.
564 static void iwl_pcie_rx_allocator(struct iwl_trans
*trans
)
566 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
567 struct iwl_rb_allocator
*rba
= &trans_pcie
->rba
;
568 struct list_head local_empty
;
569 int pending
= atomic_read(&rba
->req_pending
);
571 IWL_DEBUG_TPT(trans
, "Pending allocation requests = %d\n", pending
);
573 /* If we were scheduled - there is at least one request */
574 spin_lock(&rba
->lock
);
575 /* swap out the rba->rbd_empty to a local list */
576 list_replace_init(&rba
->rbd_empty
, &local_empty
);
577 spin_unlock(&rba
->lock
);
581 LIST_HEAD(local_allocated
);
582 gfp_t gfp_mask
= GFP_KERNEL
;
584 /* Do not post a warning if there are only a few requests */
585 if (pending
< RX_PENDING_WATERMARK
)
586 gfp_mask
|= __GFP_NOWARN
;
588 for (i
= 0; i
< RX_CLAIM_REQ_ALLOC
;) {
589 struct iwl_rx_mem_buffer
*rxb
;
592 /* List should never be empty - each reused RBD is
593 * returned to the list, and initial pool covers any
594 * possible gap between the time the page is allocated
595 * to the time the RBD is added.
597 BUG_ON(list_empty(&local_empty
));
598 /* Get the first rxb from the rbd list */
599 rxb
= list_first_entry(&local_empty
,
600 struct iwl_rx_mem_buffer
, list
);
603 /* Alloc a new receive buffer */
604 page
= iwl_pcie_rx_alloc_page(trans
, &rxb
->offset
,
610 /* Get physical address of the RB */
611 rxb
->page_dma
= dma_map_page(trans
->dev
, page
,
613 trans_pcie
->rx_buf_bytes
,
615 if (dma_mapping_error(trans
->dev
, rxb
->page_dma
)) {
617 __free_pages(page
, trans_pcie
->rx_page_order
);
621 /* move the allocated entry to the out list */
622 list_move(&rxb
->list
, &local_allocated
);
626 atomic_dec(&rba
->req_pending
);
630 pending
= atomic_read(&rba
->req_pending
);
633 "Got more pending allocation requests = %d\n",
637 spin_lock(&rba
->lock
);
638 /* add the allocated rbds to the allocator allocated list */
639 list_splice_tail(&local_allocated
, &rba
->rbd_allocated
);
640 /* get more empty RBDs for current pending requests */
641 list_splice_tail_init(&rba
->rbd_empty
, &local_empty
);
642 spin_unlock(&rba
->lock
);
644 atomic_inc(&rba
->req_ready
);
648 spin_lock(&rba
->lock
);
649 /* return unused rbds to the allocator empty list */
650 list_splice_tail(&local_empty
, &rba
->rbd_empty
);
651 spin_unlock(&rba
->lock
);
653 IWL_DEBUG_TPT(trans
, "%s, exit.\n", __func__
);
657 * iwl_pcie_rx_allocator_get - returns the pre-allocated pages
659 .* Called by queue when the queue posted allocation request and
660 * has freed 8 RBDs in order to restock itself.
661 * This function directly moves the allocated RBs to the queue's ownership
662 * and updates the relevant counters.
664 static void iwl_pcie_rx_allocator_get(struct iwl_trans
*trans
,
667 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
668 struct iwl_rb_allocator
*rba
= &trans_pcie
->rba
;
671 lockdep_assert_held(&rxq
->lock
);
674 * atomic_dec_if_positive returns req_ready - 1 for any scenario.
675 * If req_ready is 0 atomic_dec_if_positive will return -1 and this
676 * function will return early, as there are no ready requests.
677 * atomic_dec_if_positive will perofrm the *actual* decrement only if
678 * req_ready > 0, i.e. - there are ready requests and the function
679 * hands one request to the caller.
681 if (atomic_dec_if_positive(&rba
->req_ready
) < 0)
684 spin_lock(&rba
->lock
);
685 for (i
= 0; i
< RX_CLAIM_REQ_ALLOC
; i
++) {
686 /* Get next free Rx buffer, remove it from free list */
687 struct iwl_rx_mem_buffer
*rxb
=
688 list_first_entry(&rba
->rbd_allocated
,
689 struct iwl_rx_mem_buffer
, list
);
691 list_move(&rxb
->list
, &rxq
->rx_free
);
693 spin_unlock(&rba
->lock
);
695 rxq
->used_count
-= RX_CLAIM_REQ_ALLOC
;
696 rxq
->free_count
+= RX_CLAIM_REQ_ALLOC
;
699 void iwl_pcie_rx_allocator_work(struct work_struct
*data
)
701 struct iwl_rb_allocator
*rba_p
=
702 container_of(data
, struct iwl_rb_allocator
, rx_alloc
);
703 struct iwl_trans_pcie
*trans_pcie
=
704 container_of(rba_p
, struct iwl_trans_pcie
, rba
);
706 iwl_pcie_rx_allocator(trans_pcie
->trans
);
709 static int iwl_pcie_free_bd_size(struct iwl_trans
*trans
, bool use_rx_td
)
711 struct iwl_rx_transfer_desc
*rx_td
;
714 return sizeof(*rx_td
);
716 return trans
->trans_cfg
->mq_rx_supported
? sizeof(__le64
) :
720 static void iwl_pcie_free_rxq_dma(struct iwl_trans
*trans
,
723 struct device
*dev
= trans
->dev
;
724 bool use_rx_td
= (trans
->trans_cfg
->device_family
>=
725 IWL_DEVICE_FAMILY_AX210
);
726 int free_size
= iwl_pcie_free_bd_size(trans
, use_rx_td
);
729 dma_free_coherent(trans
->dev
,
730 free_size
* rxq
->queue_size
,
731 rxq
->bd
, rxq
->bd_dma
);
735 rxq
->rb_stts_dma
= 0;
739 dma_free_coherent(trans
->dev
,
740 (use_rx_td
? sizeof(*rxq
->cd
) :
741 sizeof(__le32
)) * rxq
->queue_size
,
742 rxq
->used_bd
, rxq
->used_bd_dma
);
743 rxq
->used_bd_dma
= 0;
746 if (trans
->trans_cfg
->device_family
< IWL_DEVICE_FAMILY_AX210
)
750 dma_free_coherent(dev
, sizeof(__le16
),
751 rxq
->tr_tail
, rxq
->tr_tail_dma
);
752 rxq
->tr_tail_dma
= 0;
756 dma_free_coherent(dev
, sizeof(__le16
),
757 rxq
->cr_tail
, rxq
->cr_tail_dma
);
758 rxq
->cr_tail_dma
= 0;
762 static int iwl_pcie_alloc_rxq_dma(struct iwl_trans
*trans
,
765 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
766 struct device
*dev
= trans
->dev
;
769 bool use_rx_td
= (trans
->trans_cfg
->device_family
>=
770 IWL_DEVICE_FAMILY_AX210
);
771 size_t rb_stts_size
= use_rx_td
? sizeof(__le16
) :
772 sizeof(struct iwl_rb_status
);
774 spin_lock_init(&rxq
->lock
);
775 if (trans
->trans_cfg
->mq_rx_supported
)
776 rxq
->queue_size
= trans
->cfg
->num_rbds
;
778 rxq
->queue_size
= RX_QUEUE_SIZE
;
780 free_size
= iwl_pcie_free_bd_size(trans
, use_rx_td
);
783 * Allocate the circular buffer of Read Buffer Descriptors
786 rxq
->bd
= dma_alloc_coherent(dev
, free_size
* rxq
->queue_size
,
787 &rxq
->bd_dma
, GFP_KERNEL
);
791 if (trans
->trans_cfg
->mq_rx_supported
) {
792 rxq
->used_bd
= dma_alloc_coherent(dev
,
793 (use_rx_td
? sizeof(*rxq
->cd
) : sizeof(__le32
)) * rxq
->queue_size
,
800 rxq
->rb_stts
= trans_pcie
->base_rb_stts
+ rxq
->id
* rb_stts_size
;
802 trans_pcie
->base_rb_stts_dma
+ rxq
->id
* rb_stts_size
;
807 /* Allocate the driver's pointer to TR tail */
808 rxq
->tr_tail
= dma_alloc_coherent(dev
, sizeof(__le16
),
809 &rxq
->tr_tail_dma
, GFP_KERNEL
);
813 /* Allocate the driver's pointer to CR tail */
814 rxq
->cr_tail
= dma_alloc_coherent(dev
, sizeof(__le16
),
815 &rxq
->cr_tail_dma
, GFP_KERNEL
);
822 for (i
= 0; i
< trans
->num_rx_queues
; i
++) {
823 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
[i
];
825 iwl_pcie_free_rxq_dma(trans
, rxq
);
831 static int iwl_pcie_rx_alloc(struct iwl_trans
*trans
)
833 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
834 struct iwl_rb_allocator
*rba
= &trans_pcie
->rba
;
836 size_t rb_stts_size
= trans
->trans_cfg
->device_family
>=
837 IWL_DEVICE_FAMILY_AX210
?
838 sizeof(__le16
) : sizeof(struct iwl_rb_status
);
840 if (WARN_ON(trans_pcie
->rxq
))
843 trans_pcie
->rxq
= kcalloc(trans
->num_rx_queues
, sizeof(struct iwl_rxq
),
845 trans_pcie
->rx_pool
= kcalloc(RX_POOL_SIZE(trans_pcie
->num_rx_bufs
),
846 sizeof(trans_pcie
->rx_pool
[0]),
848 trans_pcie
->global_table
=
849 kcalloc(RX_POOL_SIZE(trans_pcie
->num_rx_bufs
),
850 sizeof(trans_pcie
->global_table
[0]),
852 if (!trans_pcie
->rxq
|| !trans_pcie
->rx_pool
||
853 !trans_pcie
->global_table
) {
858 spin_lock_init(&rba
->lock
);
861 * Allocate the driver's pointer to receive buffer status.
862 * Allocate for all queues continuously (HW requirement).
864 trans_pcie
->base_rb_stts
=
865 dma_alloc_coherent(trans
->dev
,
866 rb_stts_size
* trans
->num_rx_queues
,
867 &trans_pcie
->base_rb_stts_dma
,
869 if (!trans_pcie
->base_rb_stts
) {
874 for (i
= 0; i
< trans
->num_rx_queues
; i
++) {
875 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
[i
];
878 ret
= iwl_pcie_alloc_rxq_dma(trans
, rxq
);
885 if (trans_pcie
->base_rb_stts
) {
886 dma_free_coherent(trans
->dev
,
887 rb_stts_size
* trans
->num_rx_queues
,
888 trans_pcie
->base_rb_stts
,
889 trans_pcie
->base_rb_stts_dma
);
890 trans_pcie
->base_rb_stts
= NULL
;
891 trans_pcie
->base_rb_stts_dma
= 0;
893 kfree(trans_pcie
->rx_pool
);
894 kfree(trans_pcie
->global_table
);
895 kfree(trans_pcie
->rxq
);
900 static void iwl_pcie_rx_hw_init(struct iwl_trans
*trans
, struct iwl_rxq
*rxq
)
902 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
905 const u32 rfdnlog
= RX_QUEUE_SIZE_LOG
; /* 256 RBDs */
907 switch (trans_pcie
->rx_buf_size
) {
909 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K
;
912 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K
;
915 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K
;
919 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K
;
922 if (!iwl_trans_grab_nic_access(trans
, &flags
))
926 iwl_write32(trans
, FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
927 /* reset and flush pointers */
928 iwl_write32(trans
, FH_MEM_RCSR_CHNL0_RBDCB_WPTR
, 0);
929 iwl_write32(trans
, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ
, 0);
930 iwl_write32(trans
, FH_RSCSR_CHNL0_RDPTR
, 0);
932 /* Reset driver's Rx queue write index */
933 iwl_write32(trans
, FH_RSCSR_CHNL0_RBDCB_WPTR_REG
, 0);
935 /* Tell device where to find RBD circular buffer in DRAM */
936 iwl_write32(trans
, FH_RSCSR_CHNL0_RBDCB_BASE_REG
,
937 (u32
)(rxq
->bd_dma
>> 8));
939 /* Tell device where in DRAM to update its Rx status */
940 iwl_write32(trans
, FH_RSCSR_CHNL0_STTS_WPTR_REG
,
941 rxq
->rb_stts_dma
>> 4);
944 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
945 * the credit mechanism in 5000 HW RX FIFO
946 * Direct rx interrupts to hosts
947 * Rx buffer size 4 or 8k or 12k
951 iwl_write32(trans
, FH_MEM_RCSR_CHNL0_CONFIG_REG
,
952 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL
|
953 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY
|
954 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL
|
956 (RX_RB_TIMEOUT
<< FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS
) |
957 (rfdnlog
<< FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS
));
959 iwl_trans_release_nic_access(trans
, &flags
);
961 /* Set interrupt coalescing timer to default (2048 usecs) */
962 iwl_write8(trans
, CSR_INT_COALESCING
, IWL_HOST_INT_TIMEOUT_DEF
);
964 /* W/A for interrupt coalescing bug in 7260 and 3160 */
965 if (trans
->cfg
->host_interrupt_operation_mode
)
966 iwl_set_bit(trans
, CSR_INT_COALESCING
, IWL_HOST_INT_OPER_MODE
);
969 static void iwl_pcie_rx_mq_hw_init(struct iwl_trans
*trans
)
971 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
972 u32 rb_size
, enabled
= 0;
976 switch (trans_pcie
->rx_buf_size
) {
978 rb_size
= RFH_RXF_DMA_RB_SIZE_2K
;
981 rb_size
= RFH_RXF_DMA_RB_SIZE_4K
;
984 rb_size
= RFH_RXF_DMA_RB_SIZE_8K
;
987 rb_size
= RFH_RXF_DMA_RB_SIZE_12K
;
991 rb_size
= RFH_RXF_DMA_RB_SIZE_4K
;
994 if (!iwl_trans_grab_nic_access(trans
, &flags
))
998 iwl_write_prph_no_grab(trans
, RFH_RXF_DMA_CFG
, 0);
999 /* disable free amd used rx queue operation */
1000 iwl_write_prph_no_grab(trans
, RFH_RXF_RXQ_ACTIVE
, 0);
1002 for (i
= 0; i
< trans
->num_rx_queues
; i
++) {
1003 /* Tell device where to find RBD free table in DRAM */
1004 iwl_write_prph64_no_grab(trans
,
1005 RFH_Q_FRBDCB_BA_LSB(i
),
1006 trans_pcie
->rxq
[i
].bd_dma
);
1007 /* Tell device where to find RBD used table in DRAM */
1008 iwl_write_prph64_no_grab(trans
,
1009 RFH_Q_URBDCB_BA_LSB(i
),
1010 trans_pcie
->rxq
[i
].used_bd_dma
);
1011 /* Tell device where in DRAM to update its Rx status */
1012 iwl_write_prph64_no_grab(trans
,
1013 RFH_Q_URBD_STTS_WPTR_LSB(i
),
1014 trans_pcie
->rxq
[i
].rb_stts_dma
);
1015 /* Reset device indice tables */
1016 iwl_write_prph_no_grab(trans
, RFH_Q_FRBDCB_WIDX(i
), 0);
1017 iwl_write_prph_no_grab(trans
, RFH_Q_FRBDCB_RIDX(i
), 0);
1018 iwl_write_prph_no_grab(trans
, RFH_Q_URBDCB_WIDX(i
), 0);
1020 enabled
|= BIT(i
) | BIT(i
+ 16);
1025 * Rx buffer size 4 or 8k or 12k
1026 * Min RB size 4 or 8
1027 * Drop frames that exceed RB size
1030 iwl_write_prph_no_grab(trans
, RFH_RXF_DMA_CFG
,
1031 RFH_DMA_EN_ENABLE_VAL
| rb_size
|
1032 RFH_RXF_DMA_MIN_RB_4_8
|
1033 RFH_RXF_DMA_DROP_TOO_LARGE_MASK
|
1034 RFH_RXF_DMA_RBDCB_SIZE_512
);
1037 * Activate DMA snooping.
1038 * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe
1039 * Default queue is 0
1041 iwl_write_prph_no_grab(trans
, RFH_GEN_CFG
,
1042 RFH_GEN_CFG_RFH_DMA_SNOOP
|
1043 RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM
, 0) |
1044 RFH_GEN_CFG_SERVICE_DMA_SNOOP
|
1045 RFH_GEN_CFG_VAL(RB_CHUNK_SIZE
,
1046 trans
->trans_cfg
->integrated
?
1047 RFH_GEN_CFG_RB_CHUNK_SIZE_64
:
1048 RFH_GEN_CFG_RB_CHUNK_SIZE_128
));
1049 /* Enable the relevant rx queues */
1050 iwl_write_prph_no_grab(trans
, RFH_RXF_RXQ_ACTIVE
, enabled
);
1052 iwl_trans_release_nic_access(trans
, &flags
);
1054 /* Set interrupt coalescing timer to default (2048 usecs) */
1055 iwl_write8(trans
, CSR_INT_COALESCING
, IWL_HOST_INT_TIMEOUT_DEF
);
1058 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq
*rxq
)
1060 lockdep_assert_held(&rxq
->lock
);
1062 INIT_LIST_HEAD(&rxq
->rx_free
);
1063 INIT_LIST_HEAD(&rxq
->rx_used
);
1064 rxq
->free_count
= 0;
1065 rxq
->used_count
= 0;
1068 int iwl_pcie_dummy_napi_poll(struct napi_struct
*napi
, int budget
)
1074 static int _iwl_pcie_rx_init(struct iwl_trans
*trans
)
1076 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1077 struct iwl_rxq
*def_rxq
;
1078 struct iwl_rb_allocator
*rba
= &trans_pcie
->rba
;
1079 int i
, err
, queue_size
, allocator_pool_size
, num_alloc
;
1081 if (!trans_pcie
->rxq
) {
1082 err
= iwl_pcie_rx_alloc(trans
);
1086 def_rxq
= trans_pcie
->rxq
;
1088 cancel_work_sync(&rba
->rx_alloc
);
1090 spin_lock(&rba
->lock
);
1091 atomic_set(&rba
->req_pending
, 0);
1092 atomic_set(&rba
->req_ready
, 0);
1093 INIT_LIST_HEAD(&rba
->rbd_allocated
);
1094 INIT_LIST_HEAD(&rba
->rbd_empty
);
1095 spin_unlock(&rba
->lock
);
1097 /* free all first - we might be reconfigured for a different size */
1098 iwl_pcie_free_rbs_pool(trans
);
1100 for (i
= 0; i
< RX_QUEUE_SIZE
; i
++)
1101 def_rxq
->queue
[i
] = NULL
;
1103 for (i
= 0; i
< trans
->num_rx_queues
; i
++) {
1104 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
[i
];
1106 spin_lock(&rxq
->lock
);
1108 * Set read write pointer to reflect that we have processed
1109 * and used all buffers, but have not restocked the Rx queue
1110 * with fresh buffers
1114 rxq
->write_actual
= 0;
1115 memset(rxq
->rb_stts
, 0,
1116 (trans
->trans_cfg
->device_family
>=
1117 IWL_DEVICE_FAMILY_AX210
) ?
1118 sizeof(__le16
) : sizeof(struct iwl_rb_status
));
1120 iwl_pcie_rx_init_rxb_lists(rxq
);
1122 if (!rxq
->napi
.poll
)
1123 netif_napi_add(&trans_pcie
->napi_dev
, &rxq
->napi
,
1124 iwl_pcie_dummy_napi_poll
, 64);
1126 spin_unlock(&rxq
->lock
);
1129 /* move the pool to the default queue and allocator ownerships */
1130 queue_size
= trans
->trans_cfg
->mq_rx_supported
?
1131 trans_pcie
->num_rx_bufs
- 1 : RX_QUEUE_SIZE
;
1132 allocator_pool_size
= trans
->num_rx_queues
*
1133 (RX_CLAIM_REQ_ALLOC
- RX_POST_REQ_ALLOC
);
1134 num_alloc
= queue_size
+ allocator_pool_size
;
1136 for (i
= 0; i
< num_alloc
; i
++) {
1137 struct iwl_rx_mem_buffer
*rxb
= &trans_pcie
->rx_pool
[i
];
1139 if (i
< allocator_pool_size
)
1140 list_add(&rxb
->list
, &rba
->rbd_empty
);
1142 list_add(&rxb
->list
, &def_rxq
->rx_used
);
1143 trans_pcie
->global_table
[i
] = rxb
;
1144 rxb
->vid
= (u16
)(i
+ 1);
1145 rxb
->invalid
= true;
1148 iwl_pcie_rxq_alloc_rbs(trans
, GFP_KERNEL
, def_rxq
);
1153 int iwl_pcie_rx_init(struct iwl_trans
*trans
)
1155 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1156 int ret
= _iwl_pcie_rx_init(trans
);
1161 if (trans
->trans_cfg
->mq_rx_supported
)
1162 iwl_pcie_rx_mq_hw_init(trans
);
1164 iwl_pcie_rx_hw_init(trans
, trans_pcie
->rxq
);
1166 iwl_pcie_rxq_restock(trans
, trans_pcie
->rxq
);
1168 spin_lock(&trans_pcie
->rxq
->lock
);
1169 iwl_pcie_rxq_inc_wr_ptr(trans
, trans_pcie
->rxq
);
1170 spin_unlock(&trans_pcie
->rxq
->lock
);
1175 int iwl_pcie_gen2_rx_init(struct iwl_trans
*trans
)
1177 /* Set interrupt coalescing timer to default (2048 usecs) */
1178 iwl_write8(trans
, CSR_INT_COALESCING
, IWL_HOST_INT_TIMEOUT_DEF
);
1181 * We don't configure the RFH.
1182 * Restock will be done at alive, after firmware configured the RFH.
1184 return _iwl_pcie_rx_init(trans
);
1187 void iwl_pcie_rx_free(struct iwl_trans
*trans
)
1189 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1190 struct iwl_rb_allocator
*rba
= &trans_pcie
->rba
;
1192 size_t rb_stts_size
= trans
->trans_cfg
->device_family
>=
1193 IWL_DEVICE_FAMILY_AX210
?
1194 sizeof(__le16
) : sizeof(struct iwl_rb_status
);
1197 * if rxq is NULL, it means that nothing has been allocated,
1200 if (!trans_pcie
->rxq
) {
1201 IWL_DEBUG_INFO(trans
, "Free NULL rx context\n");
1205 cancel_work_sync(&rba
->rx_alloc
);
1207 iwl_pcie_free_rbs_pool(trans
);
1209 if (trans_pcie
->base_rb_stts
) {
1210 dma_free_coherent(trans
->dev
,
1211 rb_stts_size
* trans
->num_rx_queues
,
1212 trans_pcie
->base_rb_stts
,
1213 trans_pcie
->base_rb_stts_dma
);
1214 trans_pcie
->base_rb_stts
= NULL
;
1215 trans_pcie
->base_rb_stts_dma
= 0;
1218 for (i
= 0; i
< trans
->num_rx_queues
; i
++) {
1219 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
[i
];
1221 iwl_pcie_free_rxq_dma(trans
, rxq
);
1224 netif_napi_del(&rxq
->napi
);
1226 kfree(trans_pcie
->rx_pool
);
1227 kfree(trans_pcie
->global_table
);
1228 kfree(trans_pcie
->rxq
);
1230 if (trans_pcie
->alloc_page
)
1231 __free_pages(trans_pcie
->alloc_page
, trans_pcie
->rx_page_order
);
1234 static void iwl_pcie_rx_move_to_allocator(struct iwl_rxq
*rxq
,
1235 struct iwl_rb_allocator
*rba
)
1237 spin_lock(&rba
->lock
);
1238 list_splice_tail_init(&rxq
->rx_used
, &rba
->rbd_empty
);
1239 spin_unlock(&rba
->lock
);
1243 * iwl_pcie_rx_reuse_rbd - Recycle used RBDs
1245 * Called when a RBD can be reused. The RBD is transferred to the allocator.
1246 * When there are 2 empty RBDs - a request for allocation is posted
1248 static void iwl_pcie_rx_reuse_rbd(struct iwl_trans
*trans
,
1249 struct iwl_rx_mem_buffer
*rxb
,
1250 struct iwl_rxq
*rxq
, bool emergency
)
1252 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1253 struct iwl_rb_allocator
*rba
= &trans_pcie
->rba
;
1255 /* Move the RBD to the used list, will be moved to allocator in batches
1256 * before claiming or posting a request*/
1257 list_add_tail(&rxb
->list
, &rxq
->rx_used
);
1259 if (unlikely(emergency
))
1262 /* Count the allocator owned RBDs */
1265 /* If we have RX_POST_REQ_ALLOC new released rx buffers -
1266 * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is
1267 * used for the case we failed to claim RX_CLAIM_REQ_ALLOC,
1268 * after but we still need to post another request.
1270 if ((rxq
->used_count
% RX_CLAIM_REQ_ALLOC
) == RX_POST_REQ_ALLOC
) {
1271 /* Move the 2 RBDs to the allocator ownership.
1272 Allocator has another 6 from pool for the request completion*/
1273 iwl_pcie_rx_move_to_allocator(rxq
, rba
);
1275 atomic_inc(&rba
->req_pending
);
1276 queue_work(rba
->alloc_wq
, &rba
->rx_alloc
);
1280 static void iwl_pcie_rx_handle_rb(struct iwl_trans
*trans
,
1281 struct iwl_rxq
*rxq
,
1282 struct iwl_rx_mem_buffer
*rxb
,
1286 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1287 struct iwl_txq
*txq
= trans
->txqs
.txq
[trans
->txqs
.cmd
.q_id
];
1288 bool page_stolen
= false;
1289 int max_len
= trans_pcie
->rx_buf_bytes
;
1295 dma_unmap_page(trans
->dev
, rxb
->page_dma
, max_len
, DMA_FROM_DEVICE
);
1297 while (offset
+ sizeof(u32
) + sizeof(struct iwl_cmd_header
) < max_len
) {
1298 struct iwl_rx_packet
*pkt
;
1301 int index
, cmd_index
, len
;
1302 struct iwl_rx_cmd_buffer rxcb
= {
1303 ._offset
= rxb
->offset
+ offset
,
1304 ._rx_page_order
= trans_pcie
->rx_page_order
,
1306 ._page_stolen
= false,
1307 .truesize
= max_len
,
1310 pkt
= rxb_addr(&rxcb
);
1312 if (pkt
->len_n_flags
== cpu_to_le32(FH_RSCSR_FRAME_INVALID
)) {
1314 "Q %d: RB end marker at offset %d\n",
1319 WARN((le32_to_cpu(pkt
->len_n_flags
) & FH_RSCSR_RXQ_MASK
) >>
1320 FH_RSCSR_RXQ_POS
!= rxq
->id
,
1321 "frame on invalid queue - is on %d and indicates %d\n",
1323 (le32_to_cpu(pkt
->len_n_flags
) & FH_RSCSR_RXQ_MASK
) >>
1327 "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n",
1329 iwl_get_cmd_string(trans
,
1330 iwl_cmd_id(pkt
->hdr
.cmd
,
1333 pkt
->hdr
.group_id
, pkt
->hdr
.cmd
,
1334 le16_to_cpu(pkt
->hdr
.sequence
));
1336 len
= iwl_rx_packet_len(pkt
);
1337 len
+= sizeof(u32
); /* account for status word */
1339 offset
+= ALIGN(len
, FH_RSCSR_FRAME_ALIGN
);
1341 /* check that what the device tells us made sense */
1342 if (offset
> max_len
)
1345 trace_iwlwifi_dev_rx(trans
->dev
, trans
, pkt
, len
);
1346 trace_iwlwifi_dev_rx_data(trans
->dev
, trans
, pkt
, len
);
1348 /* Reclaim a command buffer only if this packet is a response
1349 * to a (driver-originated) command.
1350 * If the packet (e.g. Rx frame) originated from uCode,
1351 * there is no command buffer to reclaim.
1352 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1353 * but apparently a few don't get set; catch them here. */
1354 reclaim
= !(pkt
->hdr
.sequence
& SEQ_RX_FRAME
);
1355 if (reclaim
&& !pkt
->hdr
.group_id
) {
1358 for (i
= 0; i
< trans_pcie
->n_no_reclaim_cmds
; i
++) {
1359 if (trans_pcie
->no_reclaim_cmds
[i
] ==
1367 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
1368 index
= SEQ_TO_INDEX(sequence
);
1369 cmd_index
= iwl_txq_get_cmd_index(txq
, index
);
1371 if (rxq
->id
== trans_pcie
->def_rx_queue
)
1372 iwl_op_mode_rx(trans
->op_mode
, &rxq
->napi
,
1375 iwl_op_mode_rx_rss(trans
->op_mode
, &rxq
->napi
,
1379 kfree_sensitive(txq
->entries
[cmd_index
].free_buf
);
1380 txq
->entries
[cmd_index
].free_buf
= NULL
;
1384 * After here, we should always check rxcb._page_stolen,
1385 * if it is true then one of the handlers took the page.
1389 /* Invoke any callbacks, transfer the buffer to caller,
1390 * and fire off the (possibly) blocking
1391 * iwl_trans_send_cmd()
1392 * as we reclaim the driver command queue */
1393 if (!rxcb
._page_stolen
)
1394 iwl_pcie_hcmd_complete(trans
, &rxcb
);
1396 IWL_WARN(trans
, "Claim null rxb?\n");
1399 page_stolen
|= rxcb
._page_stolen
;
1400 if (trans
->trans_cfg
->device_family
>= IWL_DEVICE_FAMILY_AX210
)
1404 /* page was stolen from us -- free our reference */
1406 __free_pages(rxb
->page
, trans_pcie
->rx_page_order
);
1410 /* Reuse the page if possible. For notification packets and
1411 * SKBs that fail to Rx correctly, add them back into the
1412 * rx_free list for reuse later. */
1413 if (rxb
->page
!= NULL
) {
1415 dma_map_page(trans
->dev
, rxb
->page
, rxb
->offset
,
1416 trans_pcie
->rx_buf_bytes
,
1418 if (dma_mapping_error(trans
->dev
, rxb
->page_dma
)) {
1420 * free the page(s) as well to not break
1421 * the invariant that the items on the used
1422 * list have no page(s)
1424 __free_pages(rxb
->page
, trans_pcie
->rx_page_order
);
1426 iwl_pcie_rx_reuse_rbd(trans
, rxb
, rxq
, emergency
);
1428 list_add_tail(&rxb
->list
, &rxq
->rx_free
);
1432 iwl_pcie_rx_reuse_rbd(trans
, rxb
, rxq
, emergency
);
1435 static struct iwl_rx_mem_buffer
*iwl_pcie_get_rxb(struct iwl_trans
*trans
,
1436 struct iwl_rxq
*rxq
, int i
,
1439 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1440 struct iwl_rx_mem_buffer
*rxb
;
1443 BUILD_BUG_ON(sizeof(struct iwl_rx_completion_desc
) != 32);
1445 if (!trans
->trans_cfg
->mq_rx_supported
) {
1446 rxb
= rxq
->queue
[i
];
1447 rxq
->queue
[i
] = NULL
;
1451 if (trans
->trans_cfg
->device_family
>= IWL_DEVICE_FAMILY_AX210
) {
1452 vid
= le16_to_cpu(rxq
->cd
[i
].rbid
);
1453 *join
= rxq
->cd
[i
].flags
& IWL_RX_CD_FLAGS_FRAGMENTED
;
1455 vid
= le32_to_cpu(rxq
->bd_32
[i
]) & 0x0FFF; /* 12-bit VID */
1458 if (!vid
|| vid
> RX_POOL_SIZE(trans_pcie
->num_rx_bufs
))
1461 rxb
= trans_pcie
->global_table
[vid
- 1];
1465 IWL_DEBUG_RX(trans
, "Got virtual RB ID %u\n", (u32
)rxb
->vid
);
1467 rxb
->invalid
= true;
1472 WARN(1, "Invalid rxb from HW %u\n", (u32
)vid
);
1473 iwl_force_nmi(trans
);
1478 * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
1480 static void iwl_pcie_rx_handle(struct iwl_trans
*trans
, int queue
)
1482 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1483 struct napi_struct
*napi
;
1484 struct iwl_rxq
*rxq
;
1485 u32 r
, i
, count
= 0;
1486 bool emergency
= false;
1488 if (WARN_ON_ONCE(!trans_pcie
->rxq
|| !trans_pcie
->rxq
[queue
].bd
))
1491 rxq
= &trans_pcie
->rxq
[queue
];
1494 spin_lock(&rxq
->lock
);
1495 /* uCode's read index (stored in shared DRAM) indicates the last Rx
1496 * buffer that the driver may process (last buffer filled by ucode). */
1497 r
= le16_to_cpu(iwl_get_closed_rb_stts(trans
, rxq
)) & 0x0FFF;
1500 /* W/A 9000 device step A0 wrap-around bug */
1501 r
&= (rxq
->queue_size
- 1);
1503 /* Rx interrupt, but nothing sent from uCode */
1505 IWL_DEBUG_RX(trans
, "Q %d: HW = SW = %d\n", rxq
->id
, r
);
1508 struct iwl_rb_allocator
*rba
= &trans_pcie
->rba
;
1509 struct iwl_rx_mem_buffer
*rxb
;
1510 /* number of RBDs still waiting for page allocation */
1511 u32 rb_pending_alloc
=
1512 atomic_read(&trans_pcie
->rba
.req_pending
) *
1516 if (unlikely(rb_pending_alloc
>= rxq
->queue_size
/ 2 &&
1518 iwl_pcie_rx_move_to_allocator(rxq
, rba
);
1520 IWL_DEBUG_TPT(trans
,
1521 "RX path is in emergency. Pending allocations %d\n",
1525 IWL_DEBUG_RX(trans
, "Q %d: HW = %d, SW = %d\n", rxq
->id
, r
, i
);
1527 rxb
= iwl_pcie_get_rxb(trans
, rxq
, i
, &join
);
1531 if (unlikely(join
|| rxq
->next_rb_is_fragment
)) {
1532 rxq
->next_rb_is_fragment
= join
;
1534 * We can only get a multi-RB in the following cases:
1535 * - firmware issue, sending a too big notification
1536 * - sniffer mode with a large A-MSDU
1537 * - large MTU frames (>2k)
1538 * since the multi-RB functionality is limited to newer
1539 * hardware that cannot put multiple entries into a
1542 * Right now, the higher layers aren't set up to deal
1543 * with that, so discard all of these.
1545 list_add_tail(&rxb
->list
, &rxq
->rx_free
);
1548 iwl_pcie_rx_handle_rb(trans
, rxq
, rxb
, emergency
, i
);
1551 i
= (i
+ 1) & (rxq
->queue_size
- 1);
1554 * If we have RX_CLAIM_REQ_ALLOC released rx buffers -
1555 * try to claim the pre-allocated buffers from the allocator.
1556 * If not ready - will try to reclaim next time.
1557 * There is no need to reschedule work - allocator exits only
1560 if (rxq
->used_count
>= RX_CLAIM_REQ_ALLOC
)
1561 iwl_pcie_rx_allocator_get(trans
, rxq
);
1563 if (rxq
->used_count
% RX_CLAIM_REQ_ALLOC
== 0 && !emergency
) {
1564 /* Add the remaining empty RBDs for allocator use */
1565 iwl_pcie_rx_move_to_allocator(rxq
, rba
);
1566 } else if (emergency
) {
1570 if (rb_pending_alloc
< rxq
->queue_size
/ 3) {
1571 IWL_DEBUG_TPT(trans
,
1572 "RX path exited emergency. Pending allocations %d\n",
1578 spin_unlock(&rxq
->lock
);
1579 iwl_pcie_rxq_alloc_rbs(trans
, GFP_ATOMIC
, rxq
);
1580 iwl_pcie_rxq_restock(trans
, rxq
);
1586 /* Backtrack one entry */
1588 /* update cr tail with the rxq read pointer */
1589 if (trans
->trans_cfg
->device_family
>= IWL_DEVICE_FAMILY_AX210
)
1590 *rxq
->cr_tail
= cpu_to_le16(r
);
1591 spin_unlock(&rxq
->lock
);
1594 * handle a case where in emergency there are some unallocated RBDs.
1595 * those RBDs are in the used list, but are not tracked by the queue's
1596 * used_count which counts allocator owned RBDs.
1597 * unallocated emergency RBDs must be allocated on exit, otherwise
1598 * when called again the function may not be in emergency mode and
1599 * they will be handed to the allocator with no tracking in the RBD
1600 * allocator counters, which will lead to them never being claimed back
1602 * by allocating them here, they are now in the queue free list, and
1603 * will be restocked by the next call of iwl_pcie_rxq_restock.
1605 if (unlikely(emergency
&& count
))
1606 iwl_pcie_rxq_alloc_rbs(trans
, GFP_ATOMIC
, rxq
);
1610 napi_gro_flush(napi
, false);
1612 if (napi
->rx_count
) {
1613 netif_receive_skb_list(&napi
->rx_list
);
1614 INIT_LIST_HEAD(&napi
->rx_list
);
1619 iwl_pcie_rxq_restock(trans
, rxq
);
1622 static struct iwl_trans_pcie
*iwl_pcie_get_trans_pcie(struct msix_entry
*entry
)
1624 u8 queue
= entry
->entry
;
1625 struct msix_entry
*entries
= entry
- queue
;
1627 return container_of(entries
, struct iwl_trans_pcie
, msix_entries
[0]);
1631 * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw
1632 * This interrupt handler should be used with RSS queue only.
1634 irqreturn_t
iwl_pcie_irq_rx_msix_handler(int irq
, void *dev_id
)
1636 struct msix_entry
*entry
= dev_id
;
1637 struct iwl_trans_pcie
*trans_pcie
= iwl_pcie_get_trans_pcie(entry
);
1638 struct iwl_trans
*trans
= trans_pcie
->trans
;
1640 trace_iwlwifi_dev_irq_msix(trans
->dev
, entry
, false, 0, 0);
1642 if (WARN_ON(entry
->entry
>= trans
->num_rx_queues
))
1645 lock_map_acquire(&trans
->sync_cmd_lockdep_map
);
1648 iwl_pcie_rx_handle(trans
, entry
->entry
);
1651 iwl_pcie_clear_irq(trans
, entry
);
1653 lock_map_release(&trans
->sync_cmd_lockdep_map
);
1659 * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
1661 static void iwl_pcie_irq_handle_error(struct iwl_trans
*trans
)
1663 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1666 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
1667 if (trans
->cfg
->internal_wimax_coex
&&
1668 !trans
->cfg
->apmg_not_supported
&&
1669 (!(iwl_read_prph(trans
, APMG_CLK_CTRL_REG
) &
1670 APMS_CLK_VAL_MRB_FUNC_MODE
) ||
1671 (iwl_read_prph(trans
, APMG_PS_CTRL_REG
) &
1672 APMG_PS_CTRL_VAL_RESET_REQ
))) {
1673 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1674 iwl_op_mode_wimax_active(trans
->op_mode
);
1675 wake_up(&trans_pcie
->wait_command_queue
);
1679 for (i
= 0; i
< trans
->trans_cfg
->base_params
->num_of_queues
; i
++) {
1680 if (!trans
->txqs
.txq
[i
])
1682 del_timer(&trans
->txqs
.txq
[i
]->stuck_timer
);
1685 /* The STATUS_FW_ERROR bit is set in this function. This must happen
1686 * before we wake up the command caller, to ensure a proper cleanup. */
1687 iwl_trans_fw_error(trans
);
1689 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1690 wake_up(&trans_pcie
->wait_command_queue
);
1693 static u32
iwl_pcie_int_cause_non_ict(struct iwl_trans
*trans
)
1697 lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans
)->irq_lock
);
1699 trace_iwlwifi_dev_irq(trans
->dev
);
1701 /* Discover which interrupts are active/pending */
1702 inta
= iwl_read32(trans
, CSR_INT
);
1704 /* the thread will service interrupts and re-enable them */
1708 /* a device (PCI-E) page is 4096 bytes long */
1709 #define ICT_SHIFT 12
1710 #define ICT_SIZE (1 << ICT_SHIFT)
1711 #define ICT_COUNT (ICT_SIZE / sizeof(u32))
1713 /* interrupt handler using ict table, with this interrupt driver will
1714 * stop using INTA register to get device's interrupt, reading this register
1715 * is expensive, device will write interrupts in ICT dram table, increment
1716 * index then will fire interrupt to driver, driver will OR all ICT table
1717 * entries from current index up to table entry with 0 value. the result is
1718 * the interrupt we need to service, driver will set the entries back to 0 and
1721 static u32
iwl_pcie_int_cause_ict(struct iwl_trans
*trans
)
1723 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1728 trace_iwlwifi_dev_irq(trans
->dev
);
1730 /* Ignore interrupt if there's nothing in NIC to service.
1731 * This may be due to IRQ shared with another device,
1732 * or due to sporadic interrupts thrown from our NIC. */
1733 read
= le32_to_cpu(trans_pcie
->ict_tbl
[trans_pcie
->ict_index
]);
1734 trace_iwlwifi_dev_ict_read(trans
->dev
, trans_pcie
->ict_index
, read
);
1739 * Collect all entries up to the first 0, starting from ict_index;
1740 * note we already read at ict_index.
1744 IWL_DEBUG_ISR(trans
, "ICT index %d value 0x%08X\n",
1745 trans_pcie
->ict_index
, read
);
1746 trans_pcie
->ict_tbl
[trans_pcie
->ict_index
] = 0;
1747 trans_pcie
->ict_index
=
1748 ((trans_pcie
->ict_index
+ 1) & (ICT_COUNT
- 1));
1750 read
= le32_to_cpu(trans_pcie
->ict_tbl
[trans_pcie
->ict_index
]);
1751 trace_iwlwifi_dev_ict_read(trans
->dev
, trans_pcie
->ict_index
,
1755 /* We should not get this value, just ignore it. */
1756 if (val
== 0xffffffff)
1760 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1761 * (bit 15 before shifting it to 31) to clear when using interrupt
1762 * coalescing. fortunately, bits 18 and 19 stay set when this happens
1763 * so we use them to decide on the real state of the Rx bit.
1764 * In order words, bit 15 is set if bit 18 or bit 19 are set.
1769 inta
= (0xff & val
) | ((0xff00 & val
) << 16);
1773 void iwl_pcie_handle_rfkill_irq(struct iwl_trans
*trans
)
1775 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1776 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
1777 bool hw_rfkill
, prev
, report
;
1779 mutex_lock(&trans_pcie
->mutex
);
1780 prev
= test_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1781 hw_rfkill
= iwl_is_rfkill_set(trans
);
1783 set_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1784 set_bit(STATUS_RFKILL_HW
, &trans
->status
);
1786 if (trans_pcie
->opmode_down
)
1789 report
= test_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1791 IWL_WARN(trans
, "RF_KILL bit toggled to %s.\n",
1792 hw_rfkill
? "disable radio" : "enable radio");
1794 isr_stats
->rfkill
++;
1797 iwl_trans_pcie_rf_kill(trans
, report
);
1798 mutex_unlock(&trans_pcie
->mutex
);
1801 if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE
,
1803 IWL_DEBUG_RF_KILL(trans
,
1804 "Rfkill while SYNC HCMD in flight\n");
1805 wake_up(&trans_pcie
->wait_command_queue
);
1807 clear_bit(STATUS_RFKILL_HW
, &trans
->status
);
1808 if (trans_pcie
->opmode_down
)
1809 clear_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1813 irqreturn_t
iwl_pcie_irq_handler(int irq
, void *dev_id
)
1815 struct iwl_trans
*trans
= dev_id
;
1816 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1817 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
1821 lock_map_acquire(&trans
->sync_cmd_lockdep_map
);
1823 spin_lock(&trans_pcie
->irq_lock
);
1825 /* dram interrupt table not set yet,
1826 * use legacy interrupt.
1828 if (likely(trans_pcie
->use_ict
))
1829 inta
= iwl_pcie_int_cause_ict(trans
);
1831 inta
= iwl_pcie_int_cause_non_ict(trans
);
1833 if (iwl_have_debug_level(IWL_DL_ISR
)) {
1834 IWL_DEBUG_ISR(trans
,
1835 "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n",
1836 inta
, trans_pcie
->inta_mask
,
1837 iwl_read32(trans
, CSR_INT_MASK
),
1838 iwl_read32(trans
, CSR_FH_INT_STATUS
));
1839 if (inta
& (~trans_pcie
->inta_mask
))
1840 IWL_DEBUG_ISR(trans
,
1841 "We got a masked interrupt (0x%08x)\n",
1842 inta
& (~trans_pcie
->inta_mask
));
1845 inta
&= trans_pcie
->inta_mask
;
1848 * Ignore interrupt if there's nothing in NIC to service.
1849 * This may be due to IRQ shared with another device,
1850 * or due to sporadic interrupts thrown from our NIC.
1852 if (unlikely(!inta
)) {
1853 IWL_DEBUG_ISR(trans
, "Ignore interrupt, inta == 0\n");
1855 * Re-enable interrupts here since we don't
1856 * have anything to service
1858 if (test_bit(STATUS_INT_ENABLED
, &trans
->status
))
1859 _iwl_enable_interrupts(trans
);
1860 spin_unlock(&trans_pcie
->irq_lock
);
1861 lock_map_release(&trans
->sync_cmd_lockdep_map
);
1865 if (unlikely(inta
== 0xFFFFFFFF || (inta
& 0xFFFFFFF0) == 0xa5a5a5a0)) {
1867 * Hardware disappeared. It might have
1868 * already raised an interrupt.
1870 IWL_WARN(trans
, "HARDWARE GONE?? INTA == 0x%08x\n", inta
);
1871 spin_unlock(&trans_pcie
->irq_lock
);
1875 /* Ack/clear/reset pending uCode interrupts.
1876 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1878 /* There is a hardware bug in the interrupt mask function that some
1879 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1880 * they are disabled in the CSR_INT_MASK register. Furthermore the
1881 * ICT interrupt handling mechanism has another bug that might cause
1882 * these unmasked interrupts fail to be detected. We workaround the
1883 * hardware bugs here by ACKing all the possible interrupts so that
1884 * interrupt coalescing can still be achieved.
1886 iwl_write32(trans
, CSR_INT
, inta
| ~trans_pcie
->inta_mask
);
1888 if (iwl_have_debug_level(IWL_DL_ISR
))
1889 IWL_DEBUG_ISR(trans
, "inta 0x%08x, enabled 0x%08x\n",
1890 inta
, iwl_read32(trans
, CSR_INT_MASK
));
1892 spin_unlock(&trans_pcie
->irq_lock
);
1894 /* Now service all interrupt bits discovered above. */
1895 if (inta
& CSR_INT_BIT_HW_ERR
) {
1896 IWL_ERR(trans
, "Hardware error detected. Restarting.\n");
1898 /* Tell the device to stop sending interrupts */
1899 iwl_disable_interrupts(trans
);
1902 iwl_pcie_irq_handle_error(trans
);
1904 handled
|= CSR_INT_BIT_HW_ERR
;
1909 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1910 if (inta
& CSR_INT_BIT_SCD
) {
1911 IWL_DEBUG_ISR(trans
,
1912 "Scheduler finished to transmit the frame/frames.\n");
1916 /* Alive notification via Rx interrupt will do the real work */
1917 if (inta
& CSR_INT_BIT_ALIVE
) {
1918 IWL_DEBUG_ISR(trans
, "Alive interrupt\n");
1920 if (trans
->trans_cfg
->gen2
) {
1922 * We can restock, since firmware configured
1925 iwl_pcie_rxmq_restock(trans
, trans_pcie
->rxq
);
1928 handled
|= CSR_INT_BIT_ALIVE
;
1931 /* Safely ignore these bits for debug checks below */
1932 inta
&= ~(CSR_INT_BIT_SCD
| CSR_INT_BIT_ALIVE
);
1934 /* HW RF KILL switch toggled */
1935 if (inta
& CSR_INT_BIT_RF_KILL
) {
1936 iwl_pcie_handle_rfkill_irq(trans
);
1937 handled
|= CSR_INT_BIT_RF_KILL
;
1940 /* Chip got too hot and stopped itself */
1941 if (inta
& CSR_INT_BIT_CT_KILL
) {
1942 IWL_ERR(trans
, "Microcode CT kill error detected.\n");
1943 isr_stats
->ctkill
++;
1944 handled
|= CSR_INT_BIT_CT_KILL
;
1947 /* Error detected by uCode */
1948 if (inta
& CSR_INT_BIT_SW_ERR
) {
1949 IWL_ERR(trans
, "Microcode SW error detected. "
1950 " Restarting 0x%X.\n", inta
);
1952 iwl_pcie_irq_handle_error(trans
);
1953 handled
|= CSR_INT_BIT_SW_ERR
;
1956 /* uCode wakes up after power-down sleep */
1957 if (inta
& CSR_INT_BIT_WAKEUP
) {
1958 IWL_DEBUG_ISR(trans
, "Wakeup interrupt\n");
1959 iwl_pcie_rxq_check_wrptr(trans
);
1960 iwl_pcie_txq_check_wrptrs(trans
);
1962 isr_stats
->wakeup
++;
1964 handled
|= CSR_INT_BIT_WAKEUP
;
1967 /* All uCode command responses, including Tx command responses,
1968 * Rx "responses" (frame-received notification), and other
1969 * notifications from uCode come through here*/
1970 if (inta
& (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
|
1971 CSR_INT_BIT_RX_PERIODIC
)) {
1972 IWL_DEBUG_ISR(trans
, "Rx interrupt\n");
1973 if (inta
& (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
)) {
1974 handled
|= (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
);
1975 iwl_write32(trans
, CSR_FH_INT_STATUS
,
1976 CSR_FH_INT_RX_MASK
);
1978 if (inta
& CSR_INT_BIT_RX_PERIODIC
) {
1979 handled
|= CSR_INT_BIT_RX_PERIODIC
;
1981 CSR_INT
, CSR_INT_BIT_RX_PERIODIC
);
1983 /* Sending RX interrupt require many steps to be done in the
1985 * 1- write interrupt to current index in ICT table.
1987 * 3- update RX shared data to indicate last write index.
1988 * 4- send interrupt.
1989 * This could lead to RX race, driver could receive RX interrupt
1990 * but the shared data changes does not reflect this;
1991 * periodic interrupt will detect any dangling Rx activity.
1994 /* Disable periodic interrupt; we use it as just a one-shot. */
1995 iwl_write8(trans
, CSR_INT_PERIODIC_REG
,
1996 CSR_INT_PERIODIC_DIS
);
1999 * Enable periodic interrupt in 8 msec only if we received
2000 * real RX interrupt (instead of just periodic int), to catch
2001 * any dangling Rx interrupt. If it was just the periodic
2002 * interrupt, there was no dangling Rx activity, and no need
2003 * to extend the periodic interrupt; one-shot is enough.
2005 if (inta
& (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
))
2006 iwl_write8(trans
, CSR_INT_PERIODIC_REG
,
2007 CSR_INT_PERIODIC_ENA
);
2012 iwl_pcie_rx_handle(trans
, 0);
2016 /* This "Tx" DMA channel is used only for loading uCode */
2017 if (inta
& CSR_INT_BIT_FH_TX
) {
2018 iwl_write32(trans
, CSR_FH_INT_STATUS
, CSR_FH_INT_TX_MASK
);
2019 IWL_DEBUG_ISR(trans
, "uCode load interrupt\n");
2021 handled
|= CSR_INT_BIT_FH_TX
;
2022 /* Wake up uCode load routine, now that load is complete */
2023 trans_pcie
->ucode_write_complete
= true;
2024 wake_up(&trans_pcie
->ucode_write_waitq
);
2027 if (inta
& ~handled
) {
2028 IWL_ERR(trans
, "Unhandled INTA bits 0x%08x\n", inta
& ~handled
);
2029 isr_stats
->unhandled
++;
2032 if (inta
& ~(trans_pcie
->inta_mask
)) {
2033 IWL_WARN(trans
, "Disabled INTA bits 0x%08x were pending\n",
2034 inta
& ~trans_pcie
->inta_mask
);
2037 spin_lock(&trans_pcie
->irq_lock
);
2038 /* only Re-enable all interrupt if disabled by irq */
2039 if (test_bit(STATUS_INT_ENABLED
, &trans
->status
))
2040 _iwl_enable_interrupts(trans
);
2041 /* we are loading the firmware, enable FH_TX interrupt only */
2042 else if (handled
& CSR_INT_BIT_FH_TX
)
2043 iwl_enable_fw_load_int(trans
);
2044 /* Re-enable RF_KILL if it occurred */
2045 else if (handled
& CSR_INT_BIT_RF_KILL
)
2046 iwl_enable_rfkill_int(trans
);
2047 /* Re-enable the ALIVE / Rx interrupt if it occurred */
2048 else if (handled
& (CSR_INT_BIT_ALIVE
| CSR_INT_BIT_FH_RX
))
2049 iwl_enable_fw_load_int_ctx_info(trans
);
2050 spin_unlock(&trans_pcie
->irq_lock
);
2053 lock_map_release(&trans
->sync_cmd_lockdep_map
);
2057 /******************************************************************************
2061 ******************************************************************************/
2063 /* Free dram table */
2064 void iwl_pcie_free_ict(struct iwl_trans
*trans
)
2066 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2068 if (trans_pcie
->ict_tbl
) {
2069 dma_free_coherent(trans
->dev
, ICT_SIZE
,
2070 trans_pcie
->ict_tbl
,
2071 trans_pcie
->ict_tbl_dma
);
2072 trans_pcie
->ict_tbl
= NULL
;
2073 trans_pcie
->ict_tbl_dma
= 0;
2078 * allocate dram shared table, it is an aligned memory
2079 * block of ICT_SIZE.
2080 * also reset all data related to ICT table interrupt.
2082 int iwl_pcie_alloc_ict(struct iwl_trans
*trans
)
2084 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2086 trans_pcie
->ict_tbl
=
2087 dma_alloc_coherent(trans
->dev
, ICT_SIZE
,
2088 &trans_pcie
->ict_tbl_dma
, GFP_KERNEL
);
2089 if (!trans_pcie
->ict_tbl
)
2092 /* just an API sanity check ... it is guaranteed to be aligned */
2093 if (WARN_ON(trans_pcie
->ict_tbl_dma
& (ICT_SIZE
- 1))) {
2094 iwl_pcie_free_ict(trans
);
2101 /* Device is going up inform it about using ICT interrupt table,
2102 * also we need to tell the driver to start using ICT interrupt.
2104 void iwl_pcie_reset_ict(struct iwl_trans
*trans
)
2106 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2109 if (!trans_pcie
->ict_tbl
)
2112 spin_lock(&trans_pcie
->irq_lock
);
2113 _iwl_disable_interrupts(trans
);
2115 memset(trans_pcie
->ict_tbl
, 0, ICT_SIZE
);
2117 val
= trans_pcie
->ict_tbl_dma
>> ICT_SHIFT
;
2119 val
|= CSR_DRAM_INT_TBL_ENABLE
|
2120 CSR_DRAM_INIT_TBL_WRAP_CHECK
|
2121 CSR_DRAM_INIT_TBL_WRITE_POINTER
;
2123 IWL_DEBUG_ISR(trans
, "CSR_DRAM_INT_TBL_REG =0x%x\n", val
);
2125 iwl_write32(trans
, CSR_DRAM_INT_TBL_REG
, val
);
2126 trans_pcie
->use_ict
= true;
2127 trans_pcie
->ict_index
= 0;
2128 iwl_write32(trans
, CSR_INT
, trans_pcie
->inta_mask
);
2129 _iwl_enable_interrupts(trans
);
2130 spin_unlock(&trans_pcie
->irq_lock
);
2133 /* Device is going down disable ict interrupt usage */
2134 void iwl_pcie_disable_ict(struct iwl_trans
*trans
)
2136 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2138 spin_lock(&trans_pcie
->irq_lock
);
2139 trans_pcie
->use_ict
= false;
2140 spin_unlock(&trans_pcie
->irq_lock
);
2143 irqreturn_t
iwl_pcie_isr(int irq
, void *data
)
2145 struct iwl_trans
*trans
= data
;
2150 /* Disable (but don't clear!) interrupts here to avoid
2151 * back-to-back ISRs and sporadic interrupts from our NIC.
2152 * If we have something to service, the tasklet will re-enable ints.
2153 * If we *don't* have something, we'll re-enable before leaving here.
2155 iwl_write32(trans
, CSR_INT_MASK
, 0x00000000);
2157 return IRQ_WAKE_THREAD
;
2160 irqreturn_t
iwl_pcie_msix_isr(int irq
, void *data
)
2162 return IRQ_WAKE_THREAD
;
2165 irqreturn_t
iwl_pcie_irq_msix_handler(int irq
, void *dev_id
)
2167 struct msix_entry
*entry
= dev_id
;
2168 struct iwl_trans_pcie
*trans_pcie
= iwl_pcie_get_trans_pcie(entry
);
2169 struct iwl_trans
*trans
= trans_pcie
->trans
;
2170 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
2171 u32 inta_fh
, inta_hw
;
2173 lock_map_acquire(&trans
->sync_cmd_lockdep_map
);
2175 spin_lock(&trans_pcie
->irq_lock
);
2176 inta_fh
= iwl_read32(trans
, CSR_MSIX_FH_INT_CAUSES_AD
);
2177 inta_hw
= iwl_read32(trans
, CSR_MSIX_HW_INT_CAUSES_AD
);
2179 * Clear causes registers to avoid being handling the same cause.
2181 iwl_write32(trans
, CSR_MSIX_FH_INT_CAUSES_AD
, inta_fh
);
2182 iwl_write32(trans
, CSR_MSIX_HW_INT_CAUSES_AD
, inta_hw
);
2183 spin_unlock(&trans_pcie
->irq_lock
);
2185 trace_iwlwifi_dev_irq_msix(trans
->dev
, entry
, true, inta_fh
, inta_hw
);
2187 if (unlikely(!(inta_fh
| inta_hw
))) {
2188 IWL_DEBUG_ISR(trans
, "Ignore interrupt, inta == 0\n");
2189 lock_map_release(&trans
->sync_cmd_lockdep_map
);
2193 if (iwl_have_debug_level(IWL_DL_ISR
)) {
2194 IWL_DEBUG_ISR(trans
,
2195 "ISR inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n",
2196 inta_fh
, trans_pcie
->fh_mask
,
2197 iwl_read32(trans
, CSR_MSIX_FH_INT_MASK_AD
));
2198 if (inta_fh
& ~trans_pcie
->fh_mask
)
2199 IWL_DEBUG_ISR(trans
,
2200 "We got a masked interrupt (0x%08x)\n",
2201 inta_fh
& ~trans_pcie
->fh_mask
);
2204 inta_fh
&= trans_pcie
->fh_mask
;
2206 if ((trans_pcie
->shared_vec_mask
& IWL_SHARED_IRQ_NON_RX
) &&
2207 inta_fh
& MSIX_FH_INT_CAUSES_Q0
) {
2209 iwl_pcie_rx_handle(trans
, 0);
2213 if ((trans_pcie
->shared_vec_mask
& IWL_SHARED_IRQ_FIRST_RSS
) &&
2214 inta_fh
& MSIX_FH_INT_CAUSES_Q1
) {
2216 iwl_pcie_rx_handle(trans
, 1);
2220 /* This "Tx" DMA channel is used only for loading uCode */
2221 if (inta_fh
& MSIX_FH_INT_CAUSES_D2S_CH0_NUM
) {
2222 IWL_DEBUG_ISR(trans
, "uCode load interrupt\n");
2225 * Wake up uCode load routine,
2226 * now that load is complete
2228 trans_pcie
->ucode_write_complete
= true;
2229 wake_up(&trans_pcie
->ucode_write_waitq
);
2232 /* Error detected by uCode */
2233 if ((inta_fh
& MSIX_FH_INT_CAUSES_FH_ERR
) ||
2234 (inta_hw
& MSIX_HW_INT_CAUSES_REG_SW_ERR
)) {
2236 "Microcode SW error detected. Restarting 0x%X.\n",
2239 iwl_pcie_irq_handle_error(trans
);
2242 /* After checking FH register check HW register */
2243 if (iwl_have_debug_level(IWL_DL_ISR
)) {
2244 IWL_DEBUG_ISR(trans
,
2245 "ISR inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n",
2246 inta_hw
, trans_pcie
->hw_mask
,
2247 iwl_read32(trans
, CSR_MSIX_HW_INT_MASK_AD
));
2248 if (inta_hw
& ~trans_pcie
->hw_mask
)
2249 IWL_DEBUG_ISR(trans
,
2250 "We got a masked interrupt 0x%08x\n",
2251 inta_hw
& ~trans_pcie
->hw_mask
);
2254 inta_hw
&= trans_pcie
->hw_mask
;
2256 /* Alive notification via Rx interrupt will do the real work */
2257 if (inta_hw
& MSIX_HW_INT_CAUSES_REG_ALIVE
) {
2258 IWL_DEBUG_ISR(trans
, "Alive interrupt\n");
2260 if (trans
->trans_cfg
->gen2
) {
2261 /* We can restock, since firmware configured the RFH */
2262 iwl_pcie_rxmq_restock(trans
, trans_pcie
->rxq
);
2266 if (inta_hw
& MSIX_HW_INT_CAUSES_REG_WAKEUP
) {
2268 le32_to_cpu(trans_pcie
->prph_info
->sleep_notif
);
2269 if (sleep_notif
== IWL_D3_SLEEP_STATUS_SUSPEND
||
2270 sleep_notif
== IWL_D3_SLEEP_STATUS_RESUME
) {
2271 IWL_DEBUG_ISR(trans
,
2272 "Sx interrupt: sleep notification = 0x%x\n",
2274 trans_pcie
->sx_complete
= true;
2275 wake_up(&trans_pcie
->sx_waitq
);
2277 /* uCode wakes up after power-down sleep */
2278 IWL_DEBUG_ISR(trans
, "Wakeup interrupt\n");
2279 iwl_pcie_rxq_check_wrptr(trans
);
2280 iwl_pcie_txq_check_wrptrs(trans
);
2282 isr_stats
->wakeup
++;
2286 /* Chip got too hot and stopped itself */
2287 if (inta_hw
& MSIX_HW_INT_CAUSES_REG_CT_KILL
) {
2288 IWL_ERR(trans
, "Microcode CT kill error detected.\n");
2289 isr_stats
->ctkill
++;
2292 /* HW RF KILL switch toggled */
2293 if (inta_hw
& MSIX_HW_INT_CAUSES_REG_RF_KILL
)
2294 iwl_pcie_handle_rfkill_irq(trans
);
2296 if (inta_hw
& MSIX_HW_INT_CAUSES_REG_HW_ERR
) {
2298 "Hardware error detected. Restarting.\n");
2301 trans
->dbg
.hw_error
= true;
2302 iwl_pcie_irq_handle_error(trans
);
2305 iwl_pcie_clear_irq(trans
, entry
);
2307 lock_map_release(&trans
->sync_cmd_lockdep_map
);