1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
9 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
10 * Copyright(c) 2007 - 2015, 2018 - 2020 Intel Corporation
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * The full GNU General Public License is included in this distribution
22 * in the file called COPYING.
24 * Contact Information:
25 * Intel Linux Wireless <linuxwifi@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
31 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
32 * Copyright(c) 2007 - 2015, 2018 - 2020 Intel Corporation
33 * All rights reserved.
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
39 * * Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * * Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in
43 * the documentation and/or other materials provided with the
45 * * Neither the name Intel Corporation nor the names of its
46 * contributors may be used to endorse or promote products derived
47 * from this software without specific prior written permission.
49 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
50 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
51 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
52 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
53 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
55 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
59 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *****************************************************************************/
62 #include <linux/pci.h>
63 #include <linux/interrupt.h>
64 #include <linux/debugfs.h>
65 #include <linux/sched.h>
66 #include <linux/bitops.h>
67 #include <linux/gfp.h>
68 #include <linux/vmalloc.h>
69 #include <linux/module.h>
70 #include <linux/wait.h>
71 #include <linux/seq_file.h>
74 #include "iwl-trans.h"
78 #include "iwl-agn-hw.h"
79 #include "fw/error-dump.h"
81 #include "fw/api/tx.h"
84 #include "iwl-context-info-gen3.h"
86 /* extended range in FW SRAM */
87 #define IWL_FW_MEM_EXTENDED_START 0x40000
88 #define IWL_FW_MEM_EXTENDED_END 0x57FFF
90 void iwl_trans_pcie_dump_regs(struct iwl_trans
*trans
)
92 #define PCI_DUMP_SIZE 352
93 #define PCI_MEM_DUMP_SIZE 64
94 #define PCI_PARENT_DUMP_SIZE 524
96 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
97 struct pci_dev
*pdev
= trans_pcie
->pci_dev
;
98 u32 i
, pos
, alloc_size
, *ptr
, *buf
;
101 if (trans_pcie
->pcie_dbg_dumped_once
)
104 /* Should be a multiple of 4 */
105 BUILD_BUG_ON(PCI_DUMP_SIZE
> 4096 || PCI_DUMP_SIZE
& 0x3);
106 BUILD_BUG_ON(PCI_MEM_DUMP_SIZE
> 4096 || PCI_MEM_DUMP_SIZE
& 0x3);
107 BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE
> 4096 || PCI_PARENT_DUMP_SIZE
& 0x3);
109 /* Alloc a max size buffer */
110 alloc_size
= PCI_ERR_ROOT_ERR_SRC
+ 4 + PREFIX_LEN
;
111 alloc_size
= max_t(u32
, alloc_size
, PCI_DUMP_SIZE
+ PREFIX_LEN
);
112 alloc_size
= max_t(u32
, alloc_size
, PCI_MEM_DUMP_SIZE
+ PREFIX_LEN
);
113 alloc_size
= max_t(u32
, alloc_size
, PCI_PARENT_DUMP_SIZE
+ PREFIX_LEN
);
115 buf
= kmalloc(alloc_size
, GFP_ATOMIC
);
118 prefix
= (char *)buf
+ alloc_size
- PREFIX_LEN
;
120 IWL_ERR(trans
, "iwlwifi transaction failed, dumping registers\n");
122 /* Print wifi device registers */
123 sprintf(prefix
, "iwlwifi %s: ", pci_name(pdev
));
124 IWL_ERR(trans
, "iwlwifi device config registers:\n");
125 for (i
= 0, ptr
= buf
; i
< PCI_DUMP_SIZE
; i
+= 4, ptr
++)
126 if (pci_read_config_dword(pdev
, i
, ptr
))
128 print_hex_dump(KERN_ERR
, prefix
, DUMP_PREFIX_OFFSET
, 32, 4, buf
, i
, 0);
130 IWL_ERR(trans
, "iwlwifi device memory mapped registers:\n");
131 for (i
= 0, ptr
= buf
; i
< PCI_MEM_DUMP_SIZE
; i
+= 4, ptr
++)
132 *ptr
= iwl_read32(trans
, i
);
133 print_hex_dump(KERN_ERR
, prefix
, DUMP_PREFIX_OFFSET
, 32, 4, buf
, i
, 0);
135 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_ERR
);
137 IWL_ERR(trans
, "iwlwifi device AER capability structure:\n");
138 for (i
= 0, ptr
= buf
; i
< PCI_ERR_ROOT_COMMAND
; i
+= 4, ptr
++)
139 if (pci_read_config_dword(pdev
, pos
+ i
, ptr
))
141 print_hex_dump(KERN_ERR
, prefix
, DUMP_PREFIX_OFFSET
,
145 /* Print parent device registers next */
146 if (!pdev
->bus
->self
)
149 pdev
= pdev
->bus
->self
;
150 sprintf(prefix
, "iwlwifi %s: ", pci_name(pdev
));
152 IWL_ERR(trans
, "iwlwifi parent port (%s) config registers:\n",
154 for (i
= 0, ptr
= buf
; i
< PCI_PARENT_DUMP_SIZE
; i
+= 4, ptr
++)
155 if (pci_read_config_dword(pdev
, i
, ptr
))
157 print_hex_dump(KERN_ERR
, prefix
, DUMP_PREFIX_OFFSET
, 32, 4, buf
, i
, 0);
159 /* Print root port AER registers */
161 pdev
= pcie_find_root_port(pdev
);
163 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_ERR
);
165 IWL_ERR(trans
, "iwlwifi root port (%s) AER cap structure:\n",
167 sprintf(prefix
, "iwlwifi %s: ", pci_name(pdev
));
168 for (i
= 0, ptr
= buf
; i
<= PCI_ERR_ROOT_ERR_SRC
; i
+= 4, ptr
++)
169 if (pci_read_config_dword(pdev
, pos
+ i
, ptr
))
171 print_hex_dump(KERN_ERR
, prefix
, DUMP_PREFIX_OFFSET
, 32,
177 print_hex_dump(KERN_ERR
, prefix
, DUMP_PREFIX_OFFSET
, 32, 4, buf
, i
, 0);
178 IWL_ERR(trans
, "Read failed at 0x%X\n", i
);
180 trans_pcie
->pcie_dbg_dumped_once
= 1;
184 static void iwl_trans_pcie_sw_reset(struct iwl_trans
*trans
)
186 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
187 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
188 usleep_range(5000, 6000);
191 static void iwl_pcie_free_fw_monitor(struct iwl_trans
*trans
)
193 struct iwl_dram_data
*fw_mon
= &trans
->dbg
.fw_mon
;
198 dma_free_coherent(trans
->dev
, fw_mon
->size
, fw_mon
->block
,
201 fw_mon
->block
= NULL
;
202 fw_mon
->physical
= 0;
206 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans
*trans
,
207 u8 max_power
, u8 min_power
)
209 struct iwl_dram_data
*fw_mon
= &trans
->dbg
.fw_mon
;
211 dma_addr_t physical
= 0;
218 for (power
= max_power
; power
>= min_power
; power
--) {
220 block
= dma_alloc_coherent(trans
->dev
, size
, &physical
,
221 GFP_KERNEL
| __GFP_NOWARN
);
226 "Allocated 0x%08x bytes for firmware monitor.\n",
231 if (WARN_ON_ONCE(!block
))
234 if (power
!= max_power
)
236 "Sorry - debug buffer is only %luK while you requested %luK\n",
237 (unsigned long)BIT(power
- 10),
238 (unsigned long)BIT(max_power
- 10));
240 fw_mon
->block
= block
;
241 fw_mon
->physical
= physical
;
245 void iwl_pcie_alloc_fw_monitor(struct iwl_trans
*trans
, u8 max_power
)
248 /* default max_power is maximum */
254 if (WARN(max_power
> 26,
255 "External buffer size for monitor is too big %d, check the FW TLV\n",
259 if (trans
->dbg
.fw_mon
.size
)
262 iwl_pcie_alloc_fw_monitor_block(trans
, max_power
, 11);
265 static u32
iwl_trans_pcie_read_shr(struct iwl_trans
*trans
, u32 reg
)
267 iwl_write32(trans
, HEEP_CTRL_WRD_PCIEX_CTRL_REG
,
268 ((reg
& 0x0000ffff) | (2 << 28)));
269 return iwl_read32(trans
, HEEP_CTRL_WRD_PCIEX_DATA_REG
);
272 static void iwl_trans_pcie_write_shr(struct iwl_trans
*trans
, u32 reg
, u32 val
)
274 iwl_write32(trans
, HEEP_CTRL_WRD_PCIEX_DATA_REG
, val
);
275 iwl_write32(trans
, HEEP_CTRL_WRD_PCIEX_CTRL_REG
,
276 ((reg
& 0x0000ffff) | (3 << 28)));
279 static void iwl_pcie_set_pwr(struct iwl_trans
*trans
, bool vaux
)
281 if (trans
->cfg
->apmg_not_supported
)
284 if (vaux
&& pci_pme_capable(to_pci_dev(trans
->dev
), PCI_D3cold
))
285 iwl_set_bits_mask_prph(trans
, APMG_PS_CTRL_REG
,
286 APMG_PS_CTRL_VAL_PWR_SRC_VAUX
,
287 ~APMG_PS_CTRL_MSK_PWR_SRC
);
289 iwl_set_bits_mask_prph(trans
, APMG_PS_CTRL_REG
,
290 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
,
291 ~APMG_PS_CTRL_MSK_PWR_SRC
);
295 #define PCI_CFG_RETRY_TIMEOUT 0x041
297 void iwl_pcie_apm_config(struct iwl_trans
*trans
)
299 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
304 * L0S states have been found to be unstable with our devices
305 * and in newer hardware they are not officially supported at
306 * all, so we must always set the L0S_DISABLED bit.
308 iwl_set_bit(trans
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_DISABLED
);
310 pcie_capability_read_word(trans_pcie
->pci_dev
, PCI_EXP_LNKCTL
, &lctl
);
311 trans
->pm_support
= !(lctl
& PCI_EXP_LNKCTL_ASPM_L0S
);
313 pcie_capability_read_word(trans_pcie
->pci_dev
, PCI_EXP_DEVCTL2
, &cap
);
314 trans
->ltr_enabled
= cap
& PCI_EXP_DEVCTL2_LTR_EN
;
315 IWL_DEBUG_POWER(trans
, "L1 %sabled - LTR %sabled\n",
316 (lctl
& PCI_EXP_LNKCTL_ASPM_L1
) ? "En" : "Dis",
317 trans
->ltr_enabled
? "En" : "Dis");
321 * Start up NIC's basic functionality after it has been reset
322 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
323 * NOTE: This does not load uCode nor start the embedded processor
325 static int iwl_pcie_apm_init(struct iwl_trans
*trans
)
329 IWL_DEBUG_INFO(trans
, "Init card's basic functions\n");
332 * Use "set_bit" below rather than "write", to preserve any hardware
333 * bits already set by default after reset.
336 /* Disable L0S exit timer (platform NMI Work/Around) */
337 if (trans
->trans_cfg
->device_family
< IWL_DEVICE_FAMILY_8000
)
338 iwl_set_bit(trans
, CSR_GIO_CHICKEN_BITS
,
339 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER
);
342 * Disable L0s without affecting L1;
343 * don't wait for ICH L0s (ICH bug W/A)
345 iwl_set_bit(trans
, CSR_GIO_CHICKEN_BITS
,
346 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX
);
348 /* Set FH wait threshold to maximum (HW error during stress W/A) */
349 iwl_set_bit(trans
, CSR_DBG_HPET_MEM_REG
, CSR_DBG_HPET_MEM_REG_VAL
);
352 * Enable HAP INTA (interrupt from management bus) to
353 * wake device's PCI Express link L1a -> L0s
355 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
356 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A
);
358 iwl_pcie_apm_config(trans
);
360 /* Configure analog phase-lock-loop before activating to D0A */
361 if (trans
->trans_cfg
->base_params
->pll_cfg
)
362 iwl_set_bit(trans
, CSR_ANA_PLL_CFG
, CSR50_ANA_PLL_CFG_VAL
);
364 ret
= iwl_finish_nic_init(trans
, trans
->trans_cfg
);
368 if (trans
->cfg
->host_interrupt_operation_mode
) {
370 * This is a bit of an abuse - This is needed for 7260 / 3160
371 * only check host_interrupt_operation_mode even if this is
372 * not related to host_interrupt_operation_mode.
374 * Enable the oscillator to count wake up time for L1 exit. This
375 * consumes slightly more power (100uA) - but allows to be sure
376 * that we wake up from L1 on time.
378 * This looks weird: read twice the same register, discard the
379 * value, set a bit, and yet again, read that same register
380 * just to discard the value. But that's the way the hardware
383 iwl_read_prph(trans
, OSC_CLK
);
384 iwl_read_prph(trans
, OSC_CLK
);
385 iwl_set_bits_prph(trans
, OSC_CLK
, OSC_CLK_FORCE_CONTROL
);
386 iwl_read_prph(trans
, OSC_CLK
);
387 iwl_read_prph(trans
, OSC_CLK
);
391 * Enable DMA clock and wait for it to stabilize.
393 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
394 * bits do not disable clocks. This preserves any hardware
395 * bits already set by default in "CLK_CTRL_REG" after reset.
397 if (!trans
->cfg
->apmg_not_supported
) {
398 iwl_write_prph(trans
, APMG_CLK_EN_REG
,
399 APMG_CLK_VAL_DMA_CLK_RQT
);
402 /* Disable L1-Active */
403 iwl_set_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
404 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
406 /* Clear the interrupt in APMG if the NIC is in RFKILL */
407 iwl_write_prph(trans
, APMG_RTC_INT_STT_REG
,
408 APMG_RTC_INT_STT_RFKILL
);
411 set_bit(STATUS_DEVICE_ENABLED
, &trans
->status
);
417 * Enable LP XTAL to avoid HW bug where device may consume much power if
418 * FW is not loaded after device reset. LP XTAL is disabled by default
419 * after device HW reset. Do it only if XTAL is fed by internal source.
420 * Configure device's "persistence" mode to avoid resetting XTAL again when
421 * SHRD_HW_RST occurs in S3.
423 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans
*trans
)
427 u32 apmg_xtal_cfg_reg
;
431 __iwl_trans_pcie_set_bit(trans
, CSR_GP_CNTRL
,
432 CSR_GP_CNTRL_REG_FLAG_XTAL_ON
);
434 iwl_trans_pcie_sw_reset(trans
);
436 ret
= iwl_finish_nic_init(trans
, trans
->trans_cfg
);
438 /* Release XTAL ON request */
439 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
440 CSR_GP_CNTRL_REG_FLAG_XTAL_ON
);
445 * Clear "disable persistence" to avoid LP XTAL resetting when
446 * SHRD_HW_RST is applied in S3.
448 iwl_clear_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
449 APMG_PCIDEV_STT_VAL_PERSIST_DIS
);
452 * Force APMG XTAL to be active to prevent its disabling by HW
453 * caused by APMG idle state.
455 apmg_xtal_cfg_reg
= iwl_trans_pcie_read_shr(trans
,
456 SHR_APMG_XTAL_CFG_REG
);
457 iwl_trans_pcie_write_shr(trans
, SHR_APMG_XTAL_CFG_REG
,
459 SHR_APMG_XTAL_CFG_XTAL_ON_REQ
);
461 iwl_trans_pcie_sw_reset(trans
);
463 /* Enable LP XTAL by indirect access through CSR */
464 apmg_gp1_reg
= iwl_trans_pcie_read_shr(trans
, SHR_APMG_GP1_REG
);
465 iwl_trans_pcie_write_shr(trans
, SHR_APMG_GP1_REG
, apmg_gp1_reg
|
466 SHR_APMG_GP1_WF_XTAL_LP_EN
|
467 SHR_APMG_GP1_CHICKEN_BIT_SELECT
);
469 /* Clear delay line clock power up */
470 dl_cfg_reg
= iwl_trans_pcie_read_shr(trans
, SHR_APMG_DL_CFG_REG
);
471 iwl_trans_pcie_write_shr(trans
, SHR_APMG_DL_CFG_REG
, dl_cfg_reg
&
472 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP
);
475 * Enable persistence mode to avoid LP XTAL resetting when
476 * SHRD_HW_RST is applied in S3.
478 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
479 CSR_HW_IF_CONFIG_REG_PERSIST_MODE
);
482 * Clear "initialization complete" bit to move adapter from
483 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
485 iwl_clear_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
487 /* Activates XTAL resources monitor */
488 __iwl_trans_pcie_set_bit(trans
, CSR_MONITOR_CFG_REG
,
489 CSR_MONITOR_XTAL_RESOURCES
);
491 /* Release XTAL ON request */
492 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
493 CSR_GP_CNTRL_REG_FLAG_XTAL_ON
);
496 /* Release APMG XTAL */
497 iwl_trans_pcie_write_shr(trans
, SHR_APMG_XTAL_CFG_REG
,
499 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ
);
502 void iwl_pcie_apm_stop_master(struct iwl_trans
*trans
)
506 /* stop device's busmaster DMA activity */
507 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_STOP_MASTER
);
509 ret
= iwl_poll_bit(trans
, CSR_RESET
,
510 CSR_RESET_REG_FLAG_MASTER_DISABLED
,
511 CSR_RESET_REG_FLAG_MASTER_DISABLED
, 100);
513 IWL_WARN(trans
, "Master Disable Timed Out, 100 usec\n");
515 IWL_DEBUG_INFO(trans
, "stop master\n");
518 static void iwl_pcie_apm_stop(struct iwl_trans
*trans
, bool op_mode_leave
)
520 IWL_DEBUG_INFO(trans
, "Stop card, put in low power state\n");
523 if (!test_bit(STATUS_DEVICE_ENABLED
, &trans
->status
))
524 iwl_pcie_apm_init(trans
);
526 /* inform ME that we are leaving */
527 if (trans
->trans_cfg
->device_family
== IWL_DEVICE_FAMILY_7000
)
528 iwl_set_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
529 APMG_PCIDEV_STT_VAL_WAKE_ME
);
530 else if (trans
->trans_cfg
->device_family
>=
531 IWL_DEVICE_FAMILY_8000
) {
532 iwl_set_bit(trans
, CSR_DBG_LINK_PWR_MGMT_REG
,
533 CSR_RESET_LINK_PWR_MGMT_DISABLED
);
534 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
535 CSR_HW_IF_CONFIG_REG_PREPARE
|
536 CSR_HW_IF_CONFIG_REG_ENABLE_PME
);
538 iwl_clear_bit(trans
, CSR_DBG_LINK_PWR_MGMT_REG
,
539 CSR_RESET_LINK_PWR_MGMT_DISABLED
);
544 clear_bit(STATUS_DEVICE_ENABLED
, &trans
->status
);
546 /* Stop device's DMA activity */
547 iwl_pcie_apm_stop_master(trans
);
549 if (trans
->cfg
->lp_xtal_workaround
) {
550 iwl_pcie_apm_lp_xtal_enable(trans
);
554 iwl_trans_pcie_sw_reset(trans
);
557 * Clear "initialization complete" bit to move adapter from
558 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
560 iwl_clear_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
563 static int iwl_pcie_nic_init(struct iwl_trans
*trans
)
565 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
569 spin_lock(&trans_pcie
->irq_lock
);
570 ret
= iwl_pcie_apm_init(trans
);
571 spin_unlock(&trans_pcie
->irq_lock
);
576 iwl_pcie_set_pwr(trans
, false);
578 iwl_op_mode_nic_config(trans
->op_mode
);
580 /* Allocate the RX queue, or reset if it is already allocated */
581 iwl_pcie_rx_init(trans
);
583 /* Allocate or reset and init all Tx and Command queues */
584 if (iwl_pcie_tx_init(trans
))
587 if (trans
->trans_cfg
->base_params
->shadow_reg_enable
) {
588 /* enable shadow regs in HW */
589 iwl_set_bit(trans
, CSR_MAC_SHADOW_REG_CTRL
, 0x800FFFFF);
590 IWL_DEBUG_INFO(trans
, "Enabling shadow registers in device\n");
596 #define HW_READY_TIMEOUT (50)
598 /* Note: returns poll_bit return value, which is >= 0 if success */
599 static int iwl_pcie_set_hw_ready(struct iwl_trans
*trans
)
603 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
604 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
);
606 /* See if we got it */
607 ret
= iwl_poll_bit(trans
, CSR_HW_IF_CONFIG_REG
,
608 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
609 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
613 iwl_set_bit(trans
, CSR_MBOX_SET_REG
, CSR_MBOX_SET_REG_OS_ALIVE
);
615 IWL_DEBUG_INFO(trans
, "hardware%s ready\n", ret
< 0 ? " not" : "");
619 /* Note: returns standard 0/-ERROR code */
620 int iwl_pcie_prepare_card_hw(struct iwl_trans
*trans
)
626 IWL_DEBUG_INFO(trans
, "iwl_trans_prepare_card_hw enter\n");
628 ret
= iwl_pcie_set_hw_ready(trans
);
629 /* If the card is ready, exit 0 */
633 iwl_set_bit(trans
, CSR_DBG_LINK_PWR_MGMT_REG
,
634 CSR_RESET_LINK_PWR_MGMT_DISABLED
);
635 usleep_range(1000, 2000);
637 for (iter
= 0; iter
< 10; iter
++) {
638 /* If HW is not ready, prepare the conditions to check again */
639 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
640 CSR_HW_IF_CONFIG_REG_PREPARE
);
643 ret
= iwl_pcie_set_hw_ready(trans
);
647 usleep_range(200, 1000);
649 } while (t
< 150000);
653 IWL_ERR(trans
, "Couldn't prepare the card\n");
661 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans
*trans
,
662 u32 dst_addr
, dma_addr_t phy_addr
,
665 iwl_write32(trans
, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
666 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE
);
668 iwl_write32(trans
, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL
),
671 iwl_write32(trans
, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL
),
672 phy_addr
& FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK
);
674 iwl_write32(trans
, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL
),
675 (iwl_get_dma_hi_addr(phy_addr
)
676 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT
) | byte_cnt
);
678 iwl_write32(trans
, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL
),
679 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM
) |
680 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX
) |
681 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID
);
683 iwl_write32(trans
, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
684 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
685 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE
|
686 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD
);
689 static int iwl_pcie_load_firmware_chunk(struct iwl_trans
*trans
,
690 u32 dst_addr
, dma_addr_t phy_addr
,
693 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
697 trans_pcie
->ucode_write_complete
= false;
699 if (!iwl_trans_grab_nic_access(trans
, &flags
))
702 iwl_pcie_load_firmware_chunk_fh(trans
, dst_addr
, phy_addr
,
704 iwl_trans_release_nic_access(trans
, &flags
);
706 ret
= wait_event_timeout(trans_pcie
->ucode_write_waitq
,
707 trans_pcie
->ucode_write_complete
, 5 * HZ
);
709 IWL_ERR(trans
, "Failed to load firmware chunk!\n");
710 iwl_trans_pcie_dump_regs(trans
);
717 static int iwl_pcie_load_section(struct iwl_trans
*trans
, u8 section_num
,
718 const struct fw_desc
*section
)
722 u32 offset
, chunk_sz
= min_t(u32
, FH_MEM_TB_MAX_LENGTH
, section
->len
);
725 IWL_DEBUG_FW(trans
, "[%d] uCode section being loaded...\n",
728 v_addr
= dma_alloc_coherent(trans
->dev
, chunk_sz
, &p_addr
,
729 GFP_KERNEL
| __GFP_NOWARN
);
731 IWL_DEBUG_INFO(trans
, "Falling back to small chunks of DMA\n");
732 chunk_sz
= PAGE_SIZE
;
733 v_addr
= dma_alloc_coherent(trans
->dev
, chunk_sz
,
734 &p_addr
, GFP_KERNEL
);
739 for (offset
= 0; offset
< section
->len
; offset
+= chunk_sz
) {
740 u32 copy_size
, dst_addr
;
741 bool extended_addr
= false;
743 copy_size
= min_t(u32
, chunk_sz
, section
->len
- offset
);
744 dst_addr
= section
->offset
+ offset
;
746 if (dst_addr
>= IWL_FW_MEM_EXTENDED_START
&&
747 dst_addr
<= IWL_FW_MEM_EXTENDED_END
)
748 extended_addr
= true;
751 iwl_set_bits_prph(trans
, LMPM_CHICK
,
752 LMPM_CHICK_EXTENDED_ADDR_SPACE
);
754 memcpy(v_addr
, (u8
*)section
->data
+ offset
, copy_size
);
755 ret
= iwl_pcie_load_firmware_chunk(trans
, dst_addr
, p_addr
,
759 iwl_clear_bits_prph(trans
, LMPM_CHICK
,
760 LMPM_CHICK_EXTENDED_ADDR_SPACE
);
764 "Could not load the [%d] uCode section\n",
770 dma_free_coherent(trans
->dev
, chunk_sz
, v_addr
, p_addr
);
774 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans
*trans
,
775 const struct fw_img
*image
,
777 int *first_ucode_section
)
780 int i
, ret
= 0, sec_num
= 0x1;
781 u32 val
, last_read_idx
= 0;
785 *first_ucode_section
= 0;
788 (*first_ucode_section
)++;
791 for (i
= *first_ucode_section
; i
< image
->num_sec
; i
++) {
795 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
797 * PAGING_SEPARATOR_SECTION delimiter - separate between
798 * CPU2 non paged to CPU2 paging sec.
800 if (!image
->sec
[i
].data
||
801 image
->sec
[i
].offset
== CPU1_CPU2_SEPARATOR_SECTION
||
802 image
->sec
[i
].offset
== PAGING_SEPARATOR_SECTION
) {
804 "Break since Data not valid or Empty section, sec = %d\n",
809 ret
= iwl_pcie_load_section(trans
, i
, &image
->sec
[i
]);
813 /* Notify ucode of loaded section number and status */
814 val
= iwl_read_direct32(trans
, FH_UCODE_LOAD_STATUS
);
815 val
= val
| (sec_num
<< shift_param
);
816 iwl_write_direct32(trans
, FH_UCODE_LOAD_STATUS
, val
);
818 sec_num
= (sec_num
<< 1) | 0x1;
821 *first_ucode_section
= last_read_idx
;
823 iwl_enable_interrupts(trans
);
825 if (trans
->trans_cfg
->use_tfh
) {
827 iwl_write_prph(trans
, UREG_UCODE_LOAD_STATUS
,
830 iwl_write_prph(trans
, UREG_UCODE_LOAD_STATUS
,
834 iwl_write_direct32(trans
, FH_UCODE_LOAD_STATUS
,
837 iwl_write_direct32(trans
, FH_UCODE_LOAD_STATUS
,
844 static int iwl_pcie_load_cpu_sections(struct iwl_trans
*trans
,
845 const struct fw_img
*image
,
847 int *first_ucode_section
)
850 u32 last_read_idx
= 0;
853 *first_ucode_section
= 0;
855 (*first_ucode_section
)++;
857 for (i
= *first_ucode_section
; i
< image
->num_sec
; i
++) {
861 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
863 * PAGING_SEPARATOR_SECTION delimiter - separate between
864 * CPU2 non paged to CPU2 paging sec.
866 if (!image
->sec
[i
].data
||
867 image
->sec
[i
].offset
== CPU1_CPU2_SEPARATOR_SECTION
||
868 image
->sec
[i
].offset
== PAGING_SEPARATOR_SECTION
) {
870 "Break since Data not valid or Empty section, sec = %d\n",
875 ret
= iwl_pcie_load_section(trans
, i
, &image
->sec
[i
]);
880 *first_ucode_section
= last_read_idx
;
885 static void iwl_pcie_apply_destination_ini(struct iwl_trans
*trans
)
887 enum iwl_fw_ini_allocation_id alloc_id
= IWL_FW_INI_ALLOCATION_ID_DBGC1
;
888 struct iwl_fw_ini_allocation_tlv
*fw_mon_cfg
=
889 &trans
->dbg
.fw_mon_cfg
[alloc_id
];
890 struct iwl_dram_data
*frag
;
892 if (!iwl_trans_dbg_ini_valid(trans
))
895 if (le32_to_cpu(fw_mon_cfg
->buf_location
) ==
896 IWL_FW_INI_LOCATION_SRAM_PATH
) {
897 IWL_DEBUG_FW(trans
, "WRT: Applying SMEM buffer destination\n");
898 /* set sram monitor by enabling bit 7 */
899 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
900 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM
);
905 if (le32_to_cpu(fw_mon_cfg
->buf_location
) !=
906 IWL_FW_INI_LOCATION_DRAM_PATH
||
907 !trans
->dbg
.fw_mon_ini
[alloc_id
].num_frags
)
910 frag
= &trans
->dbg
.fw_mon_ini
[alloc_id
].frags
[0];
912 IWL_DEBUG_FW(trans
, "WRT: Applying DRAM destination (alloc_id=%u)\n",
915 iwl_write_umac_prph(trans
, MON_BUFF_BASE_ADDR_VER2
,
916 frag
->physical
>> MON_BUFF_SHIFT_VER2
);
917 iwl_write_umac_prph(trans
, MON_BUFF_END_ADDR_VER2
,
918 (frag
->physical
+ frag
->size
- 256) >>
919 MON_BUFF_SHIFT_VER2
);
922 void iwl_pcie_apply_destination(struct iwl_trans
*trans
)
924 const struct iwl_fw_dbg_dest_tlv_v1
*dest
= trans
->dbg
.dest_tlv
;
925 const struct iwl_dram_data
*fw_mon
= &trans
->dbg
.fw_mon
;
928 if (iwl_trans_dbg_ini_valid(trans
)) {
929 iwl_pcie_apply_destination_ini(trans
);
933 IWL_INFO(trans
, "Applying debug destination %s\n",
934 get_fw_dbg_mode_string(dest
->monitor_mode
));
936 if (dest
->monitor_mode
== EXTERNAL_MODE
)
937 iwl_pcie_alloc_fw_monitor(trans
, dest
->size_power
);
939 IWL_WARN(trans
, "PCI should have external buffer debug\n");
941 for (i
= 0; i
< trans
->dbg
.n_dest_reg
; i
++) {
942 u32 addr
= le32_to_cpu(dest
->reg_ops
[i
].addr
);
943 u32 val
= le32_to_cpu(dest
->reg_ops
[i
].val
);
945 switch (dest
->reg_ops
[i
].op
) {
947 iwl_write32(trans
, addr
, val
);
950 iwl_set_bit(trans
, addr
, BIT(val
));
953 iwl_clear_bit(trans
, addr
, BIT(val
));
956 iwl_write_prph(trans
, addr
, val
);
959 iwl_set_bits_prph(trans
, addr
, BIT(val
));
962 iwl_clear_bits_prph(trans
, addr
, BIT(val
));
965 if (iwl_read_prph(trans
, addr
) & BIT(val
)) {
967 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
973 IWL_ERR(trans
, "FW debug - unknown OP %d\n",
974 dest
->reg_ops
[i
].op
);
980 if (dest
->monitor_mode
== EXTERNAL_MODE
&& fw_mon
->size
) {
981 iwl_write_prph(trans
, le32_to_cpu(dest
->base_reg
),
982 fw_mon
->physical
>> dest
->base_shift
);
983 if (trans
->trans_cfg
->device_family
>= IWL_DEVICE_FAMILY_8000
)
984 iwl_write_prph(trans
, le32_to_cpu(dest
->end_reg
),
985 (fw_mon
->physical
+ fw_mon
->size
-
986 256) >> dest
->end_shift
);
988 iwl_write_prph(trans
, le32_to_cpu(dest
->end_reg
),
989 (fw_mon
->physical
+ fw_mon
->size
) >>
994 static int iwl_pcie_load_given_ucode(struct iwl_trans
*trans
,
995 const struct fw_img
*image
)
998 int first_ucode_section
;
1000 IWL_DEBUG_FW(trans
, "working with %s CPU\n",
1001 image
->is_dual_cpus
? "Dual" : "Single");
1003 /* load to FW the binary non secured sections of CPU1 */
1004 ret
= iwl_pcie_load_cpu_sections(trans
, image
, 1, &first_ucode_section
);
1008 if (image
->is_dual_cpus
) {
1009 /* set CPU2 header address */
1010 iwl_write_prph(trans
,
1011 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR
,
1012 LMPM_SECURE_CPU2_HDR_MEM_SPACE
);
1014 /* load to FW the binary sections of CPU2 */
1015 ret
= iwl_pcie_load_cpu_sections(trans
, image
, 2,
1016 &first_ucode_section
);
1021 if (iwl_pcie_dbg_on(trans
))
1022 iwl_pcie_apply_destination(trans
);
1024 iwl_enable_interrupts(trans
);
1026 /* release CPU reset */
1027 iwl_write32(trans
, CSR_RESET
, 0);
1032 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans
*trans
,
1033 const struct fw_img
*image
)
1036 int first_ucode_section
;
1038 IWL_DEBUG_FW(trans
, "working with %s CPU\n",
1039 image
->is_dual_cpus
? "Dual" : "Single");
1041 if (iwl_pcie_dbg_on(trans
))
1042 iwl_pcie_apply_destination(trans
);
1044 IWL_DEBUG_POWER(trans
, "Original WFPM value = 0x%08X\n",
1045 iwl_read_prph(trans
, WFPM_GP2
));
1048 * Set default value. On resume reading the values that were
1049 * zeored can provide debug data on the resume flow.
1050 * This is for debugging only and has no functional impact.
1052 iwl_write_prph(trans
, WFPM_GP2
, 0x01010101);
1054 /* configure the ucode to be ready to get the secured image */
1055 /* release CPU reset */
1056 iwl_write_prph(trans
, RELEASE_CPU_RESET
, RELEASE_CPU_RESET_BIT
);
1058 /* load to FW the binary Secured sections of CPU1 */
1059 ret
= iwl_pcie_load_cpu_sections_8000(trans
, image
, 1,
1060 &first_ucode_section
);
1064 /* load to FW the binary sections of CPU2 */
1065 return iwl_pcie_load_cpu_sections_8000(trans
, image
, 2,
1066 &first_ucode_section
);
1069 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans
*trans
)
1071 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1072 bool hw_rfkill
= iwl_is_rfkill_set(trans
);
1073 bool prev
= test_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1077 set_bit(STATUS_RFKILL_HW
, &trans
->status
);
1078 set_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1080 clear_bit(STATUS_RFKILL_HW
, &trans
->status
);
1081 if (trans_pcie
->opmode_down
)
1082 clear_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1085 report
= test_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1088 iwl_trans_pcie_rf_kill(trans
, report
);
1093 struct iwl_causes_list
{
1099 static struct iwl_causes_list causes_list
[] = {
1100 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM
, CSR_MSIX_FH_INT_MASK_AD
, 0},
1101 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM
, CSR_MSIX_FH_INT_MASK_AD
, 0x1},
1102 {MSIX_FH_INT_CAUSES_S2D
, CSR_MSIX_FH_INT_MASK_AD
, 0x3},
1103 {MSIX_FH_INT_CAUSES_FH_ERR
, CSR_MSIX_FH_INT_MASK_AD
, 0x5},
1104 {MSIX_HW_INT_CAUSES_REG_ALIVE
, CSR_MSIX_HW_INT_MASK_AD
, 0x10},
1105 {MSIX_HW_INT_CAUSES_REG_WAKEUP
, CSR_MSIX_HW_INT_MASK_AD
, 0x11},
1106 {MSIX_HW_INT_CAUSES_REG_IML
, CSR_MSIX_HW_INT_MASK_AD
, 0x12},
1107 {MSIX_HW_INT_CAUSES_REG_CT_KILL
, CSR_MSIX_HW_INT_MASK_AD
, 0x16},
1108 {MSIX_HW_INT_CAUSES_REG_RF_KILL
, CSR_MSIX_HW_INT_MASK_AD
, 0x17},
1109 {MSIX_HW_INT_CAUSES_REG_PERIODIC
, CSR_MSIX_HW_INT_MASK_AD
, 0x18},
1110 {MSIX_HW_INT_CAUSES_REG_SW_ERR
, CSR_MSIX_HW_INT_MASK_AD
, 0x29},
1111 {MSIX_HW_INT_CAUSES_REG_SCD
, CSR_MSIX_HW_INT_MASK_AD
, 0x2A},
1112 {MSIX_HW_INT_CAUSES_REG_FH_TX
, CSR_MSIX_HW_INT_MASK_AD
, 0x2B},
1113 {MSIX_HW_INT_CAUSES_REG_HW_ERR
, CSR_MSIX_HW_INT_MASK_AD
, 0x2D},
1114 {MSIX_HW_INT_CAUSES_REG_HAP
, CSR_MSIX_HW_INT_MASK_AD
, 0x2E},
1117 static void iwl_pcie_map_non_rx_causes(struct iwl_trans
*trans
)
1119 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1120 int val
= trans_pcie
->def_irq
| MSIX_NON_AUTO_CLEAR_CAUSE
;
1121 int i
, arr_size
= ARRAY_SIZE(causes_list
);
1122 struct iwl_causes_list
*causes
= causes_list
;
1125 * Access all non RX causes and map them to the default irq.
1126 * In case we are missing at least one interrupt vector,
1127 * the first interrupt vector will serve non-RX and FBQ causes.
1129 for (i
= 0; i
< arr_size
; i
++) {
1130 iwl_write8(trans
, CSR_MSIX_IVAR(causes
[i
].addr
), val
);
1131 iwl_clear_bit(trans
, causes
[i
].mask_reg
,
1132 causes
[i
].cause_num
);
1136 static void iwl_pcie_map_rx_causes(struct iwl_trans
*trans
)
1138 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1140 trans_pcie
->shared_vec_mask
& IWL_SHARED_IRQ_FIRST_RSS
? 1 : 0;
1144 * The first RX queue - fallback queue, which is designated for
1145 * management frame, command responses etc, is always mapped to the
1146 * first interrupt vector. The other RX queues are mapped to
1147 * the other (N - 2) interrupt vectors.
1149 val
= BIT(MSIX_FH_INT_CAUSES_Q(0));
1150 for (idx
= 1; idx
< trans
->num_rx_queues
; idx
++) {
1151 iwl_write8(trans
, CSR_MSIX_RX_IVAR(idx
),
1152 MSIX_FH_INT_CAUSES_Q(idx
- offset
));
1153 val
|= BIT(MSIX_FH_INT_CAUSES_Q(idx
));
1155 iwl_write32(trans
, CSR_MSIX_FH_INT_MASK_AD
, ~val
);
1157 val
= MSIX_FH_INT_CAUSES_Q(0);
1158 if (trans_pcie
->shared_vec_mask
& IWL_SHARED_IRQ_NON_RX
)
1159 val
|= MSIX_NON_AUTO_CLEAR_CAUSE
;
1160 iwl_write8(trans
, CSR_MSIX_RX_IVAR(0), val
);
1162 if (trans_pcie
->shared_vec_mask
& IWL_SHARED_IRQ_FIRST_RSS
)
1163 iwl_write8(trans
, CSR_MSIX_RX_IVAR(1), val
);
1166 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie
*trans_pcie
)
1168 struct iwl_trans
*trans
= trans_pcie
->trans
;
1170 if (!trans_pcie
->msix_enabled
) {
1171 if (trans
->trans_cfg
->mq_rx_supported
&&
1172 test_bit(STATUS_DEVICE_ENABLED
, &trans
->status
))
1173 iwl_write_umac_prph(trans
, UREG_CHICK
,
1174 UREG_CHICK_MSI_ENABLE
);
1178 * The IVAR table needs to be configured again after reset,
1179 * but if the device is disabled, we can't write to
1182 if (test_bit(STATUS_DEVICE_ENABLED
, &trans
->status
))
1183 iwl_write_umac_prph(trans
, UREG_CHICK
, UREG_CHICK_MSIX_ENABLE
);
1186 * Each cause from the causes list above and the RX causes is
1187 * represented as a byte in the IVAR table. The first nibble
1188 * represents the bound interrupt vector of the cause, the second
1189 * represents no auto clear for this cause. This will be set if its
1190 * interrupt vector is bound to serve other causes.
1192 iwl_pcie_map_rx_causes(trans
);
1194 iwl_pcie_map_non_rx_causes(trans
);
1197 static void iwl_pcie_init_msix(struct iwl_trans_pcie
*trans_pcie
)
1199 struct iwl_trans
*trans
= trans_pcie
->trans
;
1201 iwl_pcie_conf_msix_hw(trans_pcie
);
1203 if (!trans_pcie
->msix_enabled
)
1206 trans_pcie
->fh_init_mask
= ~iwl_read32(trans
, CSR_MSIX_FH_INT_MASK_AD
);
1207 trans_pcie
->fh_mask
= trans_pcie
->fh_init_mask
;
1208 trans_pcie
->hw_init_mask
= ~iwl_read32(trans
, CSR_MSIX_HW_INT_MASK_AD
);
1209 trans_pcie
->hw_mask
= trans_pcie
->hw_init_mask
;
1212 static void _iwl_trans_pcie_stop_device(struct iwl_trans
*trans
)
1214 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1216 lockdep_assert_held(&trans_pcie
->mutex
);
1218 if (trans_pcie
->is_down
)
1221 trans_pcie
->is_down
= true;
1223 /* tell the device to stop sending interrupts */
1224 iwl_disable_interrupts(trans
);
1226 /* device going down, Stop using ICT table */
1227 iwl_pcie_disable_ict(trans
);
1230 * If a HW restart happens during firmware loading,
1231 * then the firmware loading might call this function
1232 * and later it might be called again due to the
1233 * restart. So don't process again if the device is
1236 if (test_and_clear_bit(STATUS_DEVICE_ENABLED
, &trans
->status
)) {
1237 IWL_DEBUG_INFO(trans
,
1238 "DEVICE_ENABLED bit was set and is now cleared\n");
1239 iwl_pcie_tx_stop(trans
);
1240 iwl_pcie_rx_stop(trans
);
1242 /* Power-down device's busmaster DMA clocks */
1243 if (!trans
->cfg
->apmg_not_supported
) {
1244 iwl_write_prph(trans
, APMG_CLK_DIS_REG
,
1245 APMG_CLK_VAL_DMA_CLK_RQT
);
1250 /* Make sure (redundant) we've released our request to stay awake */
1251 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1252 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1254 /* Stop the device, and put it in low power state */
1255 iwl_pcie_apm_stop(trans
, false);
1257 iwl_trans_pcie_sw_reset(trans
);
1260 * Upon stop, the IVAR table gets erased, so msi-x won't
1261 * work. This causes a bug in RF-KILL flows, since the interrupt
1262 * that enables radio won't fire on the correct irq, and the
1263 * driver won't be able to handle the interrupt.
1264 * Configure the IVAR table again after reset.
1266 iwl_pcie_conf_msix_hw(trans_pcie
);
1269 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1270 * This is a bug in certain verions of the hardware.
1271 * Certain devices also keep sending HW RF kill interrupt all
1272 * the time, unless the interrupt is ACKed even if the interrupt
1273 * should be masked. Re-ACK all the interrupts here.
1275 iwl_disable_interrupts(trans
);
1277 /* clear all status bits */
1278 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1279 clear_bit(STATUS_INT_ENABLED
, &trans
->status
);
1280 clear_bit(STATUS_TPOWER_PMI
, &trans
->status
);
1283 * Even if we stop the HW, we still want the RF kill
1286 iwl_enable_rfkill_int(trans
);
1288 /* re-take ownership to prevent other users from stealing the device */
1289 iwl_pcie_prepare_card_hw(trans
);
1292 void iwl_pcie_synchronize_irqs(struct iwl_trans
*trans
)
1294 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1296 if (trans_pcie
->msix_enabled
) {
1299 for (i
= 0; i
< trans_pcie
->alloc_vecs
; i
++)
1300 synchronize_irq(trans_pcie
->msix_entries
[i
].vector
);
1302 synchronize_irq(trans_pcie
->pci_dev
->irq
);
1306 static int iwl_trans_pcie_start_fw(struct iwl_trans
*trans
,
1307 const struct fw_img
*fw
, bool run_in_rfkill
)
1309 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1313 /* This may fail if AMT took ownership of the device */
1314 if (iwl_pcie_prepare_card_hw(trans
)) {
1315 IWL_WARN(trans
, "Exit HW not ready\n");
1320 iwl_enable_rfkill_int(trans
);
1322 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
1325 * We enabled the RF-Kill interrupt and the handler may very
1326 * well be running. Disable the interrupts to make sure no other
1327 * interrupt can be fired.
1329 iwl_disable_interrupts(trans
);
1331 /* Make sure it finished running */
1332 iwl_pcie_synchronize_irqs(trans
);
1334 mutex_lock(&trans_pcie
->mutex
);
1336 /* If platform's RF_KILL switch is NOT set to KILL */
1337 hw_rfkill
= iwl_pcie_check_hw_rf_kill(trans
);
1338 if (hw_rfkill
&& !run_in_rfkill
) {
1343 /* Someone called stop_device, don't try to start_fw */
1344 if (trans_pcie
->is_down
) {
1346 "Can't start_fw since the HW hasn't been started\n");
1351 /* make sure rfkill handshake bits are cleared */
1352 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1353 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
,
1354 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED
);
1356 /* clear (again), then enable host interrupts */
1357 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
1359 ret
= iwl_pcie_nic_init(trans
);
1361 IWL_ERR(trans
, "Unable to init nic\n");
1366 * Now, we load the firmware and don't want to be interrupted, even
1367 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1368 * FH_TX interrupt which is needed to load the firmware). If the
1369 * RF-Kill switch is toggled, we will find out after having loaded
1370 * the firmware and return the proper value to the caller.
1372 iwl_enable_fw_load_int(trans
);
1374 /* really make sure rfkill handshake bits are cleared */
1375 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1376 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1378 /* Load the given image to the HW */
1379 if (trans
->trans_cfg
->device_family
>= IWL_DEVICE_FAMILY_8000
)
1380 ret
= iwl_pcie_load_given_ucode_8000(trans
, fw
);
1382 ret
= iwl_pcie_load_given_ucode(trans
, fw
);
1384 /* re-check RF-Kill state since we may have missed the interrupt */
1385 hw_rfkill
= iwl_pcie_check_hw_rf_kill(trans
);
1386 if (hw_rfkill
&& !run_in_rfkill
)
1390 mutex_unlock(&trans_pcie
->mutex
);
1394 static void iwl_trans_pcie_fw_alive(struct iwl_trans
*trans
, u32 scd_addr
)
1396 iwl_pcie_reset_ict(trans
);
1397 iwl_pcie_tx_start(trans
, scd_addr
);
1400 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans
*trans
,
1406 * Check again since the RF kill state may have changed while
1407 * all the interrupts were disabled, in this case we couldn't
1408 * receive the RF kill interrupt and update the state in the
1410 * Don't call the op_mode if the rkfill state hasn't changed.
1411 * This allows the op_mode to call stop_device from the rfkill
1412 * notification without endless recursion. Under very rare
1413 * circumstances, we might have a small recursion if the rfkill
1414 * state changed exactly now while we were called from stop_device.
1415 * This is very unlikely but can happen and is supported.
1417 hw_rfkill
= iwl_is_rfkill_set(trans
);
1419 set_bit(STATUS_RFKILL_HW
, &trans
->status
);
1420 set_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1422 clear_bit(STATUS_RFKILL_HW
, &trans
->status
);
1423 clear_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1425 if (hw_rfkill
!= was_in_rfkill
)
1426 iwl_trans_pcie_rf_kill(trans
, hw_rfkill
);
1429 static void iwl_trans_pcie_stop_device(struct iwl_trans
*trans
)
1431 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1434 mutex_lock(&trans_pcie
->mutex
);
1435 trans_pcie
->opmode_down
= true;
1436 was_in_rfkill
= test_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1437 _iwl_trans_pcie_stop_device(trans
);
1438 iwl_trans_pcie_handle_stop_rfkill(trans
, was_in_rfkill
);
1439 mutex_unlock(&trans_pcie
->mutex
);
1442 void iwl_trans_pcie_rf_kill(struct iwl_trans
*trans
, bool state
)
1444 struct iwl_trans_pcie __maybe_unused
*trans_pcie
=
1445 IWL_TRANS_GET_PCIE_TRANS(trans
);
1447 lockdep_assert_held(&trans_pcie
->mutex
);
1449 IWL_WARN(trans
, "reporting RF_KILL (radio %s)\n",
1450 state
? "disabled" : "enabled");
1451 if (iwl_op_mode_hw_rf_kill(trans
->op_mode
, state
)) {
1452 if (trans
->trans_cfg
->gen2
)
1453 _iwl_trans_pcie_gen2_stop_device(trans
);
1455 _iwl_trans_pcie_stop_device(trans
);
1459 void iwl_pcie_d3_complete_suspend(struct iwl_trans
*trans
,
1460 bool test
, bool reset
)
1462 iwl_disable_interrupts(trans
);
1465 * in testing mode, the host stays awake and the
1466 * hardware won't be reset (not even partially)
1471 iwl_pcie_disable_ict(trans
);
1473 iwl_pcie_synchronize_irqs(trans
);
1475 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1476 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1477 iwl_clear_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
1481 * reset TX queues -- some of their registers reset during S3
1482 * so if we don't reset everything here the D3 image would try
1483 * to execute some invalid memory upon resume
1485 iwl_trans_pcie_tx_reset(trans
);
1488 iwl_pcie_set_pwr(trans
, true);
1491 static int iwl_trans_pcie_d3_suspend(struct iwl_trans
*trans
, bool test
,
1495 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1498 /* Enable persistence mode to avoid reset */
1499 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
1500 CSR_HW_IF_CONFIG_REG_PERSIST_MODE
);
1502 if (trans
->trans_cfg
->device_family
>= IWL_DEVICE_FAMILY_AX210
) {
1503 iwl_write_umac_prph(trans
, UREG_DOORBELL_TO_ISR6
,
1504 UREG_DOORBELL_TO_ISR6_SUSPEND
);
1506 ret
= wait_event_timeout(trans_pcie
->sx_waitq
,
1507 trans_pcie
->sx_complete
, 2 * HZ
);
1509 * Invalidate it toward resume.
1511 trans_pcie
->sx_complete
= false;
1514 IWL_ERR(trans
, "Timeout entering D3\n");
1518 iwl_pcie_d3_complete_suspend(trans
, test
, reset
);
1523 static int iwl_trans_pcie_d3_resume(struct iwl_trans
*trans
,
1524 enum iwl_d3_status
*status
,
1525 bool test
, bool reset
)
1527 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1532 iwl_enable_interrupts(trans
);
1533 *status
= IWL_D3_STATUS_ALIVE
;
1537 iwl_set_bit(trans
, CSR_GP_CNTRL
,
1538 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1540 ret
= iwl_finish_nic_init(trans
, trans
->trans_cfg
);
1545 * Reconfigure IVAR table in case of MSIX or reset ict table in
1546 * MSI mode since HW reset erased it.
1547 * Also enables interrupts - none will happen as
1548 * the device doesn't know we're waking it up, only when
1549 * the opmode actually tells it after this call.
1551 iwl_pcie_conf_msix_hw(trans_pcie
);
1552 if (!trans_pcie
->msix_enabled
)
1553 iwl_pcie_reset_ict(trans
);
1554 iwl_enable_interrupts(trans
);
1556 iwl_pcie_set_pwr(trans
, false);
1559 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1560 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1562 iwl_trans_pcie_tx_reset(trans
);
1564 ret
= iwl_pcie_rx_init(trans
);
1567 "Failed to resume the device (RX reset)\n");
1572 IWL_DEBUG_POWER(trans
, "WFPM value upon resume = 0x%08X\n",
1573 iwl_read_umac_prph(trans
, WFPM_GP2
));
1575 val
= iwl_read32(trans
, CSR_RESET
);
1576 if (val
& CSR_RESET_REG_FLAG_NEVO_RESET
)
1577 *status
= IWL_D3_STATUS_RESET
;
1579 *status
= IWL_D3_STATUS_ALIVE
;
1582 if (*status
== IWL_D3_STATUS_ALIVE
&&
1583 trans
->trans_cfg
->device_family
>= IWL_DEVICE_FAMILY_AX210
) {
1584 trans_pcie
->sx_complete
= false;
1585 iwl_write_umac_prph(trans
, UREG_DOORBELL_TO_ISR6
,
1586 UREG_DOORBELL_TO_ISR6_RESUME
);
1588 ret
= wait_event_timeout(trans_pcie
->sx_waitq
,
1589 trans_pcie
->sx_complete
, 2 * HZ
);
1591 * Invalidate it toward next suspend.
1593 trans_pcie
->sx_complete
= false;
1596 IWL_ERR(trans
, "Timeout exiting D3\n");
1604 iwl_pcie_set_interrupt_capa(struct pci_dev
*pdev
,
1605 struct iwl_trans
*trans
,
1606 const struct iwl_cfg_trans_params
*cfg_trans
)
1608 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1609 int max_irqs
, num_irqs
, i
, ret
;
1611 u32 max_rx_queues
= IWL_MAX_RX_HW_QUEUES
;
1613 if (!cfg_trans
->mq_rx_supported
)
1616 if (cfg_trans
->device_family
<= IWL_DEVICE_FAMILY_9000
)
1617 max_rx_queues
= IWL_9000_MAX_RX_HW_QUEUES
;
1619 max_irqs
= min_t(u32
, num_online_cpus() + 2, max_rx_queues
);
1620 for (i
= 0; i
< max_irqs
; i
++)
1621 trans_pcie
->msix_entries
[i
].entry
= i
;
1623 num_irqs
= pci_enable_msix_range(pdev
, trans_pcie
->msix_entries
,
1624 MSIX_MIN_INTERRUPT_VECTORS
,
1627 IWL_DEBUG_INFO(trans
,
1628 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1632 trans_pcie
->def_irq
= (num_irqs
== max_irqs
) ? num_irqs
- 1 : 0;
1634 IWL_DEBUG_INFO(trans
,
1635 "MSI-X enabled. %d interrupt vectors were allocated\n",
1639 * In case the OS provides fewer interrupts than requested, different
1640 * causes will share the same interrupt vector as follows:
1641 * One interrupt less: non rx causes shared with FBQ.
1642 * Two interrupts less: non rx causes shared with FBQ and RSS.
1643 * More than two interrupts: we will use fewer RSS queues.
1645 if (num_irqs
<= max_irqs
- 2) {
1646 trans_pcie
->trans
->num_rx_queues
= num_irqs
+ 1;
1647 trans_pcie
->shared_vec_mask
= IWL_SHARED_IRQ_NON_RX
|
1648 IWL_SHARED_IRQ_FIRST_RSS
;
1649 } else if (num_irqs
== max_irqs
- 1) {
1650 trans_pcie
->trans
->num_rx_queues
= num_irqs
;
1651 trans_pcie
->shared_vec_mask
= IWL_SHARED_IRQ_NON_RX
;
1653 trans_pcie
->trans
->num_rx_queues
= num_irqs
- 1;
1655 WARN_ON(trans_pcie
->trans
->num_rx_queues
> IWL_MAX_RX_HW_QUEUES
);
1657 trans_pcie
->alloc_vecs
= num_irqs
;
1658 trans_pcie
->msix_enabled
= true;
1662 ret
= pci_enable_msi(pdev
);
1664 dev_err(&pdev
->dev
, "pci_enable_msi failed - %d\n", ret
);
1665 /* enable rfkill interrupt: hw bug w/a */
1666 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
1667 if (pci_cmd
& PCI_COMMAND_INTX_DISABLE
) {
1668 pci_cmd
&= ~PCI_COMMAND_INTX_DISABLE
;
1669 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
1674 static void iwl_pcie_irq_set_affinity(struct iwl_trans
*trans
)
1676 int iter_rx_q
, i
, ret
, cpu
, offset
;
1677 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1679 i
= trans_pcie
->shared_vec_mask
& IWL_SHARED_IRQ_FIRST_RSS
? 0 : 1;
1680 iter_rx_q
= trans_pcie
->trans
->num_rx_queues
- 1 + i
;
1682 for (; i
< iter_rx_q
; i
++) {
1684 * Get the cpu prior to the place to search
1685 * (i.e. return will be > i - 1).
1687 cpu
= cpumask_next(i
- offset
, cpu_online_mask
);
1688 cpumask_set_cpu(cpu
, &trans_pcie
->affinity_mask
[i
]);
1689 ret
= irq_set_affinity_hint(trans_pcie
->msix_entries
[i
].vector
,
1690 &trans_pcie
->affinity_mask
[i
]);
1692 IWL_ERR(trans_pcie
->trans
,
1693 "Failed to set affinity mask for IRQ %d\n",
1698 static int iwl_pcie_init_msix_handler(struct pci_dev
*pdev
,
1699 struct iwl_trans_pcie
*trans_pcie
)
1703 for (i
= 0; i
< trans_pcie
->alloc_vecs
; i
++) {
1705 struct msix_entry
*msix_entry
;
1706 const char *qname
= queue_name(&pdev
->dev
, trans_pcie
, i
);
1711 msix_entry
= &trans_pcie
->msix_entries
[i
];
1712 ret
= devm_request_threaded_irq(&pdev
->dev
,
1715 (i
== trans_pcie
->def_irq
) ?
1716 iwl_pcie_irq_msix_handler
:
1717 iwl_pcie_irq_rx_msix_handler
,
1722 IWL_ERR(trans_pcie
->trans
,
1723 "Error allocating IRQ %d\n", i
);
1728 iwl_pcie_irq_set_affinity(trans_pcie
->trans
);
1733 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans
*trans
)
1737 switch (trans
->trans_cfg
->device_family
) {
1738 case IWL_DEVICE_FAMILY_9000
:
1739 wprot
= PREG_PRPH_WPROT_9000
;
1741 case IWL_DEVICE_FAMILY_22000
:
1742 wprot
= PREG_PRPH_WPROT_22000
;
1748 hpm
= iwl_read_umac_prph_no_grab(trans
, HPM_DEBUG
);
1749 if (hpm
!= 0xa5a5a5a0 && (hpm
& PERSISTENCE_BIT
)) {
1750 u32 wprot_val
= iwl_read_umac_prph_no_grab(trans
, wprot
);
1752 if (wprot_val
& PREG_WFPM_ACCESS
) {
1754 "Error, can not clear persistence bit\n");
1757 iwl_write_umac_prph_no_grab(trans
, HPM_DEBUG
,
1758 hpm
& ~PERSISTENCE_BIT
);
1764 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans
*trans
)
1768 ret
= iwl_finish_nic_init(trans
, trans
->trans_cfg
);
1772 iwl_set_bits_prph(trans
, HPM_HIPM_GEN_CFG
,
1773 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE
);
1775 iwl_set_bits_prph(trans
, HPM_HIPM_GEN_CFG
,
1776 HPM_HIPM_GEN_CFG_CR_PG_EN
|
1777 HPM_HIPM_GEN_CFG_CR_SLP_EN
);
1779 iwl_clear_bits_prph(trans
, HPM_HIPM_GEN_CFG
,
1780 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE
);
1782 iwl_trans_pcie_sw_reset(trans
);
1787 static int _iwl_trans_pcie_start_hw(struct iwl_trans
*trans
)
1789 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1792 lockdep_assert_held(&trans_pcie
->mutex
);
1794 err
= iwl_pcie_prepare_card_hw(trans
);
1796 IWL_ERR(trans
, "Error while preparing HW: %d\n", err
);
1800 err
= iwl_trans_pcie_clear_persistence_bit(trans
);
1804 iwl_trans_pcie_sw_reset(trans
);
1806 if (trans
->trans_cfg
->device_family
== IWL_DEVICE_FAMILY_22000
&&
1807 trans
->trans_cfg
->integrated
) {
1808 err
= iwl_pcie_gen2_force_power_gating(trans
);
1813 err
= iwl_pcie_apm_init(trans
);
1817 iwl_pcie_init_msix(trans_pcie
);
1819 /* From now on, the op_mode will be kept updated about RF kill state */
1820 iwl_enable_rfkill_int(trans
);
1822 trans_pcie
->opmode_down
= false;
1824 /* Set is_down to false here so that...*/
1825 trans_pcie
->is_down
= false;
1827 /* ...rfkill can call stop_device and set it false if needed */
1828 iwl_pcie_check_hw_rf_kill(trans
);
1833 static int iwl_trans_pcie_start_hw(struct iwl_trans
*trans
)
1835 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1838 mutex_lock(&trans_pcie
->mutex
);
1839 ret
= _iwl_trans_pcie_start_hw(trans
);
1840 mutex_unlock(&trans_pcie
->mutex
);
1845 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans
*trans
)
1847 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1849 mutex_lock(&trans_pcie
->mutex
);
1851 /* disable interrupts - don't enable HW RF kill interrupt */
1852 iwl_disable_interrupts(trans
);
1854 iwl_pcie_apm_stop(trans
, true);
1856 iwl_disable_interrupts(trans
);
1858 iwl_pcie_disable_ict(trans
);
1860 mutex_unlock(&trans_pcie
->mutex
);
1862 iwl_pcie_synchronize_irqs(trans
);
1865 static void iwl_trans_pcie_write8(struct iwl_trans
*trans
, u32 ofs
, u8 val
)
1867 writeb(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1870 static void iwl_trans_pcie_write32(struct iwl_trans
*trans
, u32 ofs
, u32 val
)
1872 writel(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1875 static u32
iwl_trans_pcie_read32(struct iwl_trans
*trans
, u32 ofs
)
1877 return readl(IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1880 static u32
iwl_trans_pcie_prph_msk(struct iwl_trans
*trans
)
1882 if (trans
->trans_cfg
->device_family
>= IWL_DEVICE_FAMILY_AX210
)
1888 static u32
iwl_trans_pcie_read_prph(struct iwl_trans
*trans
, u32 reg
)
1890 u32 mask
= iwl_trans_pcie_prph_msk(trans
);
1892 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_RADDR
,
1893 ((reg
& mask
) | (3 << 24)));
1894 return iwl_trans_pcie_read32(trans
, HBUS_TARG_PRPH_RDAT
);
1897 static void iwl_trans_pcie_write_prph(struct iwl_trans
*trans
, u32 addr
,
1900 u32 mask
= iwl_trans_pcie_prph_msk(trans
);
1902 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_WADDR
,
1903 ((addr
& mask
) | (3 << 24)));
1904 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_WDAT
, val
);
1907 static void iwl_trans_pcie_configure(struct iwl_trans
*trans
,
1908 const struct iwl_trans_config
*trans_cfg
)
1910 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1912 trans
->txqs
.cmd
.q_id
= trans_cfg
->cmd_queue
;
1913 trans
->txqs
.cmd
.fifo
= trans_cfg
->cmd_fifo
;
1914 trans
->txqs
.cmd
.wdg_timeout
= trans_cfg
->cmd_q_wdg_timeout
;
1915 trans
->txqs
.page_offs
= trans_cfg
->cb_data_offs
;
1916 trans
->txqs
.dev_cmd_offs
= trans_cfg
->cb_data_offs
+ sizeof(void *);
1918 if (WARN_ON(trans_cfg
->n_no_reclaim_cmds
> MAX_NO_RECLAIM_CMDS
))
1919 trans_pcie
->n_no_reclaim_cmds
= 0;
1921 trans_pcie
->n_no_reclaim_cmds
= trans_cfg
->n_no_reclaim_cmds
;
1922 if (trans_pcie
->n_no_reclaim_cmds
)
1923 memcpy(trans_pcie
->no_reclaim_cmds
, trans_cfg
->no_reclaim_cmds
,
1924 trans_pcie
->n_no_reclaim_cmds
* sizeof(u8
));
1926 trans_pcie
->rx_buf_size
= trans_cfg
->rx_buf_size
;
1927 trans_pcie
->rx_page_order
=
1928 iwl_trans_get_rb_size_order(trans_pcie
->rx_buf_size
);
1929 trans_pcie
->rx_buf_bytes
=
1930 iwl_trans_get_rb_size(trans_pcie
->rx_buf_size
);
1931 trans_pcie
->supported_dma_mask
= DMA_BIT_MASK(12);
1932 if (trans
->trans_cfg
->device_family
>= IWL_DEVICE_FAMILY_AX210
)
1933 trans_pcie
->supported_dma_mask
= DMA_BIT_MASK(11);
1935 trans
->txqs
.bc_table_dword
= trans_cfg
->bc_table_dword
;
1936 trans_pcie
->scd_set_active
= trans_cfg
->scd_set_active
;
1938 trans
->command_groups
= trans_cfg
->command_groups
;
1939 trans
->command_groups_size
= trans_cfg
->command_groups_size
;
1941 /* Initialize NAPI here - it should be before registering to mac80211
1942 * in the opmode but after the HW struct is allocated.
1943 * As this function may be called again in some corner cases don't
1944 * do anything if NAPI was already initialized.
1946 if (trans_pcie
->napi_dev
.reg_state
!= NETREG_DUMMY
)
1947 init_dummy_netdev(&trans_pcie
->napi_dev
);
1950 void iwl_trans_pcie_free(struct iwl_trans
*trans
)
1952 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1955 iwl_pcie_synchronize_irqs(trans
);
1957 if (trans
->trans_cfg
->gen2
)
1958 iwl_txq_gen2_tx_free(trans
);
1960 iwl_pcie_tx_free(trans
);
1961 iwl_pcie_rx_free(trans
);
1963 if (trans_pcie
->rba
.alloc_wq
) {
1964 destroy_workqueue(trans_pcie
->rba
.alloc_wq
);
1965 trans_pcie
->rba
.alloc_wq
= NULL
;
1968 if (trans_pcie
->msix_enabled
) {
1969 for (i
= 0; i
< trans_pcie
->alloc_vecs
; i
++) {
1970 irq_set_affinity_hint(
1971 trans_pcie
->msix_entries
[i
].vector
,
1975 trans_pcie
->msix_enabled
= false;
1977 iwl_pcie_free_ict(trans
);
1980 iwl_pcie_free_fw_monitor(trans
);
1982 if (trans_pcie
->pnvm_dram
.size
)
1983 dma_free_coherent(trans
->dev
, trans_pcie
->pnvm_dram
.size
,
1984 trans_pcie
->pnvm_dram
.block
,
1985 trans_pcie
->pnvm_dram
.physical
);
1987 mutex_destroy(&trans_pcie
->mutex
);
1988 iwl_trans_free(trans
);
1991 static void iwl_trans_pcie_set_pmi(struct iwl_trans
*trans
, bool state
)
1994 set_bit(STATUS_TPOWER_PMI
, &trans
->status
);
1996 clear_bit(STATUS_TPOWER_PMI
, &trans
->status
);
1999 struct iwl_trans_pcie_removal
{
2000 struct pci_dev
*pdev
;
2001 struct work_struct work
;
2004 static void iwl_trans_pcie_removal_wk(struct work_struct
*wk
)
2006 struct iwl_trans_pcie_removal
*removal
=
2007 container_of(wk
, struct iwl_trans_pcie_removal
, work
);
2008 struct pci_dev
*pdev
= removal
->pdev
;
2009 static char *prop
[] = {"EVENT=INACCESSIBLE", NULL
};
2011 dev_err(&pdev
->dev
, "Device gone - attempting removal\n");
2012 kobject_uevent_env(&pdev
->dev
.kobj
, KOBJ_CHANGE
, prop
);
2013 pci_lock_rescan_remove();
2015 pci_stop_and_remove_bus_device(pdev
);
2016 pci_unlock_rescan_remove();
2019 module_put(THIS_MODULE
);
2022 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans
*trans
,
2023 unsigned long *flags
)
2026 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2028 spin_lock_irqsave(&trans_pcie
->reg_lock
, *flags
);
2030 if (trans_pcie
->cmd_hold_nic_awake
)
2033 /* this bit wakes up the NIC */
2034 __iwl_trans_pcie_set_bit(trans
, CSR_GP_CNTRL
,
2035 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
2036 if (trans
->trans_cfg
->device_family
>= IWL_DEVICE_FAMILY_8000
)
2040 * These bits say the device is running, and should keep running for
2041 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
2042 * but they do not indicate that embedded SRAM is restored yet;
2043 * HW with volatile SRAM must save/restore contents to/from
2044 * host DRAM when sleeping/waking for power-saving.
2045 * Each direction takes approximately 1/4 millisecond; with this
2046 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
2047 * series of register accesses are expected (e.g. reading Event Log),
2048 * to keep device from sleeping.
2050 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
2051 * SRAM is okay/restored. We don't check that here because this call
2052 * is just for hardware register access; but GP1 MAC_SLEEP
2053 * check is a good idea before accessing the SRAM of HW with
2054 * volatile SRAM (e.g. reading Event Log).
2056 * 5000 series and later (including 1000 series) have non-volatile SRAM,
2057 * and do not save/restore SRAM when power cycling.
2059 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
2060 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN
,
2061 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
|
2062 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP
), 15000);
2063 if (unlikely(ret
< 0)) {
2064 u32 cntrl
= iwl_read32(trans
, CSR_GP_CNTRL
);
2067 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
2070 iwl_trans_pcie_dump_regs(trans
);
2072 if (iwlwifi_mod_params
.remove_when_gone
&& cntrl
== ~0U) {
2073 struct iwl_trans_pcie_removal
*removal
;
2075 if (test_bit(STATUS_TRANS_DEAD
, &trans
->status
))
2078 IWL_ERR(trans
, "Device gone - scheduling removal!\n");
2081 * get a module reference to avoid doing this
2082 * while unloading anyway and to avoid
2083 * scheduling a work with code that's being
2086 if (!try_module_get(THIS_MODULE
)) {
2088 "Module is being unloaded - abort\n");
2092 removal
= kzalloc(sizeof(*removal
), GFP_ATOMIC
);
2094 module_put(THIS_MODULE
);
2098 * we don't need to clear this flag, because
2099 * the trans will be freed and reallocated.
2101 set_bit(STATUS_TRANS_DEAD
, &trans
->status
);
2103 removal
->pdev
= to_pci_dev(trans
->dev
);
2104 INIT_WORK(&removal
->work
, iwl_trans_pcie_removal_wk
);
2105 pci_dev_get(removal
->pdev
);
2106 schedule_work(&removal
->work
);
2108 iwl_write32(trans
, CSR_RESET
,
2109 CSR_RESET_REG_FLAG_FORCE_NMI
);
2113 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, *flags
);
2119 * Fool sparse by faking we release the lock - sparse will
2120 * track nic_access anyway.
2122 __release(&trans_pcie
->reg_lock
);
2126 static void iwl_trans_pcie_release_nic_access(struct iwl_trans
*trans
,
2127 unsigned long *flags
)
2129 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2131 lockdep_assert_held(&trans_pcie
->reg_lock
);
2134 * Fool sparse by faking we acquiring the lock - sparse will
2135 * track nic_access anyway.
2137 __acquire(&trans_pcie
->reg_lock
);
2139 if (trans_pcie
->cmd_hold_nic_awake
)
2142 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
2143 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
2145 * Above we read the CSR_GP_CNTRL register, which will flush
2146 * any previous writes, but we need the write that clears the
2147 * MAC_ACCESS_REQ bit to be performed before any other writes
2148 * scheduled on different CPUs (after we drop reg_lock).
2151 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, *flags
);
2154 static int iwl_trans_pcie_read_mem(struct iwl_trans
*trans
, u32 addr
,
2155 void *buf
, int dwords
)
2157 unsigned long flags
;
2161 while (offs
< dwords
) {
2162 /* limit the time we spin here under lock to 1/2s */
2163 ktime_t timeout
= ktime_add_us(ktime_get(), 500 * USEC_PER_MSEC
);
2165 if (iwl_trans_grab_nic_access(trans
, &flags
)) {
2166 iwl_write32(trans
, HBUS_TARG_MEM_RADDR
,
2169 while (offs
< dwords
) {
2170 vals
[offs
] = iwl_read32(trans
,
2171 HBUS_TARG_MEM_RDAT
);
2174 /* calling ktime_get is expensive so
2175 * do it once in 128 reads
2177 if (offs
% 128 == 0 && ktime_after(ktime_get(),
2181 iwl_trans_release_nic_access(trans
, &flags
);
2190 static int iwl_trans_pcie_write_mem(struct iwl_trans
*trans
, u32 addr
,
2191 const void *buf
, int dwords
)
2193 unsigned long flags
;
2195 const u32
*vals
= buf
;
2197 if (iwl_trans_grab_nic_access(trans
, &flags
)) {
2198 iwl_write32(trans
, HBUS_TARG_MEM_WADDR
, addr
);
2199 for (offs
= 0; offs
< dwords
; offs
++)
2200 iwl_write32(trans
, HBUS_TARG_MEM_WDAT
,
2201 vals
? vals
[offs
] : 0);
2202 iwl_trans_release_nic_access(trans
, &flags
);
2209 static int iwl_trans_pcie_read_config32(struct iwl_trans
*trans
, u32 ofs
,
2212 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans
)->pci_dev
,
2216 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans
*trans
, bool block
)
2220 for (i
= 0; i
< trans
->trans_cfg
->base_params
->num_of_queues
; i
++) {
2221 struct iwl_txq
*txq
= trans
->txqs
.txq
[i
];
2223 if (i
== trans
->txqs
.cmd
.q_id
)
2226 spin_lock_bh(&txq
->lock
);
2228 if (!block
&& !(WARN_ON_ONCE(!txq
->block
))) {
2231 iwl_write32(trans
, HBUS_TARG_WRPTR
,
2232 txq
->write_ptr
| (i
<< 8));
2238 spin_unlock_bh(&txq
->lock
);
2242 #define IWL_FLUSH_WAIT_MS 2000
2244 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans
*trans
, int queue
,
2245 struct iwl_trans_rxq_dma_data
*data
)
2247 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2249 if (queue
>= trans
->num_rx_queues
|| !trans_pcie
->rxq
)
2252 data
->fr_bd_cb
= trans_pcie
->rxq
[queue
].bd_dma
;
2253 data
->urbd_stts_wrptr
= trans_pcie
->rxq
[queue
].rb_stts_dma
;
2254 data
->ur_bd_cb
= trans_pcie
->rxq
[queue
].used_bd_dma
;
2255 data
->fr_bd_wid
= 0;
2260 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans
*trans
, int txq_idx
)
2262 struct iwl_txq
*txq
;
2263 unsigned long now
= jiffies
;
2267 /* Make sure the NIC is still alive in the bus */
2268 if (test_bit(STATUS_TRANS_DEAD
, &trans
->status
))
2271 if (!test_bit(txq_idx
, trans
->txqs
.queue_used
))
2274 IWL_DEBUG_TX_QUEUES(trans
, "Emptying queue %d...\n", txq_idx
);
2275 txq
= trans
->txqs
.txq
[txq_idx
];
2277 spin_lock_bh(&txq
->lock
);
2278 overflow_tx
= txq
->overflow_tx
||
2279 !skb_queue_empty(&txq
->overflow_q
);
2280 spin_unlock_bh(&txq
->lock
);
2282 wr_ptr
= READ_ONCE(txq
->write_ptr
);
2284 while ((txq
->read_ptr
!= READ_ONCE(txq
->write_ptr
) ||
2286 !time_after(jiffies
,
2287 now
+ msecs_to_jiffies(IWL_FLUSH_WAIT_MS
))) {
2288 u8 write_ptr
= READ_ONCE(txq
->write_ptr
);
2291 * If write pointer moved during the wait, warn only
2292 * if the TX came from op mode. In case TX came from
2293 * trans layer (overflow TX) don't warn.
2295 if (WARN_ONCE(wr_ptr
!= write_ptr
&& !overflow_tx
,
2296 "WR pointer moved while flushing %d -> %d\n",
2301 usleep_range(1000, 2000);
2303 spin_lock_bh(&txq
->lock
);
2304 overflow_tx
= txq
->overflow_tx
||
2305 !skb_queue_empty(&txq
->overflow_q
);
2306 spin_unlock_bh(&txq
->lock
);
2309 if (txq
->read_ptr
!= txq
->write_ptr
) {
2311 "fail to flush all tx fifo queues Q %d\n", txq_idx
);
2312 iwl_txq_log_scd_error(trans
, txq
);
2316 IWL_DEBUG_TX_QUEUES(trans
, "Queue %d is now empty.\n", txq_idx
);
2321 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans
*trans
, u32 txq_bm
)
2326 /* waiting for all the tx frames complete might take a while */
2328 cnt
< trans
->trans_cfg
->base_params
->num_of_queues
;
2331 if (cnt
== trans
->txqs
.cmd
.q_id
)
2333 if (!test_bit(cnt
, trans
->txqs
.queue_used
))
2335 if (!(BIT(cnt
) & txq_bm
))
2338 ret
= iwl_trans_pcie_wait_txq_empty(trans
, cnt
);
2346 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans
*trans
, u32 reg
,
2347 u32 mask
, u32 value
)
2349 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2350 unsigned long flags
;
2352 spin_lock_irqsave(&trans_pcie
->reg_lock
, flags
);
2353 __iwl_trans_pcie_set_bits_mask(trans
, reg
, mask
, value
);
2354 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
2357 static const char *get_csr_string(int cmd
)
2359 #define IWL_CMD(x) case x: return #x
2361 IWL_CMD(CSR_HW_IF_CONFIG_REG
);
2362 IWL_CMD(CSR_INT_COALESCING
);
2364 IWL_CMD(CSR_INT_MASK
);
2365 IWL_CMD(CSR_FH_INT_STATUS
);
2366 IWL_CMD(CSR_GPIO_IN
);
2368 IWL_CMD(CSR_GP_CNTRL
);
2369 IWL_CMD(CSR_HW_REV
);
2370 IWL_CMD(CSR_EEPROM_REG
);
2371 IWL_CMD(CSR_EEPROM_GP
);
2372 IWL_CMD(CSR_OTP_GP_REG
);
2373 IWL_CMD(CSR_GIO_REG
);
2374 IWL_CMD(CSR_GP_UCODE_REG
);
2375 IWL_CMD(CSR_GP_DRIVER_REG
);
2376 IWL_CMD(CSR_UCODE_DRV_GP1
);
2377 IWL_CMD(CSR_UCODE_DRV_GP2
);
2378 IWL_CMD(CSR_LED_REG
);
2379 IWL_CMD(CSR_DRAM_INT_TBL_REG
);
2380 IWL_CMD(CSR_GIO_CHICKEN_BITS
);
2381 IWL_CMD(CSR_ANA_PLL_CFG
);
2382 IWL_CMD(CSR_HW_REV_WA_REG
);
2383 IWL_CMD(CSR_MONITOR_STATUS_REG
);
2384 IWL_CMD(CSR_DBG_HPET_MEM_REG
);
2391 void iwl_pcie_dump_csr(struct iwl_trans
*trans
)
2394 static const u32 csr_tbl
[] = {
2395 CSR_HW_IF_CONFIG_REG
,
2413 CSR_DRAM_INT_TBL_REG
,
2414 CSR_GIO_CHICKEN_BITS
,
2416 CSR_MONITOR_STATUS_REG
,
2418 CSR_DBG_HPET_MEM_REG
2420 IWL_ERR(trans
, "CSR values:\n");
2421 IWL_ERR(trans
, "(2nd byte of CSR_INT_COALESCING is "
2422 "CSR_INT_PERIODIC_REG)\n");
2423 for (i
= 0; i
< ARRAY_SIZE(csr_tbl
); i
++) {
2424 IWL_ERR(trans
, " %25s: 0X%08x\n",
2425 get_csr_string(csr_tbl
[i
]),
2426 iwl_read32(trans
, csr_tbl
[i
]));
2430 #ifdef CONFIG_IWLWIFI_DEBUGFS
2431 /* create and remove of files */
2432 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
2433 debugfs_create_file(#name, mode, parent, trans, \
2434 &iwl_dbgfs_##name##_ops); \
2437 /* file operation */
2438 #define DEBUGFS_READ_FILE_OPS(name) \
2439 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2440 .read = iwl_dbgfs_##name##_read, \
2441 .open = simple_open, \
2442 .llseek = generic_file_llseek, \
2445 #define DEBUGFS_WRITE_FILE_OPS(name) \
2446 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2447 .write = iwl_dbgfs_##name##_write, \
2448 .open = simple_open, \
2449 .llseek = generic_file_llseek, \
2452 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
2453 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2454 .write = iwl_dbgfs_##name##_write, \
2455 .read = iwl_dbgfs_##name##_read, \
2456 .open = simple_open, \
2457 .llseek = generic_file_llseek, \
2460 struct iwl_dbgfs_tx_queue_priv
{
2461 struct iwl_trans
*trans
;
2464 struct iwl_dbgfs_tx_queue_state
{
2468 static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file
*seq
, loff_t
*pos
)
2470 struct iwl_dbgfs_tx_queue_priv
*priv
= seq
->private;
2471 struct iwl_dbgfs_tx_queue_state
*state
;
2473 if (*pos
>= priv
->trans
->trans_cfg
->base_params
->num_of_queues
)
2476 state
= kmalloc(sizeof(*state
), GFP_KERNEL
);
2483 static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file
*seq
,
2484 void *v
, loff_t
*pos
)
2486 struct iwl_dbgfs_tx_queue_priv
*priv
= seq
->private;
2487 struct iwl_dbgfs_tx_queue_state
*state
= v
;
2489 *pos
= ++state
->pos
;
2491 if (*pos
>= priv
->trans
->trans_cfg
->base_params
->num_of_queues
)
2497 static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file
*seq
, void *v
)
2502 static int iwl_dbgfs_tx_queue_seq_show(struct seq_file
*seq
, void *v
)
2504 struct iwl_dbgfs_tx_queue_priv
*priv
= seq
->private;
2505 struct iwl_dbgfs_tx_queue_state
*state
= v
;
2506 struct iwl_trans
*trans
= priv
->trans
;
2507 struct iwl_txq
*txq
= trans
->txqs
.txq
[state
->pos
];
2509 seq_printf(seq
, "hwq %.3u: used=%d stopped=%d ",
2510 (unsigned int)state
->pos
,
2511 !!test_bit(state
->pos
, trans
->txqs
.queue_used
),
2512 !!test_bit(state
->pos
, trans
->txqs
.queue_stopped
));
2515 "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d",
2516 txq
->read_ptr
, txq
->write_ptr
,
2517 txq
->need_update
, txq
->frozen
,
2518 txq
->n_window
, txq
->ampdu
);
2520 seq_puts(seq
, "(unallocated)");
2522 if (state
->pos
== trans
->txqs
.cmd
.q_id
)
2523 seq_puts(seq
, " (HCMD)");
2524 seq_puts(seq
, "\n");
2529 static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops
= {
2530 .start
= iwl_dbgfs_tx_queue_seq_start
,
2531 .next
= iwl_dbgfs_tx_queue_seq_next
,
2532 .stop
= iwl_dbgfs_tx_queue_seq_stop
,
2533 .show
= iwl_dbgfs_tx_queue_seq_show
,
2536 static int iwl_dbgfs_tx_queue_open(struct inode
*inode
, struct file
*filp
)
2538 struct iwl_dbgfs_tx_queue_priv
*priv
;
2540 priv
= __seq_open_private(filp
, &iwl_dbgfs_tx_queue_seq_ops
,
2546 priv
->trans
= inode
->i_private
;
2550 static ssize_t
iwl_dbgfs_rx_queue_read(struct file
*file
,
2551 char __user
*user_buf
,
2552 size_t count
, loff_t
*ppos
)
2554 struct iwl_trans
*trans
= file
->private_data
;
2555 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2557 int pos
= 0, i
, ret
;
2560 bufsz
= sizeof(char) * 121 * trans
->num_rx_queues
;
2562 if (!trans_pcie
->rxq
)
2565 buf
= kzalloc(bufsz
, GFP_KERNEL
);
2569 for (i
= 0; i
< trans
->num_rx_queues
&& pos
< bufsz
; i
++) {
2570 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
[i
];
2572 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "queue#: %2d\n",
2574 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "\tread: %u\n",
2576 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "\twrite: %u\n",
2578 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "\twrite_actual: %u\n",
2580 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "\tneed_update: %2d\n",
2582 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "\tfree_count: %u\n",
2585 u32 r
= __le16_to_cpu(iwl_get_closed_rb_stts(trans
,
2587 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2588 "\tclosed_rb_num: %u\n",
2591 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2592 "\tclosed_rb_num: Not Allocated\n");
2595 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
2601 static ssize_t
iwl_dbgfs_interrupt_read(struct file
*file
,
2602 char __user
*user_buf
,
2603 size_t count
, loff_t
*ppos
)
2605 struct iwl_trans
*trans
= file
->private_data
;
2606 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2607 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
2611 int bufsz
= 24 * 64; /* 24 items * 64 char per item */
2614 buf
= kzalloc(bufsz
, GFP_KERNEL
);
2618 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2619 "Interrupt Statistics Report:\n");
2621 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "HW Error:\t\t\t %u\n",
2623 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "SW Error:\t\t\t %u\n",
2625 if (isr_stats
->sw
|| isr_stats
->hw
) {
2626 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2627 "\tLast Restarting Code: 0x%X\n",
2628 isr_stats
->err_code
);
2630 #ifdef CONFIG_IWLWIFI_DEBUG
2631 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Frame transmitted:\t\t %u\n",
2633 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Alive interrupt:\t\t %u\n",
2636 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2637 "HW RF KILL switch toggled:\t %u\n", isr_stats
->rfkill
);
2639 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "CT KILL:\t\t\t %u\n",
2642 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Wakeup Interrupt:\t\t %u\n",
2645 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2646 "Rx command responses:\t\t %u\n", isr_stats
->rx
);
2648 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Tx/FH interrupt:\t\t %u\n",
2651 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Unexpected INTA:\t\t %u\n",
2652 isr_stats
->unhandled
);
2654 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
2659 static ssize_t
iwl_dbgfs_interrupt_write(struct file
*file
,
2660 const char __user
*user_buf
,
2661 size_t count
, loff_t
*ppos
)
2663 struct iwl_trans
*trans
= file
->private_data
;
2664 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2665 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
2669 ret
= kstrtou32_from_user(user_buf
, count
, 16, &reset_flag
);
2672 if (reset_flag
== 0)
2673 memset(isr_stats
, 0, sizeof(*isr_stats
));
2678 static ssize_t
iwl_dbgfs_csr_write(struct file
*file
,
2679 const char __user
*user_buf
,
2680 size_t count
, loff_t
*ppos
)
2682 struct iwl_trans
*trans
= file
->private_data
;
2684 iwl_pcie_dump_csr(trans
);
2689 static ssize_t
iwl_dbgfs_fh_reg_read(struct file
*file
,
2690 char __user
*user_buf
,
2691 size_t count
, loff_t
*ppos
)
2693 struct iwl_trans
*trans
= file
->private_data
;
2697 ret
= iwl_dump_fh(trans
, &buf
);
2702 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, ret
);
2707 static ssize_t
iwl_dbgfs_rfkill_read(struct file
*file
,
2708 char __user
*user_buf
,
2709 size_t count
, loff_t
*ppos
)
2711 struct iwl_trans
*trans
= file
->private_data
;
2712 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2716 pos
= scnprintf(buf
, sizeof(buf
), "debug: %d\nhw: %d\n",
2717 trans_pcie
->debug_rfkill
,
2718 !(iwl_read32(trans
, CSR_GP_CNTRL
) &
2719 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
));
2721 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
2724 static ssize_t
iwl_dbgfs_rfkill_write(struct file
*file
,
2725 const char __user
*user_buf
,
2726 size_t count
, loff_t
*ppos
)
2728 struct iwl_trans
*trans
= file
->private_data
;
2729 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2733 ret
= kstrtobool_from_user(user_buf
, count
, &new_value
);
2736 if (new_value
== trans_pcie
->debug_rfkill
)
2738 IWL_WARN(trans
, "changing debug rfkill %d->%d\n",
2739 trans_pcie
->debug_rfkill
, new_value
);
2740 trans_pcie
->debug_rfkill
= new_value
;
2741 iwl_pcie_handle_rfkill_irq(trans
);
2746 static int iwl_dbgfs_monitor_data_open(struct inode
*inode
,
2749 struct iwl_trans
*trans
= inode
->i_private
;
2750 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2752 if (!trans
->dbg
.dest_tlv
||
2753 trans
->dbg
.dest_tlv
->monitor_mode
!= EXTERNAL_MODE
) {
2754 IWL_ERR(trans
, "Debug destination is not set to DRAM\n");
2758 if (trans_pcie
->fw_mon_data
.state
!= IWL_FW_MON_DBGFS_STATE_CLOSED
)
2761 trans_pcie
->fw_mon_data
.state
= IWL_FW_MON_DBGFS_STATE_OPEN
;
2762 return simple_open(inode
, file
);
2765 static int iwl_dbgfs_monitor_data_release(struct inode
*inode
,
2768 struct iwl_trans_pcie
*trans_pcie
=
2769 IWL_TRANS_GET_PCIE_TRANS(inode
->i_private
);
2771 if (trans_pcie
->fw_mon_data
.state
== IWL_FW_MON_DBGFS_STATE_OPEN
)
2772 trans_pcie
->fw_mon_data
.state
= IWL_FW_MON_DBGFS_STATE_CLOSED
;
2776 static bool iwl_write_to_user_buf(char __user
*user_buf
, ssize_t count
,
2777 void *buf
, ssize_t
*size
,
2778 ssize_t
*bytes_copied
)
2780 int buf_size_left
= count
- *bytes_copied
;
2782 buf_size_left
= buf_size_left
- (buf_size_left
% sizeof(u32
));
2783 if (*size
> buf_size_left
)
2784 *size
= buf_size_left
;
2786 *size
-= copy_to_user(user_buf
, buf
, *size
);
2787 *bytes_copied
+= *size
;
2789 if (buf_size_left
== *size
)
2794 static ssize_t
iwl_dbgfs_monitor_data_read(struct file
*file
,
2795 char __user
*user_buf
,
2796 size_t count
, loff_t
*ppos
)
2798 struct iwl_trans
*trans
= file
->private_data
;
2799 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2800 void *cpu_addr
= (void *)trans
->dbg
.fw_mon
.block
, *curr_buf
;
2801 struct cont_rec
*data
= &trans_pcie
->fw_mon_data
;
2802 u32 write_ptr_addr
, wrap_cnt_addr
, write_ptr
, wrap_cnt
;
2803 ssize_t size
, bytes_copied
= 0;
2806 if (trans
->dbg
.dest_tlv
) {
2808 le32_to_cpu(trans
->dbg
.dest_tlv
->write_ptr_reg
);
2809 wrap_cnt_addr
= le32_to_cpu(trans
->dbg
.dest_tlv
->wrap_count
);
2811 write_ptr_addr
= MON_BUFF_WRPTR
;
2812 wrap_cnt_addr
= MON_BUFF_CYCLE_CNT
;
2815 if (unlikely(!trans
->dbg
.rec_on
))
2818 mutex_lock(&data
->mutex
);
2820 IWL_FW_MON_DBGFS_STATE_DISABLED
) {
2821 mutex_unlock(&data
->mutex
);
2825 /* write_ptr position in bytes rather then DW */
2826 write_ptr
= iwl_read_prph(trans
, write_ptr_addr
) * sizeof(u32
);
2827 wrap_cnt
= iwl_read_prph(trans
, wrap_cnt_addr
);
2829 if (data
->prev_wrap_cnt
== wrap_cnt
) {
2830 size
= write_ptr
- data
->prev_wr_ptr
;
2831 curr_buf
= cpu_addr
+ data
->prev_wr_ptr
;
2832 b_full
= iwl_write_to_user_buf(user_buf
, count
,
2835 data
->prev_wr_ptr
+= size
;
2837 } else if (data
->prev_wrap_cnt
== wrap_cnt
- 1 &&
2838 write_ptr
< data
->prev_wr_ptr
) {
2839 size
= trans
->dbg
.fw_mon
.size
- data
->prev_wr_ptr
;
2840 curr_buf
= cpu_addr
+ data
->prev_wr_ptr
;
2841 b_full
= iwl_write_to_user_buf(user_buf
, count
,
2844 data
->prev_wr_ptr
+= size
;
2848 b_full
= iwl_write_to_user_buf(user_buf
, count
,
2851 data
->prev_wr_ptr
= size
;
2852 data
->prev_wrap_cnt
++;
2855 if (data
->prev_wrap_cnt
== wrap_cnt
- 1 &&
2856 write_ptr
> data
->prev_wr_ptr
)
2858 "write pointer passed previous write pointer, start copying from the beginning\n");
2859 else if (!unlikely(data
->prev_wrap_cnt
== 0 &&
2860 data
->prev_wr_ptr
== 0))
2862 "monitor data is out of sync, start copying from the beginning\n");
2865 b_full
= iwl_write_to_user_buf(user_buf
, count
,
2868 data
->prev_wr_ptr
= size
;
2869 data
->prev_wrap_cnt
= wrap_cnt
;
2872 mutex_unlock(&data
->mutex
);
2874 return bytes_copied
;
2877 DEBUGFS_READ_WRITE_FILE_OPS(interrupt
);
2878 DEBUGFS_READ_FILE_OPS(fh_reg
);
2879 DEBUGFS_READ_FILE_OPS(rx_queue
);
2880 DEBUGFS_WRITE_FILE_OPS(csr
);
2881 DEBUGFS_READ_WRITE_FILE_OPS(rfkill
);
2882 static const struct file_operations iwl_dbgfs_tx_queue_ops
= {
2883 .owner
= THIS_MODULE
,
2884 .open
= iwl_dbgfs_tx_queue_open
,
2886 .llseek
= seq_lseek
,
2887 .release
= seq_release_private
,
2890 static const struct file_operations iwl_dbgfs_monitor_data_ops
= {
2891 .read
= iwl_dbgfs_monitor_data_read
,
2892 .open
= iwl_dbgfs_monitor_data_open
,
2893 .release
= iwl_dbgfs_monitor_data_release
,
2896 /* Create the debugfs files and directories */
2897 void iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
)
2899 struct dentry
*dir
= trans
->dbgfs_dir
;
2901 DEBUGFS_ADD_FILE(rx_queue
, dir
, 0400);
2902 DEBUGFS_ADD_FILE(tx_queue
, dir
, 0400);
2903 DEBUGFS_ADD_FILE(interrupt
, dir
, 0600);
2904 DEBUGFS_ADD_FILE(csr
, dir
, 0200);
2905 DEBUGFS_ADD_FILE(fh_reg
, dir
, 0400);
2906 DEBUGFS_ADD_FILE(rfkill
, dir
, 0600);
2907 DEBUGFS_ADD_FILE(monitor_data
, dir
, 0400);
2910 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans
*trans
)
2912 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2913 struct cont_rec
*data
= &trans_pcie
->fw_mon_data
;
2915 mutex_lock(&data
->mutex
);
2916 data
->state
= IWL_FW_MON_DBGFS_STATE_DISABLED
;
2917 mutex_unlock(&data
->mutex
);
2919 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2921 static u32
iwl_trans_pcie_get_cmdlen(struct iwl_trans
*trans
, void *tfd
)
2926 for (i
= 0; i
< trans
->txqs
.tfd
.max_tbs
; i
++)
2927 cmdlen
+= iwl_txq_gen1_tfd_tb_get_len(trans
, tfd
, i
);
2932 static u32
iwl_trans_pcie_dump_rbs(struct iwl_trans
*trans
,
2933 struct iwl_fw_error_dump_data
**data
,
2934 int allocated_rb_nums
)
2936 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2937 int max_len
= trans_pcie
->rx_buf_bytes
;
2938 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2939 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
[0];
2940 u32 i
, r
, j
, rb_len
= 0;
2942 spin_lock(&rxq
->lock
);
2944 r
= le16_to_cpu(iwl_get_closed_rb_stts(trans
, rxq
)) & 0x0FFF;
2946 for (i
= rxq
->read
, j
= 0;
2947 i
!= r
&& j
< allocated_rb_nums
;
2948 i
= (i
+ 1) & RX_QUEUE_MASK
, j
++) {
2949 struct iwl_rx_mem_buffer
*rxb
= rxq
->queue
[i
];
2950 struct iwl_fw_error_dump_rb
*rb
;
2952 dma_unmap_page(trans
->dev
, rxb
->page_dma
, max_len
,
2955 rb_len
+= sizeof(**data
) + sizeof(*rb
) + max_len
;
2957 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_RB
);
2958 (*data
)->len
= cpu_to_le32(sizeof(*rb
) + max_len
);
2959 rb
= (void *)(*data
)->data
;
2960 rb
->index
= cpu_to_le32(i
);
2961 memcpy(rb
->data
, page_address(rxb
->page
), max_len
);
2962 /* remap the page for the free benefit */
2963 rxb
->page_dma
= dma_map_page(trans
->dev
, rxb
->page
,
2964 rxb
->offset
, max_len
,
2967 *data
= iwl_fw_error_next_data(*data
);
2970 spin_unlock(&rxq
->lock
);
2974 #define IWL_CSR_TO_DUMP (0x250)
2976 static u32
iwl_trans_pcie_dump_csr(struct iwl_trans
*trans
,
2977 struct iwl_fw_error_dump_data
**data
)
2979 u32 csr_len
= sizeof(**data
) + IWL_CSR_TO_DUMP
;
2983 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_CSR
);
2984 (*data
)->len
= cpu_to_le32(IWL_CSR_TO_DUMP
);
2985 val
= (void *)(*data
)->data
;
2987 for (i
= 0; i
< IWL_CSR_TO_DUMP
; i
+= 4)
2988 *val
++ = cpu_to_le32(iwl_trans_pcie_read32(trans
, i
));
2990 *data
= iwl_fw_error_next_data(*data
);
2995 static u32
iwl_trans_pcie_fh_regs_dump(struct iwl_trans
*trans
,
2996 struct iwl_fw_error_dump_data
**data
)
2998 u32 fh_regs_len
= FH_MEM_UPPER_BOUND
- FH_MEM_LOWER_BOUND
;
2999 unsigned long flags
;
3003 if (!iwl_trans_grab_nic_access(trans
, &flags
))
3006 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS
);
3007 (*data
)->len
= cpu_to_le32(fh_regs_len
);
3008 val
= (void *)(*data
)->data
;
3010 if (!trans
->trans_cfg
->gen2
)
3011 for (i
= FH_MEM_LOWER_BOUND
; i
< FH_MEM_UPPER_BOUND
;
3013 *val
++ = cpu_to_le32(iwl_trans_pcie_read32(trans
, i
));
3015 for (i
= iwl_umac_prph(trans
, FH_MEM_LOWER_BOUND_GEN2
);
3016 i
< iwl_umac_prph(trans
, FH_MEM_UPPER_BOUND_GEN2
);
3018 *val
++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans
,
3021 iwl_trans_release_nic_access(trans
, &flags
);
3023 *data
= iwl_fw_error_next_data(*data
);
3025 return sizeof(**data
) + fh_regs_len
;
3029 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans
*trans
,
3030 struct iwl_fw_error_dump_fw_mon
*fw_mon_data
,
3033 u32 buf_size_in_dwords
= (monitor_len
>> 2);
3034 u32
*buffer
= (u32
*)fw_mon_data
->data
;
3035 unsigned long flags
;
3038 if (!iwl_trans_grab_nic_access(trans
, &flags
))
3041 iwl_write_umac_prph_no_grab(trans
, MON_DMARB_RD_CTL_ADDR
, 0x1);
3042 for (i
= 0; i
< buf_size_in_dwords
; i
++)
3043 buffer
[i
] = iwl_read_umac_prph_no_grab(trans
,
3044 MON_DMARB_RD_DATA_ADDR
);
3045 iwl_write_umac_prph_no_grab(trans
, MON_DMARB_RD_CTL_ADDR
, 0x0);
3047 iwl_trans_release_nic_access(trans
, &flags
);
3053 iwl_trans_pcie_dump_pointers(struct iwl_trans
*trans
,
3054 struct iwl_fw_error_dump_fw_mon
*fw_mon_data
)
3056 u32 base
, base_high
, write_ptr
, write_ptr_val
, wrap_cnt
;
3058 if (trans
->trans_cfg
->device_family
>= IWL_DEVICE_FAMILY_AX210
) {
3059 base
= DBGC_CUR_DBGBUF_BASE_ADDR_LSB
;
3060 base_high
= DBGC_CUR_DBGBUF_BASE_ADDR_MSB
;
3061 write_ptr
= DBGC_CUR_DBGBUF_STATUS
;
3062 wrap_cnt
= DBGC_DBGBUF_WRAP_AROUND
;
3063 } else if (trans
->dbg
.dest_tlv
) {
3064 write_ptr
= le32_to_cpu(trans
->dbg
.dest_tlv
->write_ptr_reg
);
3065 wrap_cnt
= le32_to_cpu(trans
->dbg
.dest_tlv
->wrap_count
);
3066 base
= le32_to_cpu(trans
->dbg
.dest_tlv
->base_reg
);
3068 base
= MON_BUFF_BASE_ADDR
;
3069 write_ptr
= MON_BUFF_WRPTR
;
3070 wrap_cnt
= MON_BUFF_CYCLE_CNT
;
3073 write_ptr_val
= iwl_read_prph(trans
, write_ptr
);
3074 fw_mon_data
->fw_mon_cycle_cnt
=
3075 cpu_to_le32(iwl_read_prph(trans
, wrap_cnt
));
3076 fw_mon_data
->fw_mon_base_ptr
=
3077 cpu_to_le32(iwl_read_prph(trans
, base
));
3078 if (trans
->trans_cfg
->device_family
>= IWL_DEVICE_FAMILY_AX210
) {
3079 fw_mon_data
->fw_mon_base_high_ptr
=
3080 cpu_to_le32(iwl_read_prph(trans
, base_high
));
3081 write_ptr_val
&= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK
;
3082 /* convert wrtPtr to DWs, to align with all HWs */
3083 write_ptr_val
>>= 2;
3085 fw_mon_data
->fw_mon_wr_ptr
= cpu_to_le32(write_ptr_val
);
3089 iwl_trans_pcie_dump_monitor(struct iwl_trans
*trans
,
3090 struct iwl_fw_error_dump_data
**data
,
3093 struct iwl_dram_data
*fw_mon
= &trans
->dbg
.fw_mon
;
3096 if (trans
->dbg
.dest_tlv
||
3098 (trans
->trans_cfg
->device_family
== IWL_DEVICE_FAMILY_7000
||
3099 trans
->trans_cfg
->device_family
>= IWL_DEVICE_FAMILY_AX210
))) {
3100 struct iwl_fw_error_dump_fw_mon
*fw_mon_data
;
3102 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR
);
3103 fw_mon_data
= (void *)(*data
)->data
;
3105 iwl_trans_pcie_dump_pointers(trans
, fw_mon_data
);
3107 len
+= sizeof(**data
) + sizeof(*fw_mon_data
);
3109 memcpy(fw_mon_data
->data
, fw_mon
->block
, fw_mon
->size
);
3110 monitor_len
= fw_mon
->size
;
3111 } else if (trans
->dbg
.dest_tlv
->monitor_mode
== SMEM_MODE
) {
3112 u32 base
= le32_to_cpu(fw_mon_data
->fw_mon_base_ptr
);
3114 * Update pointers to reflect actual values after
3117 if (trans
->dbg
.dest_tlv
->version
) {
3118 base
= (iwl_read_prph(trans
, base
) &
3119 IWL_LDBG_M2S_BUF_BA_MSK
) <<
3120 trans
->dbg
.dest_tlv
->base_shift
;
3121 base
*= IWL_M2S_UNIT_SIZE
;
3122 base
+= trans
->cfg
->smem_offset
;
3124 base
= iwl_read_prph(trans
, base
) <<
3125 trans
->dbg
.dest_tlv
->base_shift
;
3128 iwl_trans_read_mem(trans
, base
, fw_mon_data
->data
,
3129 monitor_len
/ sizeof(u32
));
3130 } else if (trans
->dbg
.dest_tlv
->monitor_mode
== MARBH_MODE
) {
3132 iwl_trans_pci_dump_marbh_monitor(trans
,
3136 /* Didn't match anything - output no monitor data */
3141 (*data
)->len
= cpu_to_le32(monitor_len
+ sizeof(*fw_mon_data
));
3147 static int iwl_trans_get_fw_monitor_len(struct iwl_trans
*trans
, u32
*len
)
3149 if (trans
->dbg
.fw_mon
.size
) {
3150 *len
+= sizeof(struct iwl_fw_error_dump_data
) +
3151 sizeof(struct iwl_fw_error_dump_fw_mon
) +
3152 trans
->dbg
.fw_mon
.size
;
3153 return trans
->dbg
.fw_mon
.size
;
3154 } else if (trans
->dbg
.dest_tlv
) {
3155 u32 base
, end
, cfg_reg
, monitor_len
;
3157 if (trans
->dbg
.dest_tlv
->version
== 1) {
3158 cfg_reg
= le32_to_cpu(trans
->dbg
.dest_tlv
->base_reg
);
3159 cfg_reg
= iwl_read_prph(trans
, cfg_reg
);
3160 base
= (cfg_reg
& IWL_LDBG_M2S_BUF_BA_MSK
) <<
3161 trans
->dbg
.dest_tlv
->base_shift
;
3162 base
*= IWL_M2S_UNIT_SIZE
;
3163 base
+= trans
->cfg
->smem_offset
;
3166 (cfg_reg
& IWL_LDBG_M2S_BUF_SIZE_MSK
) >>
3167 trans
->dbg
.dest_tlv
->end_shift
;
3168 monitor_len
*= IWL_M2S_UNIT_SIZE
;
3170 base
= le32_to_cpu(trans
->dbg
.dest_tlv
->base_reg
);
3171 end
= le32_to_cpu(trans
->dbg
.dest_tlv
->end_reg
);
3173 base
= iwl_read_prph(trans
, base
) <<
3174 trans
->dbg
.dest_tlv
->base_shift
;
3175 end
= iwl_read_prph(trans
, end
) <<
3176 trans
->dbg
.dest_tlv
->end_shift
;
3178 /* Make "end" point to the actual end */
3179 if (trans
->trans_cfg
->device_family
>=
3180 IWL_DEVICE_FAMILY_8000
||
3181 trans
->dbg
.dest_tlv
->monitor_mode
== MARBH_MODE
)
3182 end
+= (1 << trans
->dbg
.dest_tlv
->end_shift
);
3183 monitor_len
= end
- base
;
3185 *len
+= sizeof(struct iwl_fw_error_dump_data
) +
3186 sizeof(struct iwl_fw_error_dump_fw_mon
) +
3193 static struct iwl_trans_dump_data
3194 *iwl_trans_pcie_dump_data(struct iwl_trans
*trans
,
3197 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
3198 struct iwl_fw_error_dump_data
*data
;
3199 struct iwl_txq
*cmdq
= trans
->txqs
.txq
[trans
->txqs
.cmd
.q_id
];
3200 struct iwl_fw_error_dump_txcmd
*txcmd
;
3201 struct iwl_trans_dump_data
*dump_data
;
3202 u32 len
, num_rbs
= 0, monitor_len
= 0;
3204 bool dump_rbs
= test_bit(STATUS_FW_ERROR
, &trans
->status
) &&
3205 !trans
->trans_cfg
->mq_rx_supported
&&
3206 dump_mask
& BIT(IWL_FW_ERROR_DUMP_RB
);
3211 /* transport dump header */
3212 len
= sizeof(*dump_data
);
3215 if (dump_mask
& BIT(IWL_FW_ERROR_DUMP_TXCMD
) && cmdq
)
3216 len
+= sizeof(*data
) +
3217 cmdq
->n_window
* (sizeof(*txcmd
) +
3218 TFD_MAX_PAYLOAD_SIZE
);
3221 if (dump_mask
& BIT(IWL_FW_ERROR_DUMP_FW_MONITOR
))
3222 monitor_len
= iwl_trans_get_fw_monitor_len(trans
, &len
);
3225 if (dump_mask
& BIT(IWL_FW_ERROR_DUMP_CSR
))
3226 len
+= sizeof(*data
) + IWL_CSR_TO_DUMP
;
3229 if (dump_mask
& BIT(IWL_FW_ERROR_DUMP_FH_REGS
)) {
3230 if (trans
->trans_cfg
->gen2
)
3231 len
+= sizeof(*data
) +
3232 (iwl_umac_prph(trans
, FH_MEM_UPPER_BOUND_GEN2
) -
3233 iwl_umac_prph(trans
, FH_MEM_LOWER_BOUND_GEN2
));
3235 len
+= sizeof(*data
) +
3236 (FH_MEM_UPPER_BOUND
-
3237 FH_MEM_LOWER_BOUND
);
3241 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3242 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
[0];
3245 le16_to_cpu(iwl_get_closed_rb_stts(trans
, rxq
))
3247 num_rbs
= (num_rbs
- rxq
->read
) & RX_QUEUE_MASK
;
3248 len
+= num_rbs
* (sizeof(*data
) +
3249 sizeof(struct iwl_fw_error_dump_rb
) +
3250 (PAGE_SIZE
<< trans_pcie
->rx_page_order
));
3253 /* Paged memory for gen2 HW */
3254 if (trans
->trans_cfg
->gen2
&& dump_mask
& BIT(IWL_FW_ERROR_DUMP_PAGING
))
3255 for (i
= 0; i
< trans
->init_dram
.paging_cnt
; i
++)
3256 len
+= sizeof(*data
) +
3257 sizeof(struct iwl_fw_error_dump_paging
) +
3258 trans
->init_dram
.paging
[i
].size
;
3260 dump_data
= vzalloc(len
);
3265 data
= (void *)dump_data
->data
;
3267 if (dump_mask
& BIT(IWL_FW_ERROR_DUMP_TXCMD
) && cmdq
) {
3268 u16 tfd_size
= trans
->txqs
.tfd
.size
;
3270 data
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD
);
3271 txcmd
= (void *)data
->data
;
3272 spin_lock_bh(&cmdq
->lock
);
3273 ptr
= cmdq
->write_ptr
;
3274 for (i
= 0; i
< cmdq
->n_window
; i
++) {
3275 u8 idx
= iwl_txq_get_cmd_index(cmdq
, ptr
);
3279 if (trans
->trans_cfg
->use_tfh
)
3284 cmdlen
= iwl_trans_pcie_get_cmdlen(trans
,
3287 caplen
= min_t(u32
, TFD_MAX_PAYLOAD_SIZE
, cmdlen
);
3290 len
+= sizeof(*txcmd
) + caplen
;
3291 txcmd
->cmdlen
= cpu_to_le32(cmdlen
);
3292 txcmd
->caplen
= cpu_to_le32(caplen
);
3293 memcpy(txcmd
->data
, cmdq
->entries
[idx
].cmd
,
3295 txcmd
= (void *)((u8
*)txcmd
->data
+ caplen
);
3298 ptr
= iwl_txq_dec_wrap(trans
, ptr
);
3300 spin_unlock_bh(&cmdq
->lock
);
3302 data
->len
= cpu_to_le32(len
);
3303 len
+= sizeof(*data
);
3304 data
= iwl_fw_error_next_data(data
);
3307 if (dump_mask
& BIT(IWL_FW_ERROR_DUMP_CSR
))
3308 len
+= iwl_trans_pcie_dump_csr(trans
, &data
);
3309 if (dump_mask
& BIT(IWL_FW_ERROR_DUMP_FH_REGS
))
3310 len
+= iwl_trans_pcie_fh_regs_dump(trans
, &data
);
3312 len
+= iwl_trans_pcie_dump_rbs(trans
, &data
, num_rbs
);
3314 /* Paged memory for gen2 HW */
3315 if (trans
->trans_cfg
->gen2
&&
3316 dump_mask
& BIT(IWL_FW_ERROR_DUMP_PAGING
)) {
3317 for (i
= 0; i
< trans
->init_dram
.paging_cnt
; i
++) {
3318 struct iwl_fw_error_dump_paging
*paging
;
3319 u32 page_len
= trans
->init_dram
.paging
[i
].size
;
3321 data
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING
);
3322 data
->len
= cpu_to_le32(sizeof(*paging
) + page_len
);
3323 paging
= (void *)data
->data
;
3324 paging
->index
= cpu_to_le32(i
);
3325 memcpy(paging
->data
,
3326 trans
->init_dram
.paging
[i
].block
, page_len
);
3327 data
= iwl_fw_error_next_data(data
);
3329 len
+= sizeof(*data
) + sizeof(*paging
) + page_len
;
3332 if (dump_mask
& BIT(IWL_FW_ERROR_DUMP_FW_MONITOR
))
3333 len
+= iwl_trans_pcie_dump_monitor(trans
, &data
, monitor_len
);
3335 dump_data
->len
= len
;
3340 #ifdef CONFIG_PM_SLEEP
3341 static int iwl_trans_pcie_suspend(struct iwl_trans
*trans
)
3346 static void iwl_trans_pcie_resume(struct iwl_trans
*trans
)
3349 #endif /* CONFIG_PM_SLEEP */
3351 #define IWL_TRANS_COMMON_OPS \
3352 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \
3353 .write8 = iwl_trans_pcie_write8, \
3354 .write32 = iwl_trans_pcie_write32, \
3355 .read32 = iwl_trans_pcie_read32, \
3356 .read_prph = iwl_trans_pcie_read_prph, \
3357 .write_prph = iwl_trans_pcie_write_prph, \
3358 .read_mem = iwl_trans_pcie_read_mem, \
3359 .write_mem = iwl_trans_pcie_write_mem, \
3360 .read_config32 = iwl_trans_pcie_read_config32, \
3361 .configure = iwl_trans_pcie_configure, \
3362 .set_pmi = iwl_trans_pcie_set_pmi, \
3363 .sw_reset = iwl_trans_pcie_sw_reset, \
3364 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \
3365 .release_nic_access = iwl_trans_pcie_release_nic_access, \
3366 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \
3367 .dump_data = iwl_trans_pcie_dump_data, \
3368 .d3_suspend = iwl_trans_pcie_d3_suspend, \
3369 .d3_resume = iwl_trans_pcie_d3_resume, \
3370 .sync_nmi = iwl_trans_pcie_sync_nmi
3372 #ifdef CONFIG_PM_SLEEP
3373 #define IWL_TRANS_PM_OPS \
3374 .suspend = iwl_trans_pcie_suspend, \
3375 .resume = iwl_trans_pcie_resume,
3377 #define IWL_TRANS_PM_OPS
3378 #endif /* CONFIG_PM_SLEEP */
3380 static const struct iwl_trans_ops trans_ops_pcie
= {
3381 IWL_TRANS_COMMON_OPS
,
3383 .start_hw
= iwl_trans_pcie_start_hw
,
3384 .fw_alive
= iwl_trans_pcie_fw_alive
,
3385 .start_fw
= iwl_trans_pcie_start_fw
,
3386 .stop_device
= iwl_trans_pcie_stop_device
,
3388 .send_cmd
= iwl_trans_pcie_send_hcmd
,
3390 .tx
= iwl_trans_pcie_tx
,
3391 .reclaim
= iwl_txq_reclaim
,
3393 .txq_disable
= iwl_trans_pcie_txq_disable
,
3394 .txq_enable
= iwl_trans_pcie_txq_enable
,
3396 .txq_set_shared_mode
= iwl_trans_pcie_txq_set_shared_mode
,
3398 .wait_tx_queues_empty
= iwl_trans_pcie_wait_txqs_empty
,
3400 .freeze_txq_timer
= iwl_trans_txq_freeze_timer
,
3401 .block_txq_ptrs
= iwl_trans_pcie_block_txq_ptrs
,
3402 #ifdef CONFIG_IWLWIFI_DEBUGFS
3403 .debugfs_cleanup
= iwl_trans_pcie_debugfs_cleanup
,
3407 static const struct iwl_trans_ops trans_ops_pcie_gen2
= {
3408 IWL_TRANS_COMMON_OPS
,
3410 .start_hw
= iwl_trans_pcie_start_hw
,
3411 .fw_alive
= iwl_trans_pcie_gen2_fw_alive
,
3412 .start_fw
= iwl_trans_pcie_gen2_start_fw
,
3413 .stop_device
= iwl_trans_pcie_gen2_stop_device
,
3415 .send_cmd
= iwl_trans_pcie_gen2_send_hcmd
,
3417 .tx
= iwl_txq_gen2_tx
,
3418 .reclaim
= iwl_txq_reclaim
,
3420 .set_q_ptrs
= iwl_txq_set_q_ptrs
,
3422 .txq_alloc
= iwl_txq_dyn_alloc
,
3423 .txq_free
= iwl_txq_dyn_free
,
3424 .wait_txq_empty
= iwl_trans_pcie_wait_txq_empty
,
3425 .rxq_dma_data
= iwl_trans_pcie_rxq_dma_data
,
3426 .set_pnvm
= iwl_trans_pcie_ctx_info_gen3_set_pnvm
,
3427 #ifdef CONFIG_IWLWIFI_DEBUGFS
3428 .debugfs_cleanup
= iwl_trans_pcie_debugfs_cleanup
,
3432 struct iwl_trans
*iwl_trans_pcie_alloc(struct pci_dev
*pdev
,
3433 const struct pci_device_id
*ent
,
3434 const struct iwl_cfg_trans_params
*cfg_trans
)
3436 struct iwl_trans_pcie
*trans_pcie
;
3437 struct iwl_trans
*trans
;
3439 const struct iwl_trans_ops
*ops
= &trans_ops_pcie_gen2
;
3441 if (!cfg_trans
->gen2
)
3442 ops
= &trans_ops_pcie
;
3444 ret
= pcim_enable_device(pdev
);
3446 return ERR_PTR(ret
);
3448 trans
= iwl_trans_alloc(sizeof(struct iwl_trans_pcie
), &pdev
->dev
, ops
,
3451 return ERR_PTR(-ENOMEM
);
3453 trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
3455 trans_pcie
->trans
= trans
;
3456 trans_pcie
->opmode_down
= true;
3457 spin_lock_init(&trans_pcie
->irq_lock
);
3458 spin_lock_init(&trans_pcie
->reg_lock
);
3459 spin_lock_init(&trans_pcie
->alloc_page_lock
);
3460 mutex_init(&trans_pcie
->mutex
);
3461 init_waitqueue_head(&trans_pcie
->ucode_write_waitq
);
3463 trans_pcie
->rba
.alloc_wq
= alloc_workqueue("rb_allocator",
3464 WQ_HIGHPRI
| WQ_UNBOUND
, 1);
3465 if (!trans_pcie
->rba
.alloc_wq
) {
3467 goto out_free_trans
;
3469 INIT_WORK(&trans_pcie
->rba
.rx_alloc
, iwl_pcie_rx_allocator_work
);
3471 trans_pcie
->debug_rfkill
= -1;
3473 if (!cfg_trans
->base_params
->pcie_l1_allowed
) {
3475 * W/A - seems to solve weird behavior. We need to remove this
3476 * if we don't want to stay in L1 all the time. This wastes a
3479 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
|
3480 PCIE_LINK_STATE_L1
|
3481 PCIE_LINK_STATE_CLKPM
);
3484 trans_pcie
->def_rx_queue
= 0;
3486 pci_set_master(pdev
);
3488 addr_size
= trans
->txqs
.tfd
.addr_size
;
3489 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(addr_size
));
3491 ret
= pci_set_consistent_dma_mask(pdev
,
3492 DMA_BIT_MASK(addr_size
));
3494 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3496 ret
= pci_set_consistent_dma_mask(pdev
,
3498 /* both attempts failed: */
3500 dev_err(&pdev
->dev
, "No suitable DMA available\n");
3505 ret
= pcim_iomap_regions_request_all(pdev
, BIT(0), DRV_NAME
);
3507 dev_err(&pdev
->dev
, "pcim_iomap_regions_request_all failed\n");
3511 trans_pcie
->hw_base
= pcim_iomap_table(pdev
)[0];
3512 if (!trans_pcie
->hw_base
) {
3513 dev_err(&pdev
->dev
, "pcim_iomap_table failed\n");
3518 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3519 * PCI Tx retries from interfering with C3 CPU state */
3520 pci_write_config_byte(pdev
, PCI_CFG_RETRY_TIMEOUT
, 0x00);
3522 trans_pcie
->pci_dev
= pdev
;
3523 iwl_disable_interrupts(trans
);
3525 trans
->hw_rev
= iwl_read32(trans
, CSR_HW_REV
);
3526 if (trans
->hw_rev
== 0xffffffff) {
3527 dev_err(&pdev
->dev
, "HW_REV=0xFFFFFFFF, PCI issues?\n");
3533 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3534 * changed, and now the revision step also includes bit 0-1 (no more
3535 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3536 * in the old format.
3538 if (cfg_trans
->device_family
>= IWL_DEVICE_FAMILY_8000
)
3539 trans
->hw_rev
= (trans
->hw_rev
& 0xfff0) |
3540 (CSR_HW_REV_STEP(trans
->hw_rev
<< 2) << 2);
3542 IWL_DEBUG_INFO(trans
, "HW REV: 0x%0x\n", trans
->hw_rev
);
3544 iwl_pcie_set_interrupt_capa(pdev
, trans
, cfg_trans
);
3545 trans
->hw_id
= (pdev
->device
<< 16) + pdev
->subsystem_device
;
3546 snprintf(trans
->hw_id_str
, sizeof(trans
->hw_id_str
),
3547 "PCI ID: 0x%04X:0x%04X", pdev
->device
, pdev
->subsystem_device
);
3549 /* Initialize the wait queue for commands */
3550 init_waitqueue_head(&trans_pcie
->wait_command_queue
);
3552 init_waitqueue_head(&trans_pcie
->sx_waitq
);
3555 if (trans_pcie
->msix_enabled
) {
3556 ret
= iwl_pcie_init_msix_handler(pdev
, trans_pcie
);
3560 ret
= iwl_pcie_alloc_ict(trans
);
3564 ret
= devm_request_threaded_irq(&pdev
->dev
, pdev
->irq
,
3566 iwl_pcie_irq_handler
,
3567 IRQF_SHARED
, DRV_NAME
, trans
);
3569 IWL_ERR(trans
, "Error allocating IRQ %d\n", pdev
->irq
);
3572 trans_pcie
->inta_mask
= CSR_INI_SET_MASK
;
3575 #ifdef CONFIG_IWLWIFI_DEBUGFS
3576 trans_pcie
->fw_mon_data
.state
= IWL_FW_MON_DBGFS_STATE_CLOSED
;
3577 mutex_init(&trans_pcie
->fw_mon_data
.mutex
);
3580 iwl_dbg_tlv_init(trans
);
3585 iwl_pcie_free_ict(trans
);
3587 destroy_workqueue(trans_pcie
->rba
.alloc_wq
);
3589 iwl_trans_free(trans
);
3590 return ERR_PTR(ret
);
3593 void iwl_trans_pcie_sync_nmi(struct iwl_trans
*trans
)
3595 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
3596 unsigned long timeout
= jiffies
+ IWL_TRANS_NMI_TIMEOUT
;
3597 bool interrupts_enabled
= test_bit(STATUS_INT_ENABLED
, &trans
->status
);
3598 u32 inta_addr
, sw_err_bit
;
3600 if (trans_pcie
->msix_enabled
) {
3601 inta_addr
= CSR_MSIX_HW_INT_CAUSES_AD
;
3602 sw_err_bit
= MSIX_HW_INT_CAUSES_REG_SW_ERR
;
3604 inta_addr
= CSR_INT
;
3605 sw_err_bit
= CSR_INT_BIT_SW_ERR
;
3608 /* if the interrupts were already disabled, there is no point in
3609 * calling iwl_disable_interrupts
3611 if (interrupts_enabled
)
3612 iwl_disable_interrupts(trans
);
3614 iwl_force_nmi(trans
);
3615 while (time_after(timeout
, jiffies
)) {
3616 u32 inta_hw
= iwl_read32(trans
, inta_addr
);
3618 /* Error detected by uCode */
3619 if (inta_hw
& sw_err_bit
) {
3620 /* Clear causes register */
3621 iwl_write32(trans
, inta_addr
, inta_hw
& sw_err_bit
);
3628 /* enable interrupts only if there were already enabled before this
3629 * function to avoid a case were the driver enable interrupts before
3630 * proper configurations were made
3632 if (interrupts_enabled
)
3633 iwl_enable_interrupts(trans
);
3635 iwl_trans_fw_error(trans
);