]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/net/wireless/intel/iwlwifi/pcie/trans.c
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'iwlwifi-for-kalle-2016-02-15' into HEAD
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / intel / iwlwifi / pcie / trans.c
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 Intel Deutschland GmbH
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * USA
25 *
26 * The full GNU General Public License is included in this distribution
27 * in the file called COPYING.
28 *
29 * Contact Information:
30 * Intel Linux Wireless <linuxwifi@intel.com>
31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32 *
33 * BSD LICENSE
34 *
35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
37 * Copyright(c) 2016 Intel Deutschland GmbH
38 * All rights reserved.
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 *
44 * * Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * * Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
49 * distribution.
50 * * Neither the name Intel Corporation nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific prior written permission.
53 *
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 *
66 *****************************************************************************/
67 #include <linux/pci.h>
68 #include <linux/pci-aspm.h>
69 #include <linux/interrupt.h>
70 #include <linux/debugfs.h>
71 #include <linux/sched.h>
72 #include <linux/bitops.h>
73 #include <linux/gfp.h>
74 #include <linux/vmalloc.h>
75 #include <linux/pm_runtime.h>
76
77 #include "iwl-drv.h"
78 #include "iwl-trans.h"
79 #include "iwl-csr.h"
80 #include "iwl-prph.h"
81 #include "iwl-scd.h"
82 #include "iwl-agn-hw.h"
83 #include "iwl-fw-error-dump.h"
84 #include "internal.h"
85 #include "iwl-fh.h"
86
87 /* extended range in FW SRAM */
88 #define IWL_FW_MEM_EXTENDED_START 0x40000
89 #define IWL_FW_MEM_EXTENDED_END 0x57FFF
90
91 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
92 {
93 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
94
95 if (!trans_pcie->fw_mon_page)
96 return;
97
98 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
99 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
100 __free_pages(trans_pcie->fw_mon_page,
101 get_order(trans_pcie->fw_mon_size));
102 trans_pcie->fw_mon_page = NULL;
103 trans_pcie->fw_mon_phys = 0;
104 trans_pcie->fw_mon_size = 0;
105 }
106
107 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
108 {
109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
110 struct page *page = NULL;
111 dma_addr_t phys;
112 u32 size = 0;
113 u8 power;
114
115 if (!max_power) {
116 /* default max_power is maximum */
117 max_power = 26;
118 } else {
119 max_power += 11;
120 }
121
122 if (WARN(max_power > 26,
123 "External buffer size for monitor is too big %d, check the FW TLV\n",
124 max_power))
125 return;
126
127 if (trans_pcie->fw_mon_page) {
128 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
129 trans_pcie->fw_mon_size,
130 DMA_FROM_DEVICE);
131 return;
132 }
133
134 phys = 0;
135 for (power = max_power; power >= 11; power--) {
136 int order;
137
138 size = BIT(power);
139 order = get_order(size);
140 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
141 order);
142 if (!page)
143 continue;
144
145 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
146 DMA_FROM_DEVICE);
147 if (dma_mapping_error(trans->dev, phys)) {
148 __free_pages(page, order);
149 page = NULL;
150 continue;
151 }
152 IWL_INFO(trans,
153 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
154 size, order);
155 break;
156 }
157
158 if (WARN_ON_ONCE(!page))
159 return;
160
161 if (power != max_power)
162 IWL_ERR(trans,
163 "Sorry - debug buffer is only %luK while you requested %luK\n",
164 (unsigned long)BIT(power - 10),
165 (unsigned long)BIT(max_power - 10));
166
167 trans_pcie->fw_mon_page = page;
168 trans_pcie->fw_mon_phys = phys;
169 trans_pcie->fw_mon_size = size;
170 }
171
172 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
173 {
174 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
175 ((reg & 0x0000ffff) | (2 << 28)));
176 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
177 }
178
179 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
180 {
181 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
182 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
183 ((reg & 0x0000ffff) | (3 << 28)));
184 }
185
186 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
187 {
188 if (trans->cfg->apmg_not_supported)
189 return;
190
191 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
192 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
193 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
194 ~APMG_PS_CTRL_MSK_PWR_SRC);
195 else
196 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
197 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
198 ~APMG_PS_CTRL_MSK_PWR_SRC);
199 }
200
201 /* PCI registers */
202 #define PCI_CFG_RETRY_TIMEOUT 0x041
203
204 static void iwl_pcie_apm_config(struct iwl_trans *trans)
205 {
206 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
207 u16 lctl;
208 u16 cap;
209
210 /*
211 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
212 * Check if BIOS (or OS) enabled L1-ASPM on this device.
213 * If so (likely), disable L0S, so device moves directly L0->L1;
214 * costs negligible amount of power savings.
215 * If not (unlikely), enable L0S, so there is at least some
216 * power savings, even without L1.
217 */
218 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
219 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
220 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
221 else
222 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
223 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
224
225 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
226 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
227 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
228 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
229 trans->ltr_enabled ? "En" : "Dis");
230 }
231
232 /*
233 * Start up NIC's basic functionality after it has been reset
234 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
235 * NOTE: This does not load uCode nor start the embedded processor
236 */
237 static int iwl_pcie_apm_init(struct iwl_trans *trans)
238 {
239 int ret = 0;
240 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
241
242 /*
243 * Use "set_bit" below rather than "write", to preserve any hardware
244 * bits already set by default after reset.
245 */
246
247 /* Disable L0S exit timer (platform NMI Work/Around) */
248 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
249 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
250 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
251
252 /*
253 * Disable L0s without affecting L1;
254 * don't wait for ICH L0s (ICH bug W/A)
255 */
256 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
257 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
258
259 /* Set FH wait threshold to maximum (HW error during stress W/A) */
260 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
261
262 /*
263 * Enable HAP INTA (interrupt from management bus) to
264 * wake device's PCI Express link L1a -> L0s
265 */
266 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
267 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
268
269 iwl_pcie_apm_config(trans);
270
271 /* Configure analog phase-lock-loop before activating to D0A */
272 if (trans->cfg->base_params->pll_cfg_val)
273 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
274 trans->cfg->base_params->pll_cfg_val);
275
276 /*
277 * Set "initialization complete" bit to move adapter from
278 * D0U* --> D0A* (powered-up active) state.
279 */
280 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
281
282 /*
283 * Wait for clock stabilization; once stabilized, access to
284 * device-internal resources is supported, e.g. iwl_write_prph()
285 * and accesses to uCode SRAM.
286 */
287 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
289 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
290 if (ret < 0) {
291 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
292 goto out;
293 }
294
295 if (trans->cfg->host_interrupt_operation_mode) {
296 /*
297 * This is a bit of an abuse - This is needed for 7260 / 3160
298 * only check host_interrupt_operation_mode even if this is
299 * not related to host_interrupt_operation_mode.
300 *
301 * Enable the oscillator to count wake up time for L1 exit. This
302 * consumes slightly more power (100uA) - but allows to be sure
303 * that we wake up from L1 on time.
304 *
305 * This looks weird: read twice the same register, discard the
306 * value, set a bit, and yet again, read that same register
307 * just to discard the value. But that's the way the hardware
308 * seems to like it.
309 */
310 iwl_read_prph(trans, OSC_CLK);
311 iwl_read_prph(trans, OSC_CLK);
312 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
313 iwl_read_prph(trans, OSC_CLK);
314 iwl_read_prph(trans, OSC_CLK);
315 }
316
317 /*
318 * Enable DMA clock and wait for it to stabilize.
319 *
320 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
321 * bits do not disable clocks. This preserves any hardware
322 * bits already set by default in "CLK_CTRL_REG" after reset.
323 */
324 if (!trans->cfg->apmg_not_supported) {
325 iwl_write_prph(trans, APMG_CLK_EN_REG,
326 APMG_CLK_VAL_DMA_CLK_RQT);
327 udelay(20);
328
329 /* Disable L1-Active */
330 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
331 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
332
333 /* Clear the interrupt in APMG if the NIC is in RFKILL */
334 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
335 APMG_RTC_INT_STT_RFKILL);
336 }
337
338 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
339
340 out:
341 return ret;
342 }
343
344 /*
345 * Enable LP XTAL to avoid HW bug where device may consume much power if
346 * FW is not loaded after device reset. LP XTAL is disabled by default
347 * after device HW reset. Do it only if XTAL is fed by internal source.
348 * Configure device's "persistence" mode to avoid resetting XTAL again when
349 * SHRD_HW_RST occurs in S3.
350 */
351 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
352 {
353 int ret;
354 u32 apmg_gp1_reg;
355 u32 apmg_xtal_cfg_reg;
356 u32 dl_cfg_reg;
357
358 /* Force XTAL ON */
359 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
360 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
361
362 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
363 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
364
365 udelay(10);
366
367 /*
368 * Set "initialization complete" bit to move adapter from
369 * D0U* --> D0A* (powered-up active) state.
370 */
371 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
372
373 /*
374 * Wait for clock stabilization; once stabilized, access to
375 * device-internal resources is possible.
376 */
377 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
378 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
379 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
380 25000);
381 if (WARN_ON(ret < 0)) {
382 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
383 /* Release XTAL ON request */
384 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
385 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
386 return;
387 }
388
389 /*
390 * Clear "disable persistence" to avoid LP XTAL resetting when
391 * SHRD_HW_RST is applied in S3.
392 */
393 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
394 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
395
396 /*
397 * Force APMG XTAL to be active to prevent its disabling by HW
398 * caused by APMG idle state.
399 */
400 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
401 SHR_APMG_XTAL_CFG_REG);
402 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
403 apmg_xtal_cfg_reg |
404 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
405
406 /*
407 * Reset entire device again - do controller reset (results in
408 * SHRD_HW_RST). Turn MAC off before proceeding.
409 */
410 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
411
412 udelay(10);
413
414 /* Enable LP XTAL by indirect access through CSR */
415 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
416 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
417 SHR_APMG_GP1_WF_XTAL_LP_EN |
418 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
419
420 /* Clear delay line clock power up */
421 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
422 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
423 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
424
425 /*
426 * Enable persistence mode to avoid LP XTAL resetting when
427 * SHRD_HW_RST is applied in S3.
428 */
429 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
430 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
431
432 /*
433 * Clear "initialization complete" bit to move adapter from
434 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
435 */
436 iwl_clear_bit(trans, CSR_GP_CNTRL,
437 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
438
439 /* Activates XTAL resources monitor */
440 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
441 CSR_MONITOR_XTAL_RESOURCES);
442
443 /* Release XTAL ON request */
444 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
445 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
446 udelay(10);
447
448 /* Release APMG XTAL */
449 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
450 apmg_xtal_cfg_reg &
451 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
452 }
453
454 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
455 {
456 int ret = 0;
457
458 /* stop device's busmaster DMA activity */
459 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
460
461 ret = iwl_poll_bit(trans, CSR_RESET,
462 CSR_RESET_REG_FLAG_MASTER_DISABLED,
463 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
464 if (ret < 0)
465 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
466
467 IWL_DEBUG_INFO(trans, "stop master\n");
468
469 return ret;
470 }
471
472 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
473 {
474 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
475
476 if (op_mode_leave) {
477 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
478 iwl_pcie_apm_init(trans);
479
480 /* inform ME that we are leaving */
481 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
482 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
483 APMG_PCIDEV_STT_VAL_WAKE_ME);
484 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
485 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
486 CSR_RESET_LINK_PWR_MGMT_DISABLED);
487 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
488 CSR_HW_IF_CONFIG_REG_PREPARE |
489 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
490 mdelay(1);
491 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
492 CSR_RESET_LINK_PWR_MGMT_DISABLED);
493 }
494 mdelay(5);
495 }
496
497 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
498
499 /* Stop device's DMA activity */
500 iwl_pcie_apm_stop_master(trans);
501
502 if (trans->cfg->lp_xtal_workaround) {
503 iwl_pcie_apm_lp_xtal_enable(trans);
504 return;
505 }
506
507 /* Reset the entire device */
508 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
509
510 udelay(10);
511
512 /*
513 * Clear "initialization complete" bit to move adapter from
514 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
515 */
516 iwl_clear_bit(trans, CSR_GP_CNTRL,
517 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
518 }
519
520 static int iwl_pcie_nic_init(struct iwl_trans *trans)
521 {
522 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
523
524 /* nic_init */
525 spin_lock(&trans_pcie->irq_lock);
526 iwl_pcie_apm_init(trans);
527
528 spin_unlock(&trans_pcie->irq_lock);
529
530 iwl_pcie_set_pwr(trans, false);
531
532 iwl_op_mode_nic_config(trans->op_mode);
533
534 /* Allocate the RX queue, or reset if it is already allocated */
535 iwl_pcie_rx_init(trans);
536
537 /* Allocate or reset and init all Tx and Command queues */
538 if (iwl_pcie_tx_init(trans))
539 return -ENOMEM;
540
541 if (trans->cfg->base_params->shadow_reg_enable) {
542 /* enable shadow regs in HW */
543 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
544 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
545 }
546
547 return 0;
548 }
549
550 #define HW_READY_TIMEOUT (50)
551
552 /* Note: returns poll_bit return value, which is >= 0 if success */
553 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
554 {
555 int ret;
556
557 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
558 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
559
560 /* See if we got it */
561 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
562 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
563 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
564 HW_READY_TIMEOUT);
565
566 if (ret >= 0)
567 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
568
569 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
570 return ret;
571 }
572
573 /* Note: returns standard 0/-ERROR code */
574 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
575 {
576 int ret;
577 int t = 0;
578 int iter;
579
580 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
581
582 ret = iwl_pcie_set_hw_ready(trans);
583 /* If the card is ready, exit 0 */
584 if (ret >= 0)
585 return 0;
586
587 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
588 CSR_RESET_LINK_PWR_MGMT_DISABLED);
589 msleep(1);
590
591 for (iter = 0; iter < 10; iter++) {
592 /* If HW is not ready, prepare the conditions to check again */
593 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
594 CSR_HW_IF_CONFIG_REG_PREPARE);
595
596 do {
597 ret = iwl_pcie_set_hw_ready(trans);
598 if (ret >= 0)
599 return 0;
600
601 usleep_range(200, 1000);
602 t += 200;
603 } while (t < 150000);
604 msleep(25);
605 }
606
607 IWL_ERR(trans, "Couldn't prepare the card\n");
608
609 return ret;
610 }
611
612 /*
613 * ucode
614 */
615 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
616 dma_addr_t phy_addr, u32 byte_cnt)
617 {
618 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
619 int ret;
620
621 trans_pcie->ucode_write_complete = false;
622
623 iwl_write_direct32(trans,
624 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
625 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
626
627 iwl_write_direct32(trans,
628 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
629 dst_addr);
630
631 iwl_write_direct32(trans,
632 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
633 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
634
635 iwl_write_direct32(trans,
636 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
637 (iwl_get_dma_hi_addr(phy_addr)
638 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
639
640 iwl_write_direct32(trans,
641 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
642 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
643 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
644 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
645
646 iwl_write_direct32(trans,
647 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
648 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
649 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
650 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
651
652 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
653 trans_pcie->ucode_write_complete, 5 * HZ);
654 if (!ret) {
655 IWL_ERR(trans, "Failed to load firmware chunk!\n");
656 return -ETIMEDOUT;
657 }
658
659 return 0;
660 }
661
662 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
663 const struct fw_desc *section)
664 {
665 u8 *v_addr;
666 dma_addr_t p_addr;
667 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
668 int ret = 0;
669
670 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
671 section_num);
672
673 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
674 GFP_KERNEL | __GFP_NOWARN);
675 if (!v_addr) {
676 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
677 chunk_sz = PAGE_SIZE;
678 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
679 &p_addr, GFP_KERNEL);
680 if (!v_addr)
681 return -ENOMEM;
682 }
683
684 for (offset = 0; offset < section->len; offset += chunk_sz) {
685 u32 copy_size, dst_addr;
686 bool extended_addr = false;
687
688 copy_size = min_t(u32, chunk_sz, section->len - offset);
689 dst_addr = section->offset + offset;
690
691 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
692 dst_addr <= IWL_FW_MEM_EXTENDED_END)
693 extended_addr = true;
694
695 if (extended_addr)
696 iwl_set_bits_prph(trans, LMPM_CHICK,
697 LMPM_CHICK_EXTENDED_ADDR_SPACE);
698
699 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
700 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
701 copy_size);
702
703 if (extended_addr)
704 iwl_clear_bits_prph(trans, LMPM_CHICK,
705 LMPM_CHICK_EXTENDED_ADDR_SPACE);
706
707 if (ret) {
708 IWL_ERR(trans,
709 "Could not load the [%d] uCode section\n",
710 section_num);
711 break;
712 }
713 }
714
715 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
716 return ret;
717 }
718
719 /*
720 * Driver Takes the ownership on secure machine before FW load
721 * and prevent race with the BT load.
722 * W/A for ROM bug. (should be remove in the next Si step)
723 */
724 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
725 {
726 u32 val, loop = 1000;
727
728 /*
729 * Check the RSA semaphore is accessible.
730 * If the HW isn't locked and the rsa semaphore isn't accessible,
731 * we are in trouble.
732 */
733 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
734 if (val & (BIT(1) | BIT(17))) {
735 IWL_INFO(trans,
736 "can't access the RSA semaphore it is write protected\n");
737 return 0;
738 }
739
740 /* take ownership on the AUX IF */
741 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
742 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
743
744 do {
745 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
746 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
747 if (val == 0x1) {
748 iwl_write_prph(trans, RSA_ENABLE, 0);
749 return 0;
750 }
751
752 udelay(10);
753 loop--;
754 } while (loop > 0);
755
756 IWL_ERR(trans, "Failed to take ownership on secure machine\n");
757 return -EIO;
758 }
759
760 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
761 const struct fw_img *image,
762 int cpu,
763 int *first_ucode_section)
764 {
765 int shift_param;
766 int i, ret = 0, sec_num = 0x1;
767 u32 val, last_read_idx = 0;
768
769 if (cpu == 1) {
770 shift_param = 0;
771 *first_ucode_section = 0;
772 } else {
773 shift_param = 16;
774 (*first_ucode_section)++;
775 }
776
777 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
778 last_read_idx = i;
779
780 /*
781 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
782 * CPU1 to CPU2.
783 * PAGING_SEPARATOR_SECTION delimiter - separate between
784 * CPU2 non paged to CPU2 paging sec.
785 */
786 if (!image->sec[i].data ||
787 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
788 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
789 IWL_DEBUG_FW(trans,
790 "Break since Data not valid or Empty section, sec = %d\n",
791 i);
792 break;
793 }
794
795 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
796 if (ret)
797 return ret;
798
799 /* Notify the ucode of the loaded section number and status */
800 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
801 val = val | (sec_num << shift_param);
802 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
803 sec_num = (sec_num << 1) | 0x1;
804 }
805
806 *first_ucode_section = last_read_idx;
807
808 if (cpu == 1)
809 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
810 else
811 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
812
813 return 0;
814 }
815
816 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
817 const struct fw_img *image,
818 int cpu,
819 int *first_ucode_section)
820 {
821 int shift_param;
822 int i, ret = 0;
823 u32 last_read_idx = 0;
824
825 if (cpu == 1) {
826 shift_param = 0;
827 *first_ucode_section = 0;
828 } else {
829 shift_param = 16;
830 (*first_ucode_section)++;
831 }
832
833 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
834 last_read_idx = i;
835
836 /*
837 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
838 * CPU1 to CPU2.
839 * PAGING_SEPARATOR_SECTION delimiter - separate between
840 * CPU2 non paged to CPU2 paging sec.
841 */
842 if (!image->sec[i].data ||
843 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
844 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
845 IWL_DEBUG_FW(trans,
846 "Break since Data not valid or Empty section, sec = %d\n",
847 i);
848 break;
849 }
850
851 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
852 if (ret)
853 return ret;
854 }
855
856 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
857 iwl_set_bits_prph(trans,
858 CSR_UCODE_LOAD_STATUS_ADDR,
859 (LMPM_CPU_UCODE_LOADING_COMPLETED |
860 LMPM_CPU_HDRS_LOADING_COMPLETED |
861 LMPM_CPU_UCODE_LOADING_STARTED) <<
862 shift_param);
863
864 *first_ucode_section = last_read_idx;
865
866 return 0;
867 }
868
869 static void iwl_pcie_apply_destination(struct iwl_trans *trans)
870 {
871 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
872 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
873 int i;
874
875 if (dest->version)
876 IWL_ERR(trans,
877 "DBG DEST version is %d - expect issues\n",
878 dest->version);
879
880 IWL_INFO(trans, "Applying debug destination %s\n",
881 get_fw_dbg_mode_string(dest->monitor_mode));
882
883 if (dest->monitor_mode == EXTERNAL_MODE)
884 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
885 else
886 IWL_WARN(trans, "PCI should have external buffer debug\n");
887
888 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
889 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
890 u32 val = le32_to_cpu(dest->reg_ops[i].val);
891
892 switch (dest->reg_ops[i].op) {
893 case CSR_ASSIGN:
894 iwl_write32(trans, addr, val);
895 break;
896 case CSR_SETBIT:
897 iwl_set_bit(trans, addr, BIT(val));
898 break;
899 case CSR_CLEARBIT:
900 iwl_clear_bit(trans, addr, BIT(val));
901 break;
902 case PRPH_ASSIGN:
903 iwl_write_prph(trans, addr, val);
904 break;
905 case PRPH_SETBIT:
906 iwl_set_bits_prph(trans, addr, BIT(val));
907 break;
908 case PRPH_CLEARBIT:
909 iwl_clear_bits_prph(trans, addr, BIT(val));
910 break;
911 case PRPH_BLOCKBIT:
912 if (iwl_read_prph(trans, addr) & BIT(val)) {
913 IWL_ERR(trans,
914 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
915 val, addr);
916 goto monitor;
917 }
918 break;
919 default:
920 IWL_ERR(trans, "FW debug - unknown OP %d\n",
921 dest->reg_ops[i].op);
922 break;
923 }
924 }
925
926 monitor:
927 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
928 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
929 trans_pcie->fw_mon_phys >> dest->base_shift);
930 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
931 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
932 (trans_pcie->fw_mon_phys +
933 trans_pcie->fw_mon_size - 256) >>
934 dest->end_shift);
935 else
936 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
937 (trans_pcie->fw_mon_phys +
938 trans_pcie->fw_mon_size) >>
939 dest->end_shift);
940 }
941 }
942
943 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
944 const struct fw_img *image)
945 {
946 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
947 int ret = 0;
948 int first_ucode_section;
949
950 IWL_DEBUG_FW(trans, "working with %s CPU\n",
951 image->is_dual_cpus ? "Dual" : "Single");
952
953 /* load to FW the binary non secured sections of CPU1 */
954 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
955 if (ret)
956 return ret;
957
958 if (image->is_dual_cpus) {
959 /* set CPU2 header address */
960 iwl_write_prph(trans,
961 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
962 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
963
964 /* load to FW the binary sections of CPU2 */
965 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
966 &first_ucode_section);
967 if (ret)
968 return ret;
969 }
970
971 /* supported for 7000 only for the moment */
972 if (iwlwifi_mod_params.fw_monitor &&
973 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
974 iwl_pcie_alloc_fw_monitor(trans, 0);
975
976 if (trans_pcie->fw_mon_size) {
977 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
978 trans_pcie->fw_mon_phys >> 4);
979 iwl_write_prph(trans, MON_BUFF_END_ADDR,
980 (trans_pcie->fw_mon_phys +
981 trans_pcie->fw_mon_size) >> 4);
982 }
983 } else if (trans->dbg_dest_tlv) {
984 iwl_pcie_apply_destination(trans);
985 }
986
987 /* release CPU reset */
988 iwl_write32(trans, CSR_RESET, 0);
989
990 return 0;
991 }
992
993 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
994 const struct fw_img *image)
995 {
996 int ret = 0;
997 int first_ucode_section;
998
999 IWL_DEBUG_FW(trans, "working with %s CPU\n",
1000 image->is_dual_cpus ? "Dual" : "Single");
1001
1002 if (trans->dbg_dest_tlv)
1003 iwl_pcie_apply_destination(trans);
1004
1005 /* TODO: remove in the next Si step */
1006 ret = iwl_pcie_rsa_race_bug_wa(trans);
1007 if (ret)
1008 return ret;
1009
1010 /* configure the ucode to be ready to get the secured image */
1011 /* release CPU reset */
1012 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1013
1014 /* load to FW the binary Secured sections of CPU1 */
1015 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1016 &first_ucode_section);
1017 if (ret)
1018 return ret;
1019
1020 /* load to FW the binary sections of CPU2 */
1021 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1022 &first_ucode_section);
1023 }
1024
1025 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1026 {
1027 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1028 bool hw_rfkill, was_hw_rfkill;
1029
1030 lockdep_assert_held(&trans_pcie->mutex);
1031
1032 if (trans_pcie->is_down)
1033 return;
1034
1035 trans_pcie->is_down = true;
1036
1037 was_hw_rfkill = iwl_is_rfkill_set(trans);
1038
1039 /* tell the device to stop sending interrupts */
1040 spin_lock(&trans_pcie->irq_lock);
1041 iwl_disable_interrupts(trans);
1042 spin_unlock(&trans_pcie->irq_lock);
1043
1044 /* device going down, Stop using ICT table */
1045 iwl_pcie_disable_ict(trans);
1046
1047 /*
1048 * If a HW restart happens during firmware loading,
1049 * then the firmware loading might call this function
1050 * and later it might be called again due to the
1051 * restart. So don't process again if the device is
1052 * already dead.
1053 */
1054 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1055 IWL_DEBUG_INFO(trans,
1056 "DEVICE_ENABLED bit was set and is now cleared\n");
1057 iwl_pcie_tx_stop(trans);
1058 iwl_pcie_rx_stop(trans);
1059
1060 /* Power-down device's busmaster DMA clocks */
1061 if (!trans->cfg->apmg_not_supported) {
1062 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1063 APMG_CLK_VAL_DMA_CLK_RQT);
1064 udelay(5);
1065 }
1066 }
1067
1068 /* Make sure (redundant) we've released our request to stay awake */
1069 iwl_clear_bit(trans, CSR_GP_CNTRL,
1070 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1071
1072 /* Stop the device, and put it in low power state */
1073 iwl_pcie_apm_stop(trans, false);
1074
1075 /* stop and reset the on-board processor */
1076 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1077 udelay(20);
1078
1079 /*
1080 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1081 * This is a bug in certain verions of the hardware.
1082 * Certain devices also keep sending HW RF kill interrupt all
1083 * the time, unless the interrupt is ACKed even if the interrupt
1084 * should be masked. Re-ACK all the interrupts here.
1085 */
1086 spin_lock(&trans_pcie->irq_lock);
1087 iwl_disable_interrupts(trans);
1088 spin_unlock(&trans_pcie->irq_lock);
1089
1090 /* clear all status bits */
1091 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1092 clear_bit(STATUS_INT_ENABLED, &trans->status);
1093 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1094 clear_bit(STATUS_RFKILL, &trans->status);
1095
1096 /*
1097 * Even if we stop the HW, we still want the RF kill
1098 * interrupt
1099 */
1100 iwl_enable_rfkill_int(trans);
1101
1102 /*
1103 * Check again since the RF kill state may have changed while
1104 * all the interrupts were disabled, in this case we couldn't
1105 * receive the RF kill interrupt and update the state in the
1106 * op_mode.
1107 * Don't call the op_mode if the rkfill state hasn't changed.
1108 * This allows the op_mode to call stop_device from the rfkill
1109 * notification without endless recursion. Under very rare
1110 * circumstances, we might have a small recursion if the rfkill
1111 * state changed exactly now while we were called from stop_device.
1112 * This is very unlikely but can happen and is supported.
1113 */
1114 hw_rfkill = iwl_is_rfkill_set(trans);
1115 if (hw_rfkill)
1116 set_bit(STATUS_RFKILL, &trans->status);
1117 else
1118 clear_bit(STATUS_RFKILL, &trans->status);
1119 if (hw_rfkill != was_hw_rfkill)
1120 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1121
1122 /* re-take ownership to prevent other users from stealing the device */
1123 iwl_pcie_prepare_card_hw(trans);
1124 }
1125
1126 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1127 const struct fw_img *fw, bool run_in_rfkill)
1128 {
1129 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1130 bool hw_rfkill;
1131 int ret;
1132
1133 /* This may fail if AMT took ownership of the device */
1134 if (iwl_pcie_prepare_card_hw(trans)) {
1135 IWL_WARN(trans, "Exit HW not ready\n");
1136 ret = -EIO;
1137 goto out;
1138 }
1139
1140 iwl_enable_rfkill_int(trans);
1141
1142 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1143
1144 /*
1145 * We enabled the RF-Kill interrupt and the handler may very
1146 * well be running. Disable the interrupts to make sure no other
1147 * interrupt can be fired.
1148 */
1149 iwl_disable_interrupts(trans);
1150
1151 /* Make sure it finished running */
1152 synchronize_irq(trans_pcie->pci_dev->irq);
1153
1154 mutex_lock(&trans_pcie->mutex);
1155
1156 /* If platform's RF_KILL switch is NOT set to KILL */
1157 hw_rfkill = iwl_is_rfkill_set(trans);
1158 if (hw_rfkill)
1159 set_bit(STATUS_RFKILL, &trans->status);
1160 else
1161 clear_bit(STATUS_RFKILL, &trans->status);
1162 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1163 if (hw_rfkill && !run_in_rfkill) {
1164 ret = -ERFKILL;
1165 goto out;
1166 }
1167
1168 /* Someone called stop_device, don't try to start_fw */
1169 if (trans_pcie->is_down) {
1170 IWL_WARN(trans,
1171 "Can't start_fw since the HW hasn't been started\n");
1172 ret = -EIO;
1173 goto out;
1174 }
1175
1176 /* make sure rfkill handshake bits are cleared */
1177 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1178 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1179 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1180
1181 /* clear (again), then enable host interrupts */
1182 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1183
1184 ret = iwl_pcie_nic_init(trans);
1185 if (ret) {
1186 IWL_ERR(trans, "Unable to init nic\n");
1187 goto out;
1188 }
1189
1190 /*
1191 * Now, we load the firmware and don't want to be interrupted, even
1192 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1193 * FH_TX interrupt which is needed to load the firmware). If the
1194 * RF-Kill switch is toggled, we will find out after having loaded
1195 * the firmware and return the proper value to the caller.
1196 */
1197 iwl_enable_fw_load_int(trans);
1198
1199 /* really make sure rfkill handshake bits are cleared */
1200 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1201 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1202
1203 /* Load the given image to the HW */
1204 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1205 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1206 else
1207 ret = iwl_pcie_load_given_ucode(trans, fw);
1208 iwl_enable_interrupts(trans);
1209
1210 /* re-check RF-Kill state since we may have missed the interrupt */
1211 hw_rfkill = iwl_is_rfkill_set(trans);
1212 if (hw_rfkill)
1213 set_bit(STATUS_RFKILL, &trans->status);
1214 else
1215 clear_bit(STATUS_RFKILL, &trans->status);
1216
1217 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1218 if (hw_rfkill && !run_in_rfkill)
1219 ret = -ERFKILL;
1220
1221 out:
1222 mutex_unlock(&trans_pcie->mutex);
1223 return ret;
1224 }
1225
1226 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1227 {
1228 iwl_pcie_reset_ict(trans);
1229 iwl_pcie_tx_start(trans, scd_addr);
1230 }
1231
1232 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1233 {
1234 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1235
1236 mutex_lock(&trans_pcie->mutex);
1237 _iwl_trans_pcie_stop_device(trans, low_power);
1238 mutex_unlock(&trans_pcie->mutex);
1239 }
1240
1241 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1242 {
1243 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1244 IWL_TRANS_GET_PCIE_TRANS(trans);
1245
1246 lockdep_assert_held(&trans_pcie->mutex);
1247
1248 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1249 _iwl_trans_pcie_stop_device(trans, true);
1250 }
1251
1252 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1253 bool reset)
1254 {
1255 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1256
1257 if (!reset) {
1258 /* Enable persistence mode to avoid reset */
1259 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1260 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1261 }
1262
1263 iwl_disable_interrupts(trans);
1264
1265 /*
1266 * in testing mode, the host stays awake and the
1267 * hardware won't be reset (not even partially)
1268 */
1269 if (test)
1270 return;
1271
1272 iwl_pcie_disable_ict(trans);
1273
1274 synchronize_irq(trans_pcie->pci_dev->irq);
1275
1276 iwl_clear_bit(trans, CSR_GP_CNTRL,
1277 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1278 iwl_clear_bit(trans, CSR_GP_CNTRL,
1279 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1280
1281 if (reset) {
1282 /*
1283 * reset TX queues -- some of their registers reset during S3
1284 * so if we don't reset everything here the D3 image would try
1285 * to execute some invalid memory upon resume
1286 */
1287 iwl_trans_pcie_tx_reset(trans);
1288 }
1289
1290 iwl_pcie_set_pwr(trans, true);
1291 }
1292
1293 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1294 enum iwl_d3_status *status,
1295 bool test, bool reset)
1296 {
1297 u32 val;
1298 int ret;
1299
1300 if (test) {
1301 iwl_enable_interrupts(trans);
1302 *status = IWL_D3_STATUS_ALIVE;
1303 return 0;
1304 }
1305
1306 /*
1307 * Also enables interrupts - none will happen as the device doesn't
1308 * know we're waking it up, only when the opmode actually tells it
1309 * after this call.
1310 */
1311 iwl_pcie_reset_ict(trans);
1312
1313 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1314 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1315
1316 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1317 udelay(2);
1318
1319 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1320 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1321 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1322 25000);
1323 if (ret < 0) {
1324 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1325 return ret;
1326 }
1327
1328 iwl_pcie_set_pwr(trans, false);
1329
1330 if (!reset) {
1331 iwl_clear_bit(trans, CSR_GP_CNTRL,
1332 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1333 } else {
1334 iwl_trans_pcie_tx_reset(trans);
1335
1336 ret = iwl_pcie_rx_init(trans);
1337 if (ret) {
1338 IWL_ERR(trans,
1339 "Failed to resume the device (RX reset)\n");
1340 return ret;
1341 }
1342 }
1343
1344 val = iwl_read32(trans, CSR_RESET);
1345 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1346 *status = IWL_D3_STATUS_RESET;
1347 else
1348 *status = IWL_D3_STATUS_ALIVE;
1349
1350 return 0;
1351 }
1352
1353 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1354 {
1355 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1356 bool hw_rfkill;
1357 int err;
1358
1359 lockdep_assert_held(&trans_pcie->mutex);
1360
1361 err = iwl_pcie_prepare_card_hw(trans);
1362 if (err) {
1363 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1364 return err;
1365 }
1366
1367 /* Reset the entire device */
1368 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1369
1370 usleep_range(10, 15);
1371
1372 iwl_pcie_apm_init(trans);
1373
1374 /* From now on, the op_mode will be kept updated about RF kill state */
1375 iwl_enable_rfkill_int(trans);
1376
1377 /* Set is_down to false here so that...*/
1378 trans_pcie->is_down = false;
1379
1380 hw_rfkill = iwl_is_rfkill_set(trans);
1381 if (hw_rfkill)
1382 set_bit(STATUS_RFKILL, &trans->status);
1383 else
1384 clear_bit(STATUS_RFKILL, &trans->status);
1385 /* ... rfkill can call stop_device and set it false if needed */
1386 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1387
1388 /* Make sure we sync here, because we'll need full access later */
1389 if (low_power)
1390 pm_runtime_resume(trans->dev);
1391
1392 return 0;
1393 }
1394
1395 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1396 {
1397 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1398 int ret;
1399
1400 mutex_lock(&trans_pcie->mutex);
1401 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1402 mutex_unlock(&trans_pcie->mutex);
1403
1404 return ret;
1405 }
1406
1407 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1408 {
1409 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1410
1411 mutex_lock(&trans_pcie->mutex);
1412
1413 /* disable interrupts - don't enable HW RF kill interrupt */
1414 spin_lock(&trans_pcie->irq_lock);
1415 iwl_disable_interrupts(trans);
1416 spin_unlock(&trans_pcie->irq_lock);
1417
1418 iwl_pcie_apm_stop(trans, true);
1419
1420 spin_lock(&trans_pcie->irq_lock);
1421 iwl_disable_interrupts(trans);
1422 spin_unlock(&trans_pcie->irq_lock);
1423
1424 iwl_pcie_disable_ict(trans);
1425
1426 mutex_unlock(&trans_pcie->mutex);
1427
1428 synchronize_irq(trans_pcie->pci_dev->irq);
1429 }
1430
1431 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1432 {
1433 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1434 }
1435
1436 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1437 {
1438 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1439 }
1440
1441 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1442 {
1443 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1444 }
1445
1446 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1447 {
1448 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1449 ((reg & 0x000FFFFF) | (3 << 24)));
1450 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1451 }
1452
1453 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1454 u32 val)
1455 {
1456 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1457 ((addr & 0x000FFFFF) | (3 << 24)));
1458 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1459 }
1460
1461 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1462 const struct iwl_trans_config *trans_cfg)
1463 {
1464 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1465
1466 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1467 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1468 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1469 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1470 trans_pcie->n_no_reclaim_cmds = 0;
1471 else
1472 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1473 if (trans_pcie->n_no_reclaim_cmds)
1474 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1475 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1476
1477 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1478 trans_pcie->rx_page_order =
1479 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1480
1481 trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header;
1482 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1483 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1484 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1485
1486 trans->command_groups = trans_cfg->command_groups;
1487 trans->command_groups_size = trans_cfg->command_groups_size;
1488
1489 /* init ref_count to 1 (should be cleared when ucode is loaded) */
1490 trans_pcie->ref_count = 1;
1491
1492 /* Initialize NAPI here - it should be before registering to mac80211
1493 * in the opmode but after the HW struct is allocated.
1494 * As this function may be called again in some corner cases don't
1495 * do anything if NAPI was already initialized.
1496 */
1497 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1498 init_dummy_netdev(&trans_pcie->napi_dev);
1499 }
1500
1501 void iwl_trans_pcie_free(struct iwl_trans *trans)
1502 {
1503 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1504 int i;
1505
1506 /* TODO: check if this is really needed */
1507 pm_runtime_disable(trans->dev);
1508
1509 synchronize_irq(trans_pcie->pci_dev->irq);
1510
1511 iwl_pcie_tx_free(trans);
1512 iwl_pcie_rx_free(trans);
1513
1514 free_irq(trans_pcie->pci_dev->irq, trans);
1515 iwl_pcie_free_ict(trans);
1516
1517 pci_disable_msi(trans_pcie->pci_dev);
1518 iounmap(trans_pcie->hw_base);
1519 pci_release_regions(trans_pcie->pci_dev);
1520 pci_disable_device(trans_pcie->pci_dev);
1521
1522 iwl_pcie_free_fw_monitor(trans);
1523
1524 for_each_possible_cpu(i) {
1525 struct iwl_tso_hdr_page *p =
1526 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1527
1528 if (p->page)
1529 __free_page(p->page);
1530 }
1531
1532 free_percpu(trans_pcie->tso_hdr_page);
1533 iwl_trans_free(trans);
1534 }
1535
1536 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1537 {
1538 if (state)
1539 set_bit(STATUS_TPOWER_PMI, &trans->status);
1540 else
1541 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1542 }
1543
1544 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1545 unsigned long *flags)
1546 {
1547 int ret;
1548 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1549
1550 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1551
1552 if (trans_pcie->cmd_hold_nic_awake)
1553 goto out;
1554
1555 /* this bit wakes up the NIC */
1556 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1557 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1558 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1559 udelay(2);
1560
1561 /*
1562 * These bits say the device is running, and should keep running for
1563 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1564 * but they do not indicate that embedded SRAM is restored yet;
1565 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1566 * to/from host DRAM when sleeping/waking for power-saving.
1567 * Each direction takes approximately 1/4 millisecond; with this
1568 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1569 * series of register accesses are expected (e.g. reading Event Log),
1570 * to keep device from sleeping.
1571 *
1572 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1573 * SRAM is okay/restored. We don't check that here because this call
1574 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1575 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1576 *
1577 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1578 * and do not save/restore SRAM when power cycling.
1579 */
1580 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1581 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1582 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1583 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1584 if (unlikely(ret < 0)) {
1585 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1586 WARN_ONCE(1,
1587 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1588 iwl_read32(trans, CSR_GP_CNTRL));
1589 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1590 return false;
1591 }
1592
1593 out:
1594 /*
1595 * Fool sparse by faking we release the lock - sparse will
1596 * track nic_access anyway.
1597 */
1598 __release(&trans_pcie->reg_lock);
1599 return true;
1600 }
1601
1602 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1603 unsigned long *flags)
1604 {
1605 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1606
1607 lockdep_assert_held(&trans_pcie->reg_lock);
1608
1609 /*
1610 * Fool sparse by faking we acquiring the lock - sparse will
1611 * track nic_access anyway.
1612 */
1613 __acquire(&trans_pcie->reg_lock);
1614
1615 if (trans_pcie->cmd_hold_nic_awake)
1616 goto out;
1617
1618 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1619 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1620 /*
1621 * Above we read the CSR_GP_CNTRL register, which will flush
1622 * any previous writes, but we need the write that clears the
1623 * MAC_ACCESS_REQ bit to be performed before any other writes
1624 * scheduled on different CPUs (after we drop reg_lock).
1625 */
1626 mmiowb();
1627 out:
1628 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1629 }
1630
1631 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1632 void *buf, int dwords)
1633 {
1634 unsigned long flags;
1635 int offs, ret = 0;
1636 u32 *vals = buf;
1637
1638 if (iwl_trans_grab_nic_access(trans, &flags)) {
1639 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1640 for (offs = 0; offs < dwords; offs++)
1641 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1642 iwl_trans_release_nic_access(trans, &flags);
1643 } else {
1644 ret = -EBUSY;
1645 }
1646 return ret;
1647 }
1648
1649 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1650 const void *buf, int dwords)
1651 {
1652 unsigned long flags;
1653 int offs, ret = 0;
1654 const u32 *vals = buf;
1655
1656 if (iwl_trans_grab_nic_access(trans, &flags)) {
1657 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1658 for (offs = 0; offs < dwords; offs++)
1659 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1660 vals ? vals[offs] : 0);
1661 iwl_trans_release_nic_access(trans, &flags);
1662 } else {
1663 ret = -EBUSY;
1664 }
1665 return ret;
1666 }
1667
1668 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1669 unsigned long txqs,
1670 bool freeze)
1671 {
1672 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1673 int queue;
1674
1675 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1676 struct iwl_txq *txq = &trans_pcie->txq[queue];
1677 unsigned long now;
1678
1679 spin_lock_bh(&txq->lock);
1680
1681 now = jiffies;
1682
1683 if (txq->frozen == freeze)
1684 goto next_queue;
1685
1686 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1687 freeze ? "Freezing" : "Waking", queue);
1688
1689 txq->frozen = freeze;
1690
1691 if (txq->q.read_ptr == txq->q.write_ptr)
1692 goto next_queue;
1693
1694 if (freeze) {
1695 if (unlikely(time_after(now,
1696 txq->stuck_timer.expires))) {
1697 /*
1698 * The timer should have fired, maybe it is
1699 * spinning right now on the lock.
1700 */
1701 goto next_queue;
1702 }
1703 /* remember how long until the timer fires */
1704 txq->frozen_expiry_remainder =
1705 txq->stuck_timer.expires - now;
1706 del_timer(&txq->stuck_timer);
1707 goto next_queue;
1708 }
1709
1710 /*
1711 * Wake a non-empty queue -> arm timer with the
1712 * remainder before it froze
1713 */
1714 mod_timer(&txq->stuck_timer,
1715 now + txq->frozen_expiry_remainder);
1716
1717 next_queue:
1718 spin_unlock_bh(&txq->lock);
1719 }
1720 }
1721
1722 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
1723 {
1724 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1725 int i;
1726
1727 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
1728 struct iwl_txq *txq = &trans_pcie->txq[i];
1729
1730 if (i == trans_pcie->cmd_queue)
1731 continue;
1732
1733 spin_lock_bh(&txq->lock);
1734
1735 if (!block && !(WARN_ON_ONCE(!txq->block))) {
1736 txq->block--;
1737 if (!txq->block) {
1738 iwl_write32(trans, HBUS_TARG_WRPTR,
1739 txq->q.write_ptr | (i << 8));
1740 }
1741 } else if (block) {
1742 txq->block++;
1743 }
1744
1745 spin_unlock_bh(&txq->lock);
1746 }
1747 }
1748
1749 #define IWL_FLUSH_WAIT_MS 2000
1750
1751 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1752 {
1753 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1754 struct iwl_txq *txq;
1755 struct iwl_queue *q;
1756 int cnt;
1757 unsigned long now = jiffies;
1758 u32 scd_sram_addr;
1759 u8 buf[16];
1760 int ret = 0;
1761
1762 /* waiting for all the tx frames complete might take a while */
1763 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1764 u8 wr_ptr;
1765
1766 if (cnt == trans_pcie->cmd_queue)
1767 continue;
1768 if (!test_bit(cnt, trans_pcie->queue_used))
1769 continue;
1770 if (!(BIT(cnt) & txq_bm))
1771 continue;
1772
1773 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1774 txq = &trans_pcie->txq[cnt];
1775 q = &txq->q;
1776 wr_ptr = ACCESS_ONCE(q->write_ptr);
1777
1778 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1779 !time_after(jiffies,
1780 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1781 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1782
1783 if (WARN_ONCE(wr_ptr != write_ptr,
1784 "WR pointer moved while flushing %d -> %d\n",
1785 wr_ptr, write_ptr))
1786 return -ETIMEDOUT;
1787 msleep(1);
1788 }
1789
1790 if (q->read_ptr != q->write_ptr) {
1791 IWL_ERR(trans,
1792 "fail to flush all tx fifo queues Q %d\n", cnt);
1793 ret = -ETIMEDOUT;
1794 break;
1795 }
1796 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1797 }
1798
1799 if (!ret)
1800 return 0;
1801
1802 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1803 txq->q.read_ptr, txq->q.write_ptr);
1804
1805 scd_sram_addr = trans_pcie->scd_base_addr +
1806 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1807 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1808
1809 iwl_print_hex_error(trans, buf, sizeof(buf));
1810
1811 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1812 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1813 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1814
1815 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1816 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1817 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1818 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1819 u32 tbl_dw =
1820 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1821 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1822
1823 if (cnt & 0x1)
1824 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1825 else
1826 tbl_dw = tbl_dw & 0x0000FFFF;
1827
1828 IWL_ERR(trans,
1829 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1830 cnt, active ? "" : "in", fifo, tbl_dw,
1831 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1832 (TFD_QUEUE_SIZE_MAX - 1),
1833 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1834 }
1835
1836 return ret;
1837 }
1838
1839 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1840 u32 mask, u32 value)
1841 {
1842 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1843 unsigned long flags;
1844
1845 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1846 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1847 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1848 }
1849
1850 void iwl_trans_pcie_ref(struct iwl_trans *trans)
1851 {
1852 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1853 unsigned long flags;
1854
1855 if (iwlwifi_mod_params.d0i3_disable)
1856 return;
1857
1858 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1859 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1860 trans_pcie->ref_count++;
1861 pm_runtime_get(&trans_pcie->pci_dev->dev);
1862 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1863 }
1864
1865 void iwl_trans_pcie_unref(struct iwl_trans *trans)
1866 {
1867 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1868 unsigned long flags;
1869
1870 if (iwlwifi_mod_params.d0i3_disable)
1871 return;
1872
1873 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1874 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1875 if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1876 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1877 return;
1878 }
1879 trans_pcie->ref_count--;
1880
1881 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
1882 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
1883
1884 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1885 }
1886
1887 static const char *get_csr_string(int cmd)
1888 {
1889 #define IWL_CMD(x) case x: return #x
1890 switch (cmd) {
1891 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1892 IWL_CMD(CSR_INT_COALESCING);
1893 IWL_CMD(CSR_INT);
1894 IWL_CMD(CSR_INT_MASK);
1895 IWL_CMD(CSR_FH_INT_STATUS);
1896 IWL_CMD(CSR_GPIO_IN);
1897 IWL_CMD(CSR_RESET);
1898 IWL_CMD(CSR_GP_CNTRL);
1899 IWL_CMD(CSR_HW_REV);
1900 IWL_CMD(CSR_EEPROM_REG);
1901 IWL_CMD(CSR_EEPROM_GP);
1902 IWL_CMD(CSR_OTP_GP_REG);
1903 IWL_CMD(CSR_GIO_REG);
1904 IWL_CMD(CSR_GP_UCODE_REG);
1905 IWL_CMD(CSR_GP_DRIVER_REG);
1906 IWL_CMD(CSR_UCODE_DRV_GP1);
1907 IWL_CMD(CSR_UCODE_DRV_GP2);
1908 IWL_CMD(CSR_LED_REG);
1909 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1910 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1911 IWL_CMD(CSR_ANA_PLL_CFG);
1912 IWL_CMD(CSR_HW_REV_WA_REG);
1913 IWL_CMD(CSR_MONITOR_STATUS_REG);
1914 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1915 default:
1916 return "UNKNOWN";
1917 }
1918 #undef IWL_CMD
1919 }
1920
1921 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1922 {
1923 int i;
1924 static const u32 csr_tbl[] = {
1925 CSR_HW_IF_CONFIG_REG,
1926 CSR_INT_COALESCING,
1927 CSR_INT,
1928 CSR_INT_MASK,
1929 CSR_FH_INT_STATUS,
1930 CSR_GPIO_IN,
1931 CSR_RESET,
1932 CSR_GP_CNTRL,
1933 CSR_HW_REV,
1934 CSR_EEPROM_REG,
1935 CSR_EEPROM_GP,
1936 CSR_OTP_GP_REG,
1937 CSR_GIO_REG,
1938 CSR_GP_UCODE_REG,
1939 CSR_GP_DRIVER_REG,
1940 CSR_UCODE_DRV_GP1,
1941 CSR_UCODE_DRV_GP2,
1942 CSR_LED_REG,
1943 CSR_DRAM_INT_TBL_REG,
1944 CSR_GIO_CHICKEN_BITS,
1945 CSR_ANA_PLL_CFG,
1946 CSR_MONITOR_STATUS_REG,
1947 CSR_HW_REV_WA_REG,
1948 CSR_DBG_HPET_MEM_REG
1949 };
1950 IWL_ERR(trans, "CSR values:\n");
1951 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1952 "CSR_INT_PERIODIC_REG)\n");
1953 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1954 IWL_ERR(trans, " %25s: 0X%08x\n",
1955 get_csr_string(csr_tbl[i]),
1956 iwl_read32(trans, csr_tbl[i]));
1957 }
1958 }
1959
1960 #ifdef CONFIG_IWLWIFI_DEBUGFS
1961 /* create and remove of files */
1962 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1963 if (!debugfs_create_file(#name, mode, parent, trans, \
1964 &iwl_dbgfs_##name##_ops)) \
1965 goto err; \
1966 } while (0)
1967
1968 /* file operation */
1969 #define DEBUGFS_READ_FILE_OPS(name) \
1970 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1971 .read = iwl_dbgfs_##name##_read, \
1972 .open = simple_open, \
1973 .llseek = generic_file_llseek, \
1974 };
1975
1976 #define DEBUGFS_WRITE_FILE_OPS(name) \
1977 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1978 .write = iwl_dbgfs_##name##_write, \
1979 .open = simple_open, \
1980 .llseek = generic_file_llseek, \
1981 };
1982
1983 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1984 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1985 .write = iwl_dbgfs_##name##_write, \
1986 .read = iwl_dbgfs_##name##_read, \
1987 .open = simple_open, \
1988 .llseek = generic_file_llseek, \
1989 };
1990
1991 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1992 char __user *user_buf,
1993 size_t count, loff_t *ppos)
1994 {
1995 struct iwl_trans *trans = file->private_data;
1996 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1997 struct iwl_txq *txq;
1998 struct iwl_queue *q;
1999 char *buf;
2000 int pos = 0;
2001 int cnt;
2002 int ret;
2003 size_t bufsz;
2004
2005 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
2006
2007 if (!trans_pcie->txq)
2008 return -EAGAIN;
2009
2010 buf = kzalloc(bufsz, GFP_KERNEL);
2011 if (!buf)
2012 return -ENOMEM;
2013
2014 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2015 txq = &trans_pcie->txq[cnt];
2016 q = &txq->q;
2017 pos += scnprintf(buf + pos, bufsz - pos,
2018 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2019 cnt, q->read_ptr, q->write_ptr,
2020 !!test_bit(cnt, trans_pcie->queue_used),
2021 !!test_bit(cnt, trans_pcie->queue_stopped),
2022 txq->need_update, txq->frozen,
2023 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
2024 }
2025 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2026 kfree(buf);
2027 return ret;
2028 }
2029
2030 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2031 char __user *user_buf,
2032 size_t count, loff_t *ppos)
2033 {
2034 struct iwl_trans *trans = file->private_data;
2035 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2036 char *buf;
2037 int pos = 0, i, ret;
2038 size_t bufsz = sizeof(buf);
2039
2040 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2041
2042 if (!trans_pcie->rxq)
2043 return -EAGAIN;
2044
2045 buf = kzalloc(bufsz, GFP_KERNEL);
2046 if (!buf)
2047 return -ENOMEM;
2048
2049 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2050 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2051
2052 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2053 i);
2054 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2055 rxq->read);
2056 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2057 rxq->write);
2058 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2059 rxq->write_actual);
2060 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2061 rxq->need_update);
2062 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2063 rxq->free_count);
2064 if (rxq->rb_stts) {
2065 pos += scnprintf(buf + pos, bufsz - pos,
2066 "\tclosed_rb_num: %u\n",
2067 le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2068 0x0FFF);
2069 } else {
2070 pos += scnprintf(buf + pos, bufsz - pos,
2071 "\tclosed_rb_num: Not Allocated\n");
2072 }
2073 }
2074 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2075 kfree(buf);
2076
2077 return ret;
2078 }
2079
2080 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2081 char __user *user_buf,
2082 size_t count, loff_t *ppos)
2083 {
2084 struct iwl_trans *trans = file->private_data;
2085 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2086 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2087
2088 int pos = 0;
2089 char *buf;
2090 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2091 ssize_t ret;
2092
2093 buf = kzalloc(bufsz, GFP_KERNEL);
2094 if (!buf)
2095 return -ENOMEM;
2096
2097 pos += scnprintf(buf + pos, bufsz - pos,
2098 "Interrupt Statistics Report:\n");
2099
2100 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2101 isr_stats->hw);
2102 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2103 isr_stats->sw);
2104 if (isr_stats->sw || isr_stats->hw) {
2105 pos += scnprintf(buf + pos, bufsz - pos,
2106 "\tLast Restarting Code: 0x%X\n",
2107 isr_stats->err_code);
2108 }
2109 #ifdef CONFIG_IWLWIFI_DEBUG
2110 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2111 isr_stats->sch);
2112 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2113 isr_stats->alive);
2114 #endif
2115 pos += scnprintf(buf + pos, bufsz - pos,
2116 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2117
2118 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2119 isr_stats->ctkill);
2120
2121 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2122 isr_stats->wakeup);
2123
2124 pos += scnprintf(buf + pos, bufsz - pos,
2125 "Rx command responses:\t\t %u\n", isr_stats->rx);
2126
2127 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2128 isr_stats->tx);
2129
2130 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2131 isr_stats->unhandled);
2132
2133 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2134 kfree(buf);
2135 return ret;
2136 }
2137
2138 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2139 const char __user *user_buf,
2140 size_t count, loff_t *ppos)
2141 {
2142 struct iwl_trans *trans = file->private_data;
2143 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2144 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2145
2146 char buf[8];
2147 int buf_size;
2148 u32 reset_flag;
2149
2150 memset(buf, 0, sizeof(buf));
2151 buf_size = min(count, sizeof(buf) - 1);
2152 if (copy_from_user(buf, user_buf, buf_size))
2153 return -EFAULT;
2154 if (sscanf(buf, "%x", &reset_flag) != 1)
2155 return -EFAULT;
2156 if (reset_flag == 0)
2157 memset(isr_stats, 0, sizeof(*isr_stats));
2158
2159 return count;
2160 }
2161
2162 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2163 const char __user *user_buf,
2164 size_t count, loff_t *ppos)
2165 {
2166 struct iwl_trans *trans = file->private_data;
2167 char buf[8];
2168 int buf_size;
2169 int csr;
2170
2171 memset(buf, 0, sizeof(buf));
2172 buf_size = min(count, sizeof(buf) - 1);
2173 if (copy_from_user(buf, user_buf, buf_size))
2174 return -EFAULT;
2175 if (sscanf(buf, "%d", &csr) != 1)
2176 return -EFAULT;
2177
2178 iwl_pcie_dump_csr(trans);
2179
2180 return count;
2181 }
2182
2183 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2184 char __user *user_buf,
2185 size_t count, loff_t *ppos)
2186 {
2187 struct iwl_trans *trans = file->private_data;
2188 char *buf = NULL;
2189 ssize_t ret;
2190
2191 ret = iwl_dump_fh(trans, &buf);
2192 if (ret < 0)
2193 return ret;
2194 if (!buf)
2195 return -EINVAL;
2196 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2197 kfree(buf);
2198 return ret;
2199 }
2200
2201 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2202 DEBUGFS_READ_FILE_OPS(fh_reg);
2203 DEBUGFS_READ_FILE_OPS(rx_queue);
2204 DEBUGFS_READ_FILE_OPS(tx_queue);
2205 DEBUGFS_WRITE_FILE_OPS(csr);
2206
2207 /* Create the debugfs files and directories */
2208 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2209 {
2210 struct dentry *dir = trans->dbgfs_dir;
2211
2212 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2213 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2214 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2215 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2216 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2217 return 0;
2218
2219 err:
2220 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2221 return -ENOMEM;
2222 }
2223 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2224
2225 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2226 {
2227 u32 cmdlen = 0;
2228 int i;
2229
2230 for (i = 0; i < IWL_NUM_OF_TBS; i++)
2231 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2232
2233 return cmdlen;
2234 }
2235
2236 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2237 struct iwl_fw_error_dump_data **data,
2238 int allocated_rb_nums)
2239 {
2240 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2241 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2242 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2243 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2244 u32 i, r, j, rb_len = 0;
2245
2246 spin_lock(&rxq->lock);
2247
2248 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2249
2250 for (i = rxq->read, j = 0;
2251 i != r && j < allocated_rb_nums;
2252 i = (i + 1) & RX_QUEUE_MASK, j++) {
2253 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2254 struct iwl_fw_error_dump_rb *rb;
2255
2256 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2257 DMA_FROM_DEVICE);
2258
2259 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2260
2261 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2262 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2263 rb = (void *)(*data)->data;
2264 rb->index = cpu_to_le32(i);
2265 memcpy(rb->data, page_address(rxb->page), max_len);
2266 /* remap the page for the free benefit */
2267 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2268 max_len,
2269 DMA_FROM_DEVICE);
2270
2271 *data = iwl_fw_error_next_data(*data);
2272 }
2273
2274 spin_unlock(&rxq->lock);
2275
2276 return rb_len;
2277 }
2278 #define IWL_CSR_TO_DUMP (0x250)
2279
2280 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2281 struct iwl_fw_error_dump_data **data)
2282 {
2283 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2284 __le32 *val;
2285 int i;
2286
2287 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2288 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2289 val = (void *)(*data)->data;
2290
2291 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2292 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2293
2294 *data = iwl_fw_error_next_data(*data);
2295
2296 return csr_len;
2297 }
2298
2299 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2300 struct iwl_fw_error_dump_data **data)
2301 {
2302 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2303 unsigned long flags;
2304 __le32 *val;
2305 int i;
2306
2307 if (!iwl_trans_grab_nic_access(trans, &flags))
2308 return 0;
2309
2310 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2311 (*data)->len = cpu_to_le32(fh_regs_len);
2312 val = (void *)(*data)->data;
2313
2314 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2315 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2316
2317 iwl_trans_release_nic_access(trans, &flags);
2318
2319 *data = iwl_fw_error_next_data(*data);
2320
2321 return sizeof(**data) + fh_regs_len;
2322 }
2323
2324 static u32
2325 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2326 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2327 u32 monitor_len)
2328 {
2329 u32 buf_size_in_dwords = (monitor_len >> 2);
2330 u32 *buffer = (u32 *)fw_mon_data->data;
2331 unsigned long flags;
2332 u32 i;
2333
2334 if (!iwl_trans_grab_nic_access(trans, &flags))
2335 return 0;
2336
2337 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2338 for (i = 0; i < buf_size_in_dwords; i++)
2339 buffer[i] = iwl_read_prph_no_grab(trans,
2340 MON_DMARB_RD_DATA_ADDR);
2341 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2342
2343 iwl_trans_release_nic_access(trans, &flags);
2344
2345 return monitor_len;
2346 }
2347
2348 static u32
2349 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2350 struct iwl_fw_error_dump_data **data,
2351 u32 monitor_len)
2352 {
2353 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2354 u32 len = 0;
2355
2356 if ((trans_pcie->fw_mon_page &&
2357 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2358 trans->dbg_dest_tlv) {
2359 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2360 u32 base, write_ptr, wrap_cnt;
2361
2362 /* If there was a dest TLV - use the values from there */
2363 if (trans->dbg_dest_tlv) {
2364 write_ptr =
2365 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2366 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2367 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2368 } else {
2369 base = MON_BUFF_BASE_ADDR;
2370 write_ptr = MON_BUFF_WRPTR;
2371 wrap_cnt = MON_BUFF_CYCLE_CNT;
2372 }
2373
2374 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2375 fw_mon_data = (void *)(*data)->data;
2376 fw_mon_data->fw_mon_wr_ptr =
2377 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2378 fw_mon_data->fw_mon_cycle_cnt =
2379 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2380 fw_mon_data->fw_mon_base_ptr =
2381 cpu_to_le32(iwl_read_prph(trans, base));
2382
2383 len += sizeof(**data) + sizeof(*fw_mon_data);
2384 if (trans_pcie->fw_mon_page) {
2385 /*
2386 * The firmware is now asserted, it won't write anything
2387 * to the buffer. CPU can take ownership to fetch the
2388 * data. The buffer will be handed back to the device
2389 * before the firmware will be restarted.
2390 */
2391 dma_sync_single_for_cpu(trans->dev,
2392 trans_pcie->fw_mon_phys,
2393 trans_pcie->fw_mon_size,
2394 DMA_FROM_DEVICE);
2395 memcpy(fw_mon_data->data,
2396 page_address(trans_pcie->fw_mon_page),
2397 trans_pcie->fw_mon_size);
2398
2399 monitor_len = trans_pcie->fw_mon_size;
2400 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2401 /*
2402 * Update pointers to reflect actual values after
2403 * shifting
2404 */
2405 base = iwl_read_prph(trans, base) <<
2406 trans->dbg_dest_tlv->base_shift;
2407 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2408 monitor_len / sizeof(u32));
2409 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2410 monitor_len =
2411 iwl_trans_pci_dump_marbh_monitor(trans,
2412 fw_mon_data,
2413 monitor_len);
2414 } else {
2415 /* Didn't match anything - output no monitor data */
2416 monitor_len = 0;
2417 }
2418
2419 len += monitor_len;
2420 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2421 }
2422
2423 return len;
2424 }
2425
2426 static struct iwl_trans_dump_data
2427 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
2428 const struct iwl_fw_dbg_trigger_tlv *trigger)
2429 {
2430 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2431 struct iwl_fw_error_dump_data *data;
2432 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2433 struct iwl_fw_error_dump_txcmd *txcmd;
2434 struct iwl_trans_dump_data *dump_data;
2435 u32 len, num_rbs;
2436 u32 monitor_len;
2437 int i, ptr;
2438 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2439 !trans->cfg->mq_rx_supported;
2440
2441 /* transport dump header */
2442 len = sizeof(*dump_data);
2443
2444 /* host commands */
2445 len += sizeof(*data) +
2446 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2447
2448 /* FW monitor */
2449 if (trans_pcie->fw_mon_page) {
2450 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2451 trans_pcie->fw_mon_size;
2452 monitor_len = trans_pcie->fw_mon_size;
2453 } else if (trans->dbg_dest_tlv) {
2454 u32 base, end;
2455
2456 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2457 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2458
2459 base = iwl_read_prph(trans, base) <<
2460 trans->dbg_dest_tlv->base_shift;
2461 end = iwl_read_prph(trans, end) <<
2462 trans->dbg_dest_tlv->end_shift;
2463
2464 /* Make "end" point to the actual end */
2465 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2466 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2467 end += (1 << trans->dbg_dest_tlv->end_shift);
2468 monitor_len = end - base;
2469 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2470 monitor_len;
2471 } else {
2472 monitor_len = 0;
2473 }
2474
2475 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2476 dump_data = vzalloc(len);
2477 if (!dump_data)
2478 return NULL;
2479
2480 data = (void *)dump_data->data;
2481 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2482 dump_data->len = len;
2483
2484 return dump_data;
2485 }
2486
2487 /* CSR registers */
2488 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2489
2490 /* FH registers */
2491 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2492
2493 if (dump_rbs) {
2494 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2495 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2496 /* RBs */
2497 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num))
2498 & 0x0FFF;
2499 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
2500 len += num_rbs * (sizeof(*data) +
2501 sizeof(struct iwl_fw_error_dump_rb) +
2502 (PAGE_SIZE << trans_pcie->rx_page_order));
2503 }
2504
2505 dump_data = vzalloc(len);
2506 if (!dump_data)
2507 return NULL;
2508
2509 len = 0;
2510 data = (void *)dump_data->data;
2511 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2512 txcmd = (void *)data->data;
2513 spin_lock_bh(&cmdq->lock);
2514 ptr = cmdq->q.write_ptr;
2515 for (i = 0; i < cmdq->q.n_window; i++) {
2516 u8 idx = get_cmd_index(&cmdq->q, ptr);
2517 u32 caplen, cmdlen;
2518
2519 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2520 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2521
2522 if (cmdlen) {
2523 len += sizeof(*txcmd) + caplen;
2524 txcmd->cmdlen = cpu_to_le32(cmdlen);
2525 txcmd->caplen = cpu_to_le32(caplen);
2526 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2527 txcmd = (void *)((u8 *)txcmd->data + caplen);
2528 }
2529
2530 ptr = iwl_queue_dec_wrap(ptr);
2531 }
2532 spin_unlock_bh(&cmdq->lock);
2533
2534 data->len = cpu_to_le32(len);
2535 len += sizeof(*data);
2536 data = iwl_fw_error_next_data(data);
2537
2538 len += iwl_trans_pcie_dump_csr(trans, &data);
2539 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2540 if (dump_rbs)
2541 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
2542
2543 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2544
2545 dump_data->len = len;
2546
2547 return dump_data;
2548 }
2549
2550 #ifdef CONFIG_PM_SLEEP
2551 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
2552 {
2553 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2554 return iwl_pci_fw_enter_d0i3(trans);
2555
2556 return 0;
2557 }
2558
2559 static void iwl_trans_pcie_resume(struct iwl_trans *trans)
2560 {
2561 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2562 iwl_pci_fw_exit_d0i3(trans);
2563 }
2564 #endif /* CONFIG_PM_SLEEP */
2565
2566 static const struct iwl_trans_ops trans_ops_pcie = {
2567 .start_hw = iwl_trans_pcie_start_hw,
2568 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2569 .fw_alive = iwl_trans_pcie_fw_alive,
2570 .start_fw = iwl_trans_pcie_start_fw,
2571 .stop_device = iwl_trans_pcie_stop_device,
2572
2573 .d3_suspend = iwl_trans_pcie_d3_suspend,
2574 .d3_resume = iwl_trans_pcie_d3_resume,
2575
2576 #ifdef CONFIG_PM_SLEEP
2577 .suspend = iwl_trans_pcie_suspend,
2578 .resume = iwl_trans_pcie_resume,
2579 #endif /* CONFIG_PM_SLEEP */
2580
2581 .send_cmd = iwl_trans_pcie_send_hcmd,
2582
2583 .tx = iwl_trans_pcie_tx,
2584 .reclaim = iwl_trans_pcie_reclaim,
2585
2586 .txq_disable = iwl_trans_pcie_txq_disable,
2587 .txq_enable = iwl_trans_pcie_txq_enable,
2588
2589 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2590 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2591 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
2592
2593 .write8 = iwl_trans_pcie_write8,
2594 .write32 = iwl_trans_pcie_write32,
2595 .read32 = iwl_trans_pcie_read32,
2596 .read_prph = iwl_trans_pcie_read_prph,
2597 .write_prph = iwl_trans_pcie_write_prph,
2598 .read_mem = iwl_trans_pcie_read_mem,
2599 .write_mem = iwl_trans_pcie_write_mem,
2600 .configure = iwl_trans_pcie_configure,
2601 .set_pmi = iwl_trans_pcie_set_pmi,
2602 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2603 .release_nic_access = iwl_trans_pcie_release_nic_access,
2604 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2605
2606 .ref = iwl_trans_pcie_ref,
2607 .unref = iwl_trans_pcie_unref,
2608
2609 .dump_data = iwl_trans_pcie_dump_data,
2610 };
2611
2612 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2613 const struct pci_device_id *ent,
2614 const struct iwl_cfg *cfg)
2615 {
2616 struct iwl_trans_pcie *trans_pcie;
2617 struct iwl_trans *trans;
2618 u16 pci_cmd;
2619 int ret, addr_size;
2620
2621 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2622 &pdev->dev, cfg, &trans_ops_pcie, 0);
2623 if (!trans)
2624 return ERR_PTR(-ENOMEM);
2625
2626 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS;
2627
2628 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2629
2630 trans_pcie->trans = trans;
2631 spin_lock_init(&trans_pcie->irq_lock);
2632 spin_lock_init(&trans_pcie->reg_lock);
2633 spin_lock_init(&trans_pcie->ref_lock);
2634 mutex_init(&trans_pcie->mutex);
2635 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2636 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
2637 if (!trans_pcie->tso_hdr_page) {
2638 ret = -ENOMEM;
2639 goto out_no_pci;
2640 }
2641
2642 ret = pci_enable_device(pdev);
2643 if (ret)
2644 goto out_no_pci;
2645
2646 if (!cfg->base_params->pcie_l1_allowed) {
2647 /*
2648 * W/A - seems to solve weird behavior. We need to remove this
2649 * if we don't want to stay in L1 all the time. This wastes a
2650 * lot of power.
2651 */
2652 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2653 PCIE_LINK_STATE_L1 |
2654 PCIE_LINK_STATE_CLKPM);
2655 }
2656
2657 if (cfg->mq_rx_supported)
2658 addr_size = 64;
2659 else
2660 addr_size = 36;
2661
2662 pci_set_master(pdev);
2663
2664 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
2665 if (!ret)
2666 ret = pci_set_consistent_dma_mask(pdev,
2667 DMA_BIT_MASK(addr_size));
2668 if (ret) {
2669 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2670 if (!ret)
2671 ret = pci_set_consistent_dma_mask(pdev,
2672 DMA_BIT_MASK(32));
2673 /* both attempts failed: */
2674 if (ret) {
2675 dev_err(&pdev->dev, "No suitable DMA available\n");
2676 goto out_pci_disable_device;
2677 }
2678 }
2679
2680 ret = pci_request_regions(pdev, DRV_NAME);
2681 if (ret) {
2682 dev_err(&pdev->dev, "pci_request_regions failed\n");
2683 goto out_pci_disable_device;
2684 }
2685
2686 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2687 if (!trans_pcie->hw_base) {
2688 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2689 ret = -ENODEV;
2690 goto out_pci_release_regions;
2691 }
2692
2693 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2694 * PCI Tx retries from interfering with C3 CPU state */
2695 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2696
2697 trans->dev = &pdev->dev;
2698 trans_pcie->pci_dev = pdev;
2699 iwl_disable_interrupts(trans);
2700
2701 ret = pci_enable_msi(pdev);
2702 if (ret) {
2703 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", ret);
2704 /* enable rfkill interrupt: hw bug w/a */
2705 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2706 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2707 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2708 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2709 }
2710 }
2711
2712 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2713 /*
2714 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2715 * changed, and now the revision step also includes bit 0-1 (no more
2716 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2717 * in the old format.
2718 */
2719 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2720 unsigned long flags;
2721
2722 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2723 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2724
2725 ret = iwl_pcie_prepare_card_hw(trans);
2726 if (ret) {
2727 IWL_WARN(trans, "Exit HW not ready\n");
2728 goto out_pci_disable_msi;
2729 }
2730
2731 /*
2732 * in-order to recognize C step driver should read chip version
2733 * id located at the AUX bus MISC address space.
2734 */
2735 iwl_set_bit(trans, CSR_GP_CNTRL,
2736 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2737 udelay(2);
2738
2739 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2740 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2741 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2742 25000);
2743 if (ret < 0) {
2744 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2745 goto out_pci_disable_msi;
2746 }
2747
2748 if (iwl_trans_grab_nic_access(trans, &flags)) {
2749 u32 hw_step;
2750
2751 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
2752 hw_step |= ENABLE_WFPM;
2753 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
2754 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
2755 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2756 if (hw_step == 0x3)
2757 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2758 (SILICON_C_STEP << 2);
2759 iwl_trans_release_nic_access(trans, &flags);
2760 }
2761 }
2762
2763 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2764 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2765 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2766
2767 /* Initialize the wait queue for commands */
2768 init_waitqueue_head(&trans_pcie->wait_command_queue);
2769
2770 init_waitqueue_head(&trans_pcie->d0i3_waitq);
2771
2772 ret = iwl_pcie_alloc_ict(trans);
2773 if (ret)
2774 goto out_pci_disable_msi;
2775
2776 ret = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2777 iwl_pcie_irq_handler,
2778 IRQF_SHARED, DRV_NAME, trans);
2779 if (ret) {
2780 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2781 goto out_free_ict;
2782 }
2783
2784 trans_pcie->inta_mask = CSR_INI_SET_MASK;
2785
2786 #ifdef CONFIG_IWLWIFI_PCIE_RTPM
2787 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
2788 #else
2789 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
2790 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */
2791
2792 return trans;
2793
2794 out_free_ict:
2795 iwl_pcie_free_ict(trans);
2796 out_pci_disable_msi:
2797 pci_disable_msi(pdev);
2798 out_pci_release_regions:
2799 pci_release_regions(pdev);
2800 out_pci_disable_device:
2801 pci_disable_device(pdev);
2802 out_no_pci:
2803 free_percpu(trans_pcie->tso_hdr_page);
2804 iwl_trans_free(trans);
2805 return ERR_PTR(ret);
2806 }
Ubuntu Artful kernel mirror