1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
26 * The full GNU General Public License is included in this distribution
27 * in the file called COPYING.
29 * Contact Information:
30 * Intel Linux Wireless <linuxwifi@intel.com>
31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
37 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
38 * All rights reserved.
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
44 * * Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
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47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
50 * * Neither the name Intel Corporation nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific prior written permission.
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 *****************************************************************************/
67 #include <linux/pci.h>
68 #include <linux/pci-aspm.h>
69 #include <linux/interrupt.h>
70 #include <linux/debugfs.h>
71 #include <linux/sched.h>
72 #include <linux/bitops.h>
73 #include <linux/gfp.h>
74 #include <linux/vmalloc.h>
75 #include <linux/pm_runtime.h>
78 #include "iwl-trans.h"
82 #include "iwl-agn-hw.h"
83 #include "fw/error-dump.h"
87 /* extended range in FW SRAM */
88 #define IWL_FW_MEM_EXTENDED_START 0x40000
89 #define IWL_FW_MEM_EXTENDED_END 0x57FFF
91 static void iwl_pcie_free_fw_monitor(struct iwl_trans
*trans
)
93 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
95 if (!trans_pcie
->fw_mon_page
)
98 dma_unmap_page(trans
->dev
, trans_pcie
->fw_mon_phys
,
99 trans_pcie
->fw_mon_size
, DMA_FROM_DEVICE
);
100 __free_pages(trans_pcie
->fw_mon_page
,
101 get_order(trans_pcie
->fw_mon_size
));
102 trans_pcie
->fw_mon_page
= NULL
;
103 trans_pcie
->fw_mon_phys
= 0;
104 trans_pcie
->fw_mon_size
= 0;
107 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans
*trans
, u8 max_power
)
109 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
110 struct page
*page
= NULL
;
116 /* default max_power is maximum */
122 if (WARN(max_power
> 26,
123 "External buffer size for monitor is too big %d, check the FW TLV\n",
127 if (trans_pcie
->fw_mon_page
) {
128 dma_sync_single_for_device(trans
->dev
, trans_pcie
->fw_mon_phys
,
129 trans_pcie
->fw_mon_size
,
135 for (power
= max_power
; power
>= 11; power
--) {
139 order
= get_order(size
);
140 page
= alloc_pages(__GFP_COMP
| __GFP_NOWARN
| __GFP_ZERO
,
145 phys
= dma_map_page(trans
->dev
, page
, 0, PAGE_SIZE
<< order
,
147 if (dma_mapping_error(trans
->dev
, phys
)) {
148 __free_pages(page
, order
);
153 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
158 if (WARN_ON_ONCE(!page
))
161 if (power
!= max_power
)
163 "Sorry - debug buffer is only %luK while you requested %luK\n",
164 (unsigned long)BIT(power
- 10),
165 (unsigned long)BIT(max_power
- 10));
167 trans_pcie
->fw_mon_page
= page
;
168 trans_pcie
->fw_mon_phys
= phys
;
169 trans_pcie
->fw_mon_size
= size
;
172 static u32
iwl_trans_pcie_read_shr(struct iwl_trans
*trans
, u32 reg
)
174 iwl_write32(trans
, HEEP_CTRL_WRD_PCIEX_CTRL_REG
,
175 ((reg
& 0x0000ffff) | (2 << 28)));
176 return iwl_read32(trans
, HEEP_CTRL_WRD_PCIEX_DATA_REG
);
179 static void iwl_trans_pcie_write_shr(struct iwl_trans
*trans
, u32 reg
, u32 val
)
181 iwl_write32(trans
, HEEP_CTRL_WRD_PCIEX_DATA_REG
, val
);
182 iwl_write32(trans
, HEEP_CTRL_WRD_PCIEX_CTRL_REG
,
183 ((reg
& 0x0000ffff) | (3 << 28)));
186 static void iwl_pcie_set_pwr(struct iwl_trans
*trans
, bool vaux
)
188 if (trans
->cfg
->apmg_not_supported
)
191 if (vaux
&& pci_pme_capable(to_pci_dev(trans
->dev
), PCI_D3cold
))
192 iwl_set_bits_mask_prph(trans
, APMG_PS_CTRL_REG
,
193 APMG_PS_CTRL_VAL_PWR_SRC_VAUX
,
194 ~APMG_PS_CTRL_MSK_PWR_SRC
);
196 iwl_set_bits_mask_prph(trans
, APMG_PS_CTRL_REG
,
197 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
,
198 ~APMG_PS_CTRL_MSK_PWR_SRC
);
202 #define PCI_CFG_RETRY_TIMEOUT 0x041
204 void iwl_pcie_apm_config(struct iwl_trans
*trans
)
206 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
211 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
212 * Check if BIOS (or OS) enabled L1-ASPM on this device.
213 * If so (likely), disable L0S, so device moves directly L0->L1;
214 * costs negligible amount of power savings.
215 * If not (unlikely), enable L0S, so there is at least some
216 * power savings, even without L1.
218 pcie_capability_read_word(trans_pcie
->pci_dev
, PCI_EXP_LNKCTL
, &lctl
);
219 if (lctl
& PCI_EXP_LNKCTL_ASPM_L1
)
220 iwl_set_bit(trans
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
222 iwl_clear_bit(trans
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
223 trans
->pm_support
= !(lctl
& PCI_EXP_LNKCTL_ASPM_L0S
);
225 pcie_capability_read_word(trans_pcie
->pci_dev
, PCI_EXP_DEVCTL2
, &cap
);
226 trans
->ltr_enabled
= cap
& PCI_EXP_DEVCTL2_LTR_EN
;
227 IWL_DEBUG_POWER(trans
, "L1 %sabled - LTR %sabled\n",
228 (lctl
& PCI_EXP_LNKCTL_ASPM_L1
) ? "En" : "Dis",
229 trans
->ltr_enabled
? "En" : "Dis");
233 * Start up NIC's basic functionality after it has been reset
234 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
235 * NOTE: This does not load uCode nor start the embedded processor
237 static int iwl_pcie_apm_init(struct iwl_trans
*trans
)
241 IWL_DEBUG_INFO(trans
, "Init card's basic functions\n");
244 * Use "set_bit" below rather than "write", to preserve any hardware
245 * bits already set by default after reset.
248 /* Disable L0S exit timer (platform NMI Work/Around) */
249 if (trans
->cfg
->device_family
< IWL_DEVICE_FAMILY_8000
)
250 iwl_set_bit(trans
, CSR_GIO_CHICKEN_BITS
,
251 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER
);
254 * Disable L0s without affecting L1;
255 * don't wait for ICH L0s (ICH bug W/A)
257 iwl_set_bit(trans
, CSR_GIO_CHICKEN_BITS
,
258 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX
);
260 /* Set FH wait threshold to maximum (HW error during stress W/A) */
261 iwl_set_bit(trans
, CSR_DBG_HPET_MEM_REG
, CSR_DBG_HPET_MEM_REG_VAL
);
264 * Enable HAP INTA (interrupt from management bus) to
265 * wake device's PCI Express link L1a -> L0s
267 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
268 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A
);
270 iwl_pcie_apm_config(trans
);
272 /* Configure analog phase-lock-loop before activating to D0A */
273 if (trans
->cfg
->base_params
->pll_cfg
)
274 iwl_set_bit(trans
, CSR_ANA_PLL_CFG
, CSR50_ANA_PLL_CFG_VAL
);
277 * Set "initialization complete" bit to move adapter from
278 * D0U* --> D0A* (powered-up active) state.
280 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
283 * Wait for clock stabilization; once stabilized, access to
284 * device-internal resources is supported, e.g. iwl_write_prph()
285 * and accesses to uCode SRAM.
287 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
289 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
, 25000);
291 IWL_ERR(trans
, "Failed to init the card\n");
295 if (trans
->cfg
->host_interrupt_operation_mode
) {
297 * This is a bit of an abuse - This is needed for 7260 / 3160
298 * only check host_interrupt_operation_mode even if this is
299 * not related to host_interrupt_operation_mode.
301 * Enable the oscillator to count wake up time for L1 exit. This
302 * consumes slightly more power (100uA) - but allows to be sure
303 * that we wake up from L1 on time.
305 * This looks weird: read twice the same register, discard the
306 * value, set a bit, and yet again, read that same register
307 * just to discard the value. But that's the way the hardware
310 iwl_read_prph(trans
, OSC_CLK
);
311 iwl_read_prph(trans
, OSC_CLK
);
312 iwl_set_bits_prph(trans
, OSC_CLK
, OSC_CLK_FORCE_CONTROL
);
313 iwl_read_prph(trans
, OSC_CLK
);
314 iwl_read_prph(trans
, OSC_CLK
);
318 * Enable DMA clock and wait for it to stabilize.
320 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
321 * bits do not disable clocks. This preserves any hardware
322 * bits already set by default in "CLK_CTRL_REG" after reset.
324 if (!trans
->cfg
->apmg_not_supported
) {
325 iwl_write_prph(trans
, APMG_CLK_EN_REG
,
326 APMG_CLK_VAL_DMA_CLK_RQT
);
329 /* Disable L1-Active */
330 iwl_set_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
331 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
333 /* Clear the interrupt in APMG if the NIC is in RFKILL */
334 iwl_write_prph(trans
, APMG_RTC_INT_STT_REG
,
335 APMG_RTC_INT_STT_RFKILL
);
338 set_bit(STATUS_DEVICE_ENABLED
, &trans
->status
);
344 * Enable LP XTAL to avoid HW bug where device may consume much power if
345 * FW is not loaded after device reset. LP XTAL is disabled by default
346 * after device HW reset. Do it only if XTAL is fed by internal source.
347 * Configure device's "persistence" mode to avoid resetting XTAL again when
348 * SHRD_HW_RST occurs in S3.
350 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans
*trans
)
354 u32 apmg_xtal_cfg_reg
;
358 __iwl_trans_pcie_set_bit(trans
, CSR_GP_CNTRL
,
359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON
);
361 iwl_pcie_sw_reset(trans
);
364 * Set "initialization complete" bit to move adapter from
365 * D0U* --> D0A* (powered-up active) state.
367 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
370 * Wait for clock stabilization; once stabilized, access to
371 * device-internal resources is possible.
373 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
374 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
375 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
377 if (WARN_ON(ret
< 0)) {
378 IWL_ERR(trans
, "Access time out - failed to enable LP XTAL\n");
379 /* Release XTAL ON request */
380 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
381 CSR_GP_CNTRL_REG_FLAG_XTAL_ON
);
386 * Clear "disable persistence" to avoid LP XTAL resetting when
387 * SHRD_HW_RST is applied in S3.
389 iwl_clear_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
390 APMG_PCIDEV_STT_VAL_PERSIST_DIS
);
393 * Force APMG XTAL to be active to prevent its disabling by HW
394 * caused by APMG idle state.
396 apmg_xtal_cfg_reg
= iwl_trans_pcie_read_shr(trans
,
397 SHR_APMG_XTAL_CFG_REG
);
398 iwl_trans_pcie_write_shr(trans
, SHR_APMG_XTAL_CFG_REG
,
400 SHR_APMG_XTAL_CFG_XTAL_ON_REQ
);
402 iwl_pcie_sw_reset(trans
);
404 /* Enable LP XTAL by indirect access through CSR */
405 apmg_gp1_reg
= iwl_trans_pcie_read_shr(trans
, SHR_APMG_GP1_REG
);
406 iwl_trans_pcie_write_shr(trans
, SHR_APMG_GP1_REG
, apmg_gp1_reg
|
407 SHR_APMG_GP1_WF_XTAL_LP_EN
|
408 SHR_APMG_GP1_CHICKEN_BIT_SELECT
);
410 /* Clear delay line clock power up */
411 dl_cfg_reg
= iwl_trans_pcie_read_shr(trans
, SHR_APMG_DL_CFG_REG
);
412 iwl_trans_pcie_write_shr(trans
, SHR_APMG_DL_CFG_REG
, dl_cfg_reg
&
413 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP
);
416 * Enable persistence mode to avoid LP XTAL resetting when
417 * SHRD_HW_RST is applied in S3.
419 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
420 CSR_HW_IF_CONFIG_REG_PERSIST_MODE
);
423 * Clear "initialization complete" bit to move adapter from
424 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
426 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
427 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
429 /* Activates XTAL resources monitor */
430 __iwl_trans_pcie_set_bit(trans
, CSR_MONITOR_CFG_REG
,
431 CSR_MONITOR_XTAL_RESOURCES
);
433 /* Release XTAL ON request */
434 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
435 CSR_GP_CNTRL_REG_FLAG_XTAL_ON
);
438 /* Release APMG XTAL */
439 iwl_trans_pcie_write_shr(trans
, SHR_APMG_XTAL_CFG_REG
,
441 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ
);
444 void iwl_pcie_apm_stop_master(struct iwl_trans
*trans
)
448 /* stop device's busmaster DMA activity */
449 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_STOP_MASTER
);
451 ret
= iwl_poll_bit(trans
, CSR_RESET
,
452 CSR_RESET_REG_FLAG_MASTER_DISABLED
,
453 CSR_RESET_REG_FLAG_MASTER_DISABLED
, 100);
455 IWL_WARN(trans
, "Master Disable Timed Out, 100 usec\n");
457 IWL_DEBUG_INFO(trans
, "stop master\n");
460 static void iwl_pcie_apm_stop(struct iwl_trans
*trans
, bool op_mode_leave
)
462 IWL_DEBUG_INFO(trans
, "Stop card, put in low power state\n");
465 if (!test_bit(STATUS_DEVICE_ENABLED
, &trans
->status
))
466 iwl_pcie_apm_init(trans
);
468 /* inform ME that we are leaving */
469 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_7000
)
470 iwl_set_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
471 APMG_PCIDEV_STT_VAL_WAKE_ME
);
472 else if (trans
->cfg
->device_family
>= IWL_DEVICE_FAMILY_8000
) {
473 iwl_set_bit(trans
, CSR_DBG_LINK_PWR_MGMT_REG
,
474 CSR_RESET_LINK_PWR_MGMT_DISABLED
);
475 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
476 CSR_HW_IF_CONFIG_REG_PREPARE
|
477 CSR_HW_IF_CONFIG_REG_ENABLE_PME
);
479 iwl_clear_bit(trans
, CSR_DBG_LINK_PWR_MGMT_REG
,
480 CSR_RESET_LINK_PWR_MGMT_DISABLED
);
485 clear_bit(STATUS_DEVICE_ENABLED
, &trans
->status
);
487 /* Stop device's DMA activity */
488 iwl_pcie_apm_stop_master(trans
);
490 if (trans
->cfg
->lp_xtal_workaround
) {
491 iwl_pcie_apm_lp_xtal_enable(trans
);
495 iwl_pcie_sw_reset(trans
);
498 * Clear "initialization complete" bit to move adapter from
499 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
501 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
502 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
505 static int iwl_pcie_nic_init(struct iwl_trans
*trans
)
507 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
511 spin_lock(&trans_pcie
->irq_lock
);
512 ret
= iwl_pcie_apm_init(trans
);
513 spin_unlock(&trans_pcie
->irq_lock
);
518 iwl_pcie_set_pwr(trans
, false);
520 iwl_op_mode_nic_config(trans
->op_mode
);
522 /* Allocate the RX queue, or reset if it is already allocated */
523 iwl_pcie_rx_init(trans
);
525 /* Allocate or reset and init all Tx and Command queues */
526 if (iwl_pcie_tx_init(trans
))
529 if (trans
->cfg
->base_params
->shadow_reg_enable
) {
530 /* enable shadow regs in HW */
531 iwl_set_bit(trans
, CSR_MAC_SHADOW_REG_CTRL
, 0x800FFFFF);
532 IWL_DEBUG_INFO(trans
, "Enabling shadow registers in device\n");
538 #define HW_READY_TIMEOUT (50)
540 /* Note: returns poll_bit return value, which is >= 0 if success */
541 static int iwl_pcie_set_hw_ready(struct iwl_trans
*trans
)
545 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
546 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
);
548 /* See if we got it */
549 ret
= iwl_poll_bit(trans
, CSR_HW_IF_CONFIG_REG
,
550 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
551 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
555 iwl_set_bit(trans
, CSR_MBOX_SET_REG
, CSR_MBOX_SET_REG_OS_ALIVE
);
557 IWL_DEBUG_INFO(trans
, "hardware%s ready\n", ret
< 0 ? " not" : "");
561 /* Note: returns standard 0/-ERROR code */
562 int iwl_pcie_prepare_card_hw(struct iwl_trans
*trans
)
568 IWL_DEBUG_INFO(trans
, "iwl_trans_prepare_card_hw enter\n");
570 ret
= iwl_pcie_set_hw_ready(trans
);
571 /* If the card is ready, exit 0 */
575 iwl_set_bit(trans
, CSR_DBG_LINK_PWR_MGMT_REG
,
576 CSR_RESET_LINK_PWR_MGMT_DISABLED
);
577 usleep_range(1000, 2000);
579 for (iter
= 0; iter
< 10; iter
++) {
580 /* If HW is not ready, prepare the conditions to check again */
581 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
582 CSR_HW_IF_CONFIG_REG_PREPARE
);
585 ret
= iwl_pcie_set_hw_ready(trans
);
589 usleep_range(200, 1000);
591 } while (t
< 150000);
595 IWL_ERR(trans
, "Couldn't prepare the card\n");
603 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans
*trans
,
604 u32 dst_addr
, dma_addr_t phy_addr
,
607 iwl_write32(trans
, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
608 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE
);
610 iwl_write32(trans
, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL
),
613 iwl_write32(trans
, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL
),
614 phy_addr
& FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK
);
616 iwl_write32(trans
, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL
),
617 (iwl_get_dma_hi_addr(phy_addr
)
618 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT
) | byte_cnt
);
620 iwl_write32(trans
, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL
),
621 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM
) |
622 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX
) |
623 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID
);
625 iwl_write32(trans
, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
626 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
627 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE
|
628 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD
);
631 static int iwl_pcie_load_firmware_chunk(struct iwl_trans
*trans
,
632 u32 dst_addr
, dma_addr_t phy_addr
,
635 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
639 trans_pcie
->ucode_write_complete
= false;
641 if (!iwl_trans_grab_nic_access(trans
, &flags
))
644 iwl_pcie_load_firmware_chunk_fh(trans
, dst_addr
, phy_addr
,
646 iwl_trans_release_nic_access(trans
, &flags
);
648 ret
= wait_event_timeout(trans_pcie
->ucode_write_waitq
,
649 trans_pcie
->ucode_write_complete
, 5 * HZ
);
651 IWL_ERR(trans
, "Failed to load firmware chunk!\n");
658 static int iwl_pcie_load_section(struct iwl_trans
*trans
, u8 section_num
,
659 const struct fw_desc
*section
)
663 u32 offset
, chunk_sz
= min_t(u32
, FH_MEM_TB_MAX_LENGTH
, section
->len
);
666 IWL_DEBUG_FW(trans
, "[%d] uCode section being loaded...\n",
669 v_addr
= dma_alloc_coherent(trans
->dev
, chunk_sz
, &p_addr
,
670 GFP_KERNEL
| __GFP_NOWARN
);
672 IWL_DEBUG_INFO(trans
, "Falling back to small chunks of DMA\n");
673 chunk_sz
= PAGE_SIZE
;
674 v_addr
= dma_alloc_coherent(trans
->dev
, chunk_sz
,
675 &p_addr
, GFP_KERNEL
);
680 for (offset
= 0; offset
< section
->len
; offset
+= chunk_sz
) {
681 u32 copy_size
, dst_addr
;
682 bool extended_addr
= false;
684 copy_size
= min_t(u32
, chunk_sz
, section
->len
- offset
);
685 dst_addr
= section
->offset
+ offset
;
687 if (dst_addr
>= IWL_FW_MEM_EXTENDED_START
&&
688 dst_addr
<= IWL_FW_MEM_EXTENDED_END
)
689 extended_addr
= true;
692 iwl_set_bits_prph(trans
, LMPM_CHICK
,
693 LMPM_CHICK_EXTENDED_ADDR_SPACE
);
695 memcpy(v_addr
, (u8
*)section
->data
+ offset
, copy_size
);
696 ret
= iwl_pcie_load_firmware_chunk(trans
, dst_addr
, p_addr
,
700 iwl_clear_bits_prph(trans
, LMPM_CHICK
,
701 LMPM_CHICK_EXTENDED_ADDR_SPACE
);
705 "Could not load the [%d] uCode section\n",
711 dma_free_coherent(trans
->dev
, chunk_sz
, v_addr
, p_addr
);
715 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans
*trans
,
716 const struct fw_img
*image
,
718 int *first_ucode_section
)
721 int i
, ret
= 0, sec_num
= 0x1;
722 u32 val
, last_read_idx
= 0;
726 *first_ucode_section
= 0;
729 (*first_ucode_section
)++;
732 for (i
= *first_ucode_section
; i
< image
->num_sec
; i
++) {
736 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
738 * PAGING_SEPARATOR_SECTION delimiter - separate between
739 * CPU2 non paged to CPU2 paging sec.
741 if (!image
->sec
[i
].data
||
742 image
->sec
[i
].offset
== CPU1_CPU2_SEPARATOR_SECTION
||
743 image
->sec
[i
].offset
== PAGING_SEPARATOR_SECTION
) {
745 "Break since Data not valid or Empty section, sec = %d\n",
750 ret
= iwl_pcie_load_section(trans
, i
, &image
->sec
[i
]);
754 /* Notify ucode of loaded section number and status */
755 val
= iwl_read_direct32(trans
, FH_UCODE_LOAD_STATUS
);
756 val
= val
| (sec_num
<< shift_param
);
757 iwl_write_direct32(trans
, FH_UCODE_LOAD_STATUS
, val
);
759 sec_num
= (sec_num
<< 1) | 0x1;
762 *first_ucode_section
= last_read_idx
;
764 iwl_enable_interrupts(trans
);
766 if (trans
->cfg
->use_tfh
) {
768 iwl_write_prph(trans
, UREG_UCODE_LOAD_STATUS
,
771 iwl_write_prph(trans
, UREG_UCODE_LOAD_STATUS
,
775 iwl_write_direct32(trans
, FH_UCODE_LOAD_STATUS
,
778 iwl_write_direct32(trans
, FH_UCODE_LOAD_STATUS
,
785 static int iwl_pcie_load_cpu_sections(struct iwl_trans
*trans
,
786 const struct fw_img
*image
,
788 int *first_ucode_section
)
791 u32 last_read_idx
= 0;
794 *first_ucode_section
= 0;
796 (*first_ucode_section
)++;
798 for (i
= *first_ucode_section
; i
< image
->num_sec
; i
++) {
802 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
804 * PAGING_SEPARATOR_SECTION delimiter - separate between
805 * CPU2 non paged to CPU2 paging sec.
807 if (!image
->sec
[i
].data
||
808 image
->sec
[i
].offset
== CPU1_CPU2_SEPARATOR_SECTION
||
809 image
->sec
[i
].offset
== PAGING_SEPARATOR_SECTION
) {
811 "Break since Data not valid or Empty section, sec = %d\n",
816 ret
= iwl_pcie_load_section(trans
, i
, &image
->sec
[i
]);
821 *first_ucode_section
= last_read_idx
;
826 void iwl_pcie_apply_destination(struct iwl_trans
*trans
)
828 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
829 const struct iwl_fw_dbg_dest_tlv
*dest
= trans
->dbg_dest_tlv
;
834 "DBG DEST version is %d - expect issues\n",
837 IWL_INFO(trans
, "Applying debug destination %s\n",
838 get_fw_dbg_mode_string(dest
->monitor_mode
));
840 if (dest
->monitor_mode
== EXTERNAL_MODE
)
841 iwl_pcie_alloc_fw_monitor(trans
, dest
->size_power
);
843 IWL_WARN(trans
, "PCI should have external buffer debug\n");
845 for (i
= 0; i
< trans
->dbg_dest_reg_num
; i
++) {
846 u32 addr
= le32_to_cpu(dest
->reg_ops
[i
].addr
);
847 u32 val
= le32_to_cpu(dest
->reg_ops
[i
].val
);
849 switch (dest
->reg_ops
[i
].op
) {
851 iwl_write32(trans
, addr
, val
);
854 iwl_set_bit(trans
, addr
, BIT(val
));
857 iwl_clear_bit(trans
, addr
, BIT(val
));
860 iwl_write_prph(trans
, addr
, val
);
863 iwl_set_bits_prph(trans
, addr
, BIT(val
));
866 iwl_clear_bits_prph(trans
, addr
, BIT(val
));
869 if (iwl_read_prph(trans
, addr
) & BIT(val
)) {
871 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
877 IWL_ERR(trans
, "FW debug - unknown OP %d\n",
878 dest
->reg_ops
[i
].op
);
884 if (dest
->monitor_mode
== EXTERNAL_MODE
&& trans_pcie
->fw_mon_size
) {
885 iwl_write_prph(trans
, le32_to_cpu(dest
->base_reg
),
886 trans_pcie
->fw_mon_phys
>> dest
->base_shift
);
887 if (trans
->cfg
->device_family
>= IWL_DEVICE_FAMILY_8000
)
888 iwl_write_prph(trans
, le32_to_cpu(dest
->end_reg
),
889 (trans_pcie
->fw_mon_phys
+
890 trans_pcie
->fw_mon_size
- 256) >>
893 iwl_write_prph(trans
, le32_to_cpu(dest
->end_reg
),
894 (trans_pcie
->fw_mon_phys
+
895 trans_pcie
->fw_mon_size
) >>
900 static int iwl_pcie_load_given_ucode(struct iwl_trans
*trans
,
901 const struct fw_img
*image
)
903 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
905 int first_ucode_section
;
907 IWL_DEBUG_FW(trans
, "working with %s CPU\n",
908 image
->is_dual_cpus
? "Dual" : "Single");
910 /* load to FW the binary non secured sections of CPU1 */
911 ret
= iwl_pcie_load_cpu_sections(trans
, image
, 1, &first_ucode_section
);
915 if (image
->is_dual_cpus
) {
916 /* set CPU2 header address */
917 iwl_write_prph(trans
,
918 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR
,
919 LMPM_SECURE_CPU2_HDR_MEM_SPACE
);
921 /* load to FW the binary sections of CPU2 */
922 ret
= iwl_pcie_load_cpu_sections(trans
, image
, 2,
923 &first_ucode_section
);
928 /* supported for 7000 only for the moment */
929 if (iwlwifi_mod_params
.fw_monitor
&&
930 trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_7000
) {
931 iwl_pcie_alloc_fw_monitor(trans
, 0);
933 if (trans_pcie
->fw_mon_size
) {
934 iwl_write_prph(trans
, MON_BUFF_BASE_ADDR
,
935 trans_pcie
->fw_mon_phys
>> 4);
936 iwl_write_prph(trans
, MON_BUFF_END_ADDR
,
937 (trans_pcie
->fw_mon_phys
+
938 trans_pcie
->fw_mon_size
) >> 4);
940 } else if (trans
->dbg_dest_tlv
) {
941 iwl_pcie_apply_destination(trans
);
944 iwl_enable_interrupts(trans
);
946 /* release CPU reset */
947 iwl_write32(trans
, CSR_RESET
, 0);
952 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans
*trans
,
953 const struct fw_img
*image
)
956 int first_ucode_section
;
958 IWL_DEBUG_FW(trans
, "working with %s CPU\n",
959 image
->is_dual_cpus
? "Dual" : "Single");
961 if (trans
->dbg_dest_tlv
)
962 iwl_pcie_apply_destination(trans
);
964 IWL_DEBUG_POWER(trans
, "Original WFPM value = 0x%08X\n",
965 iwl_read_prph(trans
, WFPM_GP2
));
968 * Set default value. On resume reading the values that were
969 * zeored can provide debug data on the resume flow.
970 * This is for debugging only and has no functional impact.
972 iwl_write_prph(trans
, WFPM_GP2
, 0x01010101);
974 /* configure the ucode to be ready to get the secured image */
975 /* release CPU reset */
976 iwl_write_prph(trans
, RELEASE_CPU_RESET
, RELEASE_CPU_RESET_BIT
);
978 /* load to FW the binary Secured sections of CPU1 */
979 ret
= iwl_pcie_load_cpu_sections_8000(trans
, image
, 1,
980 &first_ucode_section
);
984 /* load to FW the binary sections of CPU2 */
985 return iwl_pcie_load_cpu_sections_8000(trans
, image
, 2,
986 &first_ucode_section
);
989 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans
*trans
)
991 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
992 bool hw_rfkill
= iwl_is_rfkill_set(trans
);
993 bool prev
= test_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
997 set_bit(STATUS_RFKILL_HW
, &trans
->status
);
998 set_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1000 clear_bit(STATUS_RFKILL_HW
, &trans
->status
);
1001 if (trans_pcie
->opmode_down
)
1002 clear_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1005 report
= test_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1008 iwl_trans_pcie_rf_kill(trans
, report
);
1013 struct iwl_causes_list
{
1019 static struct iwl_causes_list causes_list
[] = {
1020 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM
, CSR_MSIX_FH_INT_MASK_AD
, 0},
1021 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM
, CSR_MSIX_FH_INT_MASK_AD
, 0x1},
1022 {MSIX_FH_INT_CAUSES_S2D
, CSR_MSIX_FH_INT_MASK_AD
, 0x3},
1023 {MSIX_FH_INT_CAUSES_FH_ERR
, CSR_MSIX_FH_INT_MASK_AD
, 0x5},
1024 {MSIX_HW_INT_CAUSES_REG_ALIVE
, CSR_MSIX_HW_INT_MASK_AD
, 0x10},
1025 {MSIX_HW_INT_CAUSES_REG_WAKEUP
, CSR_MSIX_HW_INT_MASK_AD
, 0x11},
1026 {MSIX_HW_INT_CAUSES_REG_CT_KILL
, CSR_MSIX_HW_INT_MASK_AD
, 0x16},
1027 {MSIX_HW_INT_CAUSES_REG_RF_KILL
, CSR_MSIX_HW_INT_MASK_AD
, 0x17},
1028 {MSIX_HW_INT_CAUSES_REG_PERIODIC
, CSR_MSIX_HW_INT_MASK_AD
, 0x18},
1029 {MSIX_HW_INT_CAUSES_REG_SW_ERR
, CSR_MSIX_HW_INT_MASK_AD
, 0x29},
1030 {MSIX_HW_INT_CAUSES_REG_SCD
, CSR_MSIX_HW_INT_MASK_AD
, 0x2A},
1031 {MSIX_HW_INT_CAUSES_REG_FH_TX
, CSR_MSIX_HW_INT_MASK_AD
, 0x2B},
1032 {MSIX_HW_INT_CAUSES_REG_HW_ERR
, CSR_MSIX_HW_INT_MASK_AD
, 0x2D},
1033 {MSIX_HW_INT_CAUSES_REG_HAP
, CSR_MSIX_HW_INT_MASK_AD
, 0x2E},
1036 static void iwl_pcie_map_non_rx_causes(struct iwl_trans
*trans
)
1038 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1039 int val
= trans_pcie
->def_irq
| MSIX_NON_AUTO_CLEAR_CAUSE
;
1043 * Access all non RX causes and map them to the default irq.
1044 * In case we are missing at least one interrupt vector,
1045 * the first interrupt vector will serve non-RX and FBQ causes.
1047 for (i
= 0; i
< ARRAY_SIZE(causes_list
); i
++) {
1048 iwl_write8(trans
, CSR_MSIX_IVAR(causes_list
[i
].addr
), val
);
1049 iwl_clear_bit(trans
, causes_list
[i
].mask_reg
,
1050 causes_list
[i
].cause_num
);
1054 static void iwl_pcie_map_rx_causes(struct iwl_trans
*trans
)
1056 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1058 trans_pcie
->shared_vec_mask
& IWL_SHARED_IRQ_FIRST_RSS
? 1 : 0;
1062 * The first RX queue - fallback queue, which is designated for
1063 * management frame, command responses etc, is always mapped to the
1064 * first interrupt vector. The other RX queues are mapped to
1065 * the other (N - 2) interrupt vectors.
1067 val
= BIT(MSIX_FH_INT_CAUSES_Q(0));
1068 for (idx
= 1; idx
< trans
->num_rx_queues
; idx
++) {
1069 iwl_write8(trans
, CSR_MSIX_RX_IVAR(idx
),
1070 MSIX_FH_INT_CAUSES_Q(idx
- offset
));
1071 val
|= BIT(MSIX_FH_INT_CAUSES_Q(idx
));
1073 iwl_write32(trans
, CSR_MSIX_FH_INT_MASK_AD
, ~val
);
1075 val
= MSIX_FH_INT_CAUSES_Q(0);
1076 if (trans_pcie
->shared_vec_mask
& IWL_SHARED_IRQ_NON_RX
)
1077 val
|= MSIX_NON_AUTO_CLEAR_CAUSE
;
1078 iwl_write8(trans
, CSR_MSIX_RX_IVAR(0), val
);
1080 if (trans_pcie
->shared_vec_mask
& IWL_SHARED_IRQ_FIRST_RSS
)
1081 iwl_write8(trans
, CSR_MSIX_RX_IVAR(1), val
);
1084 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie
*trans_pcie
)
1086 struct iwl_trans
*trans
= trans_pcie
->trans
;
1088 if (!trans_pcie
->msix_enabled
) {
1089 if (trans
->cfg
->mq_rx_supported
&&
1090 test_bit(STATUS_DEVICE_ENABLED
, &trans
->status
))
1091 iwl_write_prph(trans
, UREG_CHICK
,
1092 UREG_CHICK_MSI_ENABLE
);
1096 * The IVAR table needs to be configured again after reset,
1097 * but if the device is disabled, we can't write to
1100 if (test_bit(STATUS_DEVICE_ENABLED
, &trans
->status
))
1101 iwl_write_prph(trans
, UREG_CHICK
, UREG_CHICK_MSIX_ENABLE
);
1104 * Each cause from the causes list above and the RX causes is
1105 * represented as a byte in the IVAR table. The first nibble
1106 * represents the bound interrupt vector of the cause, the second
1107 * represents no auto clear for this cause. This will be set if its
1108 * interrupt vector is bound to serve other causes.
1110 iwl_pcie_map_rx_causes(trans
);
1112 iwl_pcie_map_non_rx_causes(trans
);
1115 static void iwl_pcie_init_msix(struct iwl_trans_pcie
*trans_pcie
)
1117 struct iwl_trans
*trans
= trans_pcie
->trans
;
1119 iwl_pcie_conf_msix_hw(trans_pcie
);
1121 if (!trans_pcie
->msix_enabled
)
1124 trans_pcie
->fh_init_mask
= ~iwl_read32(trans
, CSR_MSIX_FH_INT_MASK_AD
);
1125 trans_pcie
->fh_mask
= trans_pcie
->fh_init_mask
;
1126 trans_pcie
->hw_init_mask
= ~iwl_read32(trans
, CSR_MSIX_HW_INT_MASK_AD
);
1127 trans_pcie
->hw_mask
= trans_pcie
->hw_init_mask
;
1130 static void _iwl_trans_pcie_stop_device(struct iwl_trans
*trans
, bool low_power
)
1132 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1134 lockdep_assert_held(&trans_pcie
->mutex
);
1136 if (trans_pcie
->is_down
)
1139 trans_pcie
->is_down
= true;
1141 /* tell the device to stop sending interrupts */
1142 iwl_disable_interrupts(trans
);
1144 /* device going down, Stop using ICT table */
1145 iwl_pcie_disable_ict(trans
);
1148 * If a HW restart happens during firmware loading,
1149 * then the firmware loading might call this function
1150 * and later it might be called again due to the
1151 * restart. So don't process again if the device is
1154 if (test_and_clear_bit(STATUS_DEVICE_ENABLED
, &trans
->status
)) {
1155 IWL_DEBUG_INFO(trans
,
1156 "DEVICE_ENABLED bit was set and is now cleared\n");
1157 iwl_pcie_tx_stop(trans
);
1158 iwl_pcie_rx_stop(trans
);
1160 /* Power-down device's busmaster DMA clocks */
1161 if (!trans
->cfg
->apmg_not_supported
) {
1162 iwl_write_prph(trans
, APMG_CLK_DIS_REG
,
1163 APMG_CLK_VAL_DMA_CLK_RQT
);
1168 /* Make sure (redundant) we've released our request to stay awake */
1169 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1170 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1172 /* Stop the device, and put it in low power state */
1173 iwl_pcie_apm_stop(trans
, false);
1175 iwl_pcie_sw_reset(trans
);
1178 * Upon stop, the IVAR table gets erased, so msi-x won't
1179 * work. This causes a bug in RF-KILL flows, since the interrupt
1180 * that enables radio won't fire on the correct irq, and the
1181 * driver won't be able to handle the interrupt.
1182 * Configure the IVAR table again after reset.
1184 iwl_pcie_conf_msix_hw(trans_pcie
);
1187 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1188 * This is a bug in certain verions of the hardware.
1189 * Certain devices also keep sending HW RF kill interrupt all
1190 * the time, unless the interrupt is ACKed even if the interrupt
1191 * should be masked. Re-ACK all the interrupts here.
1193 iwl_disable_interrupts(trans
);
1195 /* clear all status bits */
1196 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1197 clear_bit(STATUS_INT_ENABLED
, &trans
->status
);
1198 clear_bit(STATUS_TPOWER_PMI
, &trans
->status
);
1201 * Even if we stop the HW, we still want the RF kill
1204 iwl_enable_rfkill_int(trans
);
1206 /* re-take ownership to prevent other users from stealing the device */
1207 iwl_pcie_prepare_card_hw(trans
);
1210 void iwl_pcie_synchronize_irqs(struct iwl_trans
*trans
)
1212 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1214 if (trans_pcie
->msix_enabled
) {
1217 for (i
= 0; i
< trans_pcie
->alloc_vecs
; i
++)
1218 synchronize_irq(trans_pcie
->msix_entries
[i
].vector
);
1220 synchronize_irq(trans_pcie
->pci_dev
->irq
);
1224 static int iwl_trans_pcie_start_fw(struct iwl_trans
*trans
,
1225 const struct fw_img
*fw
, bool run_in_rfkill
)
1227 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1231 /* This may fail if AMT took ownership of the device */
1232 if (iwl_pcie_prepare_card_hw(trans
)) {
1233 IWL_WARN(trans
, "Exit HW not ready\n");
1238 iwl_enable_rfkill_int(trans
);
1240 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
1243 * We enabled the RF-Kill interrupt and the handler may very
1244 * well be running. Disable the interrupts to make sure no other
1245 * interrupt can be fired.
1247 iwl_disable_interrupts(trans
);
1249 /* Make sure it finished running */
1250 iwl_pcie_synchronize_irqs(trans
);
1252 mutex_lock(&trans_pcie
->mutex
);
1254 /* If platform's RF_KILL switch is NOT set to KILL */
1255 hw_rfkill
= iwl_pcie_check_hw_rf_kill(trans
);
1256 if (hw_rfkill
&& !run_in_rfkill
) {
1261 /* Someone called stop_device, don't try to start_fw */
1262 if (trans_pcie
->is_down
) {
1264 "Can't start_fw since the HW hasn't been started\n");
1269 /* make sure rfkill handshake bits are cleared */
1270 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1271 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
,
1272 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED
);
1274 /* clear (again), then enable host interrupts */
1275 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
1277 ret
= iwl_pcie_nic_init(trans
);
1279 IWL_ERR(trans
, "Unable to init nic\n");
1284 * Now, we load the firmware and don't want to be interrupted, even
1285 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1286 * FH_TX interrupt which is needed to load the firmware). If the
1287 * RF-Kill switch is toggled, we will find out after having loaded
1288 * the firmware and return the proper value to the caller.
1290 iwl_enable_fw_load_int(trans
);
1292 /* really make sure rfkill handshake bits are cleared */
1293 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1294 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1296 /* Load the given image to the HW */
1297 if (trans
->cfg
->device_family
>= IWL_DEVICE_FAMILY_8000
)
1298 ret
= iwl_pcie_load_given_ucode_8000(trans
, fw
);
1300 ret
= iwl_pcie_load_given_ucode(trans
, fw
);
1302 /* re-check RF-Kill state since we may have missed the interrupt */
1303 hw_rfkill
= iwl_pcie_check_hw_rf_kill(trans
);
1304 if (hw_rfkill
&& !run_in_rfkill
)
1308 mutex_unlock(&trans_pcie
->mutex
);
1312 static void iwl_trans_pcie_fw_alive(struct iwl_trans
*trans
, u32 scd_addr
)
1314 iwl_pcie_reset_ict(trans
);
1315 iwl_pcie_tx_start(trans
, scd_addr
);
1318 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans
*trans
,
1324 * Check again since the RF kill state may have changed while
1325 * all the interrupts were disabled, in this case we couldn't
1326 * receive the RF kill interrupt and update the state in the
1328 * Don't call the op_mode if the rkfill state hasn't changed.
1329 * This allows the op_mode to call stop_device from the rfkill
1330 * notification without endless recursion. Under very rare
1331 * circumstances, we might have a small recursion if the rfkill
1332 * state changed exactly now while we were called from stop_device.
1333 * This is very unlikely but can happen and is supported.
1335 hw_rfkill
= iwl_is_rfkill_set(trans
);
1337 set_bit(STATUS_RFKILL_HW
, &trans
->status
);
1338 set_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1340 clear_bit(STATUS_RFKILL_HW
, &trans
->status
);
1341 clear_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1343 if (hw_rfkill
!= was_in_rfkill
)
1344 iwl_trans_pcie_rf_kill(trans
, hw_rfkill
);
1347 static void iwl_trans_pcie_stop_device(struct iwl_trans
*trans
, bool low_power
)
1349 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1352 mutex_lock(&trans_pcie
->mutex
);
1353 trans_pcie
->opmode_down
= true;
1354 was_in_rfkill
= test_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1355 _iwl_trans_pcie_stop_device(trans
, low_power
);
1356 iwl_trans_pcie_handle_stop_rfkill(trans
, was_in_rfkill
);
1357 mutex_unlock(&trans_pcie
->mutex
);
1360 void iwl_trans_pcie_rf_kill(struct iwl_trans
*trans
, bool state
)
1362 struct iwl_trans_pcie __maybe_unused
*trans_pcie
=
1363 IWL_TRANS_GET_PCIE_TRANS(trans
);
1365 lockdep_assert_held(&trans_pcie
->mutex
);
1367 IWL_WARN(trans
, "reporting RF_KILL (radio %s)\n",
1368 state
? "disabled" : "enabled");
1369 if (iwl_op_mode_hw_rf_kill(trans
->op_mode
, state
)) {
1370 if (trans
->cfg
->gen2
)
1371 _iwl_trans_pcie_gen2_stop_device(trans
, true);
1373 _iwl_trans_pcie_stop_device(trans
, true);
1377 static void iwl_trans_pcie_d3_suspend(struct iwl_trans
*trans
, bool test
,
1381 /* Enable persistence mode to avoid reset */
1382 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
1383 CSR_HW_IF_CONFIG_REG_PERSIST_MODE
);
1386 iwl_disable_interrupts(trans
);
1389 * in testing mode, the host stays awake and the
1390 * hardware won't be reset (not even partially)
1395 iwl_pcie_disable_ict(trans
);
1397 iwl_pcie_synchronize_irqs(trans
);
1399 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1400 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1401 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1402 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
1404 iwl_pcie_enable_rx_wake(trans
, false);
1408 * reset TX queues -- some of their registers reset during S3
1409 * so if we don't reset everything here the D3 image would try
1410 * to execute some invalid memory upon resume
1412 iwl_trans_pcie_tx_reset(trans
);
1415 iwl_pcie_set_pwr(trans
, true);
1418 static int iwl_trans_pcie_d3_resume(struct iwl_trans
*trans
,
1419 enum iwl_d3_status
*status
,
1420 bool test
, bool reset
)
1422 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1427 iwl_enable_interrupts(trans
);
1428 *status
= IWL_D3_STATUS_ALIVE
;
1432 iwl_pcie_enable_rx_wake(trans
, true);
1435 * Reconfigure IVAR table in case of MSIX or reset ict table in
1436 * MSI mode since HW reset erased it.
1437 * Also enables interrupts - none will happen as
1438 * the device doesn't know we're waking it up, only when
1439 * the opmode actually tells it after this call.
1441 iwl_pcie_conf_msix_hw(trans_pcie
);
1442 if (!trans_pcie
->msix_enabled
)
1443 iwl_pcie_reset_ict(trans
);
1444 iwl_enable_interrupts(trans
);
1446 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1447 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
1449 if (trans
->cfg
->device_family
>= IWL_DEVICE_FAMILY_8000
)
1452 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
1453 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
1454 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
1457 IWL_ERR(trans
, "Failed to resume the device (mac ready)\n");
1461 iwl_pcie_set_pwr(trans
, false);
1464 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1465 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1467 iwl_trans_pcie_tx_reset(trans
);
1469 ret
= iwl_pcie_rx_init(trans
);
1472 "Failed to resume the device (RX reset)\n");
1477 IWL_DEBUG_POWER(trans
, "WFPM value upon resume = 0x%08X\n",
1478 iwl_read_prph(trans
, WFPM_GP2
));
1480 val
= iwl_read32(trans
, CSR_RESET
);
1481 if (val
& CSR_RESET_REG_FLAG_NEVO_RESET
)
1482 *status
= IWL_D3_STATUS_RESET
;
1484 *status
= IWL_D3_STATUS_ALIVE
;
1489 static void iwl_pcie_set_interrupt_capa(struct pci_dev
*pdev
,
1490 struct iwl_trans
*trans
)
1492 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1493 int max_irqs
, num_irqs
, i
, ret
, nr_online_cpus
;
1496 if (!trans
->cfg
->mq_rx_supported
)
1499 nr_online_cpus
= num_online_cpus();
1500 max_irqs
= min_t(u32
, nr_online_cpus
+ 2, IWL_MAX_RX_HW_QUEUES
);
1501 for (i
= 0; i
< max_irqs
; i
++)
1502 trans_pcie
->msix_entries
[i
].entry
= i
;
1504 num_irqs
= pci_enable_msix_range(pdev
, trans_pcie
->msix_entries
,
1505 MSIX_MIN_INTERRUPT_VECTORS
,
1508 IWL_DEBUG_INFO(trans
,
1509 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1513 trans_pcie
->def_irq
= (num_irqs
== max_irqs
) ? num_irqs
- 1 : 0;
1515 IWL_DEBUG_INFO(trans
,
1516 "MSI-X enabled. %d interrupt vectors were allocated\n",
1520 * In case the OS provides fewer interrupts than requested, different
1521 * causes will share the same interrupt vector as follows:
1522 * One interrupt less: non rx causes shared with FBQ.
1523 * Two interrupts less: non rx causes shared with FBQ and RSS.
1524 * More than two interrupts: we will use fewer RSS queues.
1526 if (num_irqs
<= nr_online_cpus
) {
1527 trans_pcie
->trans
->num_rx_queues
= num_irqs
+ 1;
1528 trans_pcie
->shared_vec_mask
= IWL_SHARED_IRQ_NON_RX
|
1529 IWL_SHARED_IRQ_FIRST_RSS
;
1530 } else if (num_irqs
== nr_online_cpus
+ 1) {
1531 trans_pcie
->trans
->num_rx_queues
= num_irqs
;
1532 trans_pcie
->shared_vec_mask
= IWL_SHARED_IRQ_NON_RX
;
1534 trans_pcie
->trans
->num_rx_queues
= num_irqs
- 1;
1537 trans_pcie
->alloc_vecs
= num_irqs
;
1538 trans_pcie
->msix_enabled
= true;
1542 ret
= pci_enable_msi(pdev
);
1544 dev_err(&pdev
->dev
, "pci_enable_msi failed - %d\n", ret
);
1545 /* enable rfkill interrupt: hw bug w/a */
1546 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
1547 if (pci_cmd
& PCI_COMMAND_INTX_DISABLE
) {
1548 pci_cmd
&= ~PCI_COMMAND_INTX_DISABLE
;
1549 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
1554 static void iwl_pcie_irq_set_affinity(struct iwl_trans
*trans
)
1556 int iter_rx_q
, i
, ret
, cpu
, offset
;
1557 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1559 i
= trans_pcie
->shared_vec_mask
& IWL_SHARED_IRQ_FIRST_RSS
? 0 : 1;
1560 iter_rx_q
= trans_pcie
->trans
->num_rx_queues
- 1 + i
;
1562 for (; i
< iter_rx_q
; i
++) {
1564 * Get the cpu prior to the place to search
1565 * (i.e. return will be > i - 1).
1567 cpu
= cpumask_next(i
- offset
, cpu_online_mask
);
1568 cpumask_set_cpu(cpu
, &trans_pcie
->affinity_mask
[i
]);
1569 ret
= irq_set_affinity_hint(trans_pcie
->msix_entries
[i
].vector
,
1570 &trans_pcie
->affinity_mask
[i
]);
1572 IWL_ERR(trans_pcie
->trans
,
1573 "Failed to set affinity mask for IRQ %d\n",
1578 static const char *queue_name(struct device
*dev
,
1579 struct iwl_trans_pcie
*trans_p
, int i
)
1581 if (trans_p
->shared_vec_mask
) {
1582 int vec
= trans_p
->shared_vec_mask
&
1583 IWL_SHARED_IRQ_FIRST_RSS
? 1 : 0;
1586 return DRV_NAME
": shared IRQ";
1588 return devm_kasprintf(dev
, GFP_KERNEL
,
1589 DRV_NAME
": queue %d", i
+ vec
);
1592 return DRV_NAME
": default queue";
1594 if (i
== trans_p
->alloc_vecs
- 1)
1595 return DRV_NAME
": exception";
1597 return devm_kasprintf(dev
, GFP_KERNEL
,
1598 DRV_NAME
": queue %d", i
);
1601 static int iwl_pcie_init_msix_handler(struct pci_dev
*pdev
,
1602 struct iwl_trans_pcie
*trans_pcie
)
1606 for (i
= 0; i
< trans_pcie
->alloc_vecs
; i
++) {
1608 struct msix_entry
*msix_entry
;
1609 const char *qname
= queue_name(&pdev
->dev
, trans_pcie
, i
);
1614 msix_entry
= &trans_pcie
->msix_entries
[i
];
1615 ret
= devm_request_threaded_irq(&pdev
->dev
,
1618 (i
== trans_pcie
->def_irq
) ?
1619 iwl_pcie_irq_msix_handler
:
1620 iwl_pcie_irq_rx_msix_handler
,
1625 IWL_ERR(trans_pcie
->trans
,
1626 "Error allocating IRQ %d\n", i
);
1631 iwl_pcie_irq_set_affinity(trans_pcie
->trans
);
1636 static int _iwl_trans_pcie_start_hw(struct iwl_trans
*trans
, bool low_power
)
1638 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1641 lockdep_assert_held(&trans_pcie
->mutex
);
1643 err
= iwl_pcie_prepare_card_hw(trans
);
1645 IWL_ERR(trans
, "Error while preparing HW: %d\n", err
);
1649 iwl_pcie_sw_reset(trans
);
1651 err
= iwl_pcie_apm_init(trans
);
1655 iwl_pcie_init_msix(trans_pcie
);
1657 /* From now on, the op_mode will be kept updated about RF kill state */
1658 iwl_enable_rfkill_int(trans
);
1660 trans_pcie
->opmode_down
= false;
1662 /* Set is_down to false here so that...*/
1663 trans_pcie
->is_down
= false;
1665 /* ...rfkill can call stop_device and set it false if needed */
1666 iwl_pcie_check_hw_rf_kill(trans
);
1668 /* Make sure we sync here, because we'll need full access later */
1670 pm_runtime_resume(trans
->dev
);
1675 static int iwl_trans_pcie_start_hw(struct iwl_trans
*trans
, bool low_power
)
1677 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1680 mutex_lock(&trans_pcie
->mutex
);
1681 ret
= _iwl_trans_pcie_start_hw(trans
, low_power
);
1682 mutex_unlock(&trans_pcie
->mutex
);
1687 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans
*trans
)
1689 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1691 mutex_lock(&trans_pcie
->mutex
);
1693 /* disable interrupts - don't enable HW RF kill interrupt */
1694 iwl_disable_interrupts(trans
);
1696 iwl_pcie_apm_stop(trans
, true);
1698 iwl_disable_interrupts(trans
);
1700 iwl_pcie_disable_ict(trans
);
1702 mutex_unlock(&trans_pcie
->mutex
);
1704 iwl_pcie_synchronize_irqs(trans
);
1707 static void iwl_trans_pcie_write8(struct iwl_trans
*trans
, u32 ofs
, u8 val
)
1709 writeb(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1712 static void iwl_trans_pcie_write32(struct iwl_trans
*trans
, u32 ofs
, u32 val
)
1714 writel(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1717 static u32
iwl_trans_pcie_read32(struct iwl_trans
*trans
, u32 ofs
)
1719 return readl(IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1722 static u32
iwl_trans_pcie_read_prph(struct iwl_trans
*trans
, u32 reg
)
1724 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_RADDR
,
1725 ((reg
& 0x000FFFFF) | (3 << 24)));
1726 return iwl_trans_pcie_read32(trans
, HBUS_TARG_PRPH_RDAT
);
1729 static void iwl_trans_pcie_write_prph(struct iwl_trans
*trans
, u32 addr
,
1732 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_WADDR
,
1733 ((addr
& 0x000FFFFF) | (3 << 24)));
1734 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_WDAT
, val
);
1737 static void iwl_trans_pcie_configure(struct iwl_trans
*trans
,
1738 const struct iwl_trans_config
*trans_cfg
)
1740 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1742 trans_pcie
->cmd_queue
= trans_cfg
->cmd_queue
;
1743 trans_pcie
->cmd_fifo
= trans_cfg
->cmd_fifo
;
1744 trans_pcie
->cmd_q_wdg_timeout
= trans_cfg
->cmd_q_wdg_timeout
;
1745 if (WARN_ON(trans_cfg
->n_no_reclaim_cmds
> MAX_NO_RECLAIM_CMDS
))
1746 trans_pcie
->n_no_reclaim_cmds
= 0;
1748 trans_pcie
->n_no_reclaim_cmds
= trans_cfg
->n_no_reclaim_cmds
;
1749 if (trans_pcie
->n_no_reclaim_cmds
)
1750 memcpy(trans_pcie
->no_reclaim_cmds
, trans_cfg
->no_reclaim_cmds
,
1751 trans_pcie
->n_no_reclaim_cmds
* sizeof(u8
));
1753 trans_pcie
->rx_buf_size
= trans_cfg
->rx_buf_size
;
1754 trans_pcie
->rx_page_order
=
1755 iwl_trans_get_rb_size_order(trans_pcie
->rx_buf_size
);
1757 trans_pcie
->bc_table_dword
= trans_cfg
->bc_table_dword
;
1758 trans_pcie
->scd_set_active
= trans_cfg
->scd_set_active
;
1759 trans_pcie
->sw_csum_tx
= trans_cfg
->sw_csum_tx
;
1761 trans_pcie
->page_offs
= trans_cfg
->cb_data_offs
;
1762 trans_pcie
->dev_cmd_offs
= trans_cfg
->cb_data_offs
+ sizeof(void *);
1764 trans
->command_groups
= trans_cfg
->command_groups
;
1765 trans
->command_groups_size
= trans_cfg
->command_groups_size
;
1767 /* Initialize NAPI here - it should be before registering to mac80211
1768 * in the opmode but after the HW struct is allocated.
1769 * As this function may be called again in some corner cases don't
1770 * do anything if NAPI was already initialized.
1772 if (trans_pcie
->napi_dev
.reg_state
!= NETREG_DUMMY
)
1773 init_dummy_netdev(&trans_pcie
->napi_dev
);
1776 void iwl_trans_pcie_free(struct iwl_trans
*trans
)
1778 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1781 iwl_pcie_synchronize_irqs(trans
);
1783 if (trans
->cfg
->gen2
)
1784 iwl_pcie_gen2_tx_free(trans
);
1786 iwl_pcie_tx_free(trans
);
1787 iwl_pcie_rx_free(trans
);
1789 if (trans_pcie
->rba
.alloc_wq
) {
1790 destroy_workqueue(trans_pcie
->rba
.alloc_wq
);
1791 trans_pcie
->rba
.alloc_wq
= NULL
;
1794 if (trans_pcie
->msix_enabled
) {
1795 for (i
= 0; i
< trans_pcie
->alloc_vecs
; i
++) {
1796 irq_set_affinity_hint(
1797 trans_pcie
->msix_entries
[i
].vector
,
1801 trans_pcie
->msix_enabled
= false;
1803 iwl_pcie_free_ict(trans
);
1806 iwl_pcie_free_fw_monitor(trans
);
1808 for_each_possible_cpu(i
) {
1809 struct iwl_tso_hdr_page
*p
=
1810 per_cpu_ptr(trans_pcie
->tso_hdr_page
, i
);
1813 __free_page(p
->page
);
1816 free_percpu(trans_pcie
->tso_hdr_page
);
1817 mutex_destroy(&trans_pcie
->mutex
);
1818 iwl_trans_free(trans
);
1821 static void iwl_trans_pcie_set_pmi(struct iwl_trans
*trans
, bool state
)
1824 set_bit(STATUS_TPOWER_PMI
, &trans
->status
);
1826 clear_bit(STATUS_TPOWER_PMI
, &trans
->status
);
1829 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans
*trans
,
1830 unsigned long *flags
)
1833 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1835 spin_lock_irqsave(&trans_pcie
->reg_lock
, *flags
);
1837 if (trans_pcie
->cmd_hold_nic_awake
)
1840 /* this bit wakes up the NIC */
1841 __iwl_trans_pcie_set_bit(trans
, CSR_GP_CNTRL
,
1842 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1843 if (trans
->cfg
->device_family
>= IWL_DEVICE_FAMILY_8000
)
1847 * These bits say the device is running, and should keep running for
1848 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1849 * but they do not indicate that embedded SRAM is restored yet;
1850 * HW with volatile SRAM must save/restore contents to/from
1851 * host DRAM when sleeping/waking for power-saving.
1852 * Each direction takes approximately 1/4 millisecond; with this
1853 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1854 * series of register accesses are expected (e.g. reading Event Log),
1855 * to keep device from sleeping.
1857 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1858 * SRAM is okay/restored. We don't check that here because this call
1859 * is just for hardware register access; but GP1 MAC_SLEEP
1860 * check is a good idea before accessing the SRAM of HW with
1861 * volatile SRAM (e.g. reading Event Log).
1863 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1864 * and do not save/restore SRAM when power cycling.
1866 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
1867 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN
,
1868 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
|
1869 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP
), 15000);
1870 if (unlikely(ret
< 0)) {
1871 iwl_write32(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_FORCE_NMI
);
1873 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1874 iwl_read32(trans
, CSR_GP_CNTRL
));
1875 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, *flags
);
1881 * Fool sparse by faking we release the lock - sparse will
1882 * track nic_access anyway.
1884 __release(&trans_pcie
->reg_lock
);
1888 static void iwl_trans_pcie_release_nic_access(struct iwl_trans
*trans
,
1889 unsigned long *flags
)
1891 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1893 lockdep_assert_held(&trans_pcie
->reg_lock
);
1896 * Fool sparse by faking we acquiring the lock - sparse will
1897 * track nic_access anyway.
1899 __acquire(&trans_pcie
->reg_lock
);
1901 if (trans_pcie
->cmd_hold_nic_awake
)
1904 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
1905 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1907 * Above we read the CSR_GP_CNTRL register, which will flush
1908 * any previous writes, but we need the write that clears the
1909 * MAC_ACCESS_REQ bit to be performed before any other writes
1910 * scheduled on different CPUs (after we drop reg_lock).
1914 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, *flags
);
1917 static int iwl_trans_pcie_read_mem(struct iwl_trans
*trans
, u32 addr
,
1918 void *buf
, int dwords
)
1920 unsigned long flags
;
1924 if (iwl_trans_grab_nic_access(trans
, &flags
)) {
1925 iwl_write32(trans
, HBUS_TARG_MEM_RADDR
, addr
);
1926 for (offs
= 0; offs
< dwords
; offs
++)
1927 vals
[offs
] = iwl_read32(trans
, HBUS_TARG_MEM_RDAT
);
1928 iwl_trans_release_nic_access(trans
, &flags
);
1935 static int iwl_trans_pcie_write_mem(struct iwl_trans
*trans
, u32 addr
,
1936 const void *buf
, int dwords
)
1938 unsigned long flags
;
1940 const u32
*vals
= buf
;
1942 if (iwl_trans_grab_nic_access(trans
, &flags
)) {
1943 iwl_write32(trans
, HBUS_TARG_MEM_WADDR
, addr
);
1944 for (offs
= 0; offs
< dwords
; offs
++)
1945 iwl_write32(trans
, HBUS_TARG_MEM_WDAT
,
1946 vals
? vals
[offs
] : 0);
1947 iwl_trans_release_nic_access(trans
, &flags
);
1954 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans
*trans
,
1958 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1961 for_each_set_bit(queue
, &txqs
, BITS_PER_LONG
) {
1962 struct iwl_txq
*txq
= trans_pcie
->txq
[queue
];
1965 spin_lock_bh(&txq
->lock
);
1969 if (txq
->frozen
== freeze
)
1972 IWL_DEBUG_TX_QUEUES(trans
, "%s TXQ %d\n",
1973 freeze
? "Freezing" : "Waking", queue
);
1975 txq
->frozen
= freeze
;
1977 if (txq
->read_ptr
== txq
->write_ptr
)
1981 if (unlikely(time_after(now
,
1982 txq
->stuck_timer
.expires
))) {
1984 * The timer should have fired, maybe it is
1985 * spinning right now on the lock.
1989 /* remember how long until the timer fires */
1990 txq
->frozen_expiry_remainder
=
1991 txq
->stuck_timer
.expires
- now
;
1992 del_timer(&txq
->stuck_timer
);
1997 * Wake a non-empty queue -> arm timer with the
1998 * remainder before it froze
2000 mod_timer(&txq
->stuck_timer
,
2001 now
+ txq
->frozen_expiry_remainder
);
2004 spin_unlock_bh(&txq
->lock
);
2008 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans
*trans
, bool block
)
2010 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2013 for (i
= 0; i
< trans
->cfg
->base_params
->num_of_queues
; i
++) {
2014 struct iwl_txq
*txq
= trans_pcie
->txq
[i
];
2016 if (i
== trans_pcie
->cmd_queue
)
2019 spin_lock_bh(&txq
->lock
);
2021 if (!block
&& !(WARN_ON_ONCE(!txq
->block
))) {
2024 iwl_write32(trans
, HBUS_TARG_WRPTR
,
2025 txq
->write_ptr
| (i
<< 8));
2031 spin_unlock_bh(&txq
->lock
);
2035 #define IWL_FLUSH_WAIT_MS 2000
2037 void iwl_trans_pcie_log_scd_error(struct iwl_trans
*trans
, struct iwl_txq
*txq
)
2039 u32 txq_id
= txq
->id
;
2044 if (trans
->cfg
->use_tfh
) {
2045 IWL_ERR(trans
, "Queue %d is stuck %d %d\n", txq_id
,
2046 txq
->read_ptr
, txq
->write_ptr
);
2047 /* TODO: access new SCD registers and dump them */
2051 status
= iwl_read_prph(trans
, SCD_QUEUE_STATUS_BITS(txq_id
));
2052 fifo
= (status
>> SCD_QUEUE_STTS_REG_POS_TXF
) & 0x7;
2053 active
= !!(status
& BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE
));
2056 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2057 txq_id
, active
? "" : "in", fifo
,
2058 jiffies_to_msecs(txq
->wd_timeout
),
2059 txq
->read_ptr
, txq
->write_ptr
,
2060 iwl_read_prph(trans
, SCD_QUEUE_RDPTR(txq_id
)) &
2061 (TFD_QUEUE_SIZE_MAX
- 1),
2062 iwl_read_prph(trans
, SCD_QUEUE_WRPTR(txq_id
)) &
2063 (TFD_QUEUE_SIZE_MAX
- 1),
2064 iwl_read_direct32(trans
, FH_TX_TRB_REG(fifo
)));
2067 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans
*trans
, int txq_idx
)
2069 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2070 struct iwl_txq
*txq
;
2071 unsigned long now
= jiffies
;
2074 if (!test_bit(txq_idx
, trans_pcie
->queue_used
))
2077 IWL_DEBUG_TX_QUEUES(trans
, "Emptying queue %d...\n", txq_idx
);
2078 txq
= trans_pcie
->txq
[txq_idx
];
2079 wr_ptr
= READ_ONCE(txq
->write_ptr
);
2081 while (txq
->read_ptr
!= READ_ONCE(txq
->write_ptr
) &&
2082 !time_after(jiffies
,
2083 now
+ msecs_to_jiffies(IWL_FLUSH_WAIT_MS
))) {
2084 u8 write_ptr
= READ_ONCE(txq
->write_ptr
);
2086 if (WARN_ONCE(wr_ptr
!= write_ptr
,
2087 "WR pointer moved while flushing %d -> %d\n",
2090 usleep_range(1000, 2000);
2093 if (txq
->read_ptr
!= txq
->write_ptr
) {
2095 "fail to flush all tx fifo queues Q %d\n", txq_idx
);
2096 iwl_trans_pcie_log_scd_error(trans
, txq
);
2100 IWL_DEBUG_TX_QUEUES(trans
, "Queue %d is now empty.\n", txq_idx
);
2105 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans
*trans
, u32 txq_bm
)
2107 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2111 /* waiting for all the tx frames complete might take a while */
2112 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
2114 if (cnt
== trans_pcie
->cmd_queue
)
2116 if (!test_bit(cnt
, trans_pcie
->queue_used
))
2118 if (!(BIT(cnt
) & txq_bm
))
2121 ret
= iwl_trans_pcie_wait_txq_empty(trans
, cnt
);
2129 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans
*trans
, u32 reg
,
2130 u32 mask
, u32 value
)
2132 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2133 unsigned long flags
;
2135 spin_lock_irqsave(&trans_pcie
->reg_lock
, flags
);
2136 __iwl_trans_pcie_set_bits_mask(trans
, reg
, mask
, value
);
2137 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
2140 static void iwl_trans_pcie_ref(struct iwl_trans
*trans
)
2142 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2144 if (iwlwifi_mod_params
.d0i3_disable
)
2147 pm_runtime_get(&trans_pcie
->pci_dev
->dev
);
2150 IWL_DEBUG_RPM(trans
, "runtime usage count: %d\n",
2151 atomic_read(&trans_pcie
->pci_dev
->dev
.power
.usage_count
));
2152 #endif /* CONFIG_PM */
2155 static void iwl_trans_pcie_unref(struct iwl_trans
*trans
)
2157 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2159 if (iwlwifi_mod_params
.d0i3_disable
)
2162 pm_runtime_mark_last_busy(&trans_pcie
->pci_dev
->dev
);
2163 pm_runtime_put_autosuspend(&trans_pcie
->pci_dev
->dev
);
2166 IWL_DEBUG_RPM(trans
, "runtime usage count: %d\n",
2167 atomic_read(&trans_pcie
->pci_dev
->dev
.power
.usage_count
));
2168 #endif /* CONFIG_PM */
2171 static const char *get_csr_string(int cmd
)
2173 #define IWL_CMD(x) case x: return #x
2175 IWL_CMD(CSR_HW_IF_CONFIG_REG
);
2176 IWL_CMD(CSR_INT_COALESCING
);
2178 IWL_CMD(CSR_INT_MASK
);
2179 IWL_CMD(CSR_FH_INT_STATUS
);
2180 IWL_CMD(CSR_GPIO_IN
);
2182 IWL_CMD(CSR_GP_CNTRL
);
2183 IWL_CMD(CSR_HW_REV
);
2184 IWL_CMD(CSR_EEPROM_REG
);
2185 IWL_CMD(CSR_EEPROM_GP
);
2186 IWL_CMD(CSR_OTP_GP_REG
);
2187 IWL_CMD(CSR_GIO_REG
);
2188 IWL_CMD(CSR_GP_UCODE_REG
);
2189 IWL_CMD(CSR_GP_DRIVER_REG
);
2190 IWL_CMD(CSR_UCODE_DRV_GP1
);
2191 IWL_CMD(CSR_UCODE_DRV_GP2
);
2192 IWL_CMD(CSR_LED_REG
);
2193 IWL_CMD(CSR_DRAM_INT_TBL_REG
);
2194 IWL_CMD(CSR_GIO_CHICKEN_BITS
);
2195 IWL_CMD(CSR_ANA_PLL_CFG
);
2196 IWL_CMD(CSR_HW_REV_WA_REG
);
2197 IWL_CMD(CSR_MONITOR_STATUS_REG
);
2198 IWL_CMD(CSR_DBG_HPET_MEM_REG
);
2205 void iwl_pcie_dump_csr(struct iwl_trans
*trans
)
2208 static const u32 csr_tbl
[] = {
2209 CSR_HW_IF_CONFIG_REG
,
2227 CSR_DRAM_INT_TBL_REG
,
2228 CSR_GIO_CHICKEN_BITS
,
2230 CSR_MONITOR_STATUS_REG
,
2232 CSR_DBG_HPET_MEM_REG
2234 IWL_ERR(trans
, "CSR values:\n");
2235 IWL_ERR(trans
, "(2nd byte of CSR_INT_COALESCING is "
2236 "CSR_INT_PERIODIC_REG)\n");
2237 for (i
= 0; i
< ARRAY_SIZE(csr_tbl
); i
++) {
2238 IWL_ERR(trans
, " %25s: 0X%08x\n",
2239 get_csr_string(csr_tbl
[i
]),
2240 iwl_read32(trans
, csr_tbl
[i
]));
2244 #ifdef CONFIG_IWLWIFI_DEBUGFS
2245 /* create and remove of files */
2246 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
2247 if (!debugfs_create_file(#name, mode, parent, trans, \
2248 &iwl_dbgfs_##name##_ops)) \
2252 /* file operation */
2253 #define DEBUGFS_READ_FILE_OPS(name) \
2254 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2255 .read = iwl_dbgfs_##name##_read, \
2256 .open = simple_open, \
2257 .llseek = generic_file_llseek, \
2260 #define DEBUGFS_WRITE_FILE_OPS(name) \
2261 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2262 .write = iwl_dbgfs_##name##_write, \
2263 .open = simple_open, \
2264 .llseek = generic_file_llseek, \
2267 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
2268 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2269 .write = iwl_dbgfs_##name##_write, \
2270 .read = iwl_dbgfs_##name##_read, \
2271 .open = simple_open, \
2272 .llseek = generic_file_llseek, \
2275 static ssize_t
iwl_dbgfs_tx_queue_read(struct file
*file
,
2276 char __user
*user_buf
,
2277 size_t count
, loff_t
*ppos
)
2279 struct iwl_trans
*trans
= file
->private_data
;
2280 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2281 struct iwl_txq
*txq
;
2288 bufsz
= sizeof(char) * 75 * trans
->cfg
->base_params
->num_of_queues
;
2290 if (!trans_pcie
->txq_memory
)
2293 buf
= kzalloc(bufsz
, GFP_KERNEL
);
2297 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
2298 txq
= trans_pcie
->txq
[cnt
];
2299 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2300 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2301 cnt
, txq
->read_ptr
, txq
->write_ptr
,
2302 !!test_bit(cnt
, trans_pcie
->queue_used
),
2303 !!test_bit(cnt
, trans_pcie
->queue_stopped
),
2304 txq
->need_update
, txq
->frozen
,
2305 (cnt
== trans_pcie
->cmd_queue
? " HCMD" : ""));
2307 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
2312 static ssize_t
iwl_dbgfs_rx_queue_read(struct file
*file
,
2313 char __user
*user_buf
,
2314 size_t count
, loff_t
*ppos
)
2316 struct iwl_trans
*trans
= file
->private_data
;
2317 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2319 int pos
= 0, i
, ret
;
2320 size_t bufsz
= sizeof(buf
);
2322 bufsz
= sizeof(char) * 121 * trans
->num_rx_queues
;
2324 if (!trans_pcie
->rxq
)
2327 buf
= kzalloc(bufsz
, GFP_KERNEL
);
2331 for (i
= 0; i
< trans
->num_rx_queues
&& pos
< bufsz
; i
++) {
2332 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
[i
];
2334 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "queue#: %2d\n",
2336 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "\tread: %u\n",
2338 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "\twrite: %u\n",
2340 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "\twrite_actual: %u\n",
2342 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "\tneed_update: %2d\n",
2344 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "\tfree_count: %u\n",
2347 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2348 "\tclosed_rb_num: %u\n",
2349 le16_to_cpu(rxq
->rb_stts
->closed_rb_num
) &
2352 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2353 "\tclosed_rb_num: Not Allocated\n");
2356 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
2362 static ssize_t
iwl_dbgfs_interrupt_read(struct file
*file
,
2363 char __user
*user_buf
,
2364 size_t count
, loff_t
*ppos
)
2366 struct iwl_trans
*trans
= file
->private_data
;
2367 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2368 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
2372 int bufsz
= 24 * 64; /* 24 items * 64 char per item */
2375 buf
= kzalloc(bufsz
, GFP_KERNEL
);
2379 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2380 "Interrupt Statistics Report:\n");
2382 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "HW Error:\t\t\t %u\n",
2384 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "SW Error:\t\t\t %u\n",
2386 if (isr_stats
->sw
|| isr_stats
->hw
) {
2387 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2388 "\tLast Restarting Code: 0x%X\n",
2389 isr_stats
->err_code
);
2391 #ifdef CONFIG_IWLWIFI_DEBUG
2392 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Frame transmitted:\t\t %u\n",
2394 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Alive interrupt:\t\t %u\n",
2397 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2398 "HW RF KILL switch toggled:\t %u\n", isr_stats
->rfkill
);
2400 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "CT KILL:\t\t\t %u\n",
2403 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Wakeup Interrupt:\t\t %u\n",
2406 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2407 "Rx command responses:\t\t %u\n", isr_stats
->rx
);
2409 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Tx/FH interrupt:\t\t %u\n",
2412 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Unexpected INTA:\t\t %u\n",
2413 isr_stats
->unhandled
);
2415 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
2420 static ssize_t
iwl_dbgfs_interrupt_write(struct file
*file
,
2421 const char __user
*user_buf
,
2422 size_t count
, loff_t
*ppos
)
2424 struct iwl_trans
*trans
= file
->private_data
;
2425 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2426 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
2430 ret
= kstrtou32_from_user(user_buf
, count
, 16, &reset_flag
);
2433 if (reset_flag
== 0)
2434 memset(isr_stats
, 0, sizeof(*isr_stats
));
2439 static ssize_t
iwl_dbgfs_csr_write(struct file
*file
,
2440 const char __user
*user_buf
,
2441 size_t count
, loff_t
*ppos
)
2443 struct iwl_trans
*trans
= file
->private_data
;
2445 iwl_pcie_dump_csr(trans
);
2450 static ssize_t
iwl_dbgfs_fh_reg_read(struct file
*file
,
2451 char __user
*user_buf
,
2452 size_t count
, loff_t
*ppos
)
2454 struct iwl_trans
*trans
= file
->private_data
;
2458 ret
= iwl_dump_fh(trans
, &buf
);
2463 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, ret
);
2468 static ssize_t
iwl_dbgfs_rfkill_read(struct file
*file
,
2469 char __user
*user_buf
,
2470 size_t count
, loff_t
*ppos
)
2472 struct iwl_trans
*trans
= file
->private_data
;
2473 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2477 pos
= scnprintf(buf
, sizeof(buf
), "debug: %d\nhw: %d\n",
2478 trans_pcie
->debug_rfkill
,
2479 !(iwl_read32(trans
, CSR_GP_CNTRL
) &
2480 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
));
2482 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
2485 static ssize_t
iwl_dbgfs_rfkill_write(struct file
*file
,
2486 const char __user
*user_buf
,
2487 size_t count
, loff_t
*ppos
)
2489 struct iwl_trans
*trans
= file
->private_data
;
2490 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2491 bool old
= trans_pcie
->debug_rfkill
;
2494 ret
= kstrtobool_from_user(user_buf
, count
, &trans_pcie
->debug_rfkill
);
2497 if (old
== trans_pcie
->debug_rfkill
)
2499 IWL_WARN(trans
, "changing debug rfkill %d->%d\n",
2500 old
, trans_pcie
->debug_rfkill
);
2501 iwl_pcie_handle_rfkill_irq(trans
);
2506 DEBUGFS_READ_WRITE_FILE_OPS(interrupt
);
2507 DEBUGFS_READ_FILE_OPS(fh_reg
);
2508 DEBUGFS_READ_FILE_OPS(rx_queue
);
2509 DEBUGFS_READ_FILE_OPS(tx_queue
);
2510 DEBUGFS_WRITE_FILE_OPS(csr
);
2511 DEBUGFS_READ_WRITE_FILE_OPS(rfkill
);
2513 /* Create the debugfs files and directories */
2514 int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
)
2516 struct dentry
*dir
= trans
->dbgfs_dir
;
2518 DEBUGFS_ADD_FILE(rx_queue
, dir
, S_IRUSR
);
2519 DEBUGFS_ADD_FILE(tx_queue
, dir
, S_IRUSR
);
2520 DEBUGFS_ADD_FILE(interrupt
, dir
, S_IWUSR
| S_IRUSR
);
2521 DEBUGFS_ADD_FILE(csr
, dir
, S_IWUSR
);
2522 DEBUGFS_ADD_FILE(fh_reg
, dir
, S_IRUSR
);
2523 DEBUGFS_ADD_FILE(rfkill
, dir
, S_IWUSR
| S_IRUSR
);
2527 IWL_ERR(trans
, "failed to create the trans debugfs entry\n");
2530 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2532 static u32
iwl_trans_pcie_get_cmdlen(struct iwl_trans
*trans
, void *tfd
)
2534 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2538 for (i
= 0; i
< trans_pcie
->max_tbs
; i
++)
2539 cmdlen
+= iwl_pcie_tfd_tb_get_len(trans
, tfd
, i
);
2544 static u32
iwl_trans_pcie_dump_rbs(struct iwl_trans
*trans
,
2545 struct iwl_fw_error_dump_data
**data
,
2546 int allocated_rb_nums
)
2548 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2549 int max_len
= PAGE_SIZE
<< trans_pcie
->rx_page_order
;
2550 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2551 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
[0];
2552 u32 i
, r
, j
, rb_len
= 0;
2554 spin_lock(&rxq
->lock
);
2556 r
= le16_to_cpu(READ_ONCE(rxq
->rb_stts
->closed_rb_num
)) & 0x0FFF;
2558 for (i
= rxq
->read
, j
= 0;
2559 i
!= r
&& j
< allocated_rb_nums
;
2560 i
= (i
+ 1) & RX_QUEUE_MASK
, j
++) {
2561 struct iwl_rx_mem_buffer
*rxb
= rxq
->queue
[i
];
2562 struct iwl_fw_error_dump_rb
*rb
;
2564 dma_unmap_page(trans
->dev
, rxb
->page_dma
, max_len
,
2567 rb_len
+= sizeof(**data
) + sizeof(*rb
) + max_len
;
2569 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_RB
);
2570 (*data
)->len
= cpu_to_le32(sizeof(*rb
) + max_len
);
2571 rb
= (void *)(*data
)->data
;
2572 rb
->index
= cpu_to_le32(i
);
2573 memcpy(rb
->data
, page_address(rxb
->page
), max_len
);
2574 /* remap the page for the free benefit */
2575 rxb
->page_dma
= dma_map_page(trans
->dev
, rxb
->page
, 0,
2579 *data
= iwl_fw_error_next_data(*data
);
2582 spin_unlock(&rxq
->lock
);
2586 #define IWL_CSR_TO_DUMP (0x250)
2588 static u32
iwl_trans_pcie_dump_csr(struct iwl_trans
*trans
,
2589 struct iwl_fw_error_dump_data
**data
)
2591 u32 csr_len
= sizeof(**data
) + IWL_CSR_TO_DUMP
;
2595 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_CSR
);
2596 (*data
)->len
= cpu_to_le32(IWL_CSR_TO_DUMP
);
2597 val
= (void *)(*data
)->data
;
2599 for (i
= 0; i
< IWL_CSR_TO_DUMP
; i
+= 4)
2600 *val
++ = cpu_to_le32(iwl_trans_pcie_read32(trans
, i
));
2602 *data
= iwl_fw_error_next_data(*data
);
2607 static u32
iwl_trans_pcie_fh_regs_dump(struct iwl_trans
*trans
,
2608 struct iwl_fw_error_dump_data
**data
)
2610 u32 fh_regs_len
= FH_MEM_UPPER_BOUND
- FH_MEM_LOWER_BOUND
;
2611 unsigned long flags
;
2615 if (!iwl_trans_grab_nic_access(trans
, &flags
))
2618 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS
);
2619 (*data
)->len
= cpu_to_le32(fh_regs_len
);
2620 val
= (void *)(*data
)->data
;
2622 if (!trans
->cfg
->gen2
)
2623 for (i
= FH_MEM_LOWER_BOUND
; i
< FH_MEM_UPPER_BOUND
;
2625 *val
++ = cpu_to_le32(iwl_trans_pcie_read32(trans
, i
));
2627 for (i
= FH_MEM_LOWER_BOUND_GEN2
; i
< FH_MEM_UPPER_BOUND_GEN2
;
2629 *val
++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans
,
2632 iwl_trans_release_nic_access(trans
, &flags
);
2634 *data
= iwl_fw_error_next_data(*data
);
2636 return sizeof(**data
) + fh_regs_len
;
2640 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans
*trans
,
2641 struct iwl_fw_error_dump_fw_mon
*fw_mon_data
,
2644 u32 buf_size_in_dwords
= (monitor_len
>> 2);
2645 u32
*buffer
= (u32
*)fw_mon_data
->data
;
2646 unsigned long flags
;
2649 if (!iwl_trans_grab_nic_access(trans
, &flags
))
2652 iwl_write_prph_no_grab(trans
, MON_DMARB_RD_CTL_ADDR
, 0x1);
2653 for (i
= 0; i
< buf_size_in_dwords
; i
++)
2654 buffer
[i
] = iwl_read_prph_no_grab(trans
,
2655 MON_DMARB_RD_DATA_ADDR
);
2656 iwl_write_prph_no_grab(trans
, MON_DMARB_RD_CTL_ADDR
, 0x0);
2658 iwl_trans_release_nic_access(trans
, &flags
);
2664 iwl_trans_pcie_dump_monitor(struct iwl_trans
*trans
,
2665 struct iwl_fw_error_dump_data
**data
,
2668 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2671 if ((trans_pcie
->fw_mon_page
&&
2672 trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_7000
) ||
2673 trans
->dbg_dest_tlv
) {
2674 struct iwl_fw_error_dump_fw_mon
*fw_mon_data
;
2675 u32 base
, write_ptr
, wrap_cnt
;
2677 /* If there was a dest TLV - use the values from there */
2678 if (trans
->dbg_dest_tlv
) {
2680 le32_to_cpu(trans
->dbg_dest_tlv
->write_ptr_reg
);
2681 wrap_cnt
= le32_to_cpu(trans
->dbg_dest_tlv
->wrap_count
);
2682 base
= le32_to_cpu(trans
->dbg_dest_tlv
->base_reg
);
2684 base
= MON_BUFF_BASE_ADDR
;
2685 write_ptr
= MON_BUFF_WRPTR
;
2686 wrap_cnt
= MON_BUFF_CYCLE_CNT
;
2689 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR
);
2690 fw_mon_data
= (void *)(*data
)->data
;
2691 fw_mon_data
->fw_mon_wr_ptr
=
2692 cpu_to_le32(iwl_read_prph(trans
, write_ptr
));
2693 fw_mon_data
->fw_mon_cycle_cnt
=
2694 cpu_to_le32(iwl_read_prph(trans
, wrap_cnt
));
2695 fw_mon_data
->fw_mon_base_ptr
=
2696 cpu_to_le32(iwl_read_prph(trans
, base
));
2698 len
+= sizeof(**data
) + sizeof(*fw_mon_data
);
2699 if (trans_pcie
->fw_mon_page
) {
2701 * The firmware is now asserted, it won't write anything
2702 * to the buffer. CPU can take ownership to fetch the
2703 * data. The buffer will be handed back to the device
2704 * before the firmware will be restarted.
2706 dma_sync_single_for_cpu(trans
->dev
,
2707 trans_pcie
->fw_mon_phys
,
2708 trans_pcie
->fw_mon_size
,
2710 memcpy(fw_mon_data
->data
,
2711 page_address(trans_pcie
->fw_mon_page
),
2712 trans_pcie
->fw_mon_size
);
2714 monitor_len
= trans_pcie
->fw_mon_size
;
2715 } else if (trans
->dbg_dest_tlv
->monitor_mode
== SMEM_MODE
) {
2717 * Update pointers to reflect actual values after
2720 base
= iwl_read_prph(trans
, base
) <<
2721 trans
->dbg_dest_tlv
->base_shift
;
2722 iwl_trans_read_mem(trans
, base
, fw_mon_data
->data
,
2723 monitor_len
/ sizeof(u32
));
2724 } else if (trans
->dbg_dest_tlv
->monitor_mode
== MARBH_MODE
) {
2726 iwl_trans_pci_dump_marbh_monitor(trans
,
2730 /* Didn't match anything - output no monitor data */
2735 (*data
)->len
= cpu_to_le32(monitor_len
+ sizeof(*fw_mon_data
));
2741 static struct iwl_trans_dump_data
2742 *iwl_trans_pcie_dump_data(struct iwl_trans
*trans
,
2743 const struct iwl_fw_dbg_trigger_tlv
*trigger
)
2745 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2746 struct iwl_fw_error_dump_data
*data
;
2747 struct iwl_txq
*cmdq
= trans_pcie
->txq
[trans_pcie
->cmd_queue
];
2748 struct iwl_fw_error_dump_txcmd
*txcmd
;
2749 struct iwl_trans_dump_data
*dump_data
;
2753 bool dump_rbs
= test_bit(STATUS_FW_ERROR
, &trans
->status
) &&
2754 !trans
->cfg
->mq_rx_supported
;
2756 /* transport dump header */
2757 len
= sizeof(*dump_data
);
2760 len
+= sizeof(*data
) +
2761 cmdq
->n_window
* (sizeof(*txcmd
) + TFD_MAX_PAYLOAD_SIZE
);
2764 if (trans_pcie
->fw_mon_page
) {
2765 len
+= sizeof(*data
) + sizeof(struct iwl_fw_error_dump_fw_mon
) +
2766 trans_pcie
->fw_mon_size
;
2767 monitor_len
= trans_pcie
->fw_mon_size
;
2768 } else if (trans
->dbg_dest_tlv
) {
2771 base
= le32_to_cpu(trans
->dbg_dest_tlv
->base_reg
);
2772 end
= le32_to_cpu(trans
->dbg_dest_tlv
->end_reg
);
2774 base
= iwl_read_prph(trans
, base
) <<
2775 trans
->dbg_dest_tlv
->base_shift
;
2776 end
= iwl_read_prph(trans
, end
) <<
2777 trans
->dbg_dest_tlv
->end_shift
;
2779 /* Make "end" point to the actual end */
2780 if (trans
->cfg
->device_family
>= IWL_DEVICE_FAMILY_8000
||
2781 trans
->dbg_dest_tlv
->monitor_mode
== MARBH_MODE
)
2782 end
+= (1 << trans
->dbg_dest_tlv
->end_shift
);
2783 monitor_len
= end
- base
;
2784 len
+= sizeof(*data
) + sizeof(struct iwl_fw_error_dump_fw_mon
) +
2790 if (trigger
&& (trigger
->mode
& IWL_FW_DBG_TRIGGER_MONITOR_ONLY
)) {
2791 dump_data
= vzalloc(len
);
2795 data
= (void *)dump_data
->data
;
2796 len
= iwl_trans_pcie_dump_monitor(trans
, &data
, monitor_len
);
2797 dump_data
->len
= len
;
2803 len
+= sizeof(*data
) + IWL_CSR_TO_DUMP
;
2806 if (trans
->cfg
->gen2
)
2807 len
+= sizeof(*data
) +
2808 (FH_MEM_UPPER_BOUND_GEN2
- FH_MEM_LOWER_BOUND_GEN2
);
2810 len
+= sizeof(*data
) +
2811 (FH_MEM_UPPER_BOUND
- FH_MEM_LOWER_BOUND
);
2814 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2815 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
[0];
2817 num_rbs
= le16_to_cpu(READ_ONCE(rxq
->rb_stts
->closed_rb_num
))
2819 num_rbs
= (num_rbs
- rxq
->read
) & RX_QUEUE_MASK
;
2820 len
+= num_rbs
* (sizeof(*data
) +
2821 sizeof(struct iwl_fw_error_dump_rb
) +
2822 (PAGE_SIZE
<< trans_pcie
->rx_page_order
));
2825 /* Paged memory for gen2 HW */
2826 if (trans
->cfg
->gen2
)
2827 for (i
= 0; i
< trans_pcie
->init_dram
.paging_cnt
; i
++)
2828 len
+= sizeof(*data
) +
2829 sizeof(struct iwl_fw_error_dump_paging
) +
2830 trans_pcie
->init_dram
.paging
[i
].size
;
2832 dump_data
= vzalloc(len
);
2837 data
= (void *)dump_data
->data
;
2838 data
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD
);
2839 txcmd
= (void *)data
->data
;
2840 spin_lock_bh(&cmdq
->lock
);
2841 ptr
= cmdq
->write_ptr
;
2842 for (i
= 0; i
< cmdq
->n_window
; i
++) {
2843 u8 idx
= iwl_pcie_get_cmd_index(cmdq
, ptr
);
2846 cmdlen
= iwl_trans_pcie_get_cmdlen(trans
, cmdq
->tfds
+
2847 trans_pcie
->tfd_size
* ptr
);
2848 caplen
= min_t(u32
, TFD_MAX_PAYLOAD_SIZE
, cmdlen
);
2851 len
+= sizeof(*txcmd
) + caplen
;
2852 txcmd
->cmdlen
= cpu_to_le32(cmdlen
);
2853 txcmd
->caplen
= cpu_to_le32(caplen
);
2854 memcpy(txcmd
->data
, cmdq
->entries
[idx
].cmd
, caplen
);
2855 txcmd
= (void *)((u8
*)txcmd
->data
+ caplen
);
2858 ptr
= iwl_queue_dec_wrap(ptr
);
2860 spin_unlock_bh(&cmdq
->lock
);
2862 data
->len
= cpu_to_le32(len
);
2863 len
+= sizeof(*data
);
2864 data
= iwl_fw_error_next_data(data
);
2866 len
+= iwl_trans_pcie_dump_csr(trans
, &data
);
2867 len
+= iwl_trans_pcie_fh_regs_dump(trans
, &data
);
2869 len
+= iwl_trans_pcie_dump_rbs(trans
, &data
, num_rbs
);
2871 /* Paged memory for gen2 HW */
2872 if (trans
->cfg
->gen2
) {
2873 for (i
= 0; i
< trans_pcie
->init_dram
.paging_cnt
; i
++) {
2874 struct iwl_fw_error_dump_paging
*paging
;
2876 trans_pcie
->init_dram
.paging
[i
].physical
;
2877 u32 page_len
= trans_pcie
->init_dram
.paging
[i
].size
;
2879 data
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING
);
2880 data
->len
= cpu_to_le32(sizeof(*paging
) + page_len
);
2881 paging
= (void *)data
->data
;
2882 paging
->index
= cpu_to_le32(i
);
2883 dma_sync_single_for_cpu(trans
->dev
, addr
, page_len
,
2885 memcpy(paging
->data
,
2886 trans_pcie
->init_dram
.paging
[i
].block
, page_len
);
2887 data
= iwl_fw_error_next_data(data
);
2889 len
+= sizeof(*data
) + sizeof(*paging
) + page_len
;
2893 len
+= iwl_trans_pcie_dump_monitor(trans
, &data
, monitor_len
);
2895 dump_data
->len
= len
;
2900 #ifdef CONFIG_PM_SLEEP
2901 static int iwl_trans_pcie_suspend(struct iwl_trans
*trans
)
2903 if (trans
->runtime_pm_mode
== IWL_PLAT_PM_MODE_D0I3
&&
2904 (trans
->system_pm_mode
== IWL_PLAT_PM_MODE_D0I3
))
2905 return iwl_pci_fw_enter_d0i3(trans
);
2910 static void iwl_trans_pcie_resume(struct iwl_trans
*trans
)
2912 if (trans
->runtime_pm_mode
== IWL_PLAT_PM_MODE_D0I3
&&
2913 (trans
->system_pm_mode
== IWL_PLAT_PM_MODE_D0I3
))
2914 iwl_pci_fw_exit_d0i3(trans
);
2916 #endif /* CONFIG_PM_SLEEP */
2918 #define IWL_TRANS_COMMON_OPS \
2919 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \
2920 .write8 = iwl_trans_pcie_write8, \
2921 .write32 = iwl_trans_pcie_write32, \
2922 .read32 = iwl_trans_pcie_read32, \
2923 .read_prph = iwl_trans_pcie_read_prph, \
2924 .write_prph = iwl_trans_pcie_write_prph, \
2925 .read_mem = iwl_trans_pcie_read_mem, \
2926 .write_mem = iwl_trans_pcie_write_mem, \
2927 .configure = iwl_trans_pcie_configure, \
2928 .set_pmi = iwl_trans_pcie_set_pmi, \
2929 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \
2930 .release_nic_access = iwl_trans_pcie_release_nic_access, \
2931 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \
2932 .ref = iwl_trans_pcie_ref, \
2933 .unref = iwl_trans_pcie_unref, \
2934 .dump_data = iwl_trans_pcie_dump_data, \
2935 .d3_suspend = iwl_trans_pcie_d3_suspend, \
2936 .d3_resume = iwl_trans_pcie_d3_resume
2938 #ifdef CONFIG_PM_SLEEP
2939 #define IWL_TRANS_PM_OPS \
2940 .suspend = iwl_trans_pcie_suspend, \
2941 .resume = iwl_trans_pcie_resume,
2943 #define IWL_TRANS_PM_OPS
2944 #endif /* CONFIG_PM_SLEEP */
2946 static const struct iwl_trans_ops trans_ops_pcie
= {
2947 IWL_TRANS_COMMON_OPS
,
2949 .start_hw
= iwl_trans_pcie_start_hw
,
2950 .fw_alive
= iwl_trans_pcie_fw_alive
,
2951 .start_fw
= iwl_trans_pcie_start_fw
,
2952 .stop_device
= iwl_trans_pcie_stop_device
,
2954 .send_cmd
= iwl_trans_pcie_send_hcmd
,
2956 .tx
= iwl_trans_pcie_tx
,
2957 .reclaim
= iwl_trans_pcie_reclaim
,
2959 .txq_disable
= iwl_trans_pcie_txq_disable
,
2960 .txq_enable
= iwl_trans_pcie_txq_enable
,
2962 .txq_set_shared_mode
= iwl_trans_pcie_txq_set_shared_mode
,
2964 .wait_tx_queues_empty
= iwl_trans_pcie_wait_txqs_empty
,
2966 .freeze_txq_timer
= iwl_trans_pcie_freeze_txq_timer
,
2967 .block_txq_ptrs
= iwl_trans_pcie_block_txq_ptrs
,
2970 static const struct iwl_trans_ops trans_ops_pcie_gen2
= {
2971 IWL_TRANS_COMMON_OPS
,
2973 .start_hw
= iwl_trans_pcie_start_hw
,
2974 .fw_alive
= iwl_trans_pcie_gen2_fw_alive
,
2975 .start_fw
= iwl_trans_pcie_gen2_start_fw
,
2976 .stop_device
= iwl_trans_pcie_gen2_stop_device
,
2978 .send_cmd
= iwl_trans_pcie_gen2_send_hcmd
,
2980 .tx
= iwl_trans_pcie_gen2_tx
,
2981 .reclaim
= iwl_trans_pcie_reclaim
,
2983 .txq_alloc
= iwl_trans_pcie_dyn_txq_alloc
,
2984 .txq_free
= iwl_trans_pcie_dyn_txq_free
,
2985 .wait_txq_empty
= iwl_trans_pcie_wait_txq_empty
,
2988 struct iwl_trans
*iwl_trans_pcie_alloc(struct pci_dev
*pdev
,
2989 const struct pci_device_id
*ent
,
2990 const struct iwl_cfg
*cfg
)
2992 struct iwl_trans_pcie
*trans_pcie
;
2993 struct iwl_trans
*trans
;
2996 ret
= pcim_enable_device(pdev
);
2998 return ERR_PTR(ret
);
3001 trans
= iwl_trans_alloc(sizeof(struct iwl_trans_pcie
),
3002 &pdev
->dev
, cfg
, &trans_ops_pcie_gen2
);
3004 trans
= iwl_trans_alloc(sizeof(struct iwl_trans_pcie
),
3005 &pdev
->dev
, cfg
, &trans_ops_pcie
);
3007 return ERR_PTR(-ENOMEM
);
3009 trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
3011 trans_pcie
->trans
= trans
;
3012 trans_pcie
->opmode_down
= true;
3013 spin_lock_init(&trans_pcie
->irq_lock
);
3014 spin_lock_init(&trans_pcie
->reg_lock
);
3015 mutex_init(&trans_pcie
->mutex
);
3016 init_waitqueue_head(&trans_pcie
->ucode_write_waitq
);
3017 trans_pcie
->tso_hdr_page
= alloc_percpu(struct iwl_tso_hdr_page
);
3018 if (!trans_pcie
->tso_hdr_page
) {
3024 if (!cfg
->base_params
->pcie_l1_allowed
) {
3026 * W/A - seems to solve weird behavior. We need to remove this
3027 * if we don't want to stay in L1 all the time. This wastes a
3030 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
|
3031 PCIE_LINK_STATE_L1
|
3032 PCIE_LINK_STATE_CLKPM
);
3037 trans_pcie
->max_tbs
= IWL_TFH_NUM_TBS
;
3038 trans_pcie
->tfd_size
= sizeof(struct iwl_tfh_tfd
);
3041 trans_pcie
->max_tbs
= IWL_NUM_OF_TBS
;
3042 trans_pcie
->tfd_size
= sizeof(struct iwl_tfd
);
3044 trans
->max_skb_frags
= IWL_PCIE_MAX_FRAGS(trans_pcie
);
3046 pci_set_master(pdev
);
3048 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(addr_size
));
3050 ret
= pci_set_consistent_dma_mask(pdev
,
3051 DMA_BIT_MASK(addr_size
));
3053 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3055 ret
= pci_set_consistent_dma_mask(pdev
,
3057 /* both attempts failed: */
3059 dev_err(&pdev
->dev
, "No suitable DMA available\n");
3064 ret
= pcim_iomap_regions_request_all(pdev
, BIT(0), DRV_NAME
);
3066 dev_err(&pdev
->dev
, "pcim_iomap_regions_request_all failed\n");
3070 trans_pcie
->hw_base
= pcim_iomap_table(pdev
)[0];
3071 if (!trans_pcie
->hw_base
) {
3072 dev_err(&pdev
->dev
, "pcim_iomap_table failed\n");
3077 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3078 * PCI Tx retries from interfering with C3 CPU state */
3079 pci_write_config_byte(pdev
, PCI_CFG_RETRY_TIMEOUT
, 0x00);
3081 trans_pcie
->pci_dev
= pdev
;
3082 iwl_disable_interrupts(trans
);
3084 trans
->hw_rev
= iwl_read32(trans
, CSR_HW_REV
);
3086 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3087 * changed, and now the revision step also includes bit 0-1 (no more
3088 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3089 * in the old format.
3091 if (trans
->cfg
->device_family
>= IWL_DEVICE_FAMILY_8000
) {
3092 unsigned long flags
;
3094 trans
->hw_rev
= (trans
->hw_rev
& 0xfff0) |
3095 (CSR_HW_REV_STEP(trans
->hw_rev
<< 2) << 2);
3097 ret
= iwl_pcie_prepare_card_hw(trans
);
3099 IWL_WARN(trans
, "Exit HW not ready\n");
3104 * in-order to recognize C step driver should read chip version
3105 * id located at the AUX bus MISC address space.
3107 iwl_set_bit(trans
, CSR_GP_CNTRL
,
3108 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
3111 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
3112 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
3113 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
3116 IWL_DEBUG_INFO(trans
, "Failed to wake up the nic\n");
3120 if (iwl_trans_grab_nic_access(trans
, &flags
)) {
3123 hw_step
= iwl_read_prph_no_grab(trans
, WFPM_CTRL_REG
);
3124 hw_step
|= ENABLE_WFPM
;
3125 iwl_write_prph_no_grab(trans
, WFPM_CTRL_REG
, hw_step
);
3126 hw_step
= iwl_read_prph_no_grab(trans
, AUX_MISC_REG
);
3127 hw_step
= (hw_step
>> HW_STEP_LOCATION_BITS
) & 0xF;
3129 trans
->hw_rev
= (trans
->hw_rev
& 0xFFFFFFF3) |
3130 (SILICON_C_STEP
<< 2);
3131 iwl_trans_release_nic_access(trans
, &flags
);
3136 * 9000-series integrated A-step has a problem with suspend/resume
3137 * and sometimes even causes the whole platform to get stuck. This
3138 * workaround makes the hardware not go into the problematic state.
3140 if (trans
->cfg
->integrated
&&
3141 trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_9000
&&
3142 CSR_HW_REV_STEP(trans
->hw_rev
) == SILICON_A_STEP
)
3143 iwl_set_bit(trans
, CSR_HOST_CHICKEN
,
3144 CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME
);
3146 #if IS_ENABLED(CONFIG_IWLMVM)
3147 trans
->hw_rf_id
= iwl_read32(trans
, CSR_HW_RF_ID
);
3148 if (trans
->hw_rf_id
== CSR_HW_RF_ID_TYPE_HR
) {
3151 hw_status
= iwl_read_prph(trans
, UMAG_GEN_HW_STATUS
);
3152 if (hw_status
& UMAG_GEN_HW_IS_FPGA
)
3153 trans
->cfg
= &iwla000_2ax_cfg_qnj_hr_f0
;
3155 trans
->cfg
= &iwla000_2ac_cfg_hr
;
3159 iwl_pcie_set_interrupt_capa(pdev
, trans
);
3160 trans
->hw_id
= (pdev
->device
<< 16) + pdev
->subsystem_device
;
3161 snprintf(trans
->hw_id_str
, sizeof(trans
->hw_id_str
),
3162 "PCI ID: 0x%04X:0x%04X", pdev
->device
, pdev
->subsystem_device
);
3164 /* Initialize the wait queue for commands */
3165 init_waitqueue_head(&trans_pcie
->wait_command_queue
);
3167 init_waitqueue_head(&trans_pcie
->d0i3_waitq
);
3169 if (trans_pcie
->msix_enabled
) {
3170 ret
= iwl_pcie_init_msix_handler(pdev
, trans_pcie
);
3174 ret
= iwl_pcie_alloc_ict(trans
);
3178 ret
= devm_request_threaded_irq(&pdev
->dev
, pdev
->irq
,
3180 iwl_pcie_irq_handler
,
3181 IRQF_SHARED
, DRV_NAME
, trans
);
3183 IWL_ERR(trans
, "Error allocating IRQ %d\n", pdev
->irq
);
3186 trans_pcie
->inta_mask
= CSR_INI_SET_MASK
;
3189 trans_pcie
->rba
.alloc_wq
= alloc_workqueue("rb_allocator",
3190 WQ_HIGHPRI
| WQ_UNBOUND
, 1);
3191 INIT_WORK(&trans_pcie
->rba
.rx_alloc
, iwl_pcie_rx_allocator_work
);
3193 #ifdef CONFIG_IWLWIFI_PCIE_RTPM
3194 trans
->runtime_pm_mode
= IWL_PLAT_PM_MODE_D0I3
;
3196 trans
->runtime_pm_mode
= IWL_PLAT_PM_MODE_DISABLED
;
3197 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */
3202 iwl_pcie_free_ict(trans
);
3204 free_percpu(trans_pcie
->tso_hdr_page
);
3205 iwl_trans_free(trans
);
3206 return ERR_PTR(ret
);