1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 Intel Deutschland GmbH
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
26 * The full GNU General Public License is included in this distribution
27 * in the file called COPYING.
29 * Contact Information:
30 * Intel Linux Wireless <linuxwifi@intel.com>
31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
37 * Copyright(c) 2016 Intel Deutschland GmbH
38 * All rights reserved.
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
44 * * Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
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47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
50 * * Neither the name Intel Corporation nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific prior written permission.
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 *****************************************************************************/
67 #include <linux/pci.h>
68 #include <linux/pci-aspm.h>
69 #include <linux/interrupt.h>
70 #include <linux/debugfs.h>
71 #include <linux/sched.h>
72 #include <linux/bitops.h>
73 #include <linux/gfp.h>
74 #include <linux/vmalloc.h>
77 #include "iwl-trans.h"
81 #include "iwl-agn-hw.h"
82 #include "iwl-fw-error-dump.h"
86 /* extended range in FW SRAM */
87 #define IWL_FW_MEM_EXTENDED_START 0x40000
88 #define IWL_FW_MEM_EXTENDED_END 0x57FFF
90 static void iwl_pcie_free_fw_monitor(struct iwl_trans
*trans
)
92 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
94 if (!trans_pcie
->fw_mon_page
)
97 dma_unmap_page(trans
->dev
, trans_pcie
->fw_mon_phys
,
98 trans_pcie
->fw_mon_size
, DMA_FROM_DEVICE
);
99 __free_pages(trans_pcie
->fw_mon_page
,
100 get_order(trans_pcie
->fw_mon_size
));
101 trans_pcie
->fw_mon_page
= NULL
;
102 trans_pcie
->fw_mon_phys
= 0;
103 trans_pcie
->fw_mon_size
= 0;
106 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans
*trans
, u8 max_power
)
108 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
109 struct page
*page
= NULL
;
115 /* default max_power is maximum */
121 if (WARN(max_power
> 26,
122 "External buffer size for monitor is too big %d, check the FW TLV\n",
126 if (trans_pcie
->fw_mon_page
) {
127 dma_sync_single_for_device(trans
->dev
, trans_pcie
->fw_mon_phys
,
128 trans_pcie
->fw_mon_size
,
134 for (power
= max_power
; power
>= 11; power
--) {
138 order
= get_order(size
);
139 page
= alloc_pages(__GFP_COMP
| __GFP_NOWARN
| __GFP_ZERO
,
144 phys
= dma_map_page(trans
->dev
, page
, 0, PAGE_SIZE
<< order
,
146 if (dma_mapping_error(trans
->dev
, phys
)) {
147 __free_pages(page
, order
);
152 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
157 if (WARN_ON_ONCE(!page
))
160 if (power
!= max_power
)
162 "Sorry - debug buffer is only %luK while you requested %luK\n",
163 (unsigned long)BIT(power
- 10),
164 (unsigned long)BIT(max_power
- 10));
166 trans_pcie
->fw_mon_page
= page
;
167 trans_pcie
->fw_mon_phys
= phys
;
168 trans_pcie
->fw_mon_size
= size
;
171 static u32
iwl_trans_pcie_read_shr(struct iwl_trans
*trans
, u32 reg
)
173 iwl_write32(trans
, HEEP_CTRL_WRD_PCIEX_CTRL_REG
,
174 ((reg
& 0x0000ffff) | (2 << 28)));
175 return iwl_read32(trans
, HEEP_CTRL_WRD_PCIEX_DATA_REG
);
178 static void iwl_trans_pcie_write_shr(struct iwl_trans
*trans
, u32 reg
, u32 val
)
180 iwl_write32(trans
, HEEP_CTRL_WRD_PCIEX_DATA_REG
, val
);
181 iwl_write32(trans
, HEEP_CTRL_WRD_PCIEX_CTRL_REG
,
182 ((reg
& 0x0000ffff) | (3 << 28)));
185 static void iwl_pcie_set_pwr(struct iwl_trans
*trans
, bool vaux
)
187 if (trans
->cfg
->apmg_not_supported
)
190 if (vaux
&& pci_pme_capable(to_pci_dev(trans
->dev
), PCI_D3cold
))
191 iwl_set_bits_mask_prph(trans
, APMG_PS_CTRL_REG
,
192 APMG_PS_CTRL_VAL_PWR_SRC_VAUX
,
193 ~APMG_PS_CTRL_MSK_PWR_SRC
);
195 iwl_set_bits_mask_prph(trans
, APMG_PS_CTRL_REG
,
196 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
,
197 ~APMG_PS_CTRL_MSK_PWR_SRC
);
201 #define PCI_CFG_RETRY_TIMEOUT 0x041
203 static void iwl_pcie_apm_config(struct iwl_trans
*trans
)
205 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
210 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
211 * Check if BIOS (or OS) enabled L1-ASPM on this device.
212 * If so (likely), disable L0S, so device moves directly L0->L1;
213 * costs negligible amount of power savings.
214 * If not (unlikely), enable L0S, so there is at least some
215 * power savings, even without L1.
217 pcie_capability_read_word(trans_pcie
->pci_dev
, PCI_EXP_LNKCTL
, &lctl
);
218 if (lctl
& PCI_EXP_LNKCTL_ASPM_L1
)
219 iwl_set_bit(trans
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
221 iwl_clear_bit(trans
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
222 trans
->pm_support
= !(lctl
& PCI_EXP_LNKCTL_ASPM_L0S
);
224 pcie_capability_read_word(trans_pcie
->pci_dev
, PCI_EXP_DEVCTL2
, &cap
);
225 trans
->ltr_enabled
= cap
& PCI_EXP_DEVCTL2_LTR_EN
;
226 dev_info(trans
->dev
, "L1 %sabled - LTR %sabled\n",
227 (lctl
& PCI_EXP_LNKCTL_ASPM_L1
) ? "En" : "Dis",
228 trans
->ltr_enabled
? "En" : "Dis");
232 * Start up NIC's basic functionality after it has been reset
233 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
234 * NOTE: This does not load uCode nor start the embedded processor
236 static int iwl_pcie_apm_init(struct iwl_trans
*trans
)
239 IWL_DEBUG_INFO(trans
, "Init card's basic functions\n");
242 * Use "set_bit" below rather than "write", to preserve any hardware
243 * bits already set by default after reset.
246 /* Disable L0S exit timer (platform NMI Work/Around) */
247 if (trans
->cfg
->device_family
!= IWL_DEVICE_FAMILY_8000
)
248 iwl_set_bit(trans
, CSR_GIO_CHICKEN_BITS
,
249 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER
);
252 * Disable L0s without affecting L1;
253 * don't wait for ICH L0s (ICH bug W/A)
255 iwl_set_bit(trans
, CSR_GIO_CHICKEN_BITS
,
256 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX
);
258 /* Set FH wait threshold to maximum (HW error during stress W/A) */
259 iwl_set_bit(trans
, CSR_DBG_HPET_MEM_REG
, CSR_DBG_HPET_MEM_REG_VAL
);
262 * Enable HAP INTA (interrupt from management bus) to
263 * wake device's PCI Express link L1a -> L0s
265 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
266 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A
);
268 iwl_pcie_apm_config(trans
);
270 /* Configure analog phase-lock-loop before activating to D0A */
271 if (trans
->cfg
->base_params
->pll_cfg_val
)
272 iwl_set_bit(trans
, CSR_ANA_PLL_CFG
,
273 trans
->cfg
->base_params
->pll_cfg_val
);
276 * Set "initialization complete" bit to move adapter from
277 * D0U* --> D0A* (powered-up active) state.
279 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
282 * Wait for clock stabilization; once stabilized, access to
283 * device-internal resources is supported, e.g. iwl_write_prph()
284 * and accesses to uCode SRAM.
286 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
287 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
, 25000);
290 IWL_DEBUG_INFO(trans
, "Failed to init the card\n");
294 if (trans
->cfg
->host_interrupt_operation_mode
) {
296 * This is a bit of an abuse - This is needed for 7260 / 3160
297 * only check host_interrupt_operation_mode even if this is
298 * not related to host_interrupt_operation_mode.
300 * Enable the oscillator to count wake up time for L1 exit. This
301 * consumes slightly more power (100uA) - but allows to be sure
302 * that we wake up from L1 on time.
304 * This looks weird: read twice the same register, discard the
305 * value, set a bit, and yet again, read that same register
306 * just to discard the value. But that's the way the hardware
309 iwl_read_prph(trans
, OSC_CLK
);
310 iwl_read_prph(trans
, OSC_CLK
);
311 iwl_set_bits_prph(trans
, OSC_CLK
, OSC_CLK_FORCE_CONTROL
);
312 iwl_read_prph(trans
, OSC_CLK
);
313 iwl_read_prph(trans
, OSC_CLK
);
317 * Enable DMA clock and wait for it to stabilize.
319 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
320 * bits do not disable clocks. This preserves any hardware
321 * bits already set by default in "CLK_CTRL_REG" after reset.
323 if (!trans
->cfg
->apmg_not_supported
) {
324 iwl_write_prph(trans
, APMG_CLK_EN_REG
,
325 APMG_CLK_VAL_DMA_CLK_RQT
);
328 /* Disable L1-Active */
329 iwl_set_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
330 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
332 /* Clear the interrupt in APMG if the NIC is in RFKILL */
333 iwl_write_prph(trans
, APMG_RTC_INT_STT_REG
,
334 APMG_RTC_INT_STT_RFKILL
);
337 set_bit(STATUS_DEVICE_ENABLED
, &trans
->status
);
344 * Enable LP XTAL to avoid HW bug where device may consume much power if
345 * FW is not loaded after device reset. LP XTAL is disabled by default
346 * after device HW reset. Do it only if XTAL is fed by internal source.
347 * Configure device's "persistence" mode to avoid resetting XTAL again when
348 * SHRD_HW_RST occurs in S3.
350 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans
*trans
)
354 u32 apmg_xtal_cfg_reg
;
358 __iwl_trans_pcie_set_bit(trans
, CSR_GP_CNTRL
,
359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON
);
361 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
362 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
367 * Set "initialization complete" bit to move adapter from
368 * D0U* --> D0A* (powered-up active) state.
370 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
373 * Wait for clock stabilization; once stabilized, access to
374 * device-internal resources is possible.
376 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
377 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
378 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
380 if (WARN_ON(ret
< 0)) {
381 IWL_ERR(trans
, "Access time out - failed to enable LP XTAL\n");
382 /* Release XTAL ON request */
383 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
384 CSR_GP_CNTRL_REG_FLAG_XTAL_ON
);
389 * Clear "disable persistence" to avoid LP XTAL resetting when
390 * SHRD_HW_RST is applied in S3.
392 iwl_clear_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
393 APMG_PCIDEV_STT_VAL_PERSIST_DIS
);
396 * Force APMG XTAL to be active to prevent its disabling by HW
397 * caused by APMG idle state.
399 apmg_xtal_cfg_reg
= iwl_trans_pcie_read_shr(trans
,
400 SHR_APMG_XTAL_CFG_REG
);
401 iwl_trans_pcie_write_shr(trans
, SHR_APMG_XTAL_CFG_REG
,
403 SHR_APMG_XTAL_CFG_XTAL_ON_REQ
);
406 * Reset entire device again - do controller reset (results in
407 * SHRD_HW_RST). Turn MAC off before proceeding.
409 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
413 /* Enable LP XTAL by indirect access through CSR */
414 apmg_gp1_reg
= iwl_trans_pcie_read_shr(trans
, SHR_APMG_GP1_REG
);
415 iwl_trans_pcie_write_shr(trans
, SHR_APMG_GP1_REG
, apmg_gp1_reg
|
416 SHR_APMG_GP1_WF_XTAL_LP_EN
|
417 SHR_APMG_GP1_CHICKEN_BIT_SELECT
);
419 /* Clear delay line clock power up */
420 dl_cfg_reg
= iwl_trans_pcie_read_shr(trans
, SHR_APMG_DL_CFG_REG
);
421 iwl_trans_pcie_write_shr(trans
, SHR_APMG_DL_CFG_REG
, dl_cfg_reg
&
422 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP
);
425 * Enable persistence mode to avoid LP XTAL resetting when
426 * SHRD_HW_RST is applied in S3.
428 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
429 CSR_HW_IF_CONFIG_REG_PERSIST_MODE
);
432 * Clear "initialization complete" bit to move adapter from
433 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
435 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
436 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
438 /* Activates XTAL resources monitor */
439 __iwl_trans_pcie_set_bit(trans
, CSR_MONITOR_CFG_REG
,
440 CSR_MONITOR_XTAL_RESOURCES
);
442 /* Release XTAL ON request */
443 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
444 CSR_GP_CNTRL_REG_FLAG_XTAL_ON
);
447 /* Release APMG XTAL */
448 iwl_trans_pcie_write_shr(trans
, SHR_APMG_XTAL_CFG_REG
,
450 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ
);
453 static int iwl_pcie_apm_stop_master(struct iwl_trans
*trans
)
457 /* stop device's busmaster DMA activity */
458 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_STOP_MASTER
);
460 ret
= iwl_poll_bit(trans
, CSR_RESET
,
461 CSR_RESET_REG_FLAG_MASTER_DISABLED
,
462 CSR_RESET_REG_FLAG_MASTER_DISABLED
, 100);
464 IWL_WARN(trans
, "Master Disable Timed Out, 100 usec\n");
466 IWL_DEBUG_INFO(trans
, "stop master\n");
471 static void iwl_pcie_apm_stop(struct iwl_trans
*trans
, bool op_mode_leave
)
473 IWL_DEBUG_INFO(trans
, "Stop card, put in low power state\n");
476 if (!test_bit(STATUS_DEVICE_ENABLED
, &trans
->status
))
477 iwl_pcie_apm_init(trans
);
479 /* inform ME that we are leaving */
480 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_7000
)
481 iwl_set_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
482 APMG_PCIDEV_STT_VAL_WAKE_ME
);
483 else if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
) {
484 iwl_set_bit(trans
, CSR_DBG_LINK_PWR_MGMT_REG
,
485 CSR_RESET_LINK_PWR_MGMT_DISABLED
);
486 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
487 CSR_HW_IF_CONFIG_REG_PREPARE
|
488 CSR_HW_IF_CONFIG_REG_ENABLE_PME
);
490 iwl_clear_bit(trans
, CSR_DBG_LINK_PWR_MGMT_REG
,
491 CSR_RESET_LINK_PWR_MGMT_DISABLED
);
496 clear_bit(STATUS_DEVICE_ENABLED
, &trans
->status
);
498 /* Stop device's DMA activity */
499 iwl_pcie_apm_stop_master(trans
);
501 if (trans
->cfg
->lp_xtal_workaround
) {
502 iwl_pcie_apm_lp_xtal_enable(trans
);
506 /* Reset the entire device */
507 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
512 * Clear "initialization complete" bit to move adapter from
513 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
515 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
516 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
519 static int iwl_pcie_nic_init(struct iwl_trans
*trans
)
521 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
524 spin_lock(&trans_pcie
->irq_lock
);
525 iwl_pcie_apm_init(trans
);
527 spin_unlock(&trans_pcie
->irq_lock
);
529 iwl_pcie_set_pwr(trans
, false);
531 iwl_op_mode_nic_config(trans
->op_mode
);
533 /* Allocate the RX queue, or reset if it is already allocated */
534 iwl_pcie_rx_init(trans
);
536 /* Allocate or reset and init all Tx and Command queues */
537 if (iwl_pcie_tx_init(trans
))
540 if (trans
->cfg
->base_params
->shadow_reg_enable
) {
541 /* enable shadow regs in HW */
542 iwl_set_bit(trans
, CSR_MAC_SHADOW_REG_CTRL
, 0x800FFFFF);
543 IWL_DEBUG_INFO(trans
, "Enabling shadow registers in device\n");
549 #define HW_READY_TIMEOUT (50)
551 /* Note: returns poll_bit return value, which is >= 0 if success */
552 static int iwl_pcie_set_hw_ready(struct iwl_trans
*trans
)
556 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
557 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
);
559 /* See if we got it */
560 ret
= iwl_poll_bit(trans
, CSR_HW_IF_CONFIG_REG
,
561 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
562 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
566 iwl_set_bit(trans
, CSR_MBOX_SET_REG
, CSR_MBOX_SET_REG_OS_ALIVE
);
568 IWL_DEBUG_INFO(trans
, "hardware%s ready\n", ret
< 0 ? " not" : "");
572 /* Note: returns standard 0/-ERROR code */
573 static int iwl_pcie_prepare_card_hw(struct iwl_trans
*trans
)
579 IWL_DEBUG_INFO(trans
, "iwl_trans_prepare_card_hw enter\n");
581 ret
= iwl_pcie_set_hw_ready(trans
);
582 /* If the card is ready, exit 0 */
586 iwl_set_bit(trans
, CSR_DBG_LINK_PWR_MGMT_REG
,
587 CSR_RESET_LINK_PWR_MGMT_DISABLED
);
590 for (iter
= 0; iter
< 10; iter
++) {
591 /* If HW is not ready, prepare the conditions to check again */
592 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
593 CSR_HW_IF_CONFIG_REG_PREPARE
);
596 ret
= iwl_pcie_set_hw_ready(trans
);
600 usleep_range(200, 1000);
602 } while (t
< 150000);
606 IWL_ERR(trans
, "Couldn't prepare the card\n");
614 static int iwl_pcie_load_firmware_chunk(struct iwl_trans
*trans
, u32 dst_addr
,
615 dma_addr_t phy_addr
, u32 byte_cnt
)
617 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
620 trans_pcie
->ucode_write_complete
= false;
622 iwl_write_direct32(trans
,
623 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
624 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE
);
626 iwl_write_direct32(trans
,
627 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL
),
630 iwl_write_direct32(trans
,
631 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL
),
632 phy_addr
& FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK
);
634 iwl_write_direct32(trans
,
635 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL
),
636 (iwl_get_dma_hi_addr(phy_addr
)
637 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT
) | byte_cnt
);
639 iwl_write_direct32(trans
,
640 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL
),
641 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM
|
642 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX
|
643 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID
);
645 iwl_write_direct32(trans
,
646 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
647 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
648 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE
|
649 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD
);
651 ret
= wait_event_timeout(trans_pcie
->ucode_write_waitq
,
652 trans_pcie
->ucode_write_complete
, 5 * HZ
);
654 IWL_ERR(trans
, "Failed to load firmware chunk!\n");
661 static int iwl_pcie_load_section(struct iwl_trans
*trans
, u8 section_num
,
662 const struct fw_desc
*section
)
666 u32 offset
, chunk_sz
= min_t(u32
, FH_MEM_TB_MAX_LENGTH
, section
->len
);
669 IWL_DEBUG_FW(trans
, "[%d] uCode section being loaded...\n",
672 v_addr
= dma_alloc_coherent(trans
->dev
, chunk_sz
, &p_addr
,
673 GFP_KERNEL
| __GFP_NOWARN
);
675 IWL_DEBUG_INFO(trans
, "Falling back to small chunks of DMA\n");
676 chunk_sz
= PAGE_SIZE
;
677 v_addr
= dma_alloc_coherent(trans
->dev
, chunk_sz
,
678 &p_addr
, GFP_KERNEL
);
683 for (offset
= 0; offset
< section
->len
; offset
+= chunk_sz
) {
684 u32 copy_size
, dst_addr
;
685 bool extended_addr
= false;
687 copy_size
= min_t(u32
, chunk_sz
, section
->len
- offset
);
688 dst_addr
= section
->offset
+ offset
;
690 if (dst_addr
>= IWL_FW_MEM_EXTENDED_START
&&
691 dst_addr
<= IWL_FW_MEM_EXTENDED_END
)
692 extended_addr
= true;
695 iwl_set_bits_prph(trans
, LMPM_CHICK
,
696 LMPM_CHICK_EXTENDED_ADDR_SPACE
);
698 memcpy(v_addr
, (u8
*)section
->data
+ offset
, copy_size
);
699 ret
= iwl_pcie_load_firmware_chunk(trans
, dst_addr
, p_addr
,
703 iwl_clear_bits_prph(trans
, LMPM_CHICK
,
704 LMPM_CHICK_EXTENDED_ADDR_SPACE
);
708 "Could not load the [%d] uCode section\n",
714 dma_free_coherent(trans
->dev
, chunk_sz
, v_addr
, p_addr
);
719 * Driver Takes the ownership on secure machine before FW load
720 * and prevent race with the BT load.
721 * W/A for ROM bug. (should be remove in the next Si step)
723 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans
*trans
)
725 u32 val
, loop
= 1000;
728 * Check the RSA semaphore is accessible.
729 * If the HW isn't locked and the rsa semaphore isn't accessible,
732 val
= iwl_read_prph(trans
, PREG_AUX_BUS_WPROT_0
);
733 if (val
& (BIT(1) | BIT(17))) {
735 "can't access the RSA semaphore it is write protected\n");
739 /* take ownership on the AUX IF */
740 iwl_write_prph(trans
, WFPM_CTRL_REG
, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK
);
741 iwl_write_prph(trans
, AUX_MISC_MASTER1_EN
, AUX_MISC_MASTER1_EN_SBE_MSK
);
744 iwl_write_prph(trans
, AUX_MISC_MASTER1_SMPHR_STATUS
, 0x1);
745 val
= iwl_read_prph(trans
, AUX_MISC_MASTER1_SMPHR_STATUS
);
747 iwl_write_prph(trans
, RSA_ENABLE
, 0);
755 IWL_ERR(trans
, "Failed to take ownership on secure machine\n");
759 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans
*trans
,
760 const struct fw_img
*image
,
762 int *first_ucode_section
)
765 int i
, ret
= 0, sec_num
= 0x1;
766 u32 val
, last_read_idx
= 0;
770 *first_ucode_section
= 0;
773 (*first_ucode_section
)++;
776 for (i
= *first_ucode_section
; i
< IWL_UCODE_SECTION_MAX
; i
++) {
780 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
782 * PAGING_SEPARATOR_SECTION delimiter - separate between
783 * CPU2 non paged to CPU2 paging sec.
785 if (!image
->sec
[i
].data
||
786 image
->sec
[i
].offset
== CPU1_CPU2_SEPARATOR_SECTION
||
787 image
->sec
[i
].offset
== PAGING_SEPARATOR_SECTION
) {
789 "Break since Data not valid or Empty section, sec = %d\n",
794 ret
= iwl_pcie_load_section(trans
, i
, &image
->sec
[i
]);
798 /* Notify the ucode of the loaded section number and status */
799 val
= iwl_read_direct32(trans
, FH_UCODE_LOAD_STATUS
);
800 val
= val
| (sec_num
<< shift_param
);
801 iwl_write_direct32(trans
, FH_UCODE_LOAD_STATUS
, val
);
802 sec_num
= (sec_num
<< 1) | 0x1;
805 *first_ucode_section
= last_read_idx
;
808 iwl_write_direct32(trans
, FH_UCODE_LOAD_STATUS
, 0xFFFF);
810 iwl_write_direct32(trans
, FH_UCODE_LOAD_STATUS
, 0xFFFFFFFF);
815 static int iwl_pcie_load_cpu_sections(struct iwl_trans
*trans
,
816 const struct fw_img
*image
,
818 int *first_ucode_section
)
822 u32 last_read_idx
= 0;
826 *first_ucode_section
= 0;
829 (*first_ucode_section
)++;
832 for (i
= *first_ucode_section
; i
< IWL_UCODE_SECTION_MAX
; i
++) {
836 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
838 * PAGING_SEPARATOR_SECTION delimiter - separate between
839 * CPU2 non paged to CPU2 paging sec.
841 if (!image
->sec
[i
].data
||
842 image
->sec
[i
].offset
== CPU1_CPU2_SEPARATOR_SECTION
||
843 image
->sec
[i
].offset
== PAGING_SEPARATOR_SECTION
) {
845 "Break since Data not valid or Empty section, sec = %d\n",
850 ret
= iwl_pcie_load_section(trans
, i
, &image
->sec
[i
]);
855 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
)
856 iwl_set_bits_prph(trans
,
857 CSR_UCODE_LOAD_STATUS_ADDR
,
858 (LMPM_CPU_UCODE_LOADING_COMPLETED
|
859 LMPM_CPU_HDRS_LOADING_COMPLETED
|
860 LMPM_CPU_UCODE_LOADING_STARTED
) <<
863 *first_ucode_section
= last_read_idx
;
868 static void iwl_pcie_apply_destination(struct iwl_trans
*trans
)
870 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
871 const struct iwl_fw_dbg_dest_tlv
*dest
= trans
->dbg_dest_tlv
;
876 "DBG DEST version is %d - expect issues\n",
879 IWL_INFO(trans
, "Applying debug destination %s\n",
880 get_fw_dbg_mode_string(dest
->monitor_mode
));
882 if (dest
->monitor_mode
== EXTERNAL_MODE
)
883 iwl_pcie_alloc_fw_monitor(trans
, dest
->size_power
);
885 IWL_WARN(trans
, "PCI should have external buffer debug\n");
887 for (i
= 0; i
< trans
->dbg_dest_reg_num
; i
++) {
888 u32 addr
= le32_to_cpu(dest
->reg_ops
[i
].addr
);
889 u32 val
= le32_to_cpu(dest
->reg_ops
[i
].val
);
891 switch (dest
->reg_ops
[i
].op
) {
893 iwl_write32(trans
, addr
, val
);
896 iwl_set_bit(trans
, addr
, BIT(val
));
899 iwl_clear_bit(trans
, addr
, BIT(val
));
902 iwl_write_prph(trans
, addr
, val
);
905 iwl_set_bits_prph(trans
, addr
, BIT(val
));
908 iwl_clear_bits_prph(trans
, addr
, BIT(val
));
911 if (iwl_read_prph(trans
, addr
) & BIT(val
)) {
913 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
919 IWL_ERR(trans
, "FW debug - unknown OP %d\n",
920 dest
->reg_ops
[i
].op
);
926 if (dest
->monitor_mode
== EXTERNAL_MODE
&& trans_pcie
->fw_mon_size
) {
927 iwl_write_prph(trans
, le32_to_cpu(dest
->base_reg
),
928 trans_pcie
->fw_mon_phys
>> dest
->base_shift
);
929 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
)
930 iwl_write_prph(trans
, le32_to_cpu(dest
->end_reg
),
931 (trans_pcie
->fw_mon_phys
+
932 trans_pcie
->fw_mon_size
- 256) >>
935 iwl_write_prph(trans
, le32_to_cpu(dest
->end_reg
),
936 (trans_pcie
->fw_mon_phys
+
937 trans_pcie
->fw_mon_size
) >>
942 static int iwl_pcie_load_given_ucode(struct iwl_trans
*trans
,
943 const struct fw_img
*image
)
945 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
947 int first_ucode_section
;
949 IWL_DEBUG_FW(trans
, "working with %s CPU\n",
950 image
->is_dual_cpus
? "Dual" : "Single");
952 /* load to FW the binary non secured sections of CPU1 */
953 ret
= iwl_pcie_load_cpu_sections(trans
, image
, 1, &first_ucode_section
);
957 if (image
->is_dual_cpus
) {
958 /* set CPU2 header address */
959 iwl_write_prph(trans
,
960 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR
,
961 LMPM_SECURE_CPU2_HDR_MEM_SPACE
);
963 /* load to FW the binary sections of CPU2 */
964 ret
= iwl_pcie_load_cpu_sections(trans
, image
, 2,
965 &first_ucode_section
);
970 /* supported for 7000 only for the moment */
971 if (iwlwifi_mod_params
.fw_monitor
&&
972 trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_7000
) {
973 iwl_pcie_alloc_fw_monitor(trans
, 0);
975 if (trans_pcie
->fw_mon_size
) {
976 iwl_write_prph(trans
, MON_BUFF_BASE_ADDR
,
977 trans_pcie
->fw_mon_phys
>> 4);
978 iwl_write_prph(trans
, MON_BUFF_END_ADDR
,
979 (trans_pcie
->fw_mon_phys
+
980 trans_pcie
->fw_mon_size
) >> 4);
982 } else if (trans
->dbg_dest_tlv
) {
983 iwl_pcie_apply_destination(trans
);
986 /* release CPU reset */
987 iwl_write32(trans
, CSR_RESET
, 0);
992 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans
*trans
,
993 const struct fw_img
*image
)
996 int first_ucode_section
;
998 IWL_DEBUG_FW(trans
, "working with %s CPU\n",
999 image
->is_dual_cpus
? "Dual" : "Single");
1001 if (trans
->dbg_dest_tlv
)
1002 iwl_pcie_apply_destination(trans
);
1004 /* TODO: remove in the next Si step */
1005 ret
= iwl_pcie_rsa_race_bug_wa(trans
);
1009 /* configure the ucode to be ready to get the secured image */
1010 /* release CPU reset */
1011 iwl_write_prph(trans
, RELEASE_CPU_RESET
, RELEASE_CPU_RESET_BIT
);
1013 /* load to FW the binary Secured sections of CPU1 */
1014 ret
= iwl_pcie_load_cpu_sections_8000(trans
, image
, 1,
1015 &first_ucode_section
);
1019 /* load to FW the binary sections of CPU2 */
1020 return iwl_pcie_load_cpu_sections_8000(trans
, image
, 2,
1021 &first_ucode_section
);
1024 static void _iwl_trans_pcie_stop_device(struct iwl_trans
*trans
, bool low_power
)
1026 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1027 bool hw_rfkill
, was_hw_rfkill
;
1029 lockdep_assert_held(&trans_pcie
->mutex
);
1031 if (trans_pcie
->is_down
)
1034 trans_pcie
->is_down
= true;
1036 was_hw_rfkill
= iwl_is_rfkill_set(trans
);
1038 /* tell the device to stop sending interrupts */
1039 spin_lock(&trans_pcie
->irq_lock
);
1040 iwl_disable_interrupts(trans
);
1041 spin_unlock(&trans_pcie
->irq_lock
);
1043 /* device going down, Stop using ICT table */
1044 iwl_pcie_disable_ict(trans
);
1047 * If a HW restart happens during firmware loading,
1048 * then the firmware loading might call this function
1049 * and later it might be called again due to the
1050 * restart. So don't process again if the device is
1053 if (test_and_clear_bit(STATUS_DEVICE_ENABLED
, &trans
->status
)) {
1054 IWL_DEBUG_INFO(trans
,
1055 "DEVICE_ENABLED bit was set and is now cleared\n");
1056 iwl_pcie_tx_stop(trans
);
1057 iwl_pcie_rx_stop(trans
);
1059 /* Power-down device's busmaster DMA clocks */
1060 if (!trans
->cfg
->apmg_not_supported
) {
1061 iwl_write_prph(trans
, APMG_CLK_DIS_REG
,
1062 APMG_CLK_VAL_DMA_CLK_RQT
);
1067 /* Make sure (redundant) we've released our request to stay awake */
1068 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1069 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1071 /* Stop the device, and put it in low power state */
1072 iwl_pcie_apm_stop(trans
, false);
1074 /* stop and reset the on-board processor */
1075 iwl_write32(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
1079 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1080 * This is a bug in certain verions of the hardware.
1081 * Certain devices also keep sending HW RF kill interrupt all
1082 * the time, unless the interrupt is ACKed even if the interrupt
1083 * should be masked. Re-ACK all the interrupts here.
1085 spin_lock(&trans_pcie
->irq_lock
);
1086 iwl_disable_interrupts(trans
);
1087 spin_unlock(&trans_pcie
->irq_lock
);
1089 /* clear all status bits */
1090 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1091 clear_bit(STATUS_INT_ENABLED
, &trans
->status
);
1092 clear_bit(STATUS_TPOWER_PMI
, &trans
->status
);
1093 clear_bit(STATUS_RFKILL
, &trans
->status
);
1096 * Even if we stop the HW, we still want the RF kill
1099 iwl_enable_rfkill_int(trans
);
1102 * Check again since the RF kill state may have changed while
1103 * all the interrupts were disabled, in this case we couldn't
1104 * receive the RF kill interrupt and update the state in the
1106 * Don't call the op_mode if the rkfill state hasn't changed.
1107 * This allows the op_mode to call stop_device from the rfkill
1108 * notification without endless recursion. Under very rare
1109 * circumstances, we might have a small recursion if the rfkill
1110 * state changed exactly now while we were called from stop_device.
1111 * This is very unlikely but can happen and is supported.
1113 hw_rfkill
= iwl_is_rfkill_set(trans
);
1115 set_bit(STATUS_RFKILL
, &trans
->status
);
1117 clear_bit(STATUS_RFKILL
, &trans
->status
);
1118 if (hw_rfkill
!= was_hw_rfkill
)
1119 iwl_trans_pcie_rf_kill(trans
, hw_rfkill
);
1121 /* re-take ownership to prevent other users from stealing the device */
1122 iwl_pcie_prepare_card_hw(trans
);
1125 static int iwl_trans_pcie_start_fw(struct iwl_trans
*trans
,
1126 const struct fw_img
*fw
, bool run_in_rfkill
)
1128 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1132 /* This may fail if AMT took ownership of the device */
1133 if (iwl_pcie_prepare_card_hw(trans
)) {
1134 IWL_WARN(trans
, "Exit HW not ready\n");
1139 iwl_enable_rfkill_int(trans
);
1141 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
1144 * We enabled the RF-Kill interrupt and the handler may very
1145 * well be running. Disable the interrupts to make sure no other
1146 * interrupt can be fired.
1148 iwl_disable_interrupts(trans
);
1150 /* Make sure it finished running */
1151 synchronize_irq(trans_pcie
->pci_dev
->irq
);
1153 mutex_lock(&trans_pcie
->mutex
);
1155 /* If platform's RF_KILL switch is NOT set to KILL */
1156 hw_rfkill
= iwl_is_rfkill_set(trans
);
1158 set_bit(STATUS_RFKILL
, &trans
->status
);
1160 clear_bit(STATUS_RFKILL
, &trans
->status
);
1161 iwl_trans_pcie_rf_kill(trans
, hw_rfkill
);
1162 if (hw_rfkill
&& !run_in_rfkill
) {
1167 /* Someone called stop_device, don't try to start_fw */
1168 if (trans_pcie
->is_down
) {
1170 "Can't start_fw since the HW hasn't been started\n");
1175 /* make sure rfkill handshake bits are cleared */
1176 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1177 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
,
1178 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED
);
1180 /* clear (again), then enable host interrupts */
1181 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
1183 ret
= iwl_pcie_nic_init(trans
);
1185 IWL_ERR(trans
, "Unable to init nic\n");
1190 * Now, we load the firmware and don't want to be interrupted, even
1191 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1192 * FH_TX interrupt which is needed to load the firmware). If the
1193 * RF-Kill switch is toggled, we will find out after having loaded
1194 * the firmware and return the proper value to the caller.
1196 iwl_enable_fw_load_int(trans
);
1198 /* really make sure rfkill handshake bits are cleared */
1199 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1200 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1202 /* Load the given image to the HW */
1203 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
)
1204 ret
= iwl_pcie_load_given_ucode_8000(trans
, fw
);
1206 ret
= iwl_pcie_load_given_ucode(trans
, fw
);
1207 iwl_enable_interrupts(trans
);
1209 /* re-check RF-Kill state since we may have missed the interrupt */
1210 hw_rfkill
= iwl_is_rfkill_set(trans
);
1212 set_bit(STATUS_RFKILL
, &trans
->status
);
1214 clear_bit(STATUS_RFKILL
, &trans
->status
);
1216 iwl_trans_pcie_rf_kill(trans
, hw_rfkill
);
1217 if (hw_rfkill
&& !run_in_rfkill
)
1221 mutex_unlock(&trans_pcie
->mutex
);
1225 static void iwl_trans_pcie_fw_alive(struct iwl_trans
*trans
, u32 scd_addr
)
1227 iwl_pcie_reset_ict(trans
);
1228 iwl_pcie_tx_start(trans
, scd_addr
);
1231 static void iwl_trans_pcie_stop_device(struct iwl_trans
*trans
, bool low_power
)
1233 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1235 mutex_lock(&trans_pcie
->mutex
);
1236 _iwl_trans_pcie_stop_device(trans
, low_power
);
1237 mutex_unlock(&trans_pcie
->mutex
);
1240 void iwl_trans_pcie_rf_kill(struct iwl_trans
*trans
, bool state
)
1242 struct iwl_trans_pcie __maybe_unused
*trans_pcie
=
1243 IWL_TRANS_GET_PCIE_TRANS(trans
);
1245 lockdep_assert_held(&trans_pcie
->mutex
);
1247 if (iwl_op_mode_hw_rf_kill(trans
->op_mode
, state
))
1248 _iwl_trans_pcie_stop_device(trans
, true);
1251 static void iwl_trans_pcie_d3_suspend(struct iwl_trans
*trans
, bool test
)
1253 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1255 if (trans
->system_pm_mode
== IWL_PLAT_PM_MODE_D0I3
) {
1256 /* Enable persistence mode to avoid reset */
1257 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
1258 CSR_HW_IF_CONFIG_REG_PERSIST_MODE
);
1261 iwl_disable_interrupts(trans
);
1264 * in testing mode, the host stays awake and the
1265 * hardware won't be reset (not even partially)
1270 iwl_pcie_disable_ict(trans
);
1272 synchronize_irq(trans_pcie
->pci_dev
->irq
);
1274 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1275 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1276 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1277 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
1279 if (trans
->system_pm_mode
== IWL_PLAT_PM_MODE_D3
) {
1281 * reset TX queues -- some of their registers reset during S3
1282 * so if we don't reset everything here the D3 image would try
1283 * to execute some invalid memory upon resume
1285 iwl_trans_pcie_tx_reset(trans
);
1288 iwl_pcie_set_pwr(trans
, true);
1291 static int iwl_trans_pcie_d3_resume(struct iwl_trans
*trans
,
1292 enum iwl_d3_status
*status
,
1299 iwl_enable_interrupts(trans
);
1300 *status
= IWL_D3_STATUS_ALIVE
;
1305 * Also enables interrupts - none will happen as the device doesn't
1306 * know we're waking it up, only when the opmode actually tells it
1309 iwl_pcie_reset_ict(trans
);
1311 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1312 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
1314 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
)
1317 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
1318 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
1319 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
1322 IWL_ERR(trans
, "Failed to resume the device (mac ready)\n");
1326 iwl_pcie_set_pwr(trans
, false);
1328 if (trans
->system_pm_mode
== IWL_PLAT_PM_MODE_D0I3
) {
1329 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1330 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1332 iwl_trans_pcie_tx_reset(trans
);
1334 ret
= iwl_pcie_rx_init(trans
);
1337 "Failed to resume the device (RX reset)\n");
1342 val
= iwl_read32(trans
, CSR_RESET
);
1343 if (val
& CSR_RESET_REG_FLAG_NEVO_RESET
)
1344 *status
= IWL_D3_STATUS_RESET
;
1346 *status
= IWL_D3_STATUS_ALIVE
;
1351 static int _iwl_trans_pcie_start_hw(struct iwl_trans
*trans
, bool low_power
)
1353 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1357 lockdep_assert_held(&trans_pcie
->mutex
);
1359 err
= iwl_pcie_prepare_card_hw(trans
);
1361 IWL_ERR(trans
, "Error while preparing HW: %d\n", err
);
1365 /* Reset the entire device */
1366 iwl_write32(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
1368 usleep_range(10, 15);
1370 iwl_pcie_apm_init(trans
);
1372 /* From now on, the op_mode will be kept updated about RF kill state */
1373 iwl_enable_rfkill_int(trans
);
1375 /* Set is_down to false here so that...*/
1376 trans_pcie
->is_down
= false;
1378 hw_rfkill
= iwl_is_rfkill_set(trans
);
1380 set_bit(STATUS_RFKILL
, &trans
->status
);
1382 clear_bit(STATUS_RFKILL
, &trans
->status
);
1383 /* ... rfkill can call stop_device and set it false if needed */
1384 iwl_trans_pcie_rf_kill(trans
, hw_rfkill
);
1389 static int iwl_trans_pcie_start_hw(struct iwl_trans
*trans
, bool low_power
)
1391 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1394 mutex_lock(&trans_pcie
->mutex
);
1395 ret
= _iwl_trans_pcie_start_hw(trans
, low_power
);
1396 mutex_unlock(&trans_pcie
->mutex
);
1401 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans
*trans
)
1403 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1405 mutex_lock(&trans_pcie
->mutex
);
1407 /* disable interrupts - don't enable HW RF kill interrupt */
1408 spin_lock(&trans_pcie
->irq_lock
);
1409 iwl_disable_interrupts(trans
);
1410 spin_unlock(&trans_pcie
->irq_lock
);
1412 iwl_pcie_apm_stop(trans
, true);
1414 spin_lock(&trans_pcie
->irq_lock
);
1415 iwl_disable_interrupts(trans
);
1416 spin_unlock(&trans_pcie
->irq_lock
);
1418 iwl_pcie_disable_ict(trans
);
1420 mutex_unlock(&trans_pcie
->mutex
);
1422 synchronize_irq(trans_pcie
->pci_dev
->irq
);
1425 static void iwl_trans_pcie_write8(struct iwl_trans
*trans
, u32 ofs
, u8 val
)
1427 writeb(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1430 static void iwl_trans_pcie_write32(struct iwl_trans
*trans
, u32 ofs
, u32 val
)
1432 writel(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1435 static u32
iwl_trans_pcie_read32(struct iwl_trans
*trans
, u32 ofs
)
1437 return readl(IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1440 static u32
iwl_trans_pcie_read_prph(struct iwl_trans
*trans
, u32 reg
)
1442 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_RADDR
,
1443 ((reg
& 0x000FFFFF) | (3 << 24)));
1444 return iwl_trans_pcie_read32(trans
, HBUS_TARG_PRPH_RDAT
);
1447 static void iwl_trans_pcie_write_prph(struct iwl_trans
*trans
, u32 addr
,
1450 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_WADDR
,
1451 ((addr
& 0x000FFFFF) | (3 << 24)));
1452 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_WDAT
, val
);
1455 static int iwl_pcie_dummy_napi_poll(struct napi_struct
*napi
, int budget
)
1461 static void iwl_trans_pcie_configure(struct iwl_trans
*trans
,
1462 const struct iwl_trans_config
*trans_cfg
)
1464 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1466 trans_pcie
->cmd_queue
= trans_cfg
->cmd_queue
;
1467 trans_pcie
->cmd_fifo
= trans_cfg
->cmd_fifo
;
1468 trans_pcie
->cmd_q_wdg_timeout
= trans_cfg
->cmd_q_wdg_timeout
;
1469 if (WARN_ON(trans_cfg
->n_no_reclaim_cmds
> MAX_NO_RECLAIM_CMDS
))
1470 trans_pcie
->n_no_reclaim_cmds
= 0;
1472 trans_pcie
->n_no_reclaim_cmds
= trans_cfg
->n_no_reclaim_cmds
;
1473 if (trans_pcie
->n_no_reclaim_cmds
)
1474 memcpy(trans_pcie
->no_reclaim_cmds
, trans_cfg
->no_reclaim_cmds
,
1475 trans_pcie
->n_no_reclaim_cmds
* sizeof(u8
));
1477 trans_pcie
->rx_buf_size
= trans_cfg
->rx_buf_size
;
1478 trans_pcie
->rx_page_order
=
1479 iwl_trans_get_rb_size_order(trans_pcie
->rx_buf_size
);
1481 trans_pcie
->wide_cmd_header
= trans_cfg
->wide_cmd_header
;
1482 trans_pcie
->bc_table_dword
= trans_cfg
->bc_table_dword
;
1483 trans_pcie
->scd_set_active
= trans_cfg
->scd_set_active
;
1484 trans_pcie
->sw_csum_tx
= trans_cfg
->sw_csum_tx
;
1486 trans
->command_groups
= trans_cfg
->command_groups
;
1487 trans
->command_groups_size
= trans_cfg
->command_groups_size
;
1489 /* init ref_count to 1 (should be cleared when ucode is loaded) */
1490 trans_pcie
->ref_count
= 1;
1492 /* Initialize NAPI here - it should be before registering to mac80211
1493 * in the opmode but after the HW struct is allocated.
1494 * As this function may be called again in some corner cases don't
1495 * do anything if NAPI was already initialized.
1497 if (!trans_pcie
->napi
.poll
) {
1498 init_dummy_netdev(&trans_pcie
->napi_dev
);
1499 netif_napi_add(&trans_pcie
->napi_dev
, &trans_pcie
->napi
,
1500 iwl_pcie_dummy_napi_poll
, 64);
1504 void iwl_trans_pcie_free(struct iwl_trans
*trans
)
1506 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1509 synchronize_irq(trans_pcie
->pci_dev
->irq
);
1511 iwl_pcie_tx_free(trans
);
1512 iwl_pcie_rx_free(trans
);
1514 free_irq(trans_pcie
->pci_dev
->irq
, trans
);
1515 iwl_pcie_free_ict(trans
);
1517 pci_disable_msi(trans_pcie
->pci_dev
);
1518 iounmap(trans_pcie
->hw_base
);
1519 pci_release_regions(trans_pcie
->pci_dev
);
1520 pci_disable_device(trans_pcie
->pci_dev
);
1522 if (trans_pcie
->napi
.poll
)
1523 netif_napi_del(&trans_pcie
->napi
);
1525 iwl_pcie_free_fw_monitor(trans
);
1527 for_each_possible_cpu(i
) {
1528 struct iwl_tso_hdr_page
*p
=
1529 per_cpu_ptr(trans_pcie
->tso_hdr_page
, i
);
1532 __free_page(p
->page
);
1535 free_percpu(trans_pcie
->tso_hdr_page
);
1536 iwl_trans_free(trans
);
1539 static void iwl_trans_pcie_set_pmi(struct iwl_trans
*trans
, bool state
)
1542 set_bit(STATUS_TPOWER_PMI
, &trans
->status
);
1544 clear_bit(STATUS_TPOWER_PMI
, &trans
->status
);
1547 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans
*trans
,
1548 unsigned long *flags
)
1551 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1553 spin_lock_irqsave(&trans_pcie
->reg_lock
, *flags
);
1555 if (trans_pcie
->cmd_hold_nic_awake
)
1558 /* this bit wakes up the NIC */
1559 __iwl_trans_pcie_set_bit(trans
, CSR_GP_CNTRL
,
1560 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1561 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
)
1565 * These bits say the device is running, and should keep running for
1566 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1567 * but they do not indicate that embedded SRAM is restored yet;
1568 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1569 * to/from host DRAM when sleeping/waking for power-saving.
1570 * Each direction takes approximately 1/4 millisecond; with this
1571 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1572 * series of register accesses are expected (e.g. reading Event Log),
1573 * to keep device from sleeping.
1575 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1576 * SRAM is okay/restored. We don't check that here because this call
1577 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1578 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1580 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1581 * and do not save/restore SRAM when power cycling.
1583 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
1584 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN
,
1585 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
|
1586 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP
), 15000);
1587 if (unlikely(ret
< 0)) {
1588 iwl_write32(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_FORCE_NMI
);
1590 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1591 iwl_read32(trans
, CSR_GP_CNTRL
));
1592 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, *flags
);
1598 * Fool sparse by faking we release the lock - sparse will
1599 * track nic_access anyway.
1601 __release(&trans_pcie
->reg_lock
);
1605 static void iwl_trans_pcie_release_nic_access(struct iwl_trans
*trans
,
1606 unsigned long *flags
)
1608 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1610 lockdep_assert_held(&trans_pcie
->reg_lock
);
1613 * Fool sparse by faking we acquiring the lock - sparse will
1614 * track nic_access anyway.
1616 __acquire(&trans_pcie
->reg_lock
);
1618 if (trans_pcie
->cmd_hold_nic_awake
)
1621 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
1622 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1624 * Above we read the CSR_GP_CNTRL register, which will flush
1625 * any previous writes, but we need the write that clears the
1626 * MAC_ACCESS_REQ bit to be performed before any other writes
1627 * scheduled on different CPUs (after we drop reg_lock).
1631 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, *flags
);
1634 static int iwl_trans_pcie_read_mem(struct iwl_trans
*trans
, u32 addr
,
1635 void *buf
, int dwords
)
1637 unsigned long flags
;
1641 if (iwl_trans_grab_nic_access(trans
, &flags
)) {
1642 iwl_write32(trans
, HBUS_TARG_MEM_RADDR
, addr
);
1643 for (offs
= 0; offs
< dwords
; offs
++)
1644 vals
[offs
] = iwl_read32(trans
, HBUS_TARG_MEM_RDAT
);
1645 iwl_trans_release_nic_access(trans
, &flags
);
1652 static int iwl_trans_pcie_write_mem(struct iwl_trans
*trans
, u32 addr
,
1653 const void *buf
, int dwords
)
1655 unsigned long flags
;
1657 const u32
*vals
= buf
;
1659 if (iwl_trans_grab_nic_access(trans
, &flags
)) {
1660 iwl_write32(trans
, HBUS_TARG_MEM_WADDR
, addr
);
1661 for (offs
= 0; offs
< dwords
; offs
++)
1662 iwl_write32(trans
, HBUS_TARG_MEM_WDAT
,
1663 vals
? vals
[offs
] : 0);
1664 iwl_trans_release_nic_access(trans
, &flags
);
1671 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans
*trans
,
1675 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1678 for_each_set_bit(queue
, &txqs
, BITS_PER_LONG
) {
1679 struct iwl_txq
*txq
= &trans_pcie
->txq
[queue
];
1682 spin_lock_bh(&txq
->lock
);
1686 if (txq
->frozen
== freeze
)
1689 IWL_DEBUG_TX_QUEUES(trans
, "%s TXQ %d\n",
1690 freeze
? "Freezing" : "Waking", queue
);
1692 txq
->frozen
= freeze
;
1694 if (txq
->q
.read_ptr
== txq
->q
.write_ptr
)
1698 if (unlikely(time_after(now
,
1699 txq
->stuck_timer
.expires
))) {
1701 * The timer should have fired, maybe it is
1702 * spinning right now on the lock.
1706 /* remember how long until the timer fires */
1707 txq
->frozen_expiry_remainder
=
1708 txq
->stuck_timer
.expires
- now
;
1709 del_timer(&txq
->stuck_timer
);
1714 * Wake a non-empty queue -> arm timer with the
1715 * remainder before it froze
1717 mod_timer(&txq
->stuck_timer
,
1718 now
+ txq
->frozen_expiry_remainder
);
1721 spin_unlock_bh(&txq
->lock
);
1725 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans
*trans
, bool block
)
1727 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1730 for (i
= 0; i
< trans
->cfg
->base_params
->num_of_queues
; i
++) {
1731 struct iwl_txq
*txq
= &trans_pcie
->txq
[i
];
1733 if (i
== trans_pcie
->cmd_queue
)
1736 spin_lock_bh(&txq
->lock
);
1738 if (!block
&& !(WARN_ON_ONCE(!txq
->block
))) {
1741 iwl_write32(trans
, HBUS_TARG_WRPTR
,
1742 txq
->q
.write_ptr
| (i
<< 8));
1748 spin_unlock_bh(&txq
->lock
);
1752 #define IWL_FLUSH_WAIT_MS 2000
1754 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans
*trans
, u32 txq_bm
)
1756 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1757 struct iwl_txq
*txq
;
1758 struct iwl_queue
*q
;
1760 unsigned long now
= jiffies
;
1765 /* waiting for all the tx frames complete might take a while */
1766 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
1769 if (cnt
== trans_pcie
->cmd_queue
)
1771 if (!test_bit(cnt
, trans_pcie
->queue_used
))
1773 if (!(BIT(cnt
) & txq_bm
))
1776 IWL_DEBUG_TX_QUEUES(trans
, "Emptying queue %d...\n", cnt
);
1777 txq
= &trans_pcie
->txq
[cnt
];
1779 wr_ptr
= ACCESS_ONCE(q
->write_ptr
);
1781 while (q
->read_ptr
!= ACCESS_ONCE(q
->write_ptr
) &&
1782 !time_after(jiffies
,
1783 now
+ msecs_to_jiffies(IWL_FLUSH_WAIT_MS
))) {
1784 u8 write_ptr
= ACCESS_ONCE(q
->write_ptr
);
1786 if (WARN_ONCE(wr_ptr
!= write_ptr
,
1787 "WR pointer moved while flushing %d -> %d\n",
1793 if (q
->read_ptr
!= q
->write_ptr
) {
1795 "fail to flush all tx fifo queues Q %d\n", cnt
);
1799 IWL_DEBUG_TX_QUEUES(trans
, "Queue %d is now empty.\n", cnt
);
1805 IWL_ERR(trans
, "Current SW read_ptr %d write_ptr %d\n",
1806 txq
->q
.read_ptr
, txq
->q
.write_ptr
);
1808 scd_sram_addr
= trans_pcie
->scd_base_addr
+
1809 SCD_TX_STTS_QUEUE_OFFSET(txq
->q
.id
);
1810 iwl_trans_read_mem_bytes(trans
, scd_sram_addr
, buf
, sizeof(buf
));
1812 iwl_print_hex_error(trans
, buf
, sizeof(buf
));
1814 for (cnt
= 0; cnt
< FH_TCSR_CHNL_NUM
; cnt
++)
1815 IWL_ERR(trans
, "FH TRBs(%d) = 0x%08x\n", cnt
,
1816 iwl_read_direct32(trans
, FH_TX_TRB_REG(cnt
)));
1818 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
1819 u32 status
= iwl_read_prph(trans
, SCD_QUEUE_STATUS_BITS(cnt
));
1820 u8 fifo
= (status
>> SCD_QUEUE_STTS_REG_POS_TXF
) & 0x7;
1821 bool active
= !!(status
& BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE
));
1823 iwl_trans_read_mem32(trans
, trans_pcie
->scd_base_addr
+
1824 SCD_TRANS_TBL_OFFSET_QUEUE(cnt
));
1827 tbl_dw
= (tbl_dw
& 0xFFFF0000) >> 16;
1829 tbl_dw
= tbl_dw
& 0x0000FFFF;
1832 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1833 cnt
, active
? "" : "in", fifo
, tbl_dw
,
1834 iwl_read_prph(trans
, SCD_QUEUE_RDPTR(cnt
)) &
1835 (TFD_QUEUE_SIZE_MAX
- 1),
1836 iwl_read_prph(trans
, SCD_QUEUE_WRPTR(cnt
)));
1842 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans
*trans
, u32 reg
,
1843 u32 mask
, u32 value
)
1845 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1846 unsigned long flags
;
1848 spin_lock_irqsave(&trans_pcie
->reg_lock
, flags
);
1849 __iwl_trans_pcie_set_bits_mask(trans
, reg
, mask
, value
);
1850 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
1853 void iwl_trans_pcie_ref(struct iwl_trans
*trans
)
1855 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1856 unsigned long flags
;
1858 if (iwlwifi_mod_params
.d0i3_disable
)
1861 spin_lock_irqsave(&trans_pcie
->ref_lock
, flags
);
1862 IWL_DEBUG_RPM(trans
, "ref_counter: %d\n", trans_pcie
->ref_count
);
1863 trans_pcie
->ref_count
++;
1864 spin_unlock_irqrestore(&trans_pcie
->ref_lock
, flags
);
1867 void iwl_trans_pcie_unref(struct iwl_trans
*trans
)
1869 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1870 unsigned long flags
;
1872 if (iwlwifi_mod_params
.d0i3_disable
)
1875 spin_lock_irqsave(&trans_pcie
->ref_lock
, flags
);
1876 IWL_DEBUG_RPM(trans
, "ref_counter: %d\n", trans_pcie
->ref_count
);
1877 if (WARN_ON_ONCE(trans_pcie
->ref_count
== 0)) {
1878 spin_unlock_irqrestore(&trans_pcie
->ref_lock
, flags
);
1881 trans_pcie
->ref_count
--;
1882 spin_unlock_irqrestore(&trans_pcie
->ref_lock
, flags
);
1885 static const char *get_csr_string(int cmd
)
1887 #define IWL_CMD(x) case x: return #x
1889 IWL_CMD(CSR_HW_IF_CONFIG_REG
);
1890 IWL_CMD(CSR_INT_COALESCING
);
1892 IWL_CMD(CSR_INT_MASK
);
1893 IWL_CMD(CSR_FH_INT_STATUS
);
1894 IWL_CMD(CSR_GPIO_IN
);
1896 IWL_CMD(CSR_GP_CNTRL
);
1897 IWL_CMD(CSR_HW_REV
);
1898 IWL_CMD(CSR_EEPROM_REG
);
1899 IWL_CMD(CSR_EEPROM_GP
);
1900 IWL_CMD(CSR_OTP_GP_REG
);
1901 IWL_CMD(CSR_GIO_REG
);
1902 IWL_CMD(CSR_GP_UCODE_REG
);
1903 IWL_CMD(CSR_GP_DRIVER_REG
);
1904 IWL_CMD(CSR_UCODE_DRV_GP1
);
1905 IWL_CMD(CSR_UCODE_DRV_GP2
);
1906 IWL_CMD(CSR_LED_REG
);
1907 IWL_CMD(CSR_DRAM_INT_TBL_REG
);
1908 IWL_CMD(CSR_GIO_CHICKEN_BITS
);
1909 IWL_CMD(CSR_ANA_PLL_CFG
);
1910 IWL_CMD(CSR_HW_REV_WA_REG
);
1911 IWL_CMD(CSR_MONITOR_STATUS_REG
);
1912 IWL_CMD(CSR_DBG_HPET_MEM_REG
);
1919 void iwl_pcie_dump_csr(struct iwl_trans
*trans
)
1922 static const u32 csr_tbl
[] = {
1923 CSR_HW_IF_CONFIG_REG
,
1941 CSR_DRAM_INT_TBL_REG
,
1942 CSR_GIO_CHICKEN_BITS
,
1944 CSR_MONITOR_STATUS_REG
,
1946 CSR_DBG_HPET_MEM_REG
1948 IWL_ERR(trans
, "CSR values:\n");
1949 IWL_ERR(trans
, "(2nd byte of CSR_INT_COALESCING is "
1950 "CSR_INT_PERIODIC_REG)\n");
1951 for (i
= 0; i
< ARRAY_SIZE(csr_tbl
); i
++) {
1952 IWL_ERR(trans
, " %25s: 0X%08x\n",
1953 get_csr_string(csr_tbl
[i
]),
1954 iwl_read32(trans
, csr_tbl
[i
]));
1958 #ifdef CONFIG_IWLWIFI_DEBUGFS
1959 /* create and remove of files */
1960 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1961 if (!debugfs_create_file(#name, mode, parent, trans, \
1962 &iwl_dbgfs_##name##_ops)) \
1966 /* file operation */
1967 #define DEBUGFS_READ_FILE_OPS(name) \
1968 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1969 .read = iwl_dbgfs_##name##_read, \
1970 .open = simple_open, \
1971 .llseek = generic_file_llseek, \
1974 #define DEBUGFS_WRITE_FILE_OPS(name) \
1975 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1976 .write = iwl_dbgfs_##name##_write, \
1977 .open = simple_open, \
1978 .llseek = generic_file_llseek, \
1981 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1982 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1983 .write = iwl_dbgfs_##name##_write, \
1984 .read = iwl_dbgfs_##name##_read, \
1985 .open = simple_open, \
1986 .llseek = generic_file_llseek, \
1989 static ssize_t
iwl_dbgfs_tx_queue_read(struct file
*file
,
1990 char __user
*user_buf
,
1991 size_t count
, loff_t
*ppos
)
1993 struct iwl_trans
*trans
= file
->private_data
;
1994 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1995 struct iwl_txq
*txq
;
1996 struct iwl_queue
*q
;
2003 bufsz
= sizeof(char) * 75 * trans
->cfg
->base_params
->num_of_queues
;
2005 if (!trans_pcie
->txq
)
2008 buf
= kzalloc(bufsz
, GFP_KERNEL
);
2012 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
2013 txq
= &trans_pcie
->txq
[cnt
];
2015 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2016 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2017 cnt
, q
->read_ptr
, q
->write_ptr
,
2018 !!test_bit(cnt
, trans_pcie
->queue_used
),
2019 !!test_bit(cnt
, trans_pcie
->queue_stopped
),
2020 txq
->need_update
, txq
->frozen
,
2021 (cnt
== trans_pcie
->cmd_queue
? " HCMD" : ""));
2023 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
2028 static ssize_t
iwl_dbgfs_rx_queue_read(struct file
*file
,
2029 char __user
*user_buf
,
2030 size_t count
, loff_t
*ppos
)
2032 struct iwl_trans
*trans
= file
->private_data
;
2033 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2034 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
;
2037 const size_t bufsz
= sizeof(buf
);
2039 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "read: %u\n",
2041 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "write: %u\n",
2043 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "write_actual: %u\n",
2045 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "need_update: %d\n",
2047 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "free_count: %u\n",
2050 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "closed_rb_num: %u\n",
2051 le16_to_cpu(rxq
->rb_stts
->closed_rb_num
) & 0x0FFF);
2053 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2054 "closed_rb_num: Not Allocated\n");
2056 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
2059 static ssize_t
iwl_dbgfs_interrupt_read(struct file
*file
,
2060 char __user
*user_buf
,
2061 size_t count
, loff_t
*ppos
)
2063 struct iwl_trans
*trans
= file
->private_data
;
2064 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2065 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
2069 int bufsz
= 24 * 64; /* 24 items * 64 char per item */
2072 buf
= kzalloc(bufsz
, GFP_KERNEL
);
2076 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2077 "Interrupt Statistics Report:\n");
2079 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "HW Error:\t\t\t %u\n",
2081 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "SW Error:\t\t\t %u\n",
2083 if (isr_stats
->sw
|| isr_stats
->hw
) {
2084 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2085 "\tLast Restarting Code: 0x%X\n",
2086 isr_stats
->err_code
);
2088 #ifdef CONFIG_IWLWIFI_DEBUG
2089 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Frame transmitted:\t\t %u\n",
2091 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Alive interrupt:\t\t %u\n",
2094 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2095 "HW RF KILL switch toggled:\t %u\n", isr_stats
->rfkill
);
2097 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "CT KILL:\t\t\t %u\n",
2100 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Wakeup Interrupt:\t\t %u\n",
2103 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2104 "Rx command responses:\t\t %u\n", isr_stats
->rx
);
2106 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Tx/FH interrupt:\t\t %u\n",
2109 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Unexpected INTA:\t\t %u\n",
2110 isr_stats
->unhandled
);
2112 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
2117 static ssize_t
iwl_dbgfs_interrupt_write(struct file
*file
,
2118 const char __user
*user_buf
,
2119 size_t count
, loff_t
*ppos
)
2121 struct iwl_trans
*trans
= file
->private_data
;
2122 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2123 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
2129 memset(buf
, 0, sizeof(buf
));
2130 buf_size
= min(count
, sizeof(buf
) - 1);
2131 if (copy_from_user(buf
, user_buf
, buf_size
))
2133 if (sscanf(buf
, "%x", &reset_flag
) != 1)
2135 if (reset_flag
== 0)
2136 memset(isr_stats
, 0, sizeof(*isr_stats
));
2141 static ssize_t
iwl_dbgfs_csr_write(struct file
*file
,
2142 const char __user
*user_buf
,
2143 size_t count
, loff_t
*ppos
)
2145 struct iwl_trans
*trans
= file
->private_data
;
2150 memset(buf
, 0, sizeof(buf
));
2151 buf_size
= min(count
, sizeof(buf
) - 1);
2152 if (copy_from_user(buf
, user_buf
, buf_size
))
2154 if (sscanf(buf
, "%d", &csr
) != 1)
2157 iwl_pcie_dump_csr(trans
);
2162 static ssize_t
iwl_dbgfs_fh_reg_read(struct file
*file
,
2163 char __user
*user_buf
,
2164 size_t count
, loff_t
*ppos
)
2166 struct iwl_trans
*trans
= file
->private_data
;
2170 ret
= iwl_dump_fh(trans
, &buf
);
2175 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, ret
);
2180 DEBUGFS_READ_WRITE_FILE_OPS(interrupt
);
2181 DEBUGFS_READ_FILE_OPS(fh_reg
);
2182 DEBUGFS_READ_FILE_OPS(rx_queue
);
2183 DEBUGFS_READ_FILE_OPS(tx_queue
);
2184 DEBUGFS_WRITE_FILE_OPS(csr
);
2186 /* Create the debugfs files and directories */
2187 int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
)
2189 struct dentry
*dir
= trans
->dbgfs_dir
;
2191 DEBUGFS_ADD_FILE(rx_queue
, dir
, S_IRUSR
);
2192 DEBUGFS_ADD_FILE(tx_queue
, dir
, S_IRUSR
);
2193 DEBUGFS_ADD_FILE(interrupt
, dir
, S_IWUSR
| S_IRUSR
);
2194 DEBUGFS_ADD_FILE(csr
, dir
, S_IWUSR
);
2195 DEBUGFS_ADD_FILE(fh_reg
, dir
, S_IRUSR
);
2199 IWL_ERR(trans
, "failed to create the trans debugfs entry\n");
2202 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2204 static u32
iwl_trans_pcie_get_cmdlen(struct iwl_tfd
*tfd
)
2209 for (i
= 0; i
< IWL_NUM_OF_TBS
; i
++)
2210 cmdlen
+= iwl_pcie_tfd_tb_get_len(tfd
, i
);
2215 static u32
iwl_trans_pcie_dump_rbs(struct iwl_trans
*trans
,
2216 struct iwl_fw_error_dump_data
**data
,
2217 int allocated_rb_nums
)
2219 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2220 int max_len
= PAGE_SIZE
<< trans_pcie
->rx_page_order
;
2221 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
;
2222 u32 i
, r
, j
, rb_len
= 0;
2224 spin_lock(&rxq
->lock
);
2226 r
= le16_to_cpu(ACCESS_ONCE(rxq
->rb_stts
->closed_rb_num
)) & 0x0FFF;
2228 for (i
= rxq
->read
, j
= 0;
2229 i
!= r
&& j
< allocated_rb_nums
;
2230 i
= (i
+ 1) & RX_QUEUE_MASK
, j
++) {
2231 struct iwl_rx_mem_buffer
*rxb
= rxq
->queue
[i
];
2232 struct iwl_fw_error_dump_rb
*rb
;
2234 dma_unmap_page(trans
->dev
, rxb
->page_dma
, max_len
,
2237 rb_len
+= sizeof(**data
) + sizeof(*rb
) + max_len
;
2239 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_RB
);
2240 (*data
)->len
= cpu_to_le32(sizeof(*rb
) + max_len
);
2241 rb
= (void *)(*data
)->data
;
2242 rb
->index
= cpu_to_le32(i
);
2243 memcpy(rb
->data
, page_address(rxb
->page
), max_len
);
2244 /* remap the page for the free benefit */
2245 rxb
->page_dma
= dma_map_page(trans
->dev
, rxb
->page
, 0,
2249 *data
= iwl_fw_error_next_data(*data
);
2252 spin_unlock(&rxq
->lock
);
2256 #define IWL_CSR_TO_DUMP (0x250)
2258 static u32
iwl_trans_pcie_dump_csr(struct iwl_trans
*trans
,
2259 struct iwl_fw_error_dump_data
**data
)
2261 u32 csr_len
= sizeof(**data
) + IWL_CSR_TO_DUMP
;
2265 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_CSR
);
2266 (*data
)->len
= cpu_to_le32(IWL_CSR_TO_DUMP
);
2267 val
= (void *)(*data
)->data
;
2269 for (i
= 0; i
< IWL_CSR_TO_DUMP
; i
+= 4)
2270 *val
++ = cpu_to_le32(iwl_trans_pcie_read32(trans
, i
));
2272 *data
= iwl_fw_error_next_data(*data
);
2277 static u32
iwl_trans_pcie_fh_regs_dump(struct iwl_trans
*trans
,
2278 struct iwl_fw_error_dump_data
**data
)
2280 u32 fh_regs_len
= FH_MEM_UPPER_BOUND
- FH_MEM_LOWER_BOUND
;
2281 unsigned long flags
;
2285 if (!iwl_trans_grab_nic_access(trans
, &flags
))
2288 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS
);
2289 (*data
)->len
= cpu_to_le32(fh_regs_len
);
2290 val
= (void *)(*data
)->data
;
2292 for (i
= FH_MEM_LOWER_BOUND
; i
< FH_MEM_UPPER_BOUND
; i
+= sizeof(u32
))
2293 *val
++ = cpu_to_le32(iwl_trans_pcie_read32(trans
, i
));
2295 iwl_trans_release_nic_access(trans
, &flags
);
2297 *data
= iwl_fw_error_next_data(*data
);
2299 return sizeof(**data
) + fh_regs_len
;
2303 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans
*trans
,
2304 struct iwl_fw_error_dump_fw_mon
*fw_mon_data
,
2307 u32 buf_size_in_dwords
= (monitor_len
>> 2);
2308 u32
*buffer
= (u32
*)fw_mon_data
->data
;
2309 unsigned long flags
;
2312 if (!iwl_trans_grab_nic_access(trans
, &flags
))
2315 iwl_write_prph_no_grab(trans
, MON_DMARB_RD_CTL_ADDR
, 0x1);
2316 for (i
= 0; i
< buf_size_in_dwords
; i
++)
2317 buffer
[i
] = iwl_read_prph_no_grab(trans
,
2318 MON_DMARB_RD_DATA_ADDR
);
2319 iwl_write_prph_no_grab(trans
, MON_DMARB_RD_CTL_ADDR
, 0x0);
2321 iwl_trans_release_nic_access(trans
, &flags
);
2327 iwl_trans_pcie_dump_monitor(struct iwl_trans
*trans
,
2328 struct iwl_fw_error_dump_data
**data
,
2331 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2334 if ((trans_pcie
->fw_mon_page
&&
2335 trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_7000
) ||
2336 trans
->dbg_dest_tlv
) {
2337 struct iwl_fw_error_dump_fw_mon
*fw_mon_data
;
2338 u32 base
, write_ptr
, wrap_cnt
;
2340 /* If there was a dest TLV - use the values from there */
2341 if (trans
->dbg_dest_tlv
) {
2343 le32_to_cpu(trans
->dbg_dest_tlv
->write_ptr_reg
);
2344 wrap_cnt
= le32_to_cpu(trans
->dbg_dest_tlv
->wrap_count
);
2345 base
= le32_to_cpu(trans
->dbg_dest_tlv
->base_reg
);
2347 base
= MON_BUFF_BASE_ADDR
;
2348 write_ptr
= MON_BUFF_WRPTR
;
2349 wrap_cnt
= MON_BUFF_CYCLE_CNT
;
2352 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR
);
2353 fw_mon_data
= (void *)(*data
)->data
;
2354 fw_mon_data
->fw_mon_wr_ptr
=
2355 cpu_to_le32(iwl_read_prph(trans
, write_ptr
));
2356 fw_mon_data
->fw_mon_cycle_cnt
=
2357 cpu_to_le32(iwl_read_prph(trans
, wrap_cnt
));
2358 fw_mon_data
->fw_mon_base_ptr
=
2359 cpu_to_le32(iwl_read_prph(trans
, base
));
2361 len
+= sizeof(**data
) + sizeof(*fw_mon_data
);
2362 if (trans_pcie
->fw_mon_page
) {
2364 * The firmware is now asserted, it won't write anything
2365 * to the buffer. CPU can take ownership to fetch the
2366 * data. The buffer will be handed back to the device
2367 * before the firmware will be restarted.
2369 dma_sync_single_for_cpu(trans
->dev
,
2370 trans_pcie
->fw_mon_phys
,
2371 trans_pcie
->fw_mon_size
,
2373 memcpy(fw_mon_data
->data
,
2374 page_address(trans_pcie
->fw_mon_page
),
2375 trans_pcie
->fw_mon_size
);
2377 monitor_len
= trans_pcie
->fw_mon_size
;
2378 } else if (trans
->dbg_dest_tlv
->monitor_mode
== SMEM_MODE
) {
2380 * Update pointers to reflect actual values after
2383 base
= iwl_read_prph(trans
, base
) <<
2384 trans
->dbg_dest_tlv
->base_shift
;
2385 iwl_trans_read_mem(trans
, base
, fw_mon_data
->data
,
2386 monitor_len
/ sizeof(u32
));
2387 } else if (trans
->dbg_dest_tlv
->monitor_mode
== MARBH_MODE
) {
2389 iwl_trans_pci_dump_marbh_monitor(trans
,
2393 /* Didn't match anything - output no monitor data */
2398 (*data
)->len
= cpu_to_le32(monitor_len
+ sizeof(*fw_mon_data
));
2404 static struct iwl_trans_dump_data
2405 *iwl_trans_pcie_dump_data(struct iwl_trans
*trans
,
2406 const struct iwl_fw_dbg_trigger_tlv
*trigger
)
2408 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2409 struct iwl_fw_error_dump_data
*data
;
2410 struct iwl_txq
*cmdq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
2411 struct iwl_fw_error_dump_txcmd
*txcmd
;
2412 struct iwl_trans_dump_data
*dump_data
;
2416 bool dump_rbs
= test_bit(STATUS_FW_ERROR
, &trans
->status
);
2418 /* transport dump header */
2419 len
= sizeof(*dump_data
);
2422 len
+= sizeof(*data
) +
2423 cmdq
->q
.n_window
* (sizeof(*txcmd
) + TFD_MAX_PAYLOAD_SIZE
);
2426 if (trans_pcie
->fw_mon_page
) {
2427 len
+= sizeof(*data
) + sizeof(struct iwl_fw_error_dump_fw_mon
) +
2428 trans_pcie
->fw_mon_size
;
2429 monitor_len
= trans_pcie
->fw_mon_size
;
2430 } else if (trans
->dbg_dest_tlv
) {
2433 base
= le32_to_cpu(trans
->dbg_dest_tlv
->base_reg
);
2434 end
= le32_to_cpu(trans
->dbg_dest_tlv
->end_reg
);
2436 base
= iwl_read_prph(trans
, base
) <<
2437 trans
->dbg_dest_tlv
->base_shift
;
2438 end
= iwl_read_prph(trans
, end
) <<
2439 trans
->dbg_dest_tlv
->end_shift
;
2441 /* Make "end" point to the actual end */
2442 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
||
2443 trans
->dbg_dest_tlv
->monitor_mode
== MARBH_MODE
)
2444 end
+= (1 << trans
->dbg_dest_tlv
->end_shift
);
2445 monitor_len
= end
- base
;
2446 len
+= sizeof(*data
) + sizeof(struct iwl_fw_error_dump_fw_mon
) +
2452 if (trigger
&& (trigger
->mode
& IWL_FW_DBG_TRIGGER_MONITOR_ONLY
)) {
2453 dump_data
= vzalloc(len
);
2457 data
= (void *)dump_data
->data
;
2458 len
= iwl_trans_pcie_dump_monitor(trans
, &data
, monitor_len
);
2459 dump_data
->len
= len
;
2465 len
+= sizeof(*data
) + IWL_CSR_TO_DUMP
;
2468 len
+= sizeof(*data
) + (FH_MEM_UPPER_BOUND
- FH_MEM_LOWER_BOUND
);
2472 num_rbs
= le16_to_cpu(ACCESS_ONCE(
2473 trans_pcie
->rxq
.rb_stts
->closed_rb_num
))
2475 num_rbs
= (num_rbs
- trans_pcie
->rxq
.read
) & RX_QUEUE_MASK
;
2476 len
+= num_rbs
* (sizeof(*data
) +
2477 sizeof(struct iwl_fw_error_dump_rb
) +
2478 (PAGE_SIZE
<< trans_pcie
->rx_page_order
));
2481 dump_data
= vzalloc(len
);
2486 data
= (void *)dump_data
->data
;
2487 data
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD
);
2488 txcmd
= (void *)data
->data
;
2489 spin_lock_bh(&cmdq
->lock
);
2490 ptr
= cmdq
->q
.write_ptr
;
2491 for (i
= 0; i
< cmdq
->q
.n_window
; i
++) {
2492 u8 idx
= get_cmd_index(&cmdq
->q
, ptr
);
2495 cmdlen
= iwl_trans_pcie_get_cmdlen(&cmdq
->tfds
[ptr
]);
2496 caplen
= min_t(u32
, TFD_MAX_PAYLOAD_SIZE
, cmdlen
);
2499 len
+= sizeof(*txcmd
) + caplen
;
2500 txcmd
->cmdlen
= cpu_to_le32(cmdlen
);
2501 txcmd
->caplen
= cpu_to_le32(caplen
);
2502 memcpy(txcmd
->data
, cmdq
->entries
[idx
].cmd
, caplen
);
2503 txcmd
= (void *)((u8
*)txcmd
->data
+ caplen
);
2506 ptr
= iwl_queue_dec_wrap(ptr
);
2508 spin_unlock_bh(&cmdq
->lock
);
2510 data
->len
= cpu_to_le32(len
);
2511 len
+= sizeof(*data
);
2512 data
= iwl_fw_error_next_data(data
);
2514 len
+= iwl_trans_pcie_dump_csr(trans
, &data
);
2515 len
+= iwl_trans_pcie_fh_regs_dump(trans
, &data
);
2517 len
+= iwl_trans_pcie_dump_rbs(trans
, &data
, num_rbs
);
2519 len
+= iwl_trans_pcie_dump_monitor(trans
, &data
, monitor_len
);
2521 dump_data
->len
= len
;
2526 static const struct iwl_trans_ops trans_ops_pcie
= {
2527 .start_hw
= iwl_trans_pcie_start_hw
,
2528 .op_mode_leave
= iwl_trans_pcie_op_mode_leave
,
2529 .fw_alive
= iwl_trans_pcie_fw_alive
,
2530 .start_fw
= iwl_trans_pcie_start_fw
,
2531 .stop_device
= iwl_trans_pcie_stop_device
,
2533 .d3_suspend
= iwl_trans_pcie_d3_suspend
,
2534 .d3_resume
= iwl_trans_pcie_d3_resume
,
2536 .send_cmd
= iwl_trans_pcie_send_hcmd
,
2538 .tx
= iwl_trans_pcie_tx
,
2539 .reclaim
= iwl_trans_pcie_reclaim
,
2541 .txq_disable
= iwl_trans_pcie_txq_disable
,
2542 .txq_enable
= iwl_trans_pcie_txq_enable
,
2544 .wait_tx_queue_empty
= iwl_trans_pcie_wait_txq_empty
,
2545 .freeze_txq_timer
= iwl_trans_pcie_freeze_txq_timer
,
2546 .block_txq_ptrs
= iwl_trans_pcie_block_txq_ptrs
,
2548 .write8
= iwl_trans_pcie_write8
,
2549 .write32
= iwl_trans_pcie_write32
,
2550 .read32
= iwl_trans_pcie_read32
,
2551 .read_prph
= iwl_trans_pcie_read_prph
,
2552 .write_prph
= iwl_trans_pcie_write_prph
,
2553 .read_mem
= iwl_trans_pcie_read_mem
,
2554 .write_mem
= iwl_trans_pcie_write_mem
,
2555 .configure
= iwl_trans_pcie_configure
,
2556 .set_pmi
= iwl_trans_pcie_set_pmi
,
2557 .grab_nic_access
= iwl_trans_pcie_grab_nic_access
,
2558 .release_nic_access
= iwl_trans_pcie_release_nic_access
,
2559 .set_bits_mask
= iwl_trans_pcie_set_bits_mask
,
2561 .ref
= iwl_trans_pcie_ref
,
2562 .unref
= iwl_trans_pcie_unref
,
2564 .dump_data
= iwl_trans_pcie_dump_data
,
2567 struct iwl_trans
*iwl_trans_pcie_alloc(struct pci_dev
*pdev
,
2568 const struct pci_device_id
*ent
,
2569 const struct iwl_cfg
*cfg
)
2571 struct iwl_trans_pcie
*trans_pcie
;
2572 struct iwl_trans
*trans
;
2576 trans
= iwl_trans_alloc(sizeof(struct iwl_trans_pcie
),
2577 &pdev
->dev
, cfg
, &trans_ops_pcie
, 0);
2579 return ERR_PTR(-ENOMEM
);
2581 trans
->max_skb_frags
= IWL_PCIE_MAX_FRAGS
;
2583 trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2585 trans_pcie
->trans
= trans
;
2586 spin_lock_init(&trans_pcie
->irq_lock
);
2587 spin_lock_init(&trans_pcie
->reg_lock
);
2588 spin_lock_init(&trans_pcie
->ref_lock
);
2589 mutex_init(&trans_pcie
->mutex
);
2590 init_waitqueue_head(&trans_pcie
->ucode_write_waitq
);
2591 trans_pcie
->tso_hdr_page
= alloc_percpu(struct iwl_tso_hdr_page
);
2592 if (!trans_pcie
->tso_hdr_page
) {
2597 ret
= pci_enable_device(pdev
);
2601 if (!cfg
->base_params
->pcie_l1_allowed
) {
2603 * W/A - seems to solve weird behavior. We need to remove this
2604 * if we don't want to stay in L1 all the time. This wastes a
2607 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
|
2608 PCIE_LINK_STATE_L1
|
2609 PCIE_LINK_STATE_CLKPM
);
2612 pci_set_master(pdev
);
2614 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(36));
2616 ret
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(36));
2618 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2620 ret
= pci_set_consistent_dma_mask(pdev
,
2622 /* both attempts failed: */
2624 dev_err(&pdev
->dev
, "No suitable DMA available\n");
2625 goto out_pci_disable_device
;
2629 ret
= pci_request_regions(pdev
, DRV_NAME
);
2631 dev_err(&pdev
->dev
, "pci_request_regions failed\n");
2632 goto out_pci_disable_device
;
2635 trans_pcie
->hw_base
= pci_ioremap_bar(pdev
, 0);
2636 if (!trans_pcie
->hw_base
) {
2637 dev_err(&pdev
->dev
, "pci_ioremap_bar failed\n");
2639 goto out_pci_release_regions
;
2642 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2643 * PCI Tx retries from interfering with C3 CPU state */
2644 pci_write_config_byte(pdev
, PCI_CFG_RETRY_TIMEOUT
, 0x00);
2646 trans
->dev
= &pdev
->dev
;
2647 trans_pcie
->pci_dev
= pdev
;
2648 iwl_disable_interrupts(trans
);
2650 ret
= pci_enable_msi(pdev
);
2652 dev_err(&pdev
->dev
, "pci_enable_msi failed(0X%x)\n", ret
);
2653 /* enable rfkill interrupt: hw bug w/a */
2654 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
2655 if (pci_cmd
& PCI_COMMAND_INTX_DISABLE
) {
2656 pci_cmd
&= ~PCI_COMMAND_INTX_DISABLE
;
2657 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
2661 trans
->hw_rev
= iwl_read32(trans
, CSR_HW_REV
);
2663 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2664 * changed, and now the revision step also includes bit 0-1 (no more
2665 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2666 * in the old format.
2668 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
) {
2669 unsigned long flags
;
2671 trans
->hw_rev
= (trans
->hw_rev
& 0xfff0) |
2672 (CSR_HW_REV_STEP(trans
->hw_rev
<< 2) << 2);
2674 ret
= iwl_pcie_prepare_card_hw(trans
);
2676 IWL_WARN(trans
, "Exit HW not ready\n");
2677 goto out_pci_disable_msi
;
2681 * in-order to recognize C step driver should read chip version
2682 * id located at the AUX bus MISC address space.
2684 iwl_set_bit(trans
, CSR_GP_CNTRL
,
2685 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
2688 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
2689 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
2690 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
2693 IWL_DEBUG_INFO(trans
, "Failed to wake up the nic\n");
2694 goto out_pci_disable_msi
;
2697 if (iwl_trans_grab_nic_access(trans
, &flags
)) {
2700 hw_step
= iwl_read_prph_no_grab(trans
, WFPM_CTRL_REG
);
2701 hw_step
|= ENABLE_WFPM
;
2702 iwl_write_prph_no_grab(trans
, WFPM_CTRL_REG
, hw_step
);
2703 hw_step
= iwl_read_prph_no_grab(trans
, AUX_MISC_REG
);
2704 hw_step
= (hw_step
>> HW_STEP_LOCATION_BITS
) & 0xF;
2706 trans
->hw_rev
= (trans
->hw_rev
& 0xFFFFFFF3) |
2707 (SILICON_C_STEP
<< 2);
2708 iwl_trans_release_nic_access(trans
, &flags
);
2712 trans
->hw_id
= (pdev
->device
<< 16) + pdev
->subsystem_device
;
2713 snprintf(trans
->hw_id_str
, sizeof(trans
->hw_id_str
),
2714 "PCI ID: 0x%04X:0x%04X", pdev
->device
, pdev
->subsystem_device
);
2716 /* Initialize the wait queue for commands */
2717 init_waitqueue_head(&trans_pcie
->wait_command_queue
);
2719 ret
= iwl_pcie_alloc_ict(trans
);
2721 goto out_pci_disable_msi
;
2723 ret
= request_threaded_irq(pdev
->irq
, iwl_pcie_isr
,
2724 iwl_pcie_irq_handler
,
2725 IRQF_SHARED
, DRV_NAME
, trans
);
2727 IWL_ERR(trans
, "Error allocating IRQ %d\n", pdev
->irq
);
2731 trans_pcie
->inta_mask
= CSR_INI_SET_MASK
;
2736 iwl_pcie_free_ict(trans
);
2737 out_pci_disable_msi
:
2738 pci_disable_msi(pdev
);
2739 out_pci_release_regions
:
2740 pci_release_regions(pdev
);
2741 out_pci_disable_device
:
2742 pci_disable_device(pdev
);
2744 free_percpu(trans_pcie
->tso_hdr_page
);
2745 iwl_trans_free(trans
);
2746 return ERR_PTR(ret
);