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[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/version.h>
30 #include <linux/init.h>
31 #include <linux/pci.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/delay.h>
34 #include <linux/skbuff.h>
35 #include <linux/netdevice.h>
36 #include <linux/wireless.h>
37 #include <net/mac80211.h>
38 #include <linux/etherdevice.h>
39 #include <asm/unaligned.h>
40
41 #include "iwl-eeprom.h"
42 #include "iwl-4965.h"
43 #include "iwl-core.h"
44 #include "iwl-io.h"
45 #include "iwl-helpers.h"
46 #include "iwl-calib.h"
47
48 /* module parameters */
49 static struct iwl_mod_params iwl4965_mod_params = {
50 .num_of_queues = IWL4965_MAX_NUM_QUEUES,
51 .enable_qos = 1,
52 .amsdu_size_8K = 1,
53 /* the rest are 0 by default */
54 };
55
56 static void iwl4965_hw_card_show_info(struct iwl_priv *priv);
57
58 #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
59 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
60 IWL_RATE_SISO_##s##M_PLCP, \
61 IWL_RATE_MIMO_##s##M_PLCP, \
62 IWL_RATE_##r##M_IEEE, \
63 IWL_RATE_##ip##M_INDEX, \
64 IWL_RATE_##in##M_INDEX, \
65 IWL_RATE_##rp##M_INDEX, \
66 IWL_RATE_##rn##M_INDEX, \
67 IWL_RATE_##pp##M_INDEX, \
68 IWL_RATE_##np##M_INDEX }
69
70 /*
71 * Parameter order:
72 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
73 *
74 * If there isn't a valid next or previous rate then INV is used which
75 * maps to IWL_RATE_INVALID
76 *
77 */
78 const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = {
79 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
80 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
81 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
82 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
83 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
84 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
85 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
86 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
87 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
88 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
89 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
90 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
91 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
92 };
93
94 #ifdef CONFIG_IWL4965_HT
95
96 static const u16 default_tid_to_tx_fifo[] = {
97 IWL_TX_FIFO_AC1,
98 IWL_TX_FIFO_AC0,
99 IWL_TX_FIFO_AC0,
100 IWL_TX_FIFO_AC1,
101 IWL_TX_FIFO_AC2,
102 IWL_TX_FIFO_AC2,
103 IWL_TX_FIFO_AC3,
104 IWL_TX_FIFO_AC3,
105 IWL_TX_FIFO_NONE,
106 IWL_TX_FIFO_NONE,
107 IWL_TX_FIFO_NONE,
108 IWL_TX_FIFO_NONE,
109 IWL_TX_FIFO_NONE,
110 IWL_TX_FIFO_NONE,
111 IWL_TX_FIFO_NONE,
112 IWL_TX_FIFO_NONE,
113 IWL_TX_FIFO_AC3
114 };
115
116 #endif /*CONFIG_IWL4965_HT */
117
118 /* check contents of special bootstrap uCode SRAM */
119 static int iwl4965_verify_bsm(struct iwl_priv *priv)
120 {
121 __le32 *image = priv->ucode_boot.v_addr;
122 u32 len = priv->ucode_boot.len;
123 u32 reg;
124 u32 val;
125
126 IWL_DEBUG_INFO("Begin verify bsm\n");
127
128 /* verify BSM SRAM contents */
129 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
130 for (reg = BSM_SRAM_LOWER_BOUND;
131 reg < BSM_SRAM_LOWER_BOUND + len;
132 reg += sizeof(u32), image++) {
133 val = iwl_read_prph(priv, reg);
134 if (val != le32_to_cpu(*image)) {
135 IWL_ERROR("BSM uCode verification failed at "
136 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
137 BSM_SRAM_LOWER_BOUND,
138 reg - BSM_SRAM_LOWER_BOUND, len,
139 val, le32_to_cpu(*image));
140 return -EIO;
141 }
142 }
143
144 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
145
146 return 0;
147 }
148
149 /**
150 * iwl4965_load_bsm - Load bootstrap instructions
151 *
152 * BSM operation:
153 *
154 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
155 * in special SRAM that does not power down during RFKILL. When powering back
156 * up after power-saving sleeps (or during initial uCode load), the BSM loads
157 * the bootstrap program into the on-board processor, and starts it.
158 *
159 * The bootstrap program loads (via DMA) instructions and data for a new
160 * program from host DRAM locations indicated by the host driver in the
161 * BSM_DRAM_* registers. Once the new program is loaded, it starts
162 * automatically.
163 *
164 * When initializing the NIC, the host driver points the BSM to the
165 * "initialize" uCode image. This uCode sets up some internal data, then
166 * notifies host via "initialize alive" that it is complete.
167 *
168 * The host then replaces the BSM_DRAM_* pointer values to point to the
169 * normal runtime uCode instructions and a backup uCode data cache buffer
170 * (filled initially with starting data values for the on-board processor),
171 * then triggers the "initialize" uCode to load and launch the runtime uCode,
172 * which begins normal operation.
173 *
174 * When doing a power-save shutdown, runtime uCode saves data SRAM into
175 * the backup data cache in DRAM before SRAM is powered down.
176 *
177 * When powering back up, the BSM loads the bootstrap program. This reloads
178 * the runtime uCode instructions and the backup data cache into SRAM,
179 * and re-launches the runtime uCode from where it left off.
180 */
181 static int iwl4965_load_bsm(struct iwl_priv *priv)
182 {
183 __le32 *image = priv->ucode_boot.v_addr;
184 u32 len = priv->ucode_boot.len;
185 dma_addr_t pinst;
186 dma_addr_t pdata;
187 u32 inst_len;
188 u32 data_len;
189 int i;
190 u32 done;
191 u32 reg_offset;
192 int ret;
193
194 IWL_DEBUG_INFO("Begin load bsm\n");
195
196 /* make sure bootstrap program is no larger than BSM's SRAM size */
197 if (len > IWL_MAX_BSM_SIZE)
198 return -EINVAL;
199
200 /* Tell bootstrap uCode where to find the "Initialize" uCode
201 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
202 * NOTE: iwl4965_initialize_alive_start() will replace these values,
203 * after the "initialize" uCode has run, to point to
204 * runtime/protocol instructions and backup data cache. */
205 pinst = priv->ucode_init.p_addr >> 4;
206 pdata = priv->ucode_init_data.p_addr >> 4;
207 inst_len = priv->ucode_init.len;
208 data_len = priv->ucode_init_data.len;
209
210 ret = iwl_grab_nic_access(priv);
211 if (ret)
212 return ret;
213
214 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
215 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
216 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
217 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
218
219 /* Fill BSM memory with bootstrap instructions */
220 for (reg_offset = BSM_SRAM_LOWER_BOUND;
221 reg_offset < BSM_SRAM_LOWER_BOUND + len;
222 reg_offset += sizeof(u32), image++)
223 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
224
225 ret = iwl4965_verify_bsm(priv);
226 if (ret) {
227 iwl_release_nic_access(priv);
228 return ret;
229 }
230
231 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
232 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
233 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
234 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
235
236 /* Load bootstrap code into instruction SRAM now,
237 * to prepare to load "initialize" uCode */
238 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
239
240 /* Wait for load of bootstrap uCode to finish */
241 for (i = 0; i < 100; i++) {
242 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
243 if (!(done & BSM_WR_CTRL_REG_BIT_START))
244 break;
245 udelay(10);
246 }
247 if (i < 100)
248 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
249 else {
250 IWL_ERROR("BSM write did not complete!\n");
251 return -EIO;
252 }
253
254 /* Enable future boot loads whenever power management unit triggers it
255 * (e.g. when powering back up after power-save shutdown) */
256 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
257
258 iwl_release_nic_access(priv);
259
260 return 0;
261 }
262
263 static int iwl4965_init_drv(struct iwl_priv *priv)
264 {
265 int ret;
266 int i;
267
268 priv->antenna = (enum iwl4965_antenna)priv->cfg->mod_params->antenna;
269 priv->retry_rate = 1;
270 priv->ibss_beacon = NULL;
271
272 spin_lock_init(&priv->lock);
273 spin_lock_init(&priv->power_data.lock);
274 spin_lock_init(&priv->sta_lock);
275 spin_lock_init(&priv->hcmd_lock);
276 spin_lock_init(&priv->lq_mngr.lock);
277
278 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
279 sizeof(struct iwl4965_shared),
280 &priv->shared_phys);
281
282 if (!priv->shared_virt) {
283 ret = -ENOMEM;
284 goto err;
285 }
286
287 memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
288
289
290 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
291 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
292
293 INIT_LIST_HEAD(&priv->free_frames);
294
295 mutex_init(&priv->mutex);
296
297 /* Clear the driver's (not device's) station table */
298 iwlcore_clear_stations_table(priv);
299
300 priv->data_retry_limit = -1;
301 priv->ieee_channels = NULL;
302 priv->ieee_rates = NULL;
303 priv->band = IEEE80211_BAND_2GHZ;
304
305 priv->iw_mode = IEEE80211_IF_TYPE_STA;
306
307 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
308 priv->valid_antenna = 0x7; /* assume all 3 connected */
309 priv->ps_mode = IWL_MIMO_PS_NONE;
310
311 /* Choose which receivers/antennas to use */
312 iwl4965_set_rxon_chain(priv);
313
314 iwlcore_reset_qos(priv);
315
316 priv->qos_data.qos_active = 0;
317 priv->qos_data.qos_cap.val = 0;
318
319 iwlcore_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
320
321 priv->rates_mask = IWL_RATES_MASK;
322 /* If power management is turned on, default to AC mode */
323 priv->power_mode = IWL_POWER_AC;
324 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
325
326 ret = iwl_init_channel_map(priv);
327 if (ret) {
328 IWL_ERROR("initializing regulatory failed: %d\n", ret);
329 goto err;
330 }
331
332 ret = iwl4965_init_geos(priv);
333 if (ret) {
334 IWL_ERROR("initializing geos failed: %d\n", ret);
335 goto err_free_channel_map;
336 }
337
338 ret = ieee80211_register_hw(priv->hw);
339 if (ret) {
340 IWL_ERROR("Failed to register network device (error %d)\n",
341 ret);
342 goto err_free_geos;
343 }
344
345 priv->hw->conf.beacon_int = 100;
346 priv->mac80211_registered = 1;
347
348 return 0;
349
350 err_free_geos:
351 iwl4965_free_geos(priv);
352 err_free_channel_map:
353 iwl_free_channel_map(priv);
354 err:
355 return ret;
356 }
357
358 static int is_fat_channel(__le32 rxon_flags)
359 {
360 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
361 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
362 }
363
364 static u8 is_single_stream(struct iwl_priv *priv)
365 {
366 #ifdef CONFIG_IWL4965_HT
367 if (!priv->current_ht_config.is_ht ||
368 (priv->current_ht_config.supp_mcs_set[1] == 0) ||
369 (priv->ps_mode == IWL_MIMO_PS_STATIC))
370 return 1;
371 #else
372 return 1;
373 #endif /*CONFIG_IWL4965_HT */
374 return 0;
375 }
376
377 int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
378 {
379 int idx = 0;
380
381 /* 4965 HT rate format */
382 if (rate_n_flags & RATE_MCS_HT_MSK) {
383 idx = (rate_n_flags & 0xff);
384
385 if (idx >= IWL_RATE_MIMO_6M_PLCP)
386 idx = idx - IWL_RATE_MIMO_6M_PLCP;
387
388 idx += IWL_FIRST_OFDM_RATE;
389 /* skip 9M not supported in ht*/
390 if (idx >= IWL_RATE_9M_INDEX)
391 idx += 1;
392 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
393 return idx;
394
395 /* 4965 legacy rate format, search for match in table */
396 } else {
397 for (idx = 0; idx < ARRAY_SIZE(iwl4965_rates); idx++)
398 if (iwl4965_rates[idx].plcp == (rate_n_flags & 0xFF))
399 return idx;
400 }
401
402 return -1;
403 }
404
405 /**
406 * translate ucode response to mac80211 tx status control values
407 */
408 void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
409 struct ieee80211_tx_control *control)
410 {
411 int rate_index;
412
413 control->antenna_sel_tx =
414 ((rate_n_flags & RATE_MCS_ANT_AB_MSK) >> RATE_MCS_ANT_POS);
415 if (rate_n_flags & RATE_MCS_HT_MSK)
416 control->flags |= IEEE80211_TXCTL_OFDM_HT;
417 if (rate_n_flags & RATE_MCS_GF_MSK)
418 control->flags |= IEEE80211_TXCTL_GREEN_FIELD;
419 if (rate_n_flags & RATE_MCS_FAT_MSK)
420 control->flags |= IEEE80211_TXCTL_40_MHZ_WIDTH;
421 if (rate_n_flags & RATE_MCS_DUP_MSK)
422 control->flags |= IEEE80211_TXCTL_DUP_DATA;
423 if (rate_n_flags & RATE_MCS_SGI_MSK)
424 control->flags |= IEEE80211_TXCTL_SHORT_GI;
425 /* since iwl4965_hwrate_to_plcp_idx is band indifferent, we always use
426 * IEEE80211_BAND_2GHZ band as it contains all the rates */
427 rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
428 if (rate_index == -1)
429 control->tx_rate = NULL;
430 else
431 control->tx_rate =
432 &priv->bands[IEEE80211_BAND_2GHZ].bitrates[rate_index];
433 }
434
435 /*
436 * Determine how many receiver/antenna chains to use.
437 * More provides better reception via diversity. Fewer saves power.
438 * MIMO (dual stream) requires at least 2, but works better with 3.
439 * This does not determine *which* chains to use, just how many.
440 */
441 static int iwl4965_get_rx_chain_counter(struct iwl_priv *priv,
442 u8 *idle_state, u8 *rx_state)
443 {
444 u8 is_single = is_single_stream(priv);
445 u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
446
447 /* # of Rx chains to use when expecting MIMO. */
448 if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
449 *rx_state = 2;
450 else
451 *rx_state = 3;
452
453 /* # Rx chains when idling and maybe trying to save power */
454 switch (priv->ps_mode) {
455 case IWL_MIMO_PS_STATIC:
456 case IWL_MIMO_PS_DYNAMIC:
457 *idle_state = (is_cam) ? 2 : 1;
458 break;
459 case IWL_MIMO_PS_NONE:
460 *idle_state = (is_cam) ? *rx_state : 1;
461 break;
462 default:
463 *idle_state = 1;
464 break;
465 }
466
467 return 0;
468 }
469
470 int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
471 {
472 int rc;
473 unsigned long flags;
474
475 spin_lock_irqsave(&priv->lock, flags);
476 rc = iwl_grab_nic_access(priv);
477 if (rc) {
478 spin_unlock_irqrestore(&priv->lock, flags);
479 return rc;
480 }
481
482 /* stop Rx DMA */
483 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
484 rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
485 (1 << 24), 1000);
486 if (rc < 0)
487 IWL_ERROR("Can't stop Rx DMA.\n");
488
489 iwl_release_nic_access(priv);
490 spin_unlock_irqrestore(&priv->lock, flags);
491
492 return 0;
493 }
494
495 static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
496 {
497 int ret;
498 unsigned long flags;
499
500 spin_lock_irqsave(&priv->lock, flags);
501 ret = iwl_grab_nic_access(priv);
502 if (ret) {
503 spin_unlock_irqrestore(&priv->lock, flags);
504 return ret;
505 }
506
507 if (!pwr_max) {
508 u32 val;
509
510 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
511 &val);
512
513 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT)
514 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
515 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
516 ~APMG_PS_CTRL_MSK_PWR_SRC);
517 } else
518 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
519 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
520 ~APMG_PS_CTRL_MSK_PWR_SRC);
521
522 iwl_release_nic_access(priv);
523 spin_unlock_irqrestore(&priv->lock, flags);
524
525 return ret;
526 }
527
528 static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
529 {
530 int ret;
531 unsigned long flags;
532 unsigned int rb_size;
533
534 spin_lock_irqsave(&priv->lock, flags);
535 ret = iwl_grab_nic_access(priv);
536 if (ret) {
537 spin_unlock_irqrestore(&priv->lock, flags);
538 return ret;
539 }
540
541 if (priv->cfg->mod_params->amsdu_size_8K)
542 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
543 else
544 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
545
546 /* Stop Rx DMA */
547 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
548
549 /* Reset driver's Rx queue write index */
550 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
551
552 /* Tell device where to find RBD circular buffer in DRAM */
553 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
554 rxq->dma_addr >> 8);
555
556 /* Tell device where in DRAM to update its Rx status */
557 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
558 (priv->shared_phys +
559 offsetof(struct iwl4965_shared, rb_closed)) >> 4);
560
561 /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
562 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
563 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
564 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
565 rb_size |
566 /* 0x10 << 4 | */
567 (RX_QUEUE_SIZE_LOG <<
568 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
569
570 /*
571 * iwl_write32(priv,CSR_INT_COAL_REG,0);
572 */
573
574 iwl_release_nic_access(priv);
575 spin_unlock_irqrestore(&priv->lock, flags);
576
577 return 0;
578 }
579
580 /* Tell 4965 where to find the "keep warm" buffer */
581 static int iwl4965_kw_init(struct iwl_priv *priv)
582 {
583 unsigned long flags;
584 int rc;
585
586 spin_lock_irqsave(&priv->lock, flags);
587 rc = iwl_grab_nic_access(priv);
588 if (rc)
589 goto out;
590
591 iwl_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
592 priv->kw.dma_addr >> 4);
593 iwl_release_nic_access(priv);
594 out:
595 spin_unlock_irqrestore(&priv->lock, flags);
596 return rc;
597 }
598
599 static int iwl4965_kw_alloc(struct iwl_priv *priv)
600 {
601 struct pci_dev *dev = priv->pci_dev;
602 struct iwl4965_kw *kw = &priv->kw;
603
604 kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */
605 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
606 if (!kw->v_addr)
607 return -ENOMEM;
608
609 return 0;
610 }
611
612 /**
613 * iwl4965_kw_free - Free the "keep warm" buffer
614 */
615 static void iwl4965_kw_free(struct iwl_priv *priv)
616 {
617 struct pci_dev *dev = priv->pci_dev;
618 struct iwl4965_kw *kw = &priv->kw;
619
620 if (kw->v_addr) {
621 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
622 memset(kw, 0, sizeof(*kw));
623 }
624 }
625
626 /**
627 * iwl4965_txq_ctx_reset - Reset TX queue context
628 * Destroys all DMA structures and initialise them again
629 *
630 * @param priv
631 * @return error code
632 */
633 static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
634 {
635 int rc = 0;
636 int txq_id, slots_num;
637 unsigned long flags;
638
639 iwl4965_kw_free(priv);
640
641 /* Free all tx/cmd queues and keep-warm buffer */
642 iwl4965_hw_txq_ctx_free(priv);
643
644 /* Alloc keep-warm buffer */
645 rc = iwl4965_kw_alloc(priv);
646 if (rc) {
647 IWL_ERROR("Keep Warm allocation failed");
648 goto error_kw;
649 }
650
651 spin_lock_irqsave(&priv->lock, flags);
652
653 rc = iwl_grab_nic_access(priv);
654 if (unlikely(rc)) {
655 IWL_ERROR("TX reset failed");
656 spin_unlock_irqrestore(&priv->lock, flags);
657 goto error_reset;
658 }
659
660 /* Turn off all Tx DMA channels */
661 iwl_write_prph(priv, IWL49_SCD_TXFACT, 0);
662 iwl_release_nic_access(priv);
663 spin_unlock_irqrestore(&priv->lock, flags);
664
665 /* Tell 4965 where to find the keep-warm buffer */
666 rc = iwl4965_kw_init(priv);
667 if (rc) {
668 IWL_ERROR("kw_init failed\n");
669 goto error_reset;
670 }
671
672 /* Alloc and init all (default 16) Tx queues,
673 * including the command queue (#4) */
674 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
675 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
676 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
677 rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
678 txq_id);
679 if (rc) {
680 IWL_ERROR("Tx %d queue init failed\n", txq_id);
681 goto error;
682 }
683 }
684
685 return rc;
686
687 error:
688 iwl4965_hw_txq_ctx_free(priv);
689 error_reset:
690 iwl4965_kw_free(priv);
691 error_kw:
692 return rc;
693 }
694
695 int iwl4965_hw_nic_init(struct iwl_priv *priv)
696 {
697 int rc;
698 unsigned long flags;
699 struct iwl4965_rx_queue *rxq = &priv->rxq;
700 u8 rev_id;
701 u32 val;
702 u8 val_link;
703
704 iwl4965_power_init_handle(priv);
705
706 /* nic_init */
707 spin_lock_irqsave(&priv->lock, flags);
708
709 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
710 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
711
712 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
713 rc = iwl_poll_bit(priv, CSR_GP_CNTRL,
714 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
715 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
716 if (rc < 0) {
717 spin_unlock_irqrestore(&priv->lock, flags);
718 IWL_DEBUG_INFO("Failed to init the card\n");
719 return rc;
720 }
721
722 rc = iwl_grab_nic_access(priv);
723 if (rc) {
724 spin_unlock_irqrestore(&priv->lock, flags);
725 return rc;
726 }
727
728 iwl_read_prph(priv, APMG_CLK_CTRL_REG);
729
730 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
731 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
732 iwl_read_prph(priv, APMG_CLK_CTRL_REG);
733
734 udelay(20);
735
736 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
737 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
738
739 iwl_release_nic_access(priv);
740 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
741 spin_unlock_irqrestore(&priv->lock, flags);
742
743 /* Determine HW type */
744 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
745 if (rc)
746 return rc;
747
748 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
749
750 iwl4965_nic_set_pwr_src(priv, 1);
751 spin_lock_irqsave(&priv->lock, flags);
752
753 if ((rev_id & 0x80) == 0x80 && (rev_id & 0x7f) < 8) {
754 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
755 /* Enable No Snoop field */
756 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
757 val & ~(1 << 11));
758 }
759
760 spin_unlock_irqrestore(&priv->lock, flags);
761
762 if (priv->eeprom.calib_version < EEPROM_TX_POWER_VERSION_NEW) {
763 IWL_ERROR("Older EEPROM detected! Aborting.\n");
764 return -EINVAL;
765 }
766
767 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
768
769 /* disable L1 entry -- workaround for pre-B1 */
770 pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
771
772 spin_lock_irqsave(&priv->lock, flags);
773
774 /* set CSR_HW_CONFIG_REG for uCode use */
775
776 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
777 CSR49_HW_IF_CONFIG_REG_BIT_4965_R |
778 CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI |
779 CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI);
780
781 rc = iwl_grab_nic_access(priv);
782 if (rc < 0) {
783 spin_unlock_irqrestore(&priv->lock, flags);
784 IWL_DEBUG_INFO("Failed to init the card\n");
785 return rc;
786 }
787
788 iwl_read_prph(priv, APMG_PS_CTRL_REG);
789 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
790 udelay(5);
791 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
792
793 iwl_release_nic_access(priv);
794 spin_unlock_irqrestore(&priv->lock, flags);
795
796 iwl4965_hw_card_show_info(priv);
797
798 /* end nic_init */
799
800 /* Allocate the RX queue, or reset if it is already allocated */
801 if (!rxq->bd) {
802 rc = iwl4965_rx_queue_alloc(priv);
803 if (rc) {
804 IWL_ERROR("Unable to initialize Rx queue\n");
805 return -ENOMEM;
806 }
807 } else
808 iwl4965_rx_queue_reset(priv, rxq);
809
810 iwl4965_rx_replenish(priv);
811
812 iwl4965_rx_init(priv, rxq);
813
814 spin_lock_irqsave(&priv->lock, flags);
815
816 rxq->need_update = 1;
817 iwl4965_rx_queue_update_write_ptr(priv, rxq);
818
819 spin_unlock_irqrestore(&priv->lock, flags);
820
821 /* Allocate and init all Tx and Command queues */
822 rc = iwl4965_txq_ctx_reset(priv);
823 if (rc)
824 return rc;
825
826 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
827 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
828
829 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
830 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
831
832 set_bit(STATUS_INIT, &priv->status);
833
834 return 0;
835 }
836
837 int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
838 {
839 int rc = 0;
840 u32 reg_val;
841 unsigned long flags;
842
843 spin_lock_irqsave(&priv->lock, flags);
844
845 /* set stop master bit */
846 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
847
848 reg_val = iwl_read32(priv, CSR_GP_CNTRL);
849
850 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
851 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
852 IWL_DEBUG_INFO("Card in power save, master is already "
853 "stopped\n");
854 else {
855 rc = iwl_poll_bit(priv, CSR_RESET,
856 CSR_RESET_REG_FLAG_MASTER_DISABLED,
857 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
858 if (rc < 0) {
859 spin_unlock_irqrestore(&priv->lock, flags);
860 return rc;
861 }
862 }
863
864 spin_unlock_irqrestore(&priv->lock, flags);
865 IWL_DEBUG_INFO("stop master\n");
866
867 return rc;
868 }
869
870 /**
871 * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
872 */
873 void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
874 {
875
876 int txq_id;
877 unsigned long flags;
878
879 /* Stop each Tx DMA channel, and wait for it to be idle */
880 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
881 spin_lock_irqsave(&priv->lock, flags);
882 if (iwl_grab_nic_access(priv)) {
883 spin_unlock_irqrestore(&priv->lock, flags);
884 continue;
885 }
886
887 iwl_write_direct32(priv,
888 IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
889 iwl_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
890 IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
891 (txq_id), 200);
892 iwl_release_nic_access(priv);
893 spin_unlock_irqrestore(&priv->lock, flags);
894 }
895
896 /* Deallocate memory for all Tx queues */
897 iwl4965_hw_txq_ctx_free(priv);
898 }
899
900 int iwl4965_hw_nic_reset(struct iwl_priv *priv)
901 {
902 int rc = 0;
903 unsigned long flags;
904
905 iwl4965_hw_nic_stop_master(priv);
906
907 spin_lock_irqsave(&priv->lock, flags);
908
909 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
910
911 udelay(10);
912
913 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
914 rc = iwl_poll_bit(priv, CSR_RESET,
915 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
916 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
917
918 udelay(10);
919
920 rc = iwl_grab_nic_access(priv);
921 if (!rc) {
922 iwl_write_prph(priv, APMG_CLK_EN_REG,
923 APMG_CLK_VAL_DMA_CLK_RQT |
924 APMG_CLK_VAL_BSM_CLK_RQT);
925
926 udelay(10);
927
928 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
929 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
930
931 iwl_release_nic_access(priv);
932 }
933
934 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
935 wake_up_interruptible(&priv->wait_command_queue);
936
937 spin_unlock_irqrestore(&priv->lock, flags);
938
939 return rc;
940
941 }
942
943 #define REG_RECALIB_PERIOD (60)
944
945 /**
946 * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
947 *
948 * This callback is provided in order to send a statistics request.
949 *
950 * This timer function is continually reset to execute within
951 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
952 * was received. We need to ensure we receive the statistics in order
953 * to update the temperature used for calibrating the TXPOWER.
954 */
955 static void iwl4965_bg_statistics_periodic(unsigned long data)
956 {
957 struct iwl_priv *priv = (struct iwl_priv *)data;
958
959 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
960 return;
961
962 iwl_send_statistics_request(priv, CMD_ASYNC);
963 }
964
965 #define CT_LIMIT_CONST 259
966 #define TM_CT_KILL_THRESHOLD 110
967
968 void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
969 {
970 struct iwl4965_ct_kill_config cmd;
971 u32 R1, R2, R3;
972 u32 temp_th;
973 u32 crit_temperature;
974 unsigned long flags;
975 int ret = 0;
976
977 spin_lock_irqsave(&priv->lock, flags);
978 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
979 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
980 spin_unlock_irqrestore(&priv->lock, flags);
981
982 if (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK) {
983 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
984 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
985 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
986 } else {
987 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
988 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
989 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
990 }
991
992 temp_th = CELSIUS_TO_KELVIN(TM_CT_KILL_THRESHOLD);
993
994 crit_temperature = ((temp_th * (R3-R1))/CT_LIMIT_CONST) + R2;
995 cmd.critical_temperature_R = cpu_to_le32(crit_temperature);
996 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
997 sizeof(cmd), &cmd);
998 if (ret)
999 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1000 else
1001 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded\n");
1002 }
1003
1004 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1005
1006 /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
1007 * Called after every association, but this runs only once!
1008 * ... once chain noise is calibrated the first time, it's good forever. */
1009 static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
1010 {
1011 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
1012
1013 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
1014 struct iwl4965_calibration_cmd cmd;
1015
1016 memset(&cmd, 0, sizeof(cmd));
1017 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1018 cmd.diff_gain_a = 0;
1019 cmd.diff_gain_b = 0;
1020 cmd.diff_gain_c = 0;
1021 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
1022 sizeof(cmd), &cmd))
1023 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
1024 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
1025 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
1026 }
1027 }
1028
1029 static void iwl4965_gain_computation(struct iwl_priv *priv,
1030 u32 *average_noise,
1031 u16 min_average_noise_antenna_i,
1032 u32 min_average_noise)
1033 {
1034 int i, ret;
1035 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
1036
1037 data->delta_gain_code[min_average_noise_antenna_i] = 0;
1038
1039 for (i = 0; i < NUM_RX_CHAINS; i++) {
1040 s32 delta_g = 0;
1041
1042 if (!(data->disconn_array[i]) &&
1043 (data->delta_gain_code[i] ==
1044 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
1045 delta_g = average_noise[i] - min_average_noise;
1046 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
1047 data->delta_gain_code[i] =
1048 min(data->delta_gain_code[i],
1049 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
1050
1051 data->delta_gain_code[i] =
1052 (data->delta_gain_code[i] | (1 << 2));
1053 } else {
1054 data->delta_gain_code[i] = 0;
1055 }
1056 }
1057 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
1058 data->delta_gain_code[0],
1059 data->delta_gain_code[1],
1060 data->delta_gain_code[2]);
1061
1062 /* Differential gain gets sent to uCode only once */
1063 if (!data->radio_write) {
1064 struct iwl4965_calibration_cmd cmd;
1065 data->radio_write = 1;
1066
1067 memset(&cmd, 0, sizeof(cmd));
1068 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1069 cmd.diff_gain_a = data->delta_gain_code[0];
1070 cmd.diff_gain_b = data->delta_gain_code[1];
1071 cmd.diff_gain_c = data->delta_gain_code[2];
1072 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
1073 sizeof(cmd), &cmd);
1074 if (ret)
1075 IWL_DEBUG_CALIB("fail sending cmd "
1076 "REPLY_PHY_CALIBRATION_CMD \n");
1077
1078 /* TODO we might want recalculate
1079 * rx_chain in rxon cmd */
1080
1081 /* Mark so we run this algo only once! */
1082 data->state = IWL_CHAIN_NOISE_CALIBRATED;
1083 }
1084 data->chain_noise_a = 0;
1085 data->chain_noise_b = 0;
1086 data->chain_noise_c = 0;
1087 data->chain_signal_a = 0;
1088 data->chain_signal_b = 0;
1089 data->chain_signal_c = 0;
1090 data->beacon_count = 0;
1091 }
1092
1093 static void iwl4965_bg_sensitivity_work(struct work_struct *work)
1094 {
1095 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1096 sensitivity_work);
1097
1098 mutex_lock(&priv->mutex);
1099
1100 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1101 test_bit(STATUS_SCANNING, &priv->status)) {
1102 mutex_unlock(&priv->mutex);
1103 return;
1104 }
1105
1106 if (priv->start_calib) {
1107 iwl_chain_noise_calibration(priv, &priv->statistics);
1108
1109 iwl_sensitivity_calibration(priv, &priv->statistics);
1110 }
1111
1112 mutex_unlock(&priv->mutex);
1113 return;
1114 }
1115 #endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
1116
1117 static void iwl4965_bg_txpower_work(struct work_struct *work)
1118 {
1119 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1120 txpower_work);
1121
1122 /* If a scan happened to start before we got here
1123 * then just return; the statistics notification will
1124 * kick off another scheduled work to compensate for
1125 * any temperature delta we missed here. */
1126 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1127 test_bit(STATUS_SCANNING, &priv->status))
1128 return;
1129
1130 mutex_lock(&priv->mutex);
1131
1132 /* Regardless of if we are assocaited, we must reconfigure the
1133 * TX power since frames can be sent on non-radar channels while
1134 * not associated */
1135 iwl4965_hw_reg_send_txpower(priv);
1136
1137 /* Update last_temperature to keep is_calib_needed from running
1138 * when it isn't needed... */
1139 priv->last_temperature = priv->temperature;
1140
1141 mutex_unlock(&priv->mutex);
1142 }
1143
1144 /*
1145 * Acquire priv->lock before calling this function !
1146 */
1147 static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
1148 {
1149 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
1150 (index & 0xff) | (txq_id << 8));
1151 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
1152 }
1153
1154 /**
1155 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
1156 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
1157 * @scd_retry: (1) Indicates queue will be used in aggregation mode
1158 *
1159 * NOTE: Acquire priv->lock before calling this function !
1160 */
1161 static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
1162 struct iwl4965_tx_queue *txq,
1163 int tx_fifo_id, int scd_retry)
1164 {
1165 int txq_id = txq->q.id;
1166
1167 /* Find out whether to activate Tx queue */
1168 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
1169
1170 /* Set up and activate */
1171 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
1172 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1173 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
1174 (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
1175 (scd_retry << SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
1176 SCD_QUEUE_STTS_REG_MSK);
1177
1178 txq->sched_retry = scd_retry;
1179
1180 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
1181 active ? "Activate" : "Deactivate",
1182 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
1183 }
1184
1185 static const u16 default_queue_to_tx_fifo[] = {
1186 IWL_TX_FIFO_AC3,
1187 IWL_TX_FIFO_AC2,
1188 IWL_TX_FIFO_AC1,
1189 IWL_TX_FIFO_AC0,
1190 IWL_CMD_FIFO_NUM,
1191 IWL_TX_FIFO_HCCA_1,
1192 IWL_TX_FIFO_HCCA_2
1193 };
1194
1195 static inline void iwl4965_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1196 {
1197 set_bit(txq_id, &priv->txq_ctx_active_msk);
1198 }
1199
1200 static inline void iwl4965_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1201 {
1202 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1203 }
1204
1205 int iwl4965_alive_notify(struct iwl_priv *priv)
1206 {
1207 u32 a;
1208 int i = 0;
1209 unsigned long flags;
1210 int ret;
1211
1212 spin_lock_irqsave(&priv->lock, flags);
1213
1214 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1215 memset(&(priv->sensitivity_data), 0,
1216 sizeof(struct iwl_sensitivity_data));
1217 memset(&(priv->chain_noise_data), 0,
1218 sizeof(struct iwl_chain_noise_data));
1219 for (i = 0; i < NUM_RX_CHAINS; i++)
1220 priv->chain_noise_data.delta_gain_code[i] =
1221 CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
1222 #endif /* CONFIG_IWL4965_RUN_TIME_CALIB*/
1223 ret = iwl_grab_nic_access(priv);
1224 if (ret) {
1225 spin_unlock_irqrestore(&priv->lock, flags);
1226 return ret;
1227 }
1228
1229 /* Clear 4965's internal Tx Scheduler data base */
1230 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
1231 a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
1232 for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
1233 iwl_write_targ_mem(priv, a, 0);
1234 for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
1235 iwl_write_targ_mem(priv, a, 0);
1236 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
1237 iwl_write_targ_mem(priv, a, 0);
1238
1239 /* Tel 4965 where to find Tx byte count tables */
1240 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
1241 (priv->shared_phys +
1242 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
1243
1244 /* Disable chain mode for all queues */
1245 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
1246
1247 /* Initialize each Tx queue (including the command queue) */
1248 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
1249
1250 /* TFD circular buffer read/write indexes */
1251 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
1252 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
1253
1254 /* Max Tx Window size for Scheduler-ACK mode */
1255 iwl_write_targ_mem(priv, priv->scd_base_addr +
1256 SCD_CONTEXT_QUEUE_OFFSET(i),
1257 (SCD_WIN_SIZE <<
1258 SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1259 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
1260
1261 /* Frame limit */
1262 iwl_write_targ_mem(priv, priv->scd_base_addr +
1263 SCD_CONTEXT_QUEUE_OFFSET(i) +
1264 sizeof(u32),
1265 (SCD_FRAME_LIMIT <<
1266 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1267 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1268
1269 }
1270 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
1271 (1 << priv->hw_params.max_txq_num) - 1);
1272
1273 /* Activate all Tx DMA/FIFO channels */
1274 iwl_write_prph(priv, IWL49_SCD_TXFACT,
1275 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
1276
1277 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
1278
1279 /* Map each Tx/cmd queue to its corresponding fifo */
1280 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
1281 int ac = default_queue_to_tx_fifo[i];
1282 iwl4965_txq_ctx_activate(priv, i);
1283 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
1284 }
1285
1286 iwl_release_nic_access(priv);
1287 spin_unlock_irqrestore(&priv->lock, flags);
1288
1289 /* Ask for statistics now, the uCode will send statistics notification
1290 * periodically after association */
1291 iwl_send_statistics_request(priv, CMD_ASYNC);
1292 return ret;
1293 }
1294
1295 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1296 static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
1297 .min_nrg_cck = 97,
1298 .max_nrg_cck = 0,
1299
1300 .auto_corr_min_ofdm = 85,
1301 .auto_corr_min_ofdm_mrc = 170,
1302 .auto_corr_min_ofdm_x1 = 105,
1303 .auto_corr_min_ofdm_mrc_x1 = 220,
1304
1305 .auto_corr_max_ofdm = 120,
1306 .auto_corr_max_ofdm_mrc = 210,
1307 .auto_corr_max_ofdm_x1 = 140,
1308 .auto_corr_max_ofdm_mrc_x1 = 270,
1309
1310 .auto_corr_min_cck = 125,
1311 .auto_corr_max_cck = 200,
1312 .auto_corr_min_cck_mrc = 200,
1313 .auto_corr_max_cck_mrc = 400,
1314
1315 .nrg_th_cck = 100,
1316 .nrg_th_ofdm = 100,
1317 };
1318 #endif
1319
1320 /**
1321 * iwl4965_hw_set_hw_params
1322 *
1323 * Called when initializing driver
1324 */
1325 int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
1326 {
1327
1328 if ((priv->cfg->mod_params->num_of_queues > IWL4965_MAX_NUM_QUEUES) ||
1329 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
1330 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
1331 IWL_MIN_NUM_QUEUES, IWL4965_MAX_NUM_QUEUES);
1332 return -EINVAL;
1333 }
1334
1335 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
1336 priv->hw_params.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
1337 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1338 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1339 if (priv->cfg->mod_params->amsdu_size_8K)
1340 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
1341 else
1342 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
1343 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
1344 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
1345 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
1346
1347 priv->hw_params.tx_chains_num = 2;
1348 priv->hw_params.rx_chains_num = 2;
1349 priv->hw_params.valid_tx_ant = (IWL_ANTENNA_MAIN | IWL_ANTENNA_AUX);
1350 priv->hw_params.valid_rx_ant = (IWL_ANTENNA_MAIN | IWL_ANTENNA_AUX);
1351 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1352 priv->hw_params.sens = &iwl4965_sensitivity;
1353 #endif
1354
1355 return 0;
1356 }
1357
1358 /**
1359 * iwl4965_hw_txq_ctx_free - Free TXQ Context
1360 *
1361 * Destroy all TX DMA queues and structures
1362 */
1363 void iwl4965_hw_txq_ctx_free(struct iwl_priv *priv)
1364 {
1365 int txq_id;
1366
1367 /* Tx queues */
1368 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1369 iwl4965_tx_queue_free(priv, &priv->txq[txq_id]);
1370
1371 /* Keep-warm buffer */
1372 iwl4965_kw_free(priv);
1373 }
1374
1375 /**
1376 * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
1377 *
1378 * Does NOT advance any TFD circular buffer read/write indexes
1379 * Does NOT free the TFD itself (which is within circular buffer)
1380 */
1381 int iwl4965_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
1382 {
1383 struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0];
1384 struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
1385 struct pci_dev *dev = priv->pci_dev;
1386 int i;
1387 int counter = 0;
1388 int index, is_odd;
1389
1390 /* Host command buffers stay mapped in memory, nothing to clean */
1391 if (txq->q.id == IWL_CMD_QUEUE_NUM)
1392 return 0;
1393
1394 /* Sanity check on number of chunks */
1395 counter = IWL_GET_BITS(*bd, num_tbs);
1396 if (counter > MAX_NUM_OF_TBS) {
1397 IWL_ERROR("Too many chunks: %i\n", counter);
1398 /* @todo issue fatal error, it is quite serious situation */
1399 return 0;
1400 }
1401
1402 /* Unmap chunks, if any.
1403 * TFD info for odd chunks is different format than for even chunks. */
1404 for (i = 0; i < counter; i++) {
1405 index = i / 2;
1406 is_odd = i & 0x1;
1407
1408 if (is_odd)
1409 pci_unmap_single(
1410 dev,
1411 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
1412 (IWL_GET_BITS(bd->pa[index],
1413 tb2_addr_hi20) << 16),
1414 IWL_GET_BITS(bd->pa[index], tb2_len),
1415 PCI_DMA_TODEVICE);
1416
1417 else if (i > 0)
1418 pci_unmap_single(dev,
1419 le32_to_cpu(bd->pa[index].tb1_addr),
1420 IWL_GET_BITS(bd->pa[index], tb1_len),
1421 PCI_DMA_TODEVICE);
1422
1423 /* Free SKB, if any, for this chunk */
1424 if (txq->txb[txq->q.read_ptr].skb[i]) {
1425 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
1426
1427 dev_kfree_skb(skb);
1428 txq->txb[txq->q.read_ptr].skb[i] = NULL;
1429 }
1430 }
1431 return 0;
1432 }
1433
1434 int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1435 {
1436 IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
1437 return -EINVAL;
1438 }
1439
1440 static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
1441 {
1442 s32 sign = 1;
1443
1444 if (num < 0) {
1445 sign = -sign;
1446 num = -num;
1447 }
1448 if (denom < 0) {
1449 sign = -sign;
1450 denom = -denom;
1451 }
1452 *res = 1;
1453 *res = ((num * 2 + denom) / (denom * 2)) * sign;
1454
1455 return 1;
1456 }
1457
1458 /**
1459 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
1460 *
1461 * Determines power supply voltage compensation for txpower calculations.
1462 * Returns number of 1/2-dB steps to subtract from gain table index,
1463 * to compensate for difference between power supply voltage during
1464 * factory measurements, vs. current power supply voltage.
1465 *
1466 * Voltage indication is higher for lower voltage.
1467 * Lower voltage requires more gain (lower gain table index).
1468 */
1469 static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
1470 s32 current_voltage)
1471 {
1472 s32 comp = 0;
1473
1474 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
1475 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
1476 return 0;
1477
1478 iwl4965_math_div_round(current_voltage - eeprom_voltage,
1479 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
1480
1481 if (current_voltage > eeprom_voltage)
1482 comp *= 2;
1483 if ((comp < -2) || (comp > 2))
1484 comp = 0;
1485
1486 return comp;
1487 }
1488
1489 static const struct iwl_channel_info *
1490 iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
1491 enum ieee80211_band band, u16 channel)
1492 {
1493 const struct iwl_channel_info *ch_info;
1494
1495 ch_info = iwl_get_channel_info(priv, band, channel);
1496
1497 if (!is_channel_valid(ch_info))
1498 return NULL;
1499
1500 return ch_info;
1501 }
1502
1503 static s32 iwl4965_get_tx_atten_grp(u16 channel)
1504 {
1505 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
1506 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
1507 return CALIB_CH_GROUP_5;
1508
1509 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
1510 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
1511 return CALIB_CH_GROUP_1;
1512
1513 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
1514 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
1515 return CALIB_CH_GROUP_2;
1516
1517 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
1518 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
1519 return CALIB_CH_GROUP_3;
1520
1521 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
1522 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
1523 return CALIB_CH_GROUP_4;
1524
1525 IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
1526 return -1;
1527 }
1528
1529 static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
1530 {
1531 s32 b = -1;
1532
1533 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
1534 if (priv->eeprom.calib_info.band_info[b].ch_from == 0)
1535 continue;
1536
1537 if ((channel >= priv->eeprom.calib_info.band_info[b].ch_from)
1538 && (channel <= priv->eeprom.calib_info.band_info[b].ch_to))
1539 break;
1540 }
1541
1542 return b;
1543 }
1544
1545 static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
1546 {
1547 s32 val;
1548
1549 if (x2 == x1)
1550 return y1;
1551 else {
1552 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
1553 return val + y2;
1554 }
1555 }
1556
1557 /**
1558 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
1559 *
1560 * Interpolates factory measurements from the two sample channels within a
1561 * sub-band, to apply to channel of interest. Interpolation is proportional to
1562 * differences in channel frequencies, which is proportional to differences
1563 * in channel number.
1564 */
1565 static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
1566 struct iwl4965_eeprom_calib_ch_info *chan_info)
1567 {
1568 s32 s = -1;
1569 u32 c;
1570 u32 m;
1571 const struct iwl4965_eeprom_calib_measure *m1;
1572 const struct iwl4965_eeprom_calib_measure *m2;
1573 struct iwl4965_eeprom_calib_measure *omeas;
1574 u32 ch_i1;
1575 u32 ch_i2;
1576
1577 s = iwl4965_get_sub_band(priv, channel);
1578 if (s >= EEPROM_TX_POWER_BANDS) {
1579 IWL_ERROR("Tx Power can not find channel %d ", channel);
1580 return -1;
1581 }
1582
1583 ch_i1 = priv->eeprom.calib_info.band_info[s].ch1.ch_num;
1584 ch_i2 = priv->eeprom.calib_info.band_info[s].ch2.ch_num;
1585 chan_info->ch_num = (u8) channel;
1586
1587 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
1588 channel, s, ch_i1, ch_i2);
1589
1590 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
1591 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
1592 m1 = &(priv->eeprom.calib_info.band_info[s].ch1.
1593 measurements[c][m]);
1594 m2 = &(priv->eeprom.calib_info.band_info[s].ch2.
1595 measurements[c][m]);
1596 omeas = &(chan_info->measurements[c][m]);
1597
1598 omeas->actual_pow =
1599 (u8) iwl4965_interpolate_value(channel, ch_i1,
1600 m1->actual_pow,
1601 ch_i2,
1602 m2->actual_pow);
1603 omeas->gain_idx =
1604 (u8) iwl4965_interpolate_value(channel, ch_i1,
1605 m1->gain_idx, ch_i2,
1606 m2->gain_idx);
1607 omeas->temperature =
1608 (u8) iwl4965_interpolate_value(channel, ch_i1,
1609 m1->temperature,
1610 ch_i2,
1611 m2->temperature);
1612 omeas->pa_det =
1613 (s8) iwl4965_interpolate_value(channel, ch_i1,
1614 m1->pa_det, ch_i2,
1615 m2->pa_det);
1616
1617 IWL_DEBUG_TXPOWER
1618 ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
1619 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
1620 IWL_DEBUG_TXPOWER
1621 ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
1622 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
1623 IWL_DEBUG_TXPOWER
1624 ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
1625 m1->pa_det, m2->pa_det, omeas->pa_det);
1626 IWL_DEBUG_TXPOWER
1627 ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
1628 m1->temperature, m2->temperature,
1629 omeas->temperature);
1630 }
1631 }
1632
1633 return 0;
1634 }
1635
1636 /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
1637 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
1638 static s32 back_off_table[] = {
1639 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
1640 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
1641 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
1642 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
1643 10 /* CCK */
1644 };
1645
1646 /* Thermal compensation values for txpower for various frequency ranges ...
1647 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
1648 static struct iwl4965_txpower_comp_entry {
1649 s32 degrees_per_05db_a;
1650 s32 degrees_per_05db_a_denom;
1651 } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
1652 {9, 2}, /* group 0 5.2, ch 34-43 */
1653 {4, 1}, /* group 1 5.2, ch 44-70 */
1654 {4, 1}, /* group 2 5.2, ch 71-124 */
1655 {4, 1}, /* group 3 5.2, ch 125-200 */
1656 {3, 1} /* group 4 2.4, ch all */
1657 };
1658
1659 static s32 get_min_power_index(s32 rate_power_index, u32 band)
1660 {
1661 if (!band) {
1662 if ((rate_power_index & 7) <= 4)
1663 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
1664 }
1665 return MIN_TX_GAIN_INDEX;
1666 }
1667
1668 struct gain_entry {
1669 u8 dsp;
1670 u8 radio;
1671 };
1672
1673 static const struct gain_entry gain_table[2][108] = {
1674 /* 5.2GHz power gain index table */
1675 {
1676 {123, 0x3F}, /* highest txpower */
1677 {117, 0x3F},
1678 {110, 0x3F},
1679 {104, 0x3F},
1680 {98, 0x3F},
1681 {110, 0x3E},
1682 {104, 0x3E},
1683 {98, 0x3E},
1684 {110, 0x3D},
1685 {104, 0x3D},
1686 {98, 0x3D},
1687 {110, 0x3C},
1688 {104, 0x3C},
1689 {98, 0x3C},
1690 {110, 0x3B},
1691 {104, 0x3B},
1692 {98, 0x3B},
1693 {110, 0x3A},
1694 {104, 0x3A},
1695 {98, 0x3A},
1696 {110, 0x39},
1697 {104, 0x39},
1698 {98, 0x39},
1699 {110, 0x38},
1700 {104, 0x38},
1701 {98, 0x38},
1702 {110, 0x37},
1703 {104, 0x37},
1704 {98, 0x37},
1705 {110, 0x36},
1706 {104, 0x36},
1707 {98, 0x36},
1708 {110, 0x35},
1709 {104, 0x35},
1710 {98, 0x35},
1711 {110, 0x34},
1712 {104, 0x34},
1713 {98, 0x34},
1714 {110, 0x33},
1715 {104, 0x33},
1716 {98, 0x33},
1717 {110, 0x32},
1718 {104, 0x32},
1719 {98, 0x32},
1720 {110, 0x31},
1721 {104, 0x31},
1722 {98, 0x31},
1723 {110, 0x30},
1724 {104, 0x30},
1725 {98, 0x30},
1726 {110, 0x25},
1727 {104, 0x25},
1728 {98, 0x25},
1729 {110, 0x24},
1730 {104, 0x24},
1731 {98, 0x24},
1732 {110, 0x23},
1733 {104, 0x23},
1734 {98, 0x23},
1735 {110, 0x22},
1736 {104, 0x18},
1737 {98, 0x18},
1738 {110, 0x17},
1739 {104, 0x17},
1740 {98, 0x17},
1741 {110, 0x16},
1742 {104, 0x16},
1743 {98, 0x16},
1744 {110, 0x15},
1745 {104, 0x15},
1746 {98, 0x15},
1747 {110, 0x14},
1748 {104, 0x14},
1749 {98, 0x14},
1750 {110, 0x13},
1751 {104, 0x13},
1752 {98, 0x13},
1753 {110, 0x12},
1754 {104, 0x08},
1755 {98, 0x08},
1756 {110, 0x07},
1757 {104, 0x07},
1758 {98, 0x07},
1759 {110, 0x06},
1760 {104, 0x06},
1761 {98, 0x06},
1762 {110, 0x05},
1763 {104, 0x05},
1764 {98, 0x05},
1765 {110, 0x04},
1766 {104, 0x04},
1767 {98, 0x04},
1768 {110, 0x03},
1769 {104, 0x03},
1770 {98, 0x03},
1771 {110, 0x02},
1772 {104, 0x02},
1773 {98, 0x02},
1774 {110, 0x01},
1775 {104, 0x01},
1776 {98, 0x01},
1777 {110, 0x00},
1778 {104, 0x00},
1779 {98, 0x00},
1780 {93, 0x00},
1781 {88, 0x00},
1782 {83, 0x00},
1783 {78, 0x00},
1784 },
1785 /* 2.4GHz power gain index table */
1786 {
1787 {110, 0x3f}, /* highest txpower */
1788 {104, 0x3f},
1789 {98, 0x3f},
1790 {110, 0x3e},
1791 {104, 0x3e},
1792 {98, 0x3e},
1793 {110, 0x3d},
1794 {104, 0x3d},
1795 {98, 0x3d},
1796 {110, 0x3c},
1797 {104, 0x3c},
1798 {98, 0x3c},
1799 {110, 0x3b},
1800 {104, 0x3b},
1801 {98, 0x3b},
1802 {110, 0x3a},
1803 {104, 0x3a},
1804 {98, 0x3a},
1805 {110, 0x39},
1806 {104, 0x39},
1807 {98, 0x39},
1808 {110, 0x38},
1809 {104, 0x38},
1810 {98, 0x38},
1811 {110, 0x37},
1812 {104, 0x37},
1813 {98, 0x37},
1814 {110, 0x36},
1815 {104, 0x36},
1816 {98, 0x36},
1817 {110, 0x35},
1818 {104, 0x35},
1819 {98, 0x35},
1820 {110, 0x34},
1821 {104, 0x34},
1822 {98, 0x34},
1823 {110, 0x33},
1824 {104, 0x33},
1825 {98, 0x33},
1826 {110, 0x32},
1827 {104, 0x32},
1828 {98, 0x32},
1829 {110, 0x31},
1830 {104, 0x31},
1831 {98, 0x31},
1832 {110, 0x30},
1833 {104, 0x30},
1834 {98, 0x30},
1835 {110, 0x6},
1836 {104, 0x6},
1837 {98, 0x6},
1838 {110, 0x5},
1839 {104, 0x5},
1840 {98, 0x5},
1841 {110, 0x4},
1842 {104, 0x4},
1843 {98, 0x4},
1844 {110, 0x3},
1845 {104, 0x3},
1846 {98, 0x3},
1847 {110, 0x2},
1848 {104, 0x2},
1849 {98, 0x2},
1850 {110, 0x1},
1851 {104, 0x1},
1852 {98, 0x1},
1853 {110, 0x0},
1854 {104, 0x0},
1855 {98, 0x0},
1856 {97, 0},
1857 {96, 0},
1858 {95, 0},
1859 {94, 0},
1860 {93, 0},
1861 {92, 0},
1862 {91, 0},
1863 {90, 0},
1864 {89, 0},
1865 {88, 0},
1866 {87, 0},
1867 {86, 0},
1868 {85, 0},
1869 {84, 0},
1870 {83, 0},
1871 {82, 0},
1872 {81, 0},
1873 {80, 0},
1874 {79, 0},
1875 {78, 0},
1876 {77, 0},
1877 {76, 0},
1878 {75, 0},
1879 {74, 0},
1880 {73, 0},
1881 {72, 0},
1882 {71, 0},
1883 {70, 0},
1884 {69, 0},
1885 {68, 0},
1886 {67, 0},
1887 {66, 0},
1888 {65, 0},
1889 {64, 0},
1890 {63, 0},
1891 {62, 0},
1892 {61, 0},
1893 {60, 0},
1894 {59, 0},
1895 }
1896 };
1897
1898 static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
1899 u8 is_fat, u8 ctrl_chan_high,
1900 struct iwl4965_tx_power_db *tx_power_tbl)
1901 {
1902 u8 saturation_power;
1903 s32 target_power;
1904 s32 user_target_power;
1905 s32 power_limit;
1906 s32 current_temp;
1907 s32 reg_limit;
1908 s32 current_regulatory;
1909 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1910 int i;
1911 int c;
1912 const struct iwl_channel_info *ch_info = NULL;
1913 struct iwl4965_eeprom_calib_ch_info ch_eeprom_info;
1914 const struct iwl4965_eeprom_calib_measure *measurement;
1915 s16 voltage;
1916 s32 init_voltage;
1917 s32 voltage_compensation;
1918 s32 degrees_per_05db_num;
1919 s32 degrees_per_05db_denom;
1920 s32 factory_temp;
1921 s32 temperature_comp[2];
1922 s32 factory_gain_index[2];
1923 s32 factory_actual_pwr[2];
1924 s32 power_index;
1925
1926 /* Sanity check requested level (dBm) */
1927 if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
1928 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
1929 priv->user_txpower_limit);
1930 return -EINVAL;
1931 }
1932 if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
1933 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
1934 priv->user_txpower_limit);
1935 return -EINVAL;
1936 }
1937
1938 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
1939 * are used for indexing into txpower table) */
1940 user_target_power = 2 * priv->user_txpower_limit;
1941
1942 /* Get current (RXON) channel, band, width */
1943 ch_info =
1944 iwl4965_get_channel_txpower_info(priv, priv->band, channel);
1945
1946 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
1947 is_fat);
1948
1949 if (!ch_info)
1950 return -EINVAL;
1951
1952 /* get txatten group, used to select 1) thermal txpower adjustment
1953 * and 2) mimo txpower balance between Tx chains. */
1954 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1955 if (txatten_grp < 0)
1956 return -EINVAL;
1957
1958 IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
1959 channel, txatten_grp);
1960
1961 if (is_fat) {
1962 if (ctrl_chan_high)
1963 channel -= 2;
1964 else
1965 channel += 2;
1966 }
1967
1968 /* hardware txpower limits ...
1969 * saturation (clipping distortion) txpowers are in half-dBm */
1970 if (band)
1971 saturation_power = priv->eeprom.calib_info.saturation_power24;
1972 else
1973 saturation_power = priv->eeprom.calib_info.saturation_power52;
1974
1975 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1976 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1977 if (band)
1978 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1979 else
1980 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1981 }
1982
1983 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1984 * max_power_avg values are in dBm, convert * 2 */
1985 if (is_fat)
1986 reg_limit = ch_info->fat_max_power_avg * 2;
1987 else
1988 reg_limit = ch_info->max_power_avg * 2;
1989
1990 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
1991 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
1992 if (band)
1993 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
1994 else
1995 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
1996 }
1997
1998 /* Interpolate txpower calibration values for this channel,
1999 * based on factory calibration tests on spaced channels. */
2000 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
2001
2002 /* calculate tx gain adjustment based on power supply voltage */
2003 voltage = priv->eeprom.calib_info.voltage;
2004 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
2005 voltage_compensation =
2006 iwl4965_get_voltage_compensation(voltage, init_voltage);
2007
2008 IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
2009 init_voltage,
2010 voltage, voltage_compensation);
2011
2012 /* get current temperature (Celsius) */
2013 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
2014 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
2015 current_temp = KELVIN_TO_CELSIUS(current_temp);
2016
2017 /* select thermal txpower adjustment params, based on channel group
2018 * (same frequency group used for mimo txatten adjustment) */
2019 degrees_per_05db_num =
2020 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
2021 degrees_per_05db_denom =
2022 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
2023
2024 /* get per-chain txpower values from factory measurements */
2025 for (c = 0; c < 2; c++) {
2026 measurement = &ch_eeprom_info.measurements[c][1];
2027
2028 /* txgain adjustment (in half-dB steps) based on difference
2029 * between factory and current temperature */
2030 factory_temp = measurement->temperature;
2031 iwl4965_math_div_round((current_temp - factory_temp) *
2032 degrees_per_05db_denom,
2033 degrees_per_05db_num,
2034 &temperature_comp[c]);
2035
2036 factory_gain_index[c] = measurement->gain_idx;
2037 factory_actual_pwr[c] = measurement->actual_pow;
2038
2039 IWL_DEBUG_TXPOWER("chain = %d\n", c);
2040 IWL_DEBUG_TXPOWER("fctry tmp %d, "
2041 "curr tmp %d, comp %d steps\n",
2042 factory_temp, current_temp,
2043 temperature_comp[c]);
2044
2045 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
2046 factory_gain_index[c],
2047 factory_actual_pwr[c]);
2048 }
2049
2050 /* for each of 33 bit-rates (including 1 for CCK) */
2051 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
2052 u8 is_mimo_rate;
2053 union iwl4965_tx_power_dual_stream tx_power;
2054
2055 /* for mimo, reduce each chain's txpower by half
2056 * (3dB, 6 steps), so total output power is regulatory
2057 * compliant. */
2058 if (i & 0x8) {
2059 current_regulatory = reg_limit -
2060 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
2061 is_mimo_rate = 1;
2062 } else {
2063 current_regulatory = reg_limit;
2064 is_mimo_rate = 0;
2065 }
2066
2067 /* find txpower limit, either hardware or regulatory */
2068 power_limit = saturation_power - back_off_table[i];
2069 if (power_limit > current_regulatory)
2070 power_limit = current_regulatory;
2071
2072 /* reduce user's txpower request if necessary
2073 * for this rate on this channel */
2074 target_power = user_target_power;
2075 if (target_power > power_limit)
2076 target_power = power_limit;
2077
2078 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
2079 i, saturation_power - back_off_table[i],
2080 current_regulatory, user_target_power,
2081 target_power);
2082
2083 /* for each of 2 Tx chains (radio transmitters) */
2084 for (c = 0; c < 2; c++) {
2085 s32 atten_value;
2086
2087 if (is_mimo_rate)
2088 atten_value =
2089 (s32)le32_to_cpu(priv->card_alive_init.
2090 tx_atten[txatten_grp][c]);
2091 else
2092 atten_value = 0;
2093
2094 /* calculate index; higher index means lower txpower */
2095 power_index = (u8) (factory_gain_index[c] -
2096 (target_power -
2097 factory_actual_pwr[c]) -
2098 temperature_comp[c] -
2099 voltage_compensation +
2100 atten_value);
2101
2102 /* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
2103 power_index); */
2104
2105 if (power_index < get_min_power_index(i, band))
2106 power_index = get_min_power_index(i, band);
2107
2108 /* adjust 5 GHz index to support negative indexes */
2109 if (!band)
2110 power_index += 9;
2111
2112 /* CCK, rate 32, reduce txpower for CCK */
2113 if (i == POWER_TABLE_CCK_ENTRY)
2114 power_index +=
2115 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
2116
2117 /* stay within the table! */
2118 if (power_index > 107) {
2119 IWL_WARNING("txpower index %d > 107\n",
2120 power_index);
2121 power_index = 107;
2122 }
2123 if (power_index < 0) {
2124 IWL_WARNING("txpower index %d < 0\n",
2125 power_index);
2126 power_index = 0;
2127 }
2128
2129 /* fill txpower command for this rate/chain */
2130 tx_power.s.radio_tx_gain[c] =
2131 gain_table[band][power_index].radio;
2132 tx_power.s.dsp_predis_atten[c] =
2133 gain_table[band][power_index].dsp;
2134
2135 IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
2136 "gain 0x%02x dsp %d\n",
2137 c, atten_value, power_index,
2138 tx_power.s.radio_tx_gain[c],
2139 tx_power.s.dsp_predis_atten[c]);
2140 }/* for each chain */
2141
2142 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
2143
2144 }/* for each rate */
2145
2146 return 0;
2147 }
2148
2149 /**
2150 * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
2151 *
2152 * Uses the active RXON for channel, band, and characteristics (fat, high)
2153 * The power limit is taken from priv->user_txpower_limit.
2154 */
2155 int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
2156 {
2157 struct iwl4965_txpowertable_cmd cmd = { 0 };
2158 int ret;
2159 u8 band = 0;
2160 u8 is_fat = 0;
2161 u8 ctrl_chan_high = 0;
2162
2163 if (test_bit(STATUS_SCANNING, &priv->status)) {
2164 /* If this gets hit a lot, switch it to a BUG() and catch
2165 * the stack trace to find out who is calling this during
2166 * a scan. */
2167 IWL_WARNING("TX Power requested while scanning!\n");
2168 return -EAGAIN;
2169 }
2170
2171 band = priv->band == IEEE80211_BAND_2GHZ;
2172
2173 is_fat = is_fat_channel(priv->active_rxon.flags);
2174
2175 if (is_fat &&
2176 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2177 ctrl_chan_high = 1;
2178
2179 cmd.band = band;
2180 cmd.channel = priv->active_rxon.channel;
2181
2182 ret = iwl4965_fill_txpower_tbl(priv, band,
2183 le16_to_cpu(priv->active_rxon.channel),
2184 is_fat, ctrl_chan_high, &cmd.tx_power);
2185 if (ret)
2186 goto out;
2187
2188 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
2189
2190 out:
2191 return ret;
2192 }
2193
2194 static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
2195 {
2196 int ret = 0;
2197 struct iwl4965_rxon_assoc_cmd rxon_assoc;
2198 const struct iwl4965_rxon_cmd *rxon1 = &priv->staging_rxon;
2199 const struct iwl4965_rxon_cmd *rxon2 = &priv->active_rxon;
2200
2201 if ((rxon1->flags == rxon2->flags) &&
2202 (rxon1->filter_flags == rxon2->filter_flags) &&
2203 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
2204 (rxon1->ofdm_ht_single_stream_basic_rates ==
2205 rxon2->ofdm_ht_single_stream_basic_rates) &&
2206 (rxon1->ofdm_ht_dual_stream_basic_rates ==
2207 rxon2->ofdm_ht_dual_stream_basic_rates) &&
2208 (rxon1->rx_chain == rxon2->rx_chain) &&
2209 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
2210 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
2211 return 0;
2212 }
2213
2214 rxon_assoc.flags = priv->staging_rxon.flags;
2215 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
2216 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
2217 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
2218 rxon_assoc.reserved = 0;
2219 rxon_assoc.ofdm_ht_single_stream_basic_rates =
2220 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
2221 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
2222 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
2223 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
2224
2225 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
2226 sizeof(rxon_assoc), &rxon_assoc, NULL);
2227 if (ret)
2228 return ret;
2229
2230 return ret;
2231 }
2232
2233
2234 int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
2235 {
2236 int rc;
2237 u8 band = 0;
2238 u8 is_fat = 0;
2239 u8 ctrl_chan_high = 0;
2240 struct iwl4965_channel_switch_cmd cmd = { 0 };
2241 const struct iwl_channel_info *ch_info;
2242
2243 band = priv->band == IEEE80211_BAND_2GHZ;
2244
2245 ch_info = iwl_get_channel_info(priv, priv->band, channel);
2246
2247 is_fat = is_fat_channel(priv->staging_rxon.flags);
2248
2249 if (is_fat &&
2250 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2251 ctrl_chan_high = 1;
2252
2253 cmd.band = band;
2254 cmd.expect_beacon = 0;
2255 cmd.channel = cpu_to_le16(channel);
2256 cmd.rxon_flags = priv->active_rxon.flags;
2257 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
2258 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
2259 if (ch_info)
2260 cmd.expect_beacon = is_channel_radar(ch_info);
2261 else
2262 cmd.expect_beacon = 1;
2263
2264 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
2265 ctrl_chan_high, &cmd.tx_power);
2266 if (rc) {
2267 IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
2268 return rc;
2269 }
2270
2271 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
2272 return rc;
2273 }
2274
2275 #define RTS_HCCA_RETRY_LIMIT 3
2276 #define RTS_DFAULT_RETRY_LIMIT 60
2277
2278 void iwl4965_hw_build_tx_cmd_rate(struct iwl_priv *priv,
2279 struct iwl_cmd *cmd,
2280 struct ieee80211_tx_control *ctrl,
2281 struct ieee80211_hdr *hdr, int sta_id,
2282 int is_hcca)
2283 {
2284 struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
2285 u8 rts_retry_limit = 0;
2286 u8 data_retry_limit = 0;
2287 u16 fc = le16_to_cpu(hdr->frame_control);
2288 u8 rate_plcp;
2289 u16 rate_flags = 0;
2290 int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1);
2291
2292 rate_plcp = iwl4965_rates[rate_idx].plcp;
2293
2294 rts_retry_limit = (is_hcca) ?
2295 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
2296
2297 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
2298 rate_flags |= RATE_MCS_CCK_MSK;
2299
2300
2301 if (ieee80211_is_probe_response(fc)) {
2302 data_retry_limit = 3;
2303 if (data_retry_limit < rts_retry_limit)
2304 rts_retry_limit = data_retry_limit;
2305 } else
2306 data_retry_limit = IWL_DEFAULT_TX_RETRY;
2307
2308 if (priv->data_retry_limit != -1)
2309 data_retry_limit = priv->data_retry_limit;
2310
2311
2312 if (ieee80211_is_data(fc)) {
2313 tx->initial_rate_index = 0;
2314 tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
2315 } else {
2316 switch (fc & IEEE80211_FCTL_STYPE) {
2317 case IEEE80211_STYPE_AUTH:
2318 case IEEE80211_STYPE_DEAUTH:
2319 case IEEE80211_STYPE_ASSOC_REQ:
2320 case IEEE80211_STYPE_REASSOC_REQ:
2321 if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
2322 tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2323 tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
2324 }
2325 break;
2326 default:
2327 break;
2328 }
2329
2330 /* Alternate between antenna A and B for successive frames */
2331 if (priv->use_ant_b_for_management_frame) {
2332 priv->use_ant_b_for_management_frame = 0;
2333 rate_flags |= RATE_MCS_ANT_B_MSK;
2334 } else {
2335 priv->use_ant_b_for_management_frame = 1;
2336 rate_flags |= RATE_MCS_ANT_A_MSK;
2337 }
2338 }
2339
2340 tx->rts_retry_limit = rts_retry_limit;
2341 tx->data_retry_limit = data_retry_limit;
2342 tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
2343 }
2344
2345 int iwl4965_hw_get_rx_read(struct iwl_priv *priv)
2346 {
2347 struct iwl4965_shared *s = priv->shared_virt;
2348 return le32_to_cpu(s->rb_closed) & 0xFFF;
2349 }
2350
2351 int iwl4965_hw_get_temperature(struct iwl_priv *priv)
2352 {
2353 return priv->temperature;
2354 }
2355
2356 unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
2357 struct iwl4965_frame *frame, u8 rate)
2358 {
2359 struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
2360 unsigned int frame_size;
2361
2362 tx_beacon_cmd = &frame->u.beacon;
2363 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2364
2365 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2366 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2367
2368 frame_size = iwl4965_fill_beacon_frame(priv,
2369 tx_beacon_cmd->frame,
2370 iwl4965_broadcast_addr,
2371 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2372
2373 BUG_ON(frame_size > MAX_MPDU_SIZE);
2374 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2375
2376 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
2377 tx_beacon_cmd->tx.rate_n_flags =
2378 iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
2379 else
2380 tx_beacon_cmd->tx.rate_n_flags =
2381 iwl4965_hw_set_rate_n_flags(rate, 0);
2382
2383 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2384 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
2385 return (sizeof(*tx_beacon_cmd) + frame_size);
2386 }
2387
2388 /*
2389 * Tell 4965 where to find circular buffer of Tx Frame Descriptors for
2390 * given Tx queue, and enable the DMA channel used for that queue.
2391 *
2392 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
2393 * channels supported in hardware.
2394 */
2395 int iwl4965_hw_tx_queue_init(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
2396 {
2397 int rc;
2398 unsigned long flags;
2399 int txq_id = txq->q.id;
2400
2401 spin_lock_irqsave(&priv->lock, flags);
2402 rc = iwl_grab_nic_access(priv);
2403 if (rc) {
2404 spin_unlock_irqrestore(&priv->lock, flags);
2405 return rc;
2406 }
2407
2408 /* Circular buffer (TFD queue in DRAM) physical base address */
2409 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
2410 txq->q.dma_addr >> 8);
2411
2412 /* Enable DMA channel, using same id as for TFD queue */
2413 iwl_write_direct32(
2414 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
2415 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
2416 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
2417 iwl_release_nic_access(priv);
2418 spin_unlock_irqrestore(&priv->lock, flags);
2419
2420 return 0;
2421 }
2422
2423 int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
2424 dma_addr_t addr, u16 len)
2425 {
2426 int index, is_odd;
2427 struct iwl4965_tfd_frame *tfd = ptr;
2428 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
2429
2430 /* Each TFD can point to a maximum 20 Tx buffers */
2431 if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
2432 IWL_ERROR("Error can not send more than %d chunks\n",
2433 MAX_NUM_OF_TBS);
2434 return -EINVAL;
2435 }
2436
2437 index = num_tbs / 2;
2438 is_odd = num_tbs & 0x1;
2439
2440 if (!is_odd) {
2441 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
2442 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
2443 iwl_get_dma_hi_address(addr));
2444 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
2445 } else {
2446 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
2447 (u32) (addr & 0xffff));
2448 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
2449 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
2450 }
2451
2452 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
2453
2454 return 0;
2455 }
2456
2457 static void iwl4965_hw_card_show_info(struct iwl_priv *priv)
2458 {
2459 u16 hw_version = priv->eeprom.board_revision_4965;
2460
2461 IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
2462 ((hw_version >> 8) & 0x0F),
2463 ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
2464
2465 IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
2466 priv->eeprom.board_pba_number_4965);
2467 }
2468
2469 #define IWL_TX_CRC_SIZE 4
2470 #define IWL_TX_DELIMITER_SIZE 4
2471
2472 /**
2473 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
2474 */
2475 static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
2476 struct iwl4965_tx_queue *txq,
2477 u16 byte_cnt)
2478 {
2479 int len;
2480 int txq_id = txq->q.id;
2481 struct iwl4965_shared *shared_data = priv->shared_virt;
2482
2483 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
2484
2485 /* Set up byte count within first 256 entries */
2486 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
2487 tfd_offset[txq->q.write_ptr], byte_cnt, len);
2488
2489 /* If within first 64 entries, duplicate at end */
2490 if (txq->q.write_ptr < IWL4965_MAX_WIN_SIZE)
2491 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
2492 tfd_offset[IWL4965_QUEUE_SIZE + txq->q.write_ptr],
2493 byte_cnt, len);
2494 }
2495
2496 /**
2497 * iwl4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2498 *
2499 * Selects how many and which Rx receivers/antennas/chains to use.
2500 * This should not be used for scan command ... it puts data in wrong place.
2501 */
2502 void iwl4965_set_rxon_chain(struct iwl_priv *priv)
2503 {
2504 u8 is_single = is_single_stream(priv);
2505 u8 idle_state, rx_state;
2506
2507 priv->staging_rxon.rx_chain = 0;
2508 rx_state = idle_state = 3;
2509
2510 /* Tell uCode which antennas are actually connected.
2511 * Before first association, we assume all antennas are connected.
2512 * Just after first association, iwl_chain_noise_calibration()
2513 * checks which antennas actually *are* connected. */
2514 priv->staging_rxon.rx_chain |=
2515 cpu_to_le16(priv->valid_antenna << RXON_RX_CHAIN_VALID_POS);
2516
2517 /* How many receivers should we use? */
2518 iwl4965_get_rx_chain_counter(priv, &idle_state, &rx_state);
2519 priv->staging_rxon.rx_chain |=
2520 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
2521 priv->staging_rxon.rx_chain |=
2522 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
2523
2524 if (!is_single && (rx_state >= 2) &&
2525 !test_bit(STATUS_POWER_PMI, &priv->status))
2526 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2527 else
2528 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2529
2530 IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
2531 }
2532
2533 /**
2534 * sign_extend - Sign extend a value using specified bit as sign-bit
2535 *
2536 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
2537 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
2538 *
2539 * @param oper value to sign extend
2540 * @param index 0 based bit index (0<=index<32) to sign bit
2541 */
2542 static s32 sign_extend(u32 oper, int index)
2543 {
2544 u8 shift = 31 - index;
2545
2546 return (s32)(oper << shift) >> shift;
2547 }
2548
2549 /**
2550 * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
2551 * @statistics: Provides the temperature reading from the uCode
2552 *
2553 * A return of <0 indicates bogus data in the statistics
2554 */
2555 int iwl4965_get_temperature(const struct iwl_priv *priv)
2556 {
2557 s32 temperature;
2558 s32 vt;
2559 s32 R1, R2, R3;
2560 u32 R4;
2561
2562 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
2563 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
2564 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
2565 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
2566 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
2567 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
2568 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
2569 } else {
2570 IWL_DEBUG_TEMP("Running temperature calibration\n");
2571 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
2572 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
2573 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
2574 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
2575 }
2576
2577 /*
2578 * Temperature is only 23 bits, so sign extend out to 32.
2579 *
2580 * NOTE If we haven't received a statistics notification yet
2581 * with an updated temperature, use R4 provided to us in the
2582 * "initialize" ALIVE response.
2583 */
2584 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
2585 vt = sign_extend(R4, 23);
2586 else
2587 vt = sign_extend(
2588 le32_to_cpu(priv->statistics.general.temperature), 23);
2589
2590 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
2591 R1, R2, R3, vt);
2592
2593 if (R3 == R1) {
2594 IWL_ERROR("Calibration conflict R1 == R3\n");
2595 return -1;
2596 }
2597
2598 /* Calculate temperature in degrees Kelvin, adjust by 97%.
2599 * Add offset to center the adjustment around 0 degrees Centigrade. */
2600 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
2601 temperature /= (R3 - R1);
2602 temperature = (temperature * 97) / 100 +
2603 TEMPERATURE_CALIB_KELVIN_OFFSET;
2604
2605 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
2606 KELVIN_TO_CELSIUS(temperature));
2607
2608 return temperature;
2609 }
2610
2611 /* Adjust Txpower only if temperature variance is greater than threshold. */
2612 #define IWL_TEMPERATURE_THRESHOLD 3
2613
2614 /**
2615 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
2616 *
2617 * If the temperature changed has changed sufficiently, then a recalibration
2618 * is needed.
2619 *
2620 * Assumes caller will replace priv->last_temperature once calibration
2621 * executed.
2622 */
2623 static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
2624 {
2625 int temp_diff;
2626
2627 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
2628 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
2629 return 0;
2630 }
2631
2632 temp_diff = priv->temperature - priv->last_temperature;
2633
2634 /* get absolute value */
2635 if (temp_diff < 0) {
2636 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
2637 temp_diff = -temp_diff;
2638 } else if (temp_diff == 0)
2639 IWL_DEBUG_POWER("Same temp, \n");
2640 else
2641 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
2642
2643 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
2644 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
2645 return 0;
2646 }
2647
2648 IWL_DEBUG_POWER("Thermal txpower calib needed\n");
2649
2650 return 1;
2651 }
2652
2653 /* Calculate noise level, based on measurements during network silence just
2654 * before arriving beacon. This measurement can be done only if we know
2655 * exactly when to expect beacons, therefore only when we're associated. */
2656 static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
2657 {
2658 struct statistics_rx_non_phy *rx_info
2659 = &(priv->statistics.rx.general);
2660 int num_active_rx = 0;
2661 int total_silence = 0;
2662 int bcn_silence_a =
2663 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
2664 int bcn_silence_b =
2665 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
2666 int bcn_silence_c =
2667 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
2668
2669 if (bcn_silence_a) {
2670 total_silence += bcn_silence_a;
2671 num_active_rx++;
2672 }
2673 if (bcn_silence_b) {
2674 total_silence += bcn_silence_b;
2675 num_active_rx++;
2676 }
2677 if (bcn_silence_c) {
2678 total_silence += bcn_silence_c;
2679 num_active_rx++;
2680 }
2681
2682 /* Average among active antennas */
2683 if (num_active_rx)
2684 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
2685 else
2686 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
2687
2688 IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
2689 bcn_silence_a, bcn_silence_b, bcn_silence_c,
2690 priv->last_rx_noise);
2691 }
2692
2693 void iwl4965_hw_rx_statistics(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
2694 {
2695 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
2696 int change;
2697 s32 temp;
2698
2699 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
2700 (int)sizeof(priv->statistics), pkt->len);
2701
2702 change = ((priv->statistics.general.temperature !=
2703 pkt->u.stats.general.temperature) ||
2704 ((priv->statistics.flag &
2705 STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
2706 (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
2707
2708 memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
2709
2710 set_bit(STATUS_STATISTICS, &priv->status);
2711
2712 /* Reschedule the statistics timer to occur in
2713 * REG_RECALIB_PERIOD seconds to ensure we get a
2714 * thermal update even if the uCode doesn't give
2715 * us one */
2716 mod_timer(&priv->statistics_periodic, jiffies +
2717 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
2718
2719 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2720 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
2721 iwl4965_rx_calc_noise(priv);
2722 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
2723 queue_work(priv->workqueue, &priv->sensitivity_work);
2724 #endif
2725 }
2726
2727 iwl_leds_background(priv);
2728
2729 /* If the hardware hasn't reported a change in
2730 * temperature then don't bother computing a
2731 * calibrated temperature value */
2732 if (!change)
2733 return;
2734
2735 temp = iwl4965_get_temperature(priv);
2736 if (temp < 0)
2737 return;
2738
2739 if (priv->temperature != temp) {
2740 if (priv->temperature)
2741 IWL_DEBUG_TEMP("Temperature changed "
2742 "from %dC to %dC\n",
2743 KELVIN_TO_CELSIUS(priv->temperature),
2744 KELVIN_TO_CELSIUS(temp));
2745 else
2746 IWL_DEBUG_TEMP("Temperature "
2747 "initialized to %dC\n",
2748 KELVIN_TO_CELSIUS(temp));
2749 }
2750
2751 priv->temperature = temp;
2752 set_bit(STATUS_TEMPERATURE, &priv->status);
2753
2754 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2755 iwl4965_is_temp_calib_needed(priv))
2756 queue_work(priv->workqueue, &priv->txpower_work);
2757 }
2758
2759 static void iwl4965_add_radiotap(struct iwl_priv *priv,
2760 struct sk_buff *skb,
2761 struct iwl4965_rx_phy_res *rx_start,
2762 struct ieee80211_rx_status *stats,
2763 u32 ampdu_status)
2764 {
2765 s8 signal = stats->ssi;
2766 s8 noise = 0;
2767 int rate = stats->rate_idx;
2768 u64 tsf = stats->mactime;
2769 __le16 antenna;
2770 __le16 phy_flags_hw = rx_start->phy_flags;
2771 struct iwl4965_rt_rx_hdr {
2772 struct ieee80211_radiotap_header rt_hdr;
2773 __le64 rt_tsf; /* TSF */
2774 u8 rt_flags; /* radiotap packet flags */
2775 u8 rt_rate; /* rate in 500kb/s */
2776 __le16 rt_channelMHz; /* channel in MHz */
2777 __le16 rt_chbitmask; /* channel bitfield */
2778 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
2779 s8 rt_dbmnoise;
2780 u8 rt_antenna; /* antenna number */
2781 } __attribute__ ((packed)) *iwl4965_rt;
2782
2783 /* TODO: We won't have enough headroom for HT frames. Fix it later. */
2784 if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
2785 if (net_ratelimit())
2786 printk(KERN_ERR "not enough headroom [%d] for "
2787 "radiotap head [%zd]\n",
2788 skb_headroom(skb), sizeof(*iwl4965_rt));
2789 return;
2790 }
2791
2792 /* put radiotap header in front of 802.11 header and data */
2793 iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
2794
2795 /* initialise radiotap header */
2796 iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
2797 iwl4965_rt->rt_hdr.it_pad = 0;
2798
2799 /* total header + data */
2800 put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
2801 &iwl4965_rt->rt_hdr.it_len);
2802
2803 /* Indicate all the fields we add to the radiotap header */
2804 put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
2805 (1 << IEEE80211_RADIOTAP_FLAGS) |
2806 (1 << IEEE80211_RADIOTAP_RATE) |
2807 (1 << IEEE80211_RADIOTAP_CHANNEL) |
2808 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
2809 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
2810 (1 << IEEE80211_RADIOTAP_ANTENNA)),
2811 &iwl4965_rt->rt_hdr.it_present);
2812
2813 /* Zero the flags, we'll add to them as we go */
2814 iwl4965_rt->rt_flags = 0;
2815
2816 put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
2817
2818 iwl4965_rt->rt_dbmsignal = signal;
2819 iwl4965_rt->rt_dbmnoise = noise;
2820
2821 /* Convert the channel frequency and set the flags */
2822 put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
2823 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
2824 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2825 IEEE80211_CHAN_5GHZ),
2826 &iwl4965_rt->rt_chbitmask);
2827 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
2828 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
2829 IEEE80211_CHAN_2GHZ),
2830 &iwl4965_rt->rt_chbitmask);
2831 else /* 802.11g */
2832 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2833 IEEE80211_CHAN_2GHZ),
2834 &iwl4965_rt->rt_chbitmask);
2835
2836 if (rate == -1)
2837 iwl4965_rt->rt_rate = 0;
2838 else
2839 iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
2840
2841 /*
2842 * "antenna number"
2843 *
2844 * It seems that the antenna field in the phy flags value
2845 * is actually a bitfield. This is undefined by radiotap,
2846 * it wants an actual antenna number but I always get "7"
2847 * for most legacy frames I receive indicating that the
2848 * same frame was received on all three RX chains.
2849 *
2850 * I think this field should be removed in favour of a
2851 * new 802.11n radiotap field "RX chains" that is defined
2852 * as a bitmask.
2853 */
2854 antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
2855 iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
2856
2857 /* set the preamble flag if appropriate */
2858 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
2859 iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2860
2861 stats->flag |= RX_FLAG_RADIOTAP;
2862 }
2863
2864 static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
2865 {
2866 /* 0 - mgmt, 1 - cnt, 2 - data */
2867 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
2868 priv->rx_stats[idx].cnt++;
2869 priv->rx_stats[idx].bytes += len;
2870 }
2871
2872 static u32 iwl4965_translate_rx_status(u32 decrypt_in)
2873 {
2874 u32 decrypt_out = 0;
2875
2876 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
2877 RX_RES_STATUS_STATION_FOUND)
2878 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
2879 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
2880
2881 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
2882
2883 /* packet was not encrypted */
2884 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2885 RX_RES_STATUS_SEC_TYPE_NONE)
2886 return decrypt_out;
2887
2888 /* packet was encrypted with unknown alg */
2889 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2890 RX_RES_STATUS_SEC_TYPE_ERR)
2891 return decrypt_out;
2892
2893 /* decryption was not done in HW */
2894 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
2895 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
2896 return decrypt_out;
2897
2898 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
2899
2900 case RX_RES_STATUS_SEC_TYPE_CCMP:
2901 /* alg is CCM: check MIC only */
2902 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
2903 /* Bad MIC */
2904 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2905 else
2906 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2907
2908 break;
2909
2910 case RX_RES_STATUS_SEC_TYPE_TKIP:
2911 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
2912 /* Bad TTAK */
2913 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
2914 break;
2915 }
2916 /* fall through if TTAK OK */
2917 default:
2918 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
2919 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2920 else
2921 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2922 break;
2923 };
2924
2925 IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
2926 decrypt_in, decrypt_out);
2927
2928 return decrypt_out;
2929 }
2930
2931 static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
2932 int include_phy,
2933 struct iwl4965_rx_mem_buffer *rxb,
2934 struct ieee80211_rx_status *stats)
2935 {
2936 struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
2937 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
2938 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
2939 struct ieee80211_hdr *hdr;
2940 u16 len;
2941 __le32 *rx_end;
2942 unsigned int skblen;
2943 u32 ampdu_status;
2944 u32 ampdu_status_legacy;
2945
2946 if (!include_phy && priv->last_phy_res[0])
2947 rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
2948
2949 if (!rx_start) {
2950 IWL_ERROR("MPDU frame without a PHY data\n");
2951 return;
2952 }
2953 if (include_phy) {
2954 hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
2955 rx_start->cfg_phy_cnt);
2956
2957 len = le16_to_cpu(rx_start->byte_count);
2958
2959 rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
2960 sizeof(struct iwl4965_rx_phy_res) +
2961 rx_start->cfg_phy_cnt + len);
2962
2963 } else {
2964 struct iwl4965_rx_mpdu_res_start *amsdu =
2965 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
2966
2967 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
2968 sizeof(struct iwl4965_rx_mpdu_res_start));
2969 len = le16_to_cpu(amsdu->byte_count);
2970 rx_start->byte_count = amsdu->byte_count;
2971 rx_end = (__le32 *) (((u8 *) hdr) + len);
2972 }
2973 if (len > priv->hw_params.max_pkt_size || len < 16) {
2974 IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
2975 return;
2976 }
2977
2978 ampdu_status = le32_to_cpu(*rx_end);
2979 skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
2980
2981 if (!include_phy) {
2982 /* New status scheme, need to translate */
2983 ampdu_status_legacy = ampdu_status;
2984 ampdu_status = iwl4965_translate_rx_status(ampdu_status);
2985 }
2986
2987 /* start from MAC */
2988 skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
2989 skb_put(rxb->skb, len); /* end where data ends */
2990
2991 /* We only process data packets if the interface is open */
2992 if (unlikely(!priv->is_open)) {
2993 IWL_DEBUG_DROP_LIMIT
2994 ("Dropping packet while interface is not open.\n");
2995 return;
2996 }
2997
2998 stats->flag = 0;
2999 hdr = (struct ieee80211_hdr *)rxb->skb->data;
3000
3001 if (!priv->cfg->mod_params->sw_crypto)
3002 iwl4965_set_decrypted_flag(priv, rxb->skb, ampdu_status, stats);
3003
3004 if (priv->add_radiotap)
3005 iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
3006
3007 iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
3008 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
3009 priv->alloc_rxb_skb--;
3010 rxb->skb = NULL;
3011 }
3012
3013 /* Calc max signal level (dBm) among 3 possible receivers */
3014 static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
3015 {
3016 /* data from PHY/DSP regarding signal strength, etc.,
3017 * contents are always there, not configurable by host. */
3018 struct iwl4965_rx_non_cfg_phy *ncphy =
3019 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
3020 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
3021 >> IWL_AGC_DB_POS;
3022
3023 u32 valid_antennae =
3024 (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
3025 >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
3026 u8 max_rssi = 0;
3027 u32 i;
3028
3029 /* Find max rssi among 3 possible receivers.
3030 * These values are measured by the digital signal processor (DSP).
3031 * They should stay fairly constant even as the signal strength varies,
3032 * if the radio's automatic gain control (AGC) is working right.
3033 * AGC value (see below) will provide the "interesting" info. */
3034 for (i = 0; i < 3; i++)
3035 if (valid_antennae & (1 << i))
3036 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
3037
3038 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
3039 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
3040 max_rssi, agc);
3041
3042 /* dBm = max_rssi dB - agc dB - constant.
3043 * Higher AGC (higher radio gain) means lower signal. */
3044 return (max_rssi - agc - IWL_RSSI_OFFSET);
3045 }
3046
3047 #ifdef CONFIG_IWL4965_HT
3048
3049 void iwl4965_init_ht_hw_capab(struct iwl_priv *priv,
3050 struct ieee80211_ht_info *ht_info,
3051 enum ieee80211_band band)
3052 {
3053 ht_info->cap = 0;
3054 memset(ht_info->supp_mcs_set, 0, 16);
3055
3056 ht_info->ht_supported = 1;
3057
3058 if (band == IEEE80211_BAND_5GHZ) {
3059 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
3060 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
3061 ht_info->supp_mcs_set[4] = 0x01;
3062 }
3063 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
3064 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
3065 ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
3066 (IWL_MIMO_PS_NONE << 2));
3067
3068 if (priv->cfg->mod_params->amsdu_size_8K)
3069 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
3070
3071 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3072 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3073
3074 ht_info->supp_mcs_set[0] = 0xFF;
3075 ht_info->supp_mcs_set[1] = 0xFF;
3076 }
3077 #endif /* CONFIG_IWL4965_HT */
3078
3079 static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
3080 {
3081 unsigned long flags;
3082
3083 spin_lock_irqsave(&priv->sta_lock, flags);
3084 priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
3085 priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3086 priv->stations[sta_id].sta.sta.modify_mask = 0;
3087 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3088 spin_unlock_irqrestore(&priv->sta_lock, flags);
3089
3090 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
3091 }
3092
3093 static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
3094 {
3095 /* FIXME: need locking over ps_status ??? */
3096 u8 sta_id = iwl_find_station(priv, addr);
3097
3098 if (sta_id != IWL_INVALID_STATION) {
3099 u8 sta_awake = priv->stations[sta_id].
3100 ps_status == STA_PS_STATUS_WAKE;
3101
3102 if (sta_awake && ps_bit)
3103 priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
3104 else if (!sta_awake && !ps_bit) {
3105 iwl4965_sta_modify_ps_wake(priv, sta_id);
3106 priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
3107 }
3108 }
3109 }
3110 #ifdef CONFIG_IWLWIFI_DEBUG
3111
3112 /**
3113 * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
3114 *
3115 * You may hack this function to show different aspects of received frames,
3116 * including selective frame dumps.
3117 * group100 parameter selects whether to show 1 out of 100 good frames.
3118 *
3119 * TODO: This was originally written for 3945, need to audit for
3120 * proper operation with 4965.
3121 */
3122 static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
3123 struct iwl4965_rx_packet *pkt,
3124 struct ieee80211_hdr *header, int group100)
3125 {
3126 u32 to_us;
3127 u32 print_summary = 0;
3128 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
3129 u32 hundred = 0;
3130 u32 dataframe = 0;
3131 u16 fc;
3132 u16 seq_ctl;
3133 u16 channel;
3134 u16 phy_flags;
3135 int rate_sym;
3136 u16 length;
3137 u16 status;
3138 u16 bcn_tmr;
3139 u32 tsf_low;
3140 u64 tsf;
3141 u8 rssi;
3142 u8 agc;
3143 u16 sig_avg;
3144 u16 noise_diff;
3145 struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
3146 struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
3147 struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
3148 u8 *data = IWL_RX_DATA(pkt);
3149
3150 if (likely(!(iwl_debug_level & IWL_DL_RX)))
3151 return;
3152
3153 /* MAC header */
3154 fc = le16_to_cpu(header->frame_control);
3155 seq_ctl = le16_to_cpu(header->seq_ctrl);
3156
3157 /* metadata */
3158 channel = le16_to_cpu(rx_hdr->channel);
3159 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
3160 rate_sym = rx_hdr->rate;
3161 length = le16_to_cpu(rx_hdr->len);
3162
3163 /* end-of-frame status and timestamp */
3164 status = le32_to_cpu(rx_end->status);
3165 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
3166 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
3167 tsf = le64_to_cpu(rx_end->timestamp);
3168
3169 /* signal statistics */
3170 rssi = rx_stats->rssi;
3171 agc = rx_stats->agc;
3172 sig_avg = le16_to_cpu(rx_stats->sig_avg);
3173 noise_diff = le16_to_cpu(rx_stats->noise_diff);
3174
3175 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
3176
3177 /* if data frame is to us and all is good,
3178 * (optionally) print summary for only 1 out of every 100 */
3179 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
3180 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
3181 dataframe = 1;
3182 if (!group100)
3183 print_summary = 1; /* print each frame */
3184 else if (priv->framecnt_to_us < 100) {
3185 priv->framecnt_to_us++;
3186 print_summary = 0;
3187 } else {
3188 priv->framecnt_to_us = 0;
3189 print_summary = 1;
3190 hundred = 1;
3191 }
3192 } else {
3193 /* print summary for all other frames */
3194 print_summary = 1;
3195 }
3196
3197 if (print_summary) {
3198 char *title;
3199 int rate_idx;
3200 u32 bitrate;
3201
3202 if (hundred)
3203 title = "100Frames";
3204 else if (fc & IEEE80211_FCTL_RETRY)
3205 title = "Retry";
3206 else if (ieee80211_is_assoc_response(fc))
3207 title = "AscRsp";
3208 else if (ieee80211_is_reassoc_response(fc))
3209 title = "RasRsp";
3210 else if (ieee80211_is_probe_response(fc)) {
3211 title = "PrbRsp";
3212 print_dump = 1; /* dump frame contents */
3213 } else if (ieee80211_is_beacon(fc)) {
3214 title = "Beacon";
3215 print_dump = 1; /* dump frame contents */
3216 } else if (ieee80211_is_atim(fc))
3217 title = "ATIM";
3218 else if (ieee80211_is_auth(fc))
3219 title = "Auth";
3220 else if (ieee80211_is_deauth(fc))
3221 title = "DeAuth";
3222 else if (ieee80211_is_disassoc(fc))
3223 title = "DisAssoc";
3224 else
3225 title = "Frame";
3226
3227 rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
3228 if (unlikely(rate_idx == -1))
3229 bitrate = 0;
3230 else
3231 bitrate = iwl4965_rates[rate_idx].ieee / 2;
3232
3233 /* print frame summary.
3234 * MAC addresses show just the last byte (for brevity),
3235 * but you can hack it to show more, if you'd like to. */
3236 if (dataframe)
3237 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
3238 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
3239 title, fc, header->addr1[5],
3240 length, rssi, channel, bitrate);
3241 else {
3242 /* src/dst addresses assume managed mode */
3243 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
3244 "src=0x%02x, rssi=%u, tim=%lu usec, "
3245 "phy=0x%02x, chnl=%d\n",
3246 title, fc, header->addr1[5],
3247 header->addr3[5], rssi,
3248 tsf_low - priv->scan_start_tsf,
3249 phy_flags, channel);
3250 }
3251 }
3252 if (print_dump)
3253 iwl_print_hex_dump(IWL_DL_RX, data, length);
3254 }
3255 #else
3256 static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
3257 struct iwl4965_rx_packet *pkt,
3258 struct ieee80211_hdr *header,
3259 int group100)
3260 {
3261 }
3262 #endif
3263
3264
3265
3266 /* Called for REPLY_RX (legacy ABG frames), or
3267 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
3268 static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
3269 struct iwl4965_rx_mem_buffer *rxb)
3270 {
3271 struct ieee80211_hdr *header;
3272 struct ieee80211_rx_status rx_status;
3273 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3274 /* Use phy data (Rx signal strength, etc.) contained within
3275 * this rx packet for legacy frames,
3276 * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
3277 int include_phy = (pkt->hdr.cmd == REPLY_RX);
3278 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3279 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
3280 (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3281 __le32 *rx_end;
3282 unsigned int len = 0;
3283 u16 fc;
3284 u8 network_packet;
3285
3286 rx_status.mactime = le64_to_cpu(rx_start->timestamp);
3287 rx_status.freq =
3288 ieee80211_frequency_to_channel(le16_to_cpu(rx_start->channel));
3289 rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
3290 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
3291 rx_status.rate_idx =
3292 iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
3293 if (rx_status.band == IEEE80211_BAND_5GHZ)
3294 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
3295
3296 rx_status.antenna = 0;
3297 rx_status.flag = 0;
3298
3299 if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
3300 IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
3301 rx_start->cfg_phy_cnt);
3302 return;
3303 }
3304
3305 if (!include_phy) {
3306 if (priv->last_phy_res[0])
3307 rx_start = (struct iwl4965_rx_phy_res *)
3308 &priv->last_phy_res[1];
3309 else
3310 rx_start = NULL;
3311 }
3312
3313 if (!rx_start) {
3314 IWL_ERROR("MPDU frame without a PHY data\n");
3315 return;
3316 }
3317
3318 if (include_phy) {
3319 header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
3320 + rx_start->cfg_phy_cnt);
3321
3322 len = le16_to_cpu(rx_start->byte_count);
3323 rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
3324 sizeof(struct iwl4965_rx_phy_res) + len);
3325 } else {
3326 struct iwl4965_rx_mpdu_res_start *amsdu =
3327 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3328
3329 header = (void *)(pkt->u.raw +
3330 sizeof(struct iwl4965_rx_mpdu_res_start));
3331 len = le16_to_cpu(amsdu->byte_count);
3332 rx_end = (__le32 *) (pkt->u.raw +
3333 sizeof(struct iwl4965_rx_mpdu_res_start) + len);
3334 }
3335
3336 if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
3337 !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
3338 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
3339 le32_to_cpu(*rx_end));
3340 return;
3341 }
3342
3343 priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
3344
3345 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
3346 rx_status.ssi = iwl4965_calc_rssi(rx_start);
3347
3348 /* Meaningful noise values are available only from beacon statistics,
3349 * which are gathered only when associated, and indicate noise
3350 * only for the associated network channel ...
3351 * Ignore these noise values while scanning (other channels) */
3352 if (iwl_is_associated(priv) &&
3353 !test_bit(STATUS_SCANNING, &priv->status)) {
3354 rx_status.noise = priv->last_rx_noise;
3355 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi,
3356 rx_status.noise);
3357 } else {
3358 rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3359 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi, 0);
3360 }
3361
3362 /* Reset beacon noise level if not associated. */
3363 if (!iwl_is_associated(priv))
3364 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3365
3366 /* Set "1" to report good data frames in groups of 100 */
3367 /* FIXME: need to optimze the call: */
3368 iwl4965_dbg_report_frame(priv, pkt, header, 1);
3369
3370 IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
3371 rx_status.ssi, rx_status.noise, rx_status.signal,
3372 (unsigned long long)rx_status.mactime);
3373
3374 network_packet = iwl4965_is_network_packet(priv, header);
3375 if (network_packet) {
3376 priv->last_rx_rssi = rx_status.ssi;
3377 priv->last_beacon_time = priv->ucode_beacon_time;
3378 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
3379 }
3380
3381 fc = le16_to_cpu(header->frame_control);
3382 switch (fc & IEEE80211_FCTL_FTYPE) {
3383 case IEEE80211_FTYPE_MGMT:
3384 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3385 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
3386 header->addr2);
3387 iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
3388 break;
3389
3390 case IEEE80211_FTYPE_CTL:
3391 #ifdef CONFIG_IWL4965_HT
3392 switch (fc & IEEE80211_FCTL_STYPE) {
3393 case IEEE80211_STYPE_BACK_REQ:
3394 IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
3395 iwl4965_handle_data_packet(priv, 0, include_phy,
3396 rxb, &rx_status);
3397 break;
3398 default:
3399 break;
3400 }
3401 #endif
3402 break;
3403
3404 case IEEE80211_FTYPE_DATA: {
3405 DECLARE_MAC_BUF(mac1);
3406 DECLARE_MAC_BUF(mac2);
3407 DECLARE_MAC_BUF(mac3);
3408
3409 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3410 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
3411 header->addr2);
3412
3413 if (unlikely(!network_packet))
3414 IWL_DEBUG_DROP("Dropping (non network): "
3415 "%s, %s, %s\n",
3416 print_mac(mac1, header->addr1),
3417 print_mac(mac2, header->addr2),
3418 print_mac(mac3, header->addr3));
3419 else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
3420 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
3421 print_mac(mac1, header->addr1),
3422 print_mac(mac2, header->addr2),
3423 print_mac(mac3, header->addr3));
3424 else
3425 iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
3426 &rx_status);
3427 break;
3428 }
3429 default:
3430 break;
3431
3432 }
3433 }
3434
3435 /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
3436 * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
3437 static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
3438 struct iwl4965_rx_mem_buffer *rxb)
3439 {
3440 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3441 priv->last_phy_res[0] = 1;
3442 memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
3443 sizeof(struct iwl4965_rx_phy_res));
3444 }
3445 static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
3446 struct iwl4965_rx_mem_buffer *rxb)
3447
3448 {
3449 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
3450 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3451 struct iwl4965_missed_beacon_notif *missed_beacon;
3452
3453 missed_beacon = &pkt->u.missed_beacon;
3454 if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
3455 IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
3456 le32_to_cpu(missed_beacon->consequtive_missed_beacons),
3457 le32_to_cpu(missed_beacon->total_missed_becons),
3458 le32_to_cpu(missed_beacon->num_recvd_beacons),
3459 le32_to_cpu(missed_beacon->num_expected_beacons));
3460 if (!test_bit(STATUS_SCANNING, &priv->status))
3461 iwl_init_sensitivity(priv);
3462 }
3463 #endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
3464 }
3465 #ifdef CONFIG_IWL4965_HT
3466
3467 /**
3468 * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
3469 */
3470 static void iwl4965_sta_modify_enable_tid_tx(struct iwl_priv *priv,
3471 int sta_id, int tid)
3472 {
3473 unsigned long flags;
3474
3475 /* Remove "disable" flag, to enable Tx for this TID */
3476 spin_lock_irqsave(&priv->sta_lock, flags);
3477 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3478 priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3479 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3480 spin_unlock_irqrestore(&priv->sta_lock, flags);
3481
3482 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
3483 }
3484
3485 /**
3486 * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
3487 *
3488 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
3489 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
3490 */
3491 static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
3492 struct iwl4965_ht_agg *agg,
3493 struct iwl4965_compressed_ba_resp*
3494 ba_resp)
3495
3496 {
3497 int i, sh, ack;
3498 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
3499 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
3500 u64 bitmap;
3501 int successes = 0;
3502 struct ieee80211_tx_status *tx_status;
3503
3504 if (unlikely(!agg->wait_for_ba)) {
3505 IWL_ERROR("Received BA when not expected\n");
3506 return -EINVAL;
3507 }
3508
3509 /* Mark that the expected block-ack response arrived */
3510 agg->wait_for_ba = 0;
3511 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
3512
3513 /* Calculate shift to align block-ack bits with our Tx window bits */
3514 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
3515 if (sh < 0) /* tbw something is wrong with indices */
3516 sh += 0x100;
3517
3518 /* don't use 64-bit values for now */
3519 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
3520
3521 if (agg->frame_count > (64 - sh)) {
3522 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
3523 return -1;
3524 }
3525
3526 /* check for success or failure according to the
3527 * transmitted bitmap and block-ack bitmap */
3528 bitmap &= agg->bitmap;
3529
3530 /* For each frame attempted in aggregation,
3531 * update driver's record of tx frame's status. */
3532 for (i = 0; i < agg->frame_count ; i++) {
3533 ack = bitmap & (1 << i);
3534 successes += !!ack;
3535 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
3536 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
3537 agg->start_idx + i);
3538 }
3539
3540 tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
3541 tx_status->flags = IEEE80211_TX_STATUS_ACK;
3542 tx_status->flags |= IEEE80211_TX_STATUS_AMPDU;
3543 tx_status->ampdu_ack_map = successes;
3544 tx_status->ampdu_ack_len = agg->frame_count;
3545 iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags,
3546 &tx_status->control);
3547
3548 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
3549
3550 return 0;
3551 }
3552
3553 /**
3554 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
3555 */
3556 static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
3557 u16 txq_id)
3558 {
3559 /* Simply stop the queue, but don't change any configuration;
3560 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
3561 iwl_write_prph(priv,
3562 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
3563 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
3564 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
3565 }
3566
3567 /**
3568 * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
3569 * priv->lock must be held by the caller
3570 */
3571 static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
3572 u16 ssn_idx, u8 tx_fifo)
3573 {
3574 int ret = 0;
3575
3576 if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
3577 IWL_WARNING("queue number too small: %d, must be > %d\n",
3578 txq_id, IWL_BACK_QUEUE_FIRST_ID);
3579 return -EINVAL;
3580 }
3581
3582 ret = iwl_grab_nic_access(priv);
3583 if (ret)
3584 return ret;
3585
3586 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3587
3588 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
3589
3590 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3591 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
3592 /* supposes that ssn_idx is valid (!= 0xFFF) */
3593 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3594
3595 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
3596 iwl4965_txq_ctx_deactivate(priv, txq_id);
3597 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
3598
3599 iwl_release_nic_access(priv);
3600
3601 return 0;
3602 }
3603
3604 int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
3605 u8 tid, int txq_id)
3606 {
3607 struct iwl4965_queue *q = &priv->txq[txq_id].q;
3608 u8 *addr = priv->stations[sta_id].sta.sta.addr;
3609 struct iwl4965_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
3610
3611 switch (priv->stations[sta_id].tid[tid].agg.state) {
3612 case IWL_EMPTYING_HW_QUEUE_DELBA:
3613 /* We are reclaiming the last packet of the */
3614 /* aggregated HW queue */
3615 if (txq_id == tid_data->agg.txq_id &&
3616 q->read_ptr == q->write_ptr) {
3617 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
3618 int tx_fifo = default_tid_to_tx_fifo[tid];
3619 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
3620 iwl4965_tx_queue_agg_disable(priv, txq_id,
3621 ssn, tx_fifo);
3622 tid_data->agg.state = IWL_AGG_OFF;
3623 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3624 }
3625 break;
3626 case IWL_EMPTYING_HW_QUEUE_ADDBA:
3627 /* We are reclaiming the last packet of the queue */
3628 if (tid_data->tfds_in_queue == 0) {
3629 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
3630 tid_data->agg.state = IWL_AGG_ON;
3631 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3632 }
3633 break;
3634 }
3635 return 0;
3636 }
3637
3638 /**
3639 * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
3640 * @index -- current index
3641 * @n_bd -- total number of entries in queue (s/b power of 2)
3642 */
3643 static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
3644 {
3645 return (index == 0) ? n_bd - 1 : index - 1;
3646 }
3647
3648 /**
3649 * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
3650 *
3651 * Handles block-acknowledge notification from device, which reports success
3652 * of frames sent via aggregation.
3653 */
3654 static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
3655 struct iwl4965_rx_mem_buffer *rxb)
3656 {
3657 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3658 struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
3659 int index;
3660 struct iwl4965_tx_queue *txq = NULL;
3661 struct iwl4965_ht_agg *agg;
3662 DECLARE_MAC_BUF(mac);
3663
3664 /* "flow" corresponds to Tx queue */
3665 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
3666
3667 /* "ssn" is start of block-ack Tx window, corresponds to index
3668 * (in Tx queue's circular buffer) of first TFD/frame in window */
3669 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
3670
3671 if (scd_flow >= priv->hw_params.max_txq_num) {
3672 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
3673 return;
3674 }
3675
3676 txq = &priv->txq[scd_flow];
3677 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
3678
3679 /* Find index just before block-ack window */
3680 index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
3681
3682 /* TODO: Need to get this copy more safely - now good for debug */
3683
3684 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
3685 "sta_id = %d\n",
3686 agg->wait_for_ba,
3687 print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
3688 ba_resp->sta_id);
3689 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
3690 "%d, scd_ssn = %d\n",
3691 ba_resp->tid,
3692 ba_resp->seq_ctl,
3693 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
3694 ba_resp->scd_flow,
3695 ba_resp->scd_ssn);
3696 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
3697 agg->start_idx,
3698 (unsigned long long)agg->bitmap);
3699
3700 /* Update driver's record of ACK vs. not for each frame in window */
3701 iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
3702
3703 /* Release all TFDs before the SSN, i.e. all TFDs in front of
3704 * block-ack window (we assume that they've been successfully
3705 * transmitted ... if not, it's too late anyway). */
3706 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
3707 int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
3708 priv->stations[ba_resp->sta_id].
3709 tid[ba_resp->tid].tfds_in_queue -= freed;
3710 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
3711 priv->mac80211_registered &&
3712 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
3713 ieee80211_wake_queue(priv->hw, scd_flow);
3714 iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
3715 ba_resp->tid, scd_flow);
3716 }
3717 }
3718
3719 /**
3720 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
3721 */
3722 static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
3723 u16 txq_id)
3724 {
3725 u32 tbl_dw_addr;
3726 u32 tbl_dw;
3727 u16 scd_q2ratid;
3728
3729 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
3730
3731 tbl_dw_addr = priv->scd_base_addr +
3732 SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
3733
3734 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
3735
3736 if (txq_id & 0x1)
3737 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
3738 else
3739 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
3740
3741 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
3742
3743 return 0;
3744 }
3745
3746
3747 /**
3748 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
3749 *
3750 * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
3751 * i.e. it must be one of the higher queues used for aggregation
3752 */
3753 static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
3754 int tx_fifo, int sta_id, int tid,
3755 u16 ssn_idx)
3756 {
3757 unsigned long flags;
3758 int rc;
3759 u16 ra_tid;
3760
3761 if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
3762 IWL_WARNING("queue number too small: %d, must be > %d\n",
3763 txq_id, IWL_BACK_QUEUE_FIRST_ID);
3764
3765 ra_tid = BUILD_RAxTID(sta_id, tid);
3766
3767 /* Modify device's station table to Tx this TID */
3768 iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
3769
3770 spin_lock_irqsave(&priv->lock, flags);
3771 rc = iwl_grab_nic_access(priv);
3772 if (rc) {
3773 spin_unlock_irqrestore(&priv->lock, flags);
3774 return rc;
3775 }
3776
3777 /* Stop this Tx queue before configuring it */
3778 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3779
3780 /* Map receiver-address / traffic-ID to this queue */
3781 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
3782
3783 /* Set this queue as a chain-building queue */
3784 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
3785
3786 /* Place first TFD at index corresponding to start sequence number.
3787 * Assumes that ssn_idx is valid (!= 0xFFF) */
3788 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3789 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
3790 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3791
3792 /* Set up Tx window size and frame limit for this queue */
3793 iwl_write_targ_mem(priv,
3794 priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
3795 (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
3796 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
3797
3798 iwl_write_targ_mem(priv, priv->scd_base_addr +
3799 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
3800 (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
3801 & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
3802
3803 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
3804
3805 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
3806 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
3807
3808 iwl_release_nic_access(priv);
3809 spin_unlock_irqrestore(&priv->lock, flags);
3810
3811 return 0;
3812 }
3813
3814 #endif /* CONFIG_IWL4965_HT */
3815
3816 /**
3817 * iwl4965_add_station - Initialize a station's hardware rate table
3818 *
3819 * The uCode's station table contains a table of fallback rates
3820 * for automatic fallback during transmission.
3821 *
3822 * NOTE: This sets up a default set of values. These will be replaced later
3823 * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
3824 * rc80211_simple.
3825 *
3826 * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
3827 * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
3828 * which requires station table entry to exist).
3829 */
3830 void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
3831 {
3832 int i, r;
3833 struct iwl_link_quality_cmd link_cmd = {
3834 .reserved1 = 0,
3835 };
3836 u16 rate_flags;
3837
3838 /* Set up the rate scaling to start at selected rate, fall back
3839 * all the way down to 1M in IEEE order, and then spin on 1M */
3840 if (is_ap)
3841 r = IWL_RATE_54M_INDEX;
3842 else if (priv->band == IEEE80211_BAND_5GHZ)
3843 r = IWL_RATE_6M_INDEX;
3844 else
3845 r = IWL_RATE_1M_INDEX;
3846
3847 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
3848 rate_flags = 0;
3849 if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
3850 rate_flags |= RATE_MCS_CCK_MSK;
3851
3852 /* Use Tx antenna B only */
3853 rate_flags |= RATE_MCS_ANT_B_MSK;
3854 rate_flags &= ~RATE_MCS_ANT_A_MSK;
3855
3856 link_cmd.rs_table[i].rate_n_flags =
3857 iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
3858 r = iwl4965_get_prev_ieee_rate(r);
3859 }
3860
3861 link_cmd.general_params.single_stream_ant_msk = 2;
3862 link_cmd.general_params.dual_stream_ant_msk = 3;
3863 link_cmd.agg_params.agg_dis_start_th = 3;
3864 link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
3865
3866 /* Update the rate scaling for control frame Tx to AP */
3867 link_cmd.sta_id = is_ap ? IWL_AP_ID : priv->hw_params.bcast_sta_id;
3868
3869 iwl_send_cmd_pdu_async(priv, REPLY_TX_LINK_QUALITY_CMD,
3870 sizeof(link_cmd), &link_cmd, NULL);
3871 }
3872
3873 #ifdef CONFIG_IWL4965_HT
3874
3875 static u8 iwl4965_is_channel_extension(struct iwl_priv *priv,
3876 enum ieee80211_band band,
3877 u16 channel, u8 extension_chan_offset)
3878 {
3879 const struct iwl_channel_info *ch_info;
3880
3881 ch_info = iwl_get_channel_info(priv, band, channel);
3882 if (!is_channel_valid(ch_info))
3883 return 0;
3884
3885 if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
3886 return 0;
3887
3888 if ((ch_info->fat_extension_channel == extension_chan_offset) ||
3889 (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
3890 return 1;
3891
3892 return 0;
3893 }
3894
3895 static u8 iwl4965_is_fat_tx_allowed(struct iwl_priv *priv,
3896 struct ieee80211_ht_info *sta_ht_inf)
3897 {
3898 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
3899
3900 if ((!iwl_ht_conf->is_ht) ||
3901 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
3902 (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
3903 return 0;
3904
3905 if (sta_ht_inf) {
3906 if ((!sta_ht_inf->ht_supported) ||
3907 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
3908 return 0;
3909 }
3910
3911 return (iwl4965_is_channel_extension(priv, priv->band,
3912 iwl_ht_conf->control_channel,
3913 iwl_ht_conf->extension_chan_offset));
3914 }
3915
3916 void iwl4965_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
3917 {
3918 struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
3919 u32 val;
3920
3921 if (!ht_info->is_ht)
3922 return;
3923
3924 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
3925 if (iwl4965_is_fat_tx_allowed(priv, NULL))
3926 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
3927 else
3928 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
3929 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
3930
3931 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
3932 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
3933 le16_to_cpu(rxon->channel),
3934 ht_info->control_channel);
3935 rxon->channel = cpu_to_le16(ht_info->control_channel);
3936 return;
3937 }
3938
3939 /* Note: control channel is opposite of extension channel */
3940 switch (ht_info->extension_chan_offset) {
3941 case IWL_EXT_CHANNEL_OFFSET_ABOVE:
3942 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
3943 break;
3944 case IWL_EXT_CHANNEL_OFFSET_BELOW:
3945 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
3946 break;
3947 case IWL_EXT_CHANNEL_OFFSET_NONE:
3948 default:
3949 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
3950 break;
3951 }
3952
3953 val = ht_info->ht_protection;
3954
3955 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
3956
3957 iwl4965_set_rxon_chain(priv);
3958
3959 IWL_DEBUG_ASSOC("supported HT rate 0x%X %X "
3960 "rxon flags 0x%X operation mode :0x%X "
3961 "extension channel offset 0x%x "
3962 "control chan %d\n",
3963 ht_info->supp_mcs_set[0], ht_info->supp_mcs_set[1],
3964 le32_to_cpu(rxon->flags), ht_info->ht_protection,
3965 ht_info->extension_chan_offset,
3966 ht_info->control_channel);
3967 return;
3968 }
3969
3970 void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index,
3971 struct ieee80211_ht_info *sta_ht_inf)
3972 {
3973 __le32 sta_flags;
3974 u8 mimo_ps_mode;
3975
3976 if (!sta_ht_inf || !sta_ht_inf->ht_supported)
3977 goto done;
3978
3979 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
3980
3981 sta_flags = priv->stations[index].sta.station_flags;
3982
3983 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
3984
3985 switch (mimo_ps_mode) {
3986 case WLAN_HT_CAP_MIMO_PS_STATIC:
3987 sta_flags |= STA_FLG_MIMO_DIS_MSK;
3988 break;
3989 case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
3990 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
3991 break;
3992 case WLAN_HT_CAP_MIMO_PS_DISABLED:
3993 break;
3994 default:
3995 IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
3996 break;
3997 }
3998
3999 sta_flags |= cpu_to_le32(
4000 (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
4001
4002 sta_flags |= cpu_to_le32(
4003 (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
4004
4005 if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf))
4006 sta_flags |= STA_FLG_FAT_EN_MSK;
4007 else
4008 sta_flags &= ~STA_FLG_FAT_EN_MSK;
4009
4010 priv->stations[index].sta.station_flags = sta_flags;
4011 done:
4012 return;
4013 }
4014
4015 static void iwl4965_sta_modify_add_ba_tid(struct iwl_priv *priv,
4016 int sta_id, int tid, u16 ssn)
4017 {
4018 unsigned long flags;
4019
4020 spin_lock_irqsave(&priv->sta_lock, flags);
4021 priv->stations[sta_id].sta.station_flags_msk = 0;
4022 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
4023 priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
4024 priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
4025 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4026 spin_unlock_irqrestore(&priv->sta_lock, flags);
4027
4028 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
4029 }
4030
4031 static void iwl4965_sta_modify_del_ba_tid(struct iwl_priv *priv,
4032 int sta_id, int tid)
4033 {
4034 unsigned long flags;
4035
4036 spin_lock_irqsave(&priv->sta_lock, flags);
4037 priv->stations[sta_id].sta.station_flags_msk = 0;
4038 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
4039 priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
4040 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4041 spin_unlock_irqrestore(&priv->sta_lock, flags);
4042
4043 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
4044 }
4045
4046 /*
4047 * Find first available (lowest unused) Tx Queue, mark it "active".
4048 * Called only when finding queue for aggregation.
4049 * Should never return anything < 7, because they should already
4050 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
4051 */
4052 static int iwl4965_txq_ctx_activate_free(struct iwl_priv *priv)
4053 {
4054 int txq_id;
4055
4056 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
4057 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
4058 return txq_id;
4059 return -1;
4060 }
4061
4062 static int iwl4965_mac_ht_tx_agg_start(struct ieee80211_hw *hw, const u8 *da,
4063 u16 tid, u16 *start_seq_num)
4064 {
4065 struct iwl_priv *priv = hw->priv;
4066 int sta_id;
4067 int tx_fifo;
4068 int txq_id;
4069 int ssn = -1;
4070 int ret = 0;
4071 unsigned long flags;
4072 struct iwl4965_tid_data *tid_data;
4073 DECLARE_MAC_BUF(mac);
4074
4075 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4076 tx_fifo = default_tid_to_tx_fifo[tid];
4077 else
4078 return -EINVAL;
4079
4080 IWL_WARNING("%s on da = %s tid = %d\n",
4081 __func__, print_mac(mac, da), tid);
4082
4083 sta_id = iwl_find_station(priv, da);
4084 if (sta_id == IWL_INVALID_STATION)
4085 return -ENXIO;
4086
4087 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
4088 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
4089 return -ENXIO;
4090 }
4091
4092 txq_id = iwl4965_txq_ctx_activate_free(priv);
4093 if (txq_id == -1)
4094 return -ENXIO;
4095
4096 spin_lock_irqsave(&priv->sta_lock, flags);
4097 tid_data = &priv->stations[sta_id].tid[tid];
4098 ssn = SEQ_TO_SN(tid_data->seq_number);
4099 tid_data->agg.txq_id = txq_id;
4100 spin_unlock_irqrestore(&priv->sta_lock, flags);
4101
4102 *start_seq_num = ssn;
4103 ret = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
4104 sta_id, tid, ssn);
4105 if (ret)
4106 return ret;
4107
4108 ret = 0;
4109 if (tid_data->tfds_in_queue == 0) {
4110 printk(KERN_ERR "HW queue is empty\n");
4111 tid_data->agg.state = IWL_AGG_ON;
4112 ieee80211_start_tx_ba_cb_irqsafe(hw, da, tid);
4113 } else {
4114 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
4115 tid_data->tfds_in_queue);
4116 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
4117 }
4118 return ret;
4119 }
4120
4121 static int iwl4965_mac_ht_tx_agg_stop(struct ieee80211_hw *hw, const u8 *da,
4122 u16 tid)
4123 {
4124
4125 struct iwl_priv *priv = hw->priv;
4126 int tx_fifo_id, txq_id, sta_id, ssn = -1;
4127 struct iwl4965_tid_data *tid_data;
4128 int ret, write_ptr, read_ptr;
4129 unsigned long flags;
4130 DECLARE_MAC_BUF(mac);
4131
4132 if (!da) {
4133 IWL_ERROR("da = NULL\n");
4134 return -EINVAL;
4135 }
4136
4137 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4138 tx_fifo_id = default_tid_to_tx_fifo[tid];
4139 else
4140 return -EINVAL;
4141
4142 sta_id = iwl_find_station(priv, da);
4143
4144 if (sta_id == IWL_INVALID_STATION)
4145 return -ENXIO;
4146
4147 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
4148 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
4149
4150 tid_data = &priv->stations[sta_id].tid[tid];
4151 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
4152 txq_id = tid_data->agg.txq_id;
4153 write_ptr = priv->txq[txq_id].q.write_ptr;
4154 read_ptr = priv->txq[txq_id].q.read_ptr;
4155
4156 /* The queue is not empty */
4157 if (write_ptr != read_ptr) {
4158 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
4159 priv->stations[sta_id].tid[tid].agg.state =
4160 IWL_EMPTYING_HW_QUEUE_DELBA;
4161 return 0;
4162 }
4163
4164 IWL_DEBUG_HT("HW queue empty\n");;
4165 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
4166
4167 spin_lock_irqsave(&priv->lock, flags);
4168 ret = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
4169 spin_unlock_irqrestore(&priv->lock, flags);
4170
4171 if (ret)
4172 return ret;
4173
4174 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, da, tid);
4175
4176 IWL_DEBUG_INFO("iwl4965_mac_ht_tx_agg_stop on da=%s tid=%d\n",
4177 print_mac(mac, da), tid);
4178
4179 return 0;
4180 }
4181
4182 int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
4183 enum ieee80211_ampdu_mlme_action action,
4184 const u8 *addr, u16 tid, u16 *ssn)
4185 {
4186 struct iwl_priv *priv = hw->priv;
4187 int sta_id;
4188 DECLARE_MAC_BUF(mac);
4189
4190 IWL_DEBUG_HT("A-MPDU action on da=%s tid=%d ",
4191 print_mac(mac, addr), tid);
4192 sta_id = iwl_find_station(priv, addr);
4193 switch (action) {
4194 case IEEE80211_AMPDU_RX_START:
4195 IWL_DEBUG_HT("start Rx\n");
4196 iwl4965_sta_modify_add_ba_tid(priv, sta_id, tid, *ssn);
4197 break;
4198 case IEEE80211_AMPDU_RX_STOP:
4199 IWL_DEBUG_HT("stop Rx\n");
4200 iwl4965_sta_modify_del_ba_tid(priv, sta_id, tid);
4201 break;
4202 case IEEE80211_AMPDU_TX_START:
4203 IWL_DEBUG_HT("start Tx\n");
4204 return iwl4965_mac_ht_tx_agg_start(hw, addr, tid, ssn);
4205 case IEEE80211_AMPDU_TX_STOP:
4206 IWL_DEBUG_HT("stop Tx\n");
4207 return iwl4965_mac_ht_tx_agg_stop(hw, addr, tid);
4208 default:
4209 IWL_DEBUG_HT("unknown\n");
4210 return -EINVAL;
4211 break;
4212 }
4213 return 0;
4214 }
4215
4216 #endif /* CONFIG_IWL4965_HT */
4217
4218 /* Set up 4965-specific Rx frame reply handlers */
4219 void iwl4965_hw_rx_handler_setup(struct iwl_priv *priv)
4220 {
4221 /* Legacy Rx frames */
4222 priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
4223
4224 /* High-throughput (HT) Rx frames */
4225 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
4226 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
4227
4228 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
4229 iwl4965_rx_missed_beacon_notif;
4230
4231 #ifdef CONFIG_IWL4965_HT
4232 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
4233 #endif /* CONFIG_IWL4965_HT */
4234 }
4235
4236 void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv)
4237 {
4238 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
4239 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
4240 INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
4241 #endif
4242 init_timer(&priv->statistics_periodic);
4243 priv->statistics_periodic.data = (unsigned long)priv;
4244 priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
4245 }
4246
4247 void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv)
4248 {
4249 del_timer_sync(&priv->statistics_periodic);
4250
4251 cancel_delayed_work(&priv->init_alive_start);
4252 }
4253
4254
4255 static struct iwl_hcmd_ops iwl4965_hcmd = {
4256 .rxon_assoc = iwl4965_send_rxon_assoc,
4257 };
4258
4259 static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
4260 .enqueue_hcmd = iwl4965_enqueue_hcmd,
4261 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
4262 .chain_noise_reset = iwl4965_chain_noise_reset,
4263 .gain_computation = iwl4965_gain_computation,
4264 #endif
4265 };
4266
4267 static struct iwl_lib_ops iwl4965_lib = {
4268 .init_drv = iwl4965_init_drv,
4269 .set_hw_params = iwl4965_hw_set_hw_params,
4270 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
4271 .hw_nic_init = iwl4965_hw_nic_init,
4272 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
4273 .alive_notify = iwl4965_alive_notify,
4274 .load_ucode = iwl4965_load_bsm,
4275 .eeprom_ops = {
4276 .verify_signature = iwlcore_eeprom_verify_signature,
4277 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
4278 .release_semaphore = iwlcore_eeprom_release_semaphore,
4279 },
4280 .radio_kill_sw = iwl4965_radio_kill_sw,
4281 };
4282
4283 static struct iwl_ops iwl4965_ops = {
4284 .lib = &iwl4965_lib,
4285 .hcmd = &iwl4965_hcmd,
4286 .utils = &iwl4965_hcmd_utils,
4287 };
4288
4289 struct iwl_cfg iwl4965_agn_cfg = {
4290 .name = "4965AGN",
4291 .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
4292 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
4293 .ops = &iwl4965_ops,
4294 .mod_params = &iwl4965_mod_params,
4295 };
4296
4297 module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
4298 MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
4299 module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
4300 MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
4301 module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
4302 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])\n");
4303 module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
4304 MODULE_PARM_DESC(debug, "debug output mask");
4305 module_param_named(
4306 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
4307 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4308
4309 module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
4310 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4311
4312 /* QoS */
4313 module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
4314 MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
4315 module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
4316 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4317
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