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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <linux/slab.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/delay.h>
37 #include <linux/sched.h>
38 #include <linux/skbuff.h>
39 #include <linux/netdevice.h>
40 #include <linux/wireless.h>
41 #include <linux/firmware.h>
42 #include <linux/etherdevice.h>
43 #include <linux/if_arp.h>
44
45 #include <net/mac80211.h>
46
47 #include <asm/div64.h>
48
49 #define DRV_NAME "iwlagn"
50
51 #include "iwl-eeprom.h"
52 #include "iwl-dev.h"
53 #include "iwl-core.h"
54 #include "iwl-io.h"
55 #include "iwl-helpers.h"
56 #include "iwl-sta.h"
57 #include "iwl-calib.h"
58 #include "iwl-agn.h"
59
60
61 /******************************************************************************
62 *
63 * module boiler plate
64 *
65 ******************************************************************************/
66
67 /*
68 * module name, copyright, version, etc.
69 */
70 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
71
72 #ifdef CONFIG_IWLWIFI_DEBUG
73 #define VD "d"
74 #else
75 #define VD
76 #endif
77
78 #define DRV_VERSION IWLWIFI_VERSION VD
79
80
81 MODULE_DESCRIPTION(DRV_DESCRIPTION);
82 MODULE_VERSION(DRV_VERSION);
83 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
84 MODULE_LICENSE("GPL");
85 MODULE_ALIAS("iwl4965");
86
87 /**
88 * iwl_commit_rxon - commit staging_rxon to hardware
89 *
90 * The RXON command in staging_rxon is committed to the hardware and
91 * the active_rxon structure is updated with the new data. This
92 * function correctly transitions out of the RXON_ASSOC_MSK state if
93 * a HW tune is required based on the RXON structure changes.
94 */
95 int iwl_commit_rxon(struct iwl_priv *priv)
96 {
97 /* cast away the const for active_rxon in this function */
98 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
99 int ret;
100 bool new_assoc =
101 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
102
103 if (!iwl_is_alive(priv))
104 return -EBUSY;
105
106 /* always get timestamp with Rx frame */
107 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
108
109 ret = iwl_check_rxon_cmd(priv);
110 if (ret) {
111 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
112 return -EINVAL;
113 }
114
115 /*
116 * receive commit_rxon request
117 * abort any previous channel switch if still in process
118 */
119 if (priv->switch_rxon.switch_in_progress &&
120 (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
121 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
122 le16_to_cpu(priv->switch_rxon.channel));
123 priv->switch_rxon.switch_in_progress = false;
124 }
125
126 /* If we don't need to send a full RXON, we can use
127 * iwl_rxon_assoc_cmd which is used to reconfigure filter
128 * and other flags for the current radio configuration. */
129 if (!iwl_full_rxon_required(priv)) {
130 ret = iwl_send_rxon_assoc(priv);
131 if (ret) {
132 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
133 return ret;
134 }
135
136 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
137 iwl_print_rx_config_cmd(priv);
138 return 0;
139 }
140
141 /* If we are currently associated and the new config requires
142 * an RXON_ASSOC and the new config wants the associated mask enabled,
143 * we must clear the associated from the active configuration
144 * before we apply the new config */
145 if (iwl_is_associated(priv) && new_assoc) {
146 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
147 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
148
149 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
150 sizeof(struct iwl_rxon_cmd),
151 &priv->active_rxon);
152
153 /* If the mask clearing failed then we set
154 * active_rxon back to what it was previously */
155 if (ret) {
156 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
157 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
158 return ret;
159 }
160 iwl_clear_ucode_stations(priv, false);
161 iwl_restore_stations(priv);
162 ret = iwl_restore_default_wep_keys(priv);
163 if (ret) {
164 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
165 return ret;
166 }
167 }
168
169 IWL_DEBUG_INFO(priv, "Sending RXON\n"
170 "* with%s RXON_FILTER_ASSOC_MSK\n"
171 "* channel = %d\n"
172 "* bssid = %pM\n",
173 (new_assoc ? "" : "out"),
174 le16_to_cpu(priv->staging_rxon.channel),
175 priv->staging_rxon.bssid_addr);
176
177 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
178
179 /* Apply the new configuration
180 * RXON unassoc clears the station table in uCode so restoration of
181 * stations is needed after it (the RXON command) completes
182 */
183 if (!new_assoc) {
184 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
185 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
186 if (ret) {
187 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
188 return ret;
189 }
190 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
191 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
192 iwl_clear_ucode_stations(priv, false);
193 iwl_restore_stations(priv);
194 ret = iwl_restore_default_wep_keys(priv);
195 if (ret) {
196 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
197 return ret;
198 }
199 }
200
201 priv->start_calib = 0;
202 if (new_assoc) {
203 /*
204 * allow CTS-to-self if possible for new association.
205 * this is relevant only for 5000 series and up,
206 * but will not damage 4965
207 */
208 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
209
210 /* Apply the new configuration
211 * RXON assoc doesn't clear the station table in uCode,
212 */
213 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
214 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
215 if (ret) {
216 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
217 return ret;
218 }
219 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
220 }
221 iwl_print_rx_config_cmd(priv);
222
223 iwl_init_sensitivity(priv);
224
225 /* If we issue a new RXON command which required a tune then we must
226 * send a new TXPOWER command or we won't be able to Tx any frames */
227 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
228 if (ret) {
229 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
230 return ret;
231 }
232
233 return 0;
234 }
235
236 void iwl_update_chain_flags(struct iwl_priv *priv)
237 {
238
239 if (priv->cfg->ops->hcmd->set_rxon_chain)
240 priv->cfg->ops->hcmd->set_rxon_chain(priv);
241 iwlcore_commit_rxon(priv);
242 }
243
244 static void iwl_clear_free_frames(struct iwl_priv *priv)
245 {
246 struct list_head *element;
247
248 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
249 priv->frames_count);
250
251 while (!list_empty(&priv->free_frames)) {
252 element = priv->free_frames.next;
253 list_del(element);
254 kfree(list_entry(element, struct iwl_frame, list));
255 priv->frames_count--;
256 }
257
258 if (priv->frames_count) {
259 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
260 priv->frames_count);
261 priv->frames_count = 0;
262 }
263 }
264
265 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
266 {
267 struct iwl_frame *frame;
268 struct list_head *element;
269 if (list_empty(&priv->free_frames)) {
270 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
271 if (!frame) {
272 IWL_ERR(priv, "Could not allocate frame!\n");
273 return NULL;
274 }
275
276 priv->frames_count++;
277 return frame;
278 }
279
280 element = priv->free_frames.next;
281 list_del(element);
282 return list_entry(element, struct iwl_frame, list);
283 }
284
285 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
286 {
287 memset(frame, 0, sizeof(*frame));
288 list_add(&frame->list, &priv->free_frames);
289 }
290
291 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
292 struct ieee80211_hdr *hdr,
293 int left)
294 {
295 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
296 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
297 (priv->iw_mode != NL80211_IFTYPE_AP)))
298 return 0;
299
300 if (priv->ibss_beacon->len > left)
301 return 0;
302
303 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
304
305 return priv->ibss_beacon->len;
306 }
307
308 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
309 static void iwl_set_beacon_tim(struct iwl_priv *priv,
310 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
311 u8 *beacon, u32 frame_size)
312 {
313 u16 tim_idx;
314 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
315
316 /*
317 * The index is relative to frame start but we start looking at the
318 * variable-length part of the beacon.
319 */
320 tim_idx = mgmt->u.beacon.variable - beacon;
321
322 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
323 while ((tim_idx < (frame_size - 2)) &&
324 (beacon[tim_idx] != WLAN_EID_TIM))
325 tim_idx += beacon[tim_idx+1] + 2;
326
327 /* If TIM field was found, set variables */
328 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
329 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
330 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
331 } else
332 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
333 }
334
335 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
336 struct iwl_frame *frame)
337 {
338 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
339 u32 frame_size;
340 u32 rate_flags;
341 u32 rate;
342 /*
343 * We have to set up the TX command, the TX Beacon command, and the
344 * beacon contents.
345 */
346
347 /* Initialize memory */
348 tx_beacon_cmd = &frame->u.beacon;
349 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
350
351 /* Set up TX beacon contents */
352 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
353 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
354 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
355 return 0;
356
357 /* Set up TX command fields */
358 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
359 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
360 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
361 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
362 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
363
364 /* Set up TX beacon command fields */
365 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
366 frame_size);
367
368 /* Set up packet rate and flags */
369 rate = iwl_rate_get_lowest_plcp(priv);
370 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
371 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
372 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
373 rate_flags |= RATE_MCS_CCK_MSK;
374 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
375 rate_flags);
376
377 return sizeof(*tx_beacon_cmd) + frame_size;
378 }
379 static int iwl_send_beacon_cmd(struct iwl_priv *priv)
380 {
381 struct iwl_frame *frame;
382 unsigned int frame_size;
383 int rc;
384
385 frame = iwl_get_free_frame(priv);
386 if (!frame) {
387 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
388 "command.\n");
389 return -ENOMEM;
390 }
391
392 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
393 if (!frame_size) {
394 IWL_ERR(priv, "Error configuring the beacon command\n");
395 iwl_free_frame(priv, frame);
396 return -EINVAL;
397 }
398
399 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
400 &frame->u.cmd[0]);
401
402 iwl_free_frame(priv, frame);
403
404 return rc;
405 }
406
407 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
408 {
409 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
410
411 dma_addr_t addr = get_unaligned_le32(&tb->lo);
412 if (sizeof(dma_addr_t) > sizeof(u32))
413 addr |=
414 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
415
416 return addr;
417 }
418
419 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
420 {
421 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
422
423 return le16_to_cpu(tb->hi_n_len) >> 4;
424 }
425
426 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
427 dma_addr_t addr, u16 len)
428 {
429 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
430 u16 hi_n_len = len << 4;
431
432 put_unaligned_le32(addr, &tb->lo);
433 if (sizeof(dma_addr_t) > sizeof(u32))
434 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
435
436 tb->hi_n_len = cpu_to_le16(hi_n_len);
437
438 tfd->num_tbs = idx + 1;
439 }
440
441 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
442 {
443 return tfd->num_tbs & 0x1f;
444 }
445
446 /**
447 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
448 * @priv - driver private data
449 * @txq - tx queue
450 *
451 * Does NOT advance any TFD circular buffer read/write indexes
452 * Does NOT free the TFD itself (which is within circular buffer)
453 */
454 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
455 {
456 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
457 struct iwl_tfd *tfd;
458 struct pci_dev *dev = priv->pci_dev;
459 int index = txq->q.read_ptr;
460 int i;
461 int num_tbs;
462
463 tfd = &tfd_tmp[index];
464
465 /* Sanity check on number of chunks */
466 num_tbs = iwl_tfd_get_num_tbs(tfd);
467
468 if (num_tbs >= IWL_NUM_OF_TBS) {
469 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
470 /* @todo issue fatal error, it is quite serious situation */
471 return;
472 }
473
474 /* Unmap tx_cmd */
475 if (num_tbs)
476 pci_unmap_single(dev,
477 pci_unmap_addr(&txq->meta[index], mapping),
478 pci_unmap_len(&txq->meta[index], len),
479 PCI_DMA_BIDIRECTIONAL);
480
481 /* Unmap chunks, if any. */
482 for (i = 1; i < num_tbs; i++) {
483 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
484 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
485
486 if (txq->txb) {
487 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
488 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
489 }
490 }
491 }
492
493 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
494 struct iwl_tx_queue *txq,
495 dma_addr_t addr, u16 len,
496 u8 reset, u8 pad)
497 {
498 struct iwl_queue *q;
499 struct iwl_tfd *tfd, *tfd_tmp;
500 u32 num_tbs;
501
502 q = &txq->q;
503 tfd_tmp = (struct iwl_tfd *)txq->tfds;
504 tfd = &tfd_tmp[q->write_ptr];
505
506 if (reset)
507 memset(tfd, 0, sizeof(*tfd));
508
509 num_tbs = iwl_tfd_get_num_tbs(tfd);
510
511 /* Each TFD can point to a maximum 20 Tx buffers */
512 if (num_tbs >= IWL_NUM_OF_TBS) {
513 IWL_ERR(priv, "Error can not send more than %d chunks\n",
514 IWL_NUM_OF_TBS);
515 return -EINVAL;
516 }
517
518 BUG_ON(addr & ~DMA_BIT_MASK(36));
519 if (unlikely(addr & ~IWL_TX_DMA_MASK))
520 IWL_ERR(priv, "Unaligned address = %llx\n",
521 (unsigned long long)addr);
522
523 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
524
525 return 0;
526 }
527
528 /*
529 * Tell nic where to find circular buffer of Tx Frame Descriptors for
530 * given Tx queue, and enable the DMA channel used for that queue.
531 *
532 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
533 * channels supported in hardware.
534 */
535 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
536 struct iwl_tx_queue *txq)
537 {
538 int txq_id = txq->q.id;
539
540 /* Circular buffer (TFD queue in DRAM) physical base address */
541 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
542 txq->q.dma_addr >> 8);
543
544 return 0;
545 }
546
547 /******************************************************************************
548 *
549 * Generic RX handler implementations
550 *
551 ******************************************************************************/
552 static void iwl_rx_reply_alive(struct iwl_priv *priv,
553 struct iwl_rx_mem_buffer *rxb)
554 {
555 struct iwl_rx_packet *pkt = rxb_addr(rxb);
556 struct iwl_alive_resp *palive;
557 struct delayed_work *pwork;
558
559 palive = &pkt->u.alive_frame;
560
561 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
562 "0x%01X 0x%01X\n",
563 palive->is_valid, palive->ver_type,
564 palive->ver_subtype);
565
566 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
567 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
568 memcpy(&priv->card_alive_init,
569 &pkt->u.alive_frame,
570 sizeof(struct iwl_init_alive_resp));
571 pwork = &priv->init_alive_start;
572 } else {
573 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
574 memcpy(&priv->card_alive, &pkt->u.alive_frame,
575 sizeof(struct iwl_alive_resp));
576 pwork = &priv->alive_start;
577 }
578
579 /* We delay the ALIVE response by 5ms to
580 * give the HW RF Kill time to activate... */
581 if (palive->is_valid == UCODE_VALID_OK)
582 queue_delayed_work(priv->workqueue, pwork,
583 msecs_to_jiffies(5));
584 else
585 IWL_WARN(priv, "uCode did not respond OK.\n");
586 }
587
588 static void iwl_bg_beacon_update(struct work_struct *work)
589 {
590 struct iwl_priv *priv =
591 container_of(work, struct iwl_priv, beacon_update);
592 struct sk_buff *beacon;
593
594 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
595 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
596
597 if (!beacon) {
598 IWL_ERR(priv, "update beacon failed\n");
599 return;
600 }
601
602 mutex_lock(&priv->mutex);
603 /* new beacon skb is allocated every time; dispose previous.*/
604 if (priv->ibss_beacon)
605 dev_kfree_skb(priv->ibss_beacon);
606
607 priv->ibss_beacon = beacon;
608 mutex_unlock(&priv->mutex);
609
610 iwl_send_beacon_cmd(priv);
611 }
612
613 /**
614 * iwl_bg_statistics_periodic - Timer callback to queue statistics
615 *
616 * This callback is provided in order to send a statistics request.
617 *
618 * This timer function is continually reset to execute within
619 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
620 * was received. We need to ensure we receive the statistics in order
621 * to update the temperature used for calibrating the TXPOWER.
622 */
623 static void iwl_bg_statistics_periodic(unsigned long data)
624 {
625 struct iwl_priv *priv = (struct iwl_priv *)data;
626
627 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
628 return;
629
630 /* dont send host command if rf-kill is on */
631 if (!iwl_is_ready_rf(priv))
632 return;
633
634 iwl_send_statistics_request(priv, CMD_ASYNC, false);
635 }
636
637
638 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
639 u32 start_idx, u32 num_events,
640 u32 mode)
641 {
642 u32 i;
643 u32 ptr; /* SRAM byte address of log data */
644 u32 ev, time, data; /* event log data */
645 unsigned long reg_flags;
646
647 if (mode == 0)
648 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
649 else
650 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
651
652 /* Make sure device is powered up for SRAM reads */
653 spin_lock_irqsave(&priv->reg_lock, reg_flags);
654 if (iwl_grab_nic_access(priv)) {
655 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
656 return;
657 }
658
659 /* Set starting address; reads will auto-increment */
660 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
661 rmb();
662
663 /*
664 * "time" is actually "data" for mode 0 (no timestamp).
665 * place event id # at far right for easier visual parsing.
666 */
667 for (i = 0; i < num_events; i++) {
668 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
669 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
670 if (mode == 0) {
671 trace_iwlwifi_dev_ucode_cont_event(priv,
672 0, time, ev);
673 } else {
674 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
675 trace_iwlwifi_dev_ucode_cont_event(priv,
676 time, data, ev);
677 }
678 }
679 /* Allow device to power down */
680 iwl_release_nic_access(priv);
681 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
682 }
683
684 static void iwl_continuous_event_trace(struct iwl_priv *priv)
685 {
686 u32 capacity; /* event log capacity in # entries */
687 u32 base; /* SRAM byte address of event log header */
688 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
689 u32 num_wraps; /* # times uCode wrapped to top of log */
690 u32 next_entry; /* index of next entry to be written by uCode */
691
692 if (priv->ucode_type == UCODE_INIT)
693 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
694 else
695 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
696 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
697 capacity = iwl_read_targ_mem(priv, base);
698 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
699 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
700 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
701 } else
702 return;
703
704 if (num_wraps == priv->event_log.num_wraps) {
705 iwl_print_cont_event_trace(priv,
706 base, priv->event_log.next_entry,
707 next_entry - priv->event_log.next_entry,
708 mode);
709 priv->event_log.non_wraps_count++;
710 } else {
711 if ((num_wraps - priv->event_log.num_wraps) > 1)
712 priv->event_log.wraps_more_count++;
713 else
714 priv->event_log.wraps_once_count++;
715 trace_iwlwifi_dev_ucode_wrap_event(priv,
716 num_wraps - priv->event_log.num_wraps,
717 next_entry, priv->event_log.next_entry);
718 if (next_entry < priv->event_log.next_entry) {
719 iwl_print_cont_event_trace(priv, base,
720 priv->event_log.next_entry,
721 capacity - priv->event_log.next_entry,
722 mode);
723
724 iwl_print_cont_event_trace(priv, base, 0,
725 next_entry, mode);
726 } else {
727 iwl_print_cont_event_trace(priv, base,
728 next_entry, capacity - next_entry,
729 mode);
730
731 iwl_print_cont_event_trace(priv, base, 0,
732 next_entry, mode);
733 }
734 }
735 priv->event_log.num_wraps = num_wraps;
736 priv->event_log.next_entry = next_entry;
737 }
738
739 /**
740 * iwl_bg_ucode_trace - Timer callback to log ucode event
741 *
742 * The timer is continually set to execute every
743 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
744 * this function is to perform continuous uCode event logging operation
745 * if enabled
746 */
747 static void iwl_bg_ucode_trace(unsigned long data)
748 {
749 struct iwl_priv *priv = (struct iwl_priv *)data;
750
751 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
752 return;
753
754 if (priv->event_log.ucode_trace) {
755 iwl_continuous_event_trace(priv);
756 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
757 mod_timer(&priv->ucode_trace,
758 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
759 }
760 }
761
762 static void iwl_rx_beacon_notif(struct iwl_priv *priv,
763 struct iwl_rx_mem_buffer *rxb)
764 {
765 #ifdef CONFIG_IWLWIFI_DEBUG
766 struct iwl_rx_packet *pkt = rxb_addr(rxb);
767 struct iwl4965_beacon_notif *beacon =
768 (struct iwl4965_beacon_notif *)pkt->u.raw;
769 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
770
771 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
772 "tsf %d %d rate %d\n",
773 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
774 beacon->beacon_notify_hdr.failure_frame,
775 le32_to_cpu(beacon->ibss_mgr_status),
776 le32_to_cpu(beacon->high_tsf),
777 le32_to_cpu(beacon->low_tsf), rate);
778 #endif
779
780 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
781 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
782 queue_work(priv->workqueue, &priv->beacon_update);
783 }
784
785 /* Handle notification from uCode that card's power state is changing
786 * due to software, hardware, or critical temperature RFKILL */
787 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
788 struct iwl_rx_mem_buffer *rxb)
789 {
790 struct iwl_rx_packet *pkt = rxb_addr(rxb);
791 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
792 unsigned long status = priv->status;
793
794 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
795 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
796 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
797 (flags & CT_CARD_DISABLED) ?
798 "Reached" : "Not reached");
799
800 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
801 CT_CARD_DISABLED)) {
802
803 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
804 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
805
806 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
807 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
808
809 if (!(flags & RXON_CARD_DISABLED)) {
810 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
811 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
812 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
813 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
814 }
815 if (flags & CT_CARD_DISABLED)
816 iwl_tt_enter_ct_kill(priv);
817 }
818 if (!(flags & CT_CARD_DISABLED))
819 iwl_tt_exit_ct_kill(priv);
820
821 if (flags & HW_CARD_DISABLED)
822 set_bit(STATUS_RF_KILL_HW, &priv->status);
823 else
824 clear_bit(STATUS_RF_KILL_HW, &priv->status);
825
826
827 if (!(flags & RXON_CARD_DISABLED))
828 iwl_scan_cancel(priv);
829
830 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
831 test_bit(STATUS_RF_KILL_HW, &priv->status)))
832 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
833 test_bit(STATUS_RF_KILL_HW, &priv->status));
834 else
835 wake_up_interruptible(&priv->wait_command_queue);
836 }
837
838 int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
839 {
840 if (src == IWL_PWR_SRC_VAUX) {
841 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
842 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
843 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
844 ~APMG_PS_CTRL_MSK_PWR_SRC);
845 } else {
846 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
847 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
848 ~APMG_PS_CTRL_MSK_PWR_SRC);
849 }
850
851 return 0;
852 }
853
854 /**
855 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
856 *
857 * Setup the RX handlers for each of the reply types sent from the uCode
858 * to the host.
859 *
860 * This function chains into the hardware specific files for them to setup
861 * any hardware specific handlers as well.
862 */
863 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
864 {
865 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
866 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
867 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
868 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
869 iwl_rx_spectrum_measure_notif;
870 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
871 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
872 iwl_rx_pm_debug_statistics_notif;
873 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
874
875 /*
876 * The same handler is used for both the REPLY to a discrete
877 * statistics request from the host as well as for the periodic
878 * statistics notifications (after received beacons) from the uCode.
879 */
880 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
881 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
882
883 iwl_setup_rx_scan_handlers(priv);
884
885 /* status change handler */
886 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
887
888 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
889 iwl_rx_missed_beacon_notif;
890 /* Rx handlers */
891 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
892 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
893 /* block ack */
894 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
895 /* Set up hardware specific Rx handlers */
896 priv->cfg->ops->lib->rx_handler_setup(priv);
897 }
898
899 /**
900 * iwl_rx_handle - Main entry function for receiving responses from uCode
901 *
902 * Uses the priv->rx_handlers callback function array to invoke
903 * the appropriate handlers, including command responses,
904 * frame-received notifications, and other notifications.
905 */
906 void iwl_rx_handle(struct iwl_priv *priv)
907 {
908 struct iwl_rx_mem_buffer *rxb;
909 struct iwl_rx_packet *pkt;
910 struct iwl_rx_queue *rxq = &priv->rxq;
911 u32 r, i;
912 int reclaim;
913 unsigned long flags;
914 u8 fill_rx = 0;
915 u32 count = 8;
916 int total_empty;
917
918 /* uCode's read index (stored in shared DRAM) indicates the last Rx
919 * buffer that the driver may process (last buffer filled by ucode). */
920 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
921 i = rxq->read;
922
923 /* Rx interrupt, but nothing sent from uCode */
924 if (i == r)
925 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
926
927 /* calculate total frames need to be restock after handling RX */
928 total_empty = r - rxq->write_actual;
929 if (total_empty < 0)
930 total_empty += RX_QUEUE_SIZE;
931
932 if (total_empty > (RX_QUEUE_SIZE / 2))
933 fill_rx = 1;
934
935 while (i != r) {
936 rxb = rxq->queue[i];
937
938 /* If an RXB doesn't have a Rx queue slot associated with it,
939 * then a bug has been introduced in the queue refilling
940 * routines -- catch it here */
941 BUG_ON(rxb == NULL);
942
943 rxq->queue[i] = NULL;
944
945 pci_unmap_page(priv->pci_dev, rxb->page_dma,
946 PAGE_SIZE << priv->hw_params.rx_page_order,
947 PCI_DMA_FROMDEVICE);
948 pkt = rxb_addr(rxb);
949
950 trace_iwlwifi_dev_rx(priv, pkt,
951 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
952
953 /* Reclaim a command buffer only if this packet is a response
954 * to a (driver-originated) command.
955 * If the packet (e.g. Rx frame) originated from uCode,
956 * there is no command buffer to reclaim.
957 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
958 * but apparently a few don't get set; catch them here. */
959 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
960 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
961 (pkt->hdr.cmd != REPLY_RX) &&
962 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
963 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
964 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
965 (pkt->hdr.cmd != REPLY_TX);
966
967 /* Based on type of command response or notification,
968 * handle those that need handling via function in
969 * rx_handlers table. See iwl_setup_rx_handlers() */
970 if (priv->rx_handlers[pkt->hdr.cmd]) {
971 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
972 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
973 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
974 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
975 } else {
976 /* No handling needed */
977 IWL_DEBUG_RX(priv,
978 "r %d i %d No handler needed for %s, 0x%02x\n",
979 r, i, get_cmd_string(pkt->hdr.cmd),
980 pkt->hdr.cmd);
981 }
982
983 /*
984 * XXX: After here, we should always check rxb->page
985 * against NULL before touching it or its virtual
986 * memory (pkt). Because some rx_handler might have
987 * already taken or freed the pages.
988 */
989
990 if (reclaim) {
991 /* Invoke any callbacks, transfer the buffer to caller,
992 * and fire off the (possibly) blocking iwl_send_cmd()
993 * as we reclaim the driver command queue */
994 if (rxb->page)
995 iwl_tx_cmd_complete(priv, rxb);
996 else
997 IWL_WARN(priv, "Claim null rxb?\n");
998 }
999
1000 /* Reuse the page if possible. For notification packets and
1001 * SKBs that fail to Rx correctly, add them back into the
1002 * rx_free list for reuse later. */
1003 spin_lock_irqsave(&rxq->lock, flags);
1004 if (rxb->page != NULL) {
1005 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1006 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1007 PCI_DMA_FROMDEVICE);
1008 list_add_tail(&rxb->list, &rxq->rx_free);
1009 rxq->free_count++;
1010 } else
1011 list_add_tail(&rxb->list, &rxq->rx_used);
1012
1013 spin_unlock_irqrestore(&rxq->lock, flags);
1014
1015 i = (i + 1) & RX_QUEUE_MASK;
1016 /* If there are a lot of unused frames,
1017 * restock the Rx queue so ucode wont assert. */
1018 if (fill_rx) {
1019 count++;
1020 if (count >= 8) {
1021 rxq->read = i;
1022 iwlagn_rx_replenish_now(priv);
1023 count = 0;
1024 }
1025 }
1026 }
1027
1028 /* Backtrack one entry */
1029 rxq->read = i;
1030 if (fill_rx)
1031 iwlagn_rx_replenish_now(priv);
1032 else
1033 iwlagn_rx_queue_restock(priv);
1034 }
1035
1036 /* call this function to flush any scheduled tasklet */
1037 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1038 {
1039 /* wait to make sure we flush pending tasklet*/
1040 synchronize_irq(priv->pci_dev->irq);
1041 tasklet_kill(&priv->irq_tasklet);
1042 }
1043
1044 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
1045 {
1046 u32 inta, handled = 0;
1047 u32 inta_fh;
1048 unsigned long flags;
1049 u32 i;
1050 #ifdef CONFIG_IWLWIFI_DEBUG
1051 u32 inta_mask;
1052 #endif
1053
1054 spin_lock_irqsave(&priv->lock, flags);
1055
1056 /* Ack/clear/reset pending uCode interrupts.
1057 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1058 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
1059 inta = iwl_read32(priv, CSR_INT);
1060 iwl_write32(priv, CSR_INT, inta);
1061
1062 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1063 * Any new interrupts that happen after this, either while we're
1064 * in this tasklet, or later, will show up in next ISR/tasklet. */
1065 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1066 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
1067
1068 #ifdef CONFIG_IWLWIFI_DEBUG
1069 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1070 /* just for debug */
1071 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1072 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1073 inta, inta_mask, inta_fh);
1074 }
1075 #endif
1076
1077 spin_unlock_irqrestore(&priv->lock, flags);
1078
1079 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1080 * atomic, make sure that inta covers all the interrupts that
1081 * we've discovered, even if FH interrupt came in just after
1082 * reading CSR_INT. */
1083 if (inta_fh & CSR49_FH_INT_RX_MASK)
1084 inta |= CSR_INT_BIT_FH_RX;
1085 if (inta_fh & CSR49_FH_INT_TX_MASK)
1086 inta |= CSR_INT_BIT_FH_TX;
1087
1088 /* Now service all interrupt bits discovered above. */
1089 if (inta & CSR_INT_BIT_HW_ERR) {
1090 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
1091
1092 /* Tell the device to stop sending interrupts */
1093 iwl_disable_interrupts(priv);
1094
1095 priv->isr_stats.hw++;
1096 iwl_irq_handle_error(priv);
1097
1098 handled |= CSR_INT_BIT_HW_ERR;
1099
1100 return;
1101 }
1102
1103 #ifdef CONFIG_IWLWIFI_DEBUG
1104 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1105 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1106 if (inta & CSR_INT_BIT_SCD) {
1107 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1108 "the frame/frames.\n");
1109 priv->isr_stats.sch++;
1110 }
1111
1112 /* Alive notification via Rx interrupt will do the real work */
1113 if (inta & CSR_INT_BIT_ALIVE) {
1114 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1115 priv->isr_stats.alive++;
1116 }
1117 }
1118 #endif
1119 /* Safely ignore these bits for debug checks below */
1120 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1121
1122 /* HW RF KILL switch toggled */
1123 if (inta & CSR_INT_BIT_RF_KILL) {
1124 int hw_rf_kill = 0;
1125 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1126 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1127 hw_rf_kill = 1;
1128
1129 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1130 hw_rf_kill ? "disable radio" : "enable radio");
1131
1132 priv->isr_stats.rfkill++;
1133
1134 /* driver only loads ucode once setting the interface up.
1135 * the driver allows loading the ucode even if the radio
1136 * is killed. Hence update the killswitch state here. The
1137 * rfkill handler will care about restarting if needed.
1138 */
1139 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1140 if (hw_rf_kill)
1141 set_bit(STATUS_RF_KILL_HW, &priv->status);
1142 else
1143 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1144 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1145 }
1146
1147 handled |= CSR_INT_BIT_RF_KILL;
1148 }
1149
1150 /* Chip got too hot and stopped itself */
1151 if (inta & CSR_INT_BIT_CT_KILL) {
1152 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1153 priv->isr_stats.ctkill++;
1154 handled |= CSR_INT_BIT_CT_KILL;
1155 }
1156
1157 /* Error detected by uCode */
1158 if (inta & CSR_INT_BIT_SW_ERR) {
1159 IWL_ERR(priv, "Microcode SW error detected. "
1160 " Restarting 0x%X.\n", inta);
1161 priv->isr_stats.sw++;
1162 priv->isr_stats.sw_err = inta;
1163 iwl_irq_handle_error(priv);
1164 handled |= CSR_INT_BIT_SW_ERR;
1165 }
1166
1167 /*
1168 * uCode wakes up after power-down sleep.
1169 * Tell device about any new tx or host commands enqueued,
1170 * and about any Rx buffers made available while asleep.
1171 */
1172 if (inta & CSR_INT_BIT_WAKEUP) {
1173 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1174 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1175 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1176 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1177 priv->isr_stats.wakeup++;
1178 handled |= CSR_INT_BIT_WAKEUP;
1179 }
1180
1181 /* All uCode command responses, including Tx command responses,
1182 * Rx "responses" (frame-received notification), and other
1183 * notifications from uCode come through here*/
1184 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1185 iwl_rx_handle(priv);
1186 priv->isr_stats.rx++;
1187 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1188 }
1189
1190 /* This "Tx" DMA channel is used only for loading uCode */
1191 if (inta & CSR_INT_BIT_FH_TX) {
1192 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1193 priv->isr_stats.tx++;
1194 handled |= CSR_INT_BIT_FH_TX;
1195 /* Wake up uCode load routine, now that load is complete */
1196 priv->ucode_write_complete = 1;
1197 wake_up_interruptible(&priv->wait_command_queue);
1198 }
1199
1200 if (inta & ~handled) {
1201 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1202 priv->isr_stats.unhandled++;
1203 }
1204
1205 if (inta & ~(priv->inta_mask)) {
1206 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1207 inta & ~priv->inta_mask);
1208 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
1209 }
1210
1211 /* Re-enable all interrupts */
1212 /* only Re-enable if diabled by irq */
1213 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1214 iwl_enable_interrupts(priv);
1215
1216 #ifdef CONFIG_IWLWIFI_DEBUG
1217 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1218 inta = iwl_read32(priv, CSR_INT);
1219 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1220 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1221 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1222 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1223 }
1224 #endif
1225 }
1226
1227 /* tasklet for iwlagn interrupt */
1228 static void iwl_irq_tasklet(struct iwl_priv *priv)
1229 {
1230 u32 inta = 0;
1231 u32 handled = 0;
1232 unsigned long flags;
1233 u32 i;
1234 #ifdef CONFIG_IWLWIFI_DEBUG
1235 u32 inta_mask;
1236 #endif
1237
1238 spin_lock_irqsave(&priv->lock, flags);
1239
1240 /* Ack/clear/reset pending uCode interrupts.
1241 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1242 */
1243 /* There is a hardware bug in the interrupt mask function that some
1244 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1245 * they are disabled in the CSR_INT_MASK register. Furthermore the
1246 * ICT interrupt handling mechanism has another bug that might cause
1247 * these unmasked interrupts fail to be detected. We workaround the
1248 * hardware bugs here by ACKing all the possible interrupts so that
1249 * interrupt coalescing can still be achieved.
1250 */
1251 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
1252
1253 inta = priv->_agn.inta;
1254
1255 #ifdef CONFIG_IWLWIFI_DEBUG
1256 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1257 /* just for debug */
1258 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1259 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1260 inta, inta_mask);
1261 }
1262 #endif
1263
1264 spin_unlock_irqrestore(&priv->lock, flags);
1265
1266 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1267 priv->_agn.inta = 0;
1268
1269 /* Now service all interrupt bits discovered above. */
1270 if (inta & CSR_INT_BIT_HW_ERR) {
1271 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
1272
1273 /* Tell the device to stop sending interrupts */
1274 iwl_disable_interrupts(priv);
1275
1276 priv->isr_stats.hw++;
1277 iwl_irq_handle_error(priv);
1278
1279 handled |= CSR_INT_BIT_HW_ERR;
1280
1281 return;
1282 }
1283
1284 #ifdef CONFIG_IWLWIFI_DEBUG
1285 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1286 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1287 if (inta & CSR_INT_BIT_SCD) {
1288 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1289 "the frame/frames.\n");
1290 priv->isr_stats.sch++;
1291 }
1292
1293 /* Alive notification via Rx interrupt will do the real work */
1294 if (inta & CSR_INT_BIT_ALIVE) {
1295 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1296 priv->isr_stats.alive++;
1297 }
1298 }
1299 #endif
1300 /* Safely ignore these bits for debug checks below */
1301 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1302
1303 /* HW RF KILL switch toggled */
1304 if (inta & CSR_INT_BIT_RF_KILL) {
1305 int hw_rf_kill = 0;
1306 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1307 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1308 hw_rf_kill = 1;
1309
1310 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1311 hw_rf_kill ? "disable radio" : "enable radio");
1312
1313 priv->isr_stats.rfkill++;
1314
1315 /* driver only loads ucode once setting the interface up.
1316 * the driver allows loading the ucode even if the radio
1317 * is killed. Hence update the killswitch state here. The
1318 * rfkill handler will care about restarting if needed.
1319 */
1320 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1321 if (hw_rf_kill)
1322 set_bit(STATUS_RF_KILL_HW, &priv->status);
1323 else
1324 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1325 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1326 }
1327
1328 handled |= CSR_INT_BIT_RF_KILL;
1329 }
1330
1331 /* Chip got too hot and stopped itself */
1332 if (inta & CSR_INT_BIT_CT_KILL) {
1333 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1334 priv->isr_stats.ctkill++;
1335 handled |= CSR_INT_BIT_CT_KILL;
1336 }
1337
1338 /* Error detected by uCode */
1339 if (inta & CSR_INT_BIT_SW_ERR) {
1340 IWL_ERR(priv, "Microcode SW error detected. "
1341 " Restarting 0x%X.\n", inta);
1342 priv->isr_stats.sw++;
1343 priv->isr_stats.sw_err = inta;
1344 iwl_irq_handle_error(priv);
1345 handled |= CSR_INT_BIT_SW_ERR;
1346 }
1347
1348 /* uCode wakes up after power-down sleep */
1349 if (inta & CSR_INT_BIT_WAKEUP) {
1350 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1351 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1352 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1353 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1354
1355 priv->isr_stats.wakeup++;
1356
1357 handled |= CSR_INT_BIT_WAKEUP;
1358 }
1359
1360 /* All uCode command responses, including Tx command responses,
1361 * Rx "responses" (frame-received notification), and other
1362 * notifications from uCode come through here*/
1363 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1364 CSR_INT_BIT_RX_PERIODIC)) {
1365 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1366 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1367 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1368 iwl_write32(priv, CSR_FH_INT_STATUS,
1369 CSR49_FH_INT_RX_MASK);
1370 }
1371 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1372 handled |= CSR_INT_BIT_RX_PERIODIC;
1373 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1374 }
1375 /* Sending RX interrupt require many steps to be done in the
1376 * the device:
1377 * 1- write interrupt to current index in ICT table.
1378 * 2- dma RX frame.
1379 * 3- update RX shared data to indicate last write index.
1380 * 4- send interrupt.
1381 * This could lead to RX race, driver could receive RX interrupt
1382 * but the shared data changes does not reflect this;
1383 * periodic interrupt will detect any dangling Rx activity.
1384 */
1385
1386 /* Disable periodic interrupt; we use it as just a one-shot. */
1387 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1388 CSR_INT_PERIODIC_DIS);
1389 iwl_rx_handle(priv);
1390
1391 /*
1392 * Enable periodic interrupt in 8 msec only if we received
1393 * real RX interrupt (instead of just periodic int), to catch
1394 * any dangling Rx interrupt. If it was just the periodic
1395 * interrupt, there was no dangling Rx activity, and no need
1396 * to extend the periodic interrupt; one-shot is enough.
1397 */
1398 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1399 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1400 CSR_INT_PERIODIC_ENA);
1401
1402 priv->isr_stats.rx++;
1403 }
1404
1405 /* This "Tx" DMA channel is used only for loading uCode */
1406 if (inta & CSR_INT_BIT_FH_TX) {
1407 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1408 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1409 priv->isr_stats.tx++;
1410 handled |= CSR_INT_BIT_FH_TX;
1411 /* Wake up uCode load routine, now that load is complete */
1412 priv->ucode_write_complete = 1;
1413 wake_up_interruptible(&priv->wait_command_queue);
1414 }
1415
1416 if (inta & ~handled) {
1417 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1418 priv->isr_stats.unhandled++;
1419 }
1420
1421 if (inta & ~(priv->inta_mask)) {
1422 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1423 inta & ~priv->inta_mask);
1424 }
1425
1426 /* Re-enable all interrupts */
1427 /* only Re-enable if diabled by irq */
1428 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1429 iwl_enable_interrupts(priv);
1430 }
1431
1432 /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1433 #define ACK_CNT_RATIO (50)
1434 #define BA_TIMEOUT_CNT (5)
1435 #define BA_TIMEOUT_MAX (16)
1436
1437 /**
1438 * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1439 *
1440 * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1441 * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1442 * operation state.
1443 */
1444 bool iwl_good_ack_health(struct iwl_priv *priv,
1445 struct iwl_rx_packet *pkt)
1446 {
1447 bool rc = true;
1448 int actual_ack_cnt_delta, expected_ack_cnt_delta;
1449 int ba_timeout_delta;
1450
1451 actual_ack_cnt_delta =
1452 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
1453 le32_to_cpu(priv->statistics.tx.actual_ack_cnt);
1454 expected_ack_cnt_delta =
1455 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
1456 le32_to_cpu(priv->statistics.tx.expected_ack_cnt);
1457 ba_timeout_delta =
1458 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
1459 le32_to_cpu(priv->statistics.tx.agg.ba_timeout);
1460 if ((priv->_agn.agg_tids_count > 0) &&
1461 (expected_ack_cnt_delta > 0) &&
1462 (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1463 < ACK_CNT_RATIO) &&
1464 (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1465 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1466 " expected_ack_cnt = %d\n",
1467 actual_ack_cnt_delta, expected_ack_cnt_delta);
1468
1469 #ifdef CONFIG_IWLWIFI_DEBUG
1470 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
1471 priv->delta_statistics.tx.rx_detected_cnt);
1472 IWL_DEBUG_RADIO(priv,
1473 "ack_or_ba_timeout_collision delta = %d\n",
1474 priv->delta_statistics.tx.
1475 ack_or_ba_timeout_collision);
1476 #endif
1477 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1478 ba_timeout_delta);
1479 if (!actual_ack_cnt_delta &&
1480 (ba_timeout_delta >= BA_TIMEOUT_MAX))
1481 rc = false;
1482 }
1483 return rc;
1484 }
1485
1486
1487 /******************************************************************************
1488 *
1489 * uCode download functions
1490 *
1491 ******************************************************************************/
1492
1493 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1494 {
1495 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1496 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1497 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1498 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1499 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1500 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1501 }
1502
1503 static void iwl_nic_start(struct iwl_priv *priv)
1504 {
1505 /* Remove all resets to allow NIC to operate */
1506 iwl_write32(priv, CSR_RESET, 0);
1507 }
1508
1509
1510 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1511 static int iwl_mac_setup_register(struct iwl_priv *priv);
1512
1513 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1514 {
1515 const char *name_pre = priv->cfg->fw_name_pre;
1516
1517 if (first)
1518 priv->fw_index = priv->cfg->ucode_api_max;
1519 else
1520 priv->fw_index--;
1521
1522 if (priv->fw_index < priv->cfg->ucode_api_min) {
1523 IWL_ERR(priv, "no suitable firmware found!\n");
1524 return -ENOENT;
1525 }
1526
1527 sprintf(priv->firmware_name, "%s%d%s",
1528 name_pre, priv->fw_index, ".ucode");
1529
1530 IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
1531 priv->firmware_name);
1532
1533 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1534 &priv->pci_dev->dev, GFP_KERNEL, priv,
1535 iwl_ucode_callback);
1536 }
1537
1538 /**
1539 * iwl_ucode_callback - callback when firmware was loaded
1540 *
1541 * If loaded successfully, copies the firmware into buffers
1542 * for the card to fetch (via DMA).
1543 */
1544 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1545 {
1546 struct iwl_priv *priv = context;
1547 struct iwl_ucode_header *ucode;
1548 const unsigned int api_max = priv->cfg->ucode_api_max;
1549 const unsigned int api_min = priv->cfg->ucode_api_min;
1550 u8 *src;
1551 size_t len;
1552 u32 api_ver, build;
1553 u32 inst_size, data_size, init_size, init_data_size, boot_size;
1554 int err;
1555 u16 eeprom_ver;
1556
1557 if (!ucode_raw) {
1558 IWL_ERR(priv, "request for firmware file '%s' failed.\n",
1559 priv->firmware_name);
1560 goto try_again;
1561 }
1562
1563 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1564 priv->firmware_name, ucode_raw->size);
1565
1566 /* Make sure that we got at least the v1 header! */
1567 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
1568 IWL_ERR(priv, "File size way too small!\n");
1569 goto try_again;
1570 }
1571
1572 /* Data from ucode file: header followed by uCode images */
1573 ucode = (struct iwl_ucode_header *)ucode_raw->data;
1574
1575 priv->ucode_ver = le32_to_cpu(ucode->ver);
1576 api_ver = IWL_UCODE_API(priv->ucode_ver);
1577 build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
1578 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
1579 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
1580 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
1581 init_data_size =
1582 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
1583 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
1584 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
1585
1586 /* api_ver should match the api version forming part of the
1587 * firmware filename ... but we don't check for that and only rely
1588 * on the API version read from firmware header from here on forward */
1589
1590 if (api_ver < api_min || api_ver > api_max) {
1591 IWL_ERR(priv, "Driver unable to support your firmware API. "
1592 "Driver supports v%u, firmware is v%u.\n",
1593 api_max, api_ver);
1594 goto try_again;
1595 }
1596
1597 if (api_ver != api_max)
1598 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
1599 "got v%u. New firmware can be obtained "
1600 "from http://www.intellinuxwireless.org.\n",
1601 api_max, api_ver);
1602
1603 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1604 IWL_UCODE_MAJOR(priv->ucode_ver),
1605 IWL_UCODE_MINOR(priv->ucode_ver),
1606 IWL_UCODE_API(priv->ucode_ver),
1607 IWL_UCODE_SERIAL(priv->ucode_ver));
1608
1609 snprintf(priv->hw->wiphy->fw_version,
1610 sizeof(priv->hw->wiphy->fw_version),
1611 "%u.%u.%u.%u",
1612 IWL_UCODE_MAJOR(priv->ucode_ver),
1613 IWL_UCODE_MINOR(priv->ucode_ver),
1614 IWL_UCODE_API(priv->ucode_ver),
1615 IWL_UCODE_SERIAL(priv->ucode_ver));
1616
1617 if (build)
1618 IWL_DEBUG_INFO(priv, "Build %u\n", build);
1619
1620 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
1621 IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
1622 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
1623 ? "OTP" : "EEPROM", eeprom_ver);
1624
1625 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1626 priv->ucode_ver);
1627 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
1628 inst_size);
1629 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
1630 data_size);
1631 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
1632 init_size);
1633 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
1634 init_data_size);
1635 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
1636 boot_size);
1637
1638 /*
1639 * For any of the failures below (before allocating pci memory)
1640 * we will try to load a version with a smaller API -- maybe the
1641 * user just got a corrupted version of the latest API.
1642 */
1643
1644 /* Verify size of file vs. image size info in file's header */
1645 if (ucode_raw->size !=
1646 priv->cfg->ops->ucode->get_header_size(api_ver) +
1647 inst_size + data_size + init_size +
1648 init_data_size + boot_size) {
1649
1650 IWL_DEBUG_INFO(priv,
1651 "uCode file size %d does not match expected size\n",
1652 (int)ucode_raw->size);
1653 goto try_again;
1654 }
1655
1656 /* Verify that uCode images will fit in card's SRAM */
1657 if (inst_size > priv->hw_params.max_inst_size) {
1658 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
1659 inst_size);
1660 goto try_again;
1661 }
1662
1663 if (data_size > priv->hw_params.max_data_size) {
1664 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
1665 data_size);
1666 goto try_again;
1667 }
1668 if (init_size > priv->hw_params.max_inst_size) {
1669 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1670 init_size);
1671 goto try_again;
1672 }
1673 if (init_data_size > priv->hw_params.max_data_size) {
1674 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
1675 init_data_size);
1676 goto try_again;
1677 }
1678 if (boot_size > priv->hw_params.max_bsm_size) {
1679 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1680 boot_size);
1681 goto try_again;
1682 }
1683
1684 /* Allocate ucode buffers for card's bus-master loading ... */
1685
1686 /* Runtime instructions and 2 copies of data:
1687 * 1) unmodified from disk
1688 * 2) backup cache for save/restore during power-downs */
1689 priv->ucode_code.len = inst_size;
1690 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
1691
1692 priv->ucode_data.len = data_size;
1693 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
1694
1695 priv->ucode_data_backup.len = data_size;
1696 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1697
1698 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1699 !priv->ucode_data_backup.v_addr)
1700 goto err_pci_alloc;
1701
1702 /* Initialization instructions and data */
1703 if (init_size && init_data_size) {
1704 priv->ucode_init.len = init_size;
1705 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
1706
1707 priv->ucode_init_data.len = init_data_size;
1708 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1709
1710 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1711 goto err_pci_alloc;
1712 }
1713
1714 /* Bootstrap (instructions only, no data) */
1715 if (boot_size) {
1716 priv->ucode_boot.len = boot_size;
1717 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
1718
1719 if (!priv->ucode_boot.v_addr)
1720 goto err_pci_alloc;
1721 }
1722
1723 /* Copy images into buffers for card's bus-master reads ... */
1724
1725 /* Runtime instructions (first block of data in file) */
1726 len = inst_size;
1727 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
1728 memcpy(priv->ucode_code.v_addr, src, len);
1729 src += len;
1730
1731 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
1732 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1733
1734 /* Runtime data (2nd block)
1735 * NOTE: Copy into backup buffer will be done in iwl_up() */
1736 len = data_size;
1737 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
1738 memcpy(priv->ucode_data.v_addr, src, len);
1739 memcpy(priv->ucode_data_backup.v_addr, src, len);
1740 src += len;
1741
1742 /* Initialization instructions (3rd block) */
1743 if (init_size) {
1744 len = init_size;
1745 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
1746 len);
1747 memcpy(priv->ucode_init.v_addr, src, len);
1748 src += len;
1749 }
1750
1751 /* Initialization data (4th block) */
1752 if (init_data_size) {
1753 len = init_data_size;
1754 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
1755 len);
1756 memcpy(priv->ucode_init_data.v_addr, src, len);
1757 src += len;
1758 }
1759
1760 /* Bootstrap instructions (5th block) */
1761 len = boot_size;
1762 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
1763 memcpy(priv->ucode_boot.v_addr, src, len);
1764
1765 /**************************************************
1766 * This is still part of probe() in a sense...
1767 *
1768 * 9. Setup and register with mac80211 and debugfs
1769 **************************************************/
1770 err = iwl_mac_setup_register(priv);
1771 if (err)
1772 goto out_unbind;
1773
1774 err = iwl_dbgfs_register(priv, DRV_NAME);
1775 if (err)
1776 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1777
1778 /* We have our copies now, allow OS release its copies */
1779 release_firmware(ucode_raw);
1780 return;
1781
1782 try_again:
1783 /* try next, if any */
1784 if (iwl_request_firmware(priv, false))
1785 goto out_unbind;
1786 release_firmware(ucode_raw);
1787 return;
1788
1789 err_pci_alloc:
1790 IWL_ERR(priv, "failed to allocate pci memory\n");
1791 iwl_dealloc_ucode_pci(priv);
1792 out_unbind:
1793 device_release_driver(&priv->pci_dev->dev);
1794 release_firmware(ucode_raw);
1795 }
1796
1797 static const char *desc_lookup_text[] = {
1798 "OK",
1799 "FAIL",
1800 "BAD_PARAM",
1801 "BAD_CHECKSUM",
1802 "NMI_INTERRUPT_WDG",
1803 "SYSASSERT",
1804 "FATAL_ERROR",
1805 "BAD_COMMAND",
1806 "HW_ERROR_TUNE_LOCK",
1807 "HW_ERROR_TEMPERATURE",
1808 "ILLEGAL_CHAN_FREQ",
1809 "VCC_NOT_STABLE",
1810 "FH_ERROR",
1811 "NMI_INTERRUPT_HOST",
1812 "NMI_INTERRUPT_ACTION_PT",
1813 "NMI_INTERRUPT_UNKNOWN",
1814 "UCODE_VERSION_MISMATCH",
1815 "HW_ERROR_ABS_LOCK",
1816 "HW_ERROR_CAL_LOCK_FAIL",
1817 "NMI_INTERRUPT_INST_ACTION_PT",
1818 "NMI_INTERRUPT_DATA_ACTION_PT",
1819 "NMI_TRM_HW_ER",
1820 "NMI_INTERRUPT_TRM",
1821 "NMI_INTERRUPT_BREAK_POINT"
1822 "DEBUG_0",
1823 "DEBUG_1",
1824 "DEBUG_2",
1825 "DEBUG_3",
1826 "ADVANCED SYSASSERT"
1827 };
1828
1829 static const char *desc_lookup(int i)
1830 {
1831 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1832
1833 if (i < 0 || i > max)
1834 i = max;
1835
1836 return desc_lookup_text[i];
1837 }
1838
1839 #define ERROR_START_OFFSET (1 * sizeof(u32))
1840 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1841
1842 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1843 {
1844 u32 data2, line;
1845 u32 desc, time, count, base, data1;
1846 u32 blink1, blink2, ilink1, ilink2;
1847 u32 pc, hcmd;
1848
1849 if (priv->ucode_type == UCODE_INIT)
1850 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1851 else
1852 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1853
1854 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1855 IWL_ERR(priv,
1856 "Not valid error log pointer 0x%08X for %s uCode\n",
1857 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
1858 return;
1859 }
1860
1861 count = iwl_read_targ_mem(priv, base);
1862
1863 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1864 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1865 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1866 priv->status, count);
1867 }
1868
1869 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1870 pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
1871 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1872 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1873 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1874 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1875 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1876 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1877 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1878 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1879 hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
1880
1881 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1882 blink1, blink2, ilink1, ilink2);
1883
1884 IWL_ERR(priv, "Desc Time "
1885 "data1 data2 line\n");
1886 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
1887 desc_lookup(desc), desc, time, data1, data2, line);
1888 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
1889 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
1890 pc, blink1, blink2, ilink1, ilink2, hcmd);
1891 }
1892
1893 #define EVENT_START_OFFSET (4 * sizeof(u32))
1894
1895 /**
1896 * iwl_print_event_log - Dump error event log to syslog
1897 *
1898 */
1899 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1900 u32 num_events, u32 mode,
1901 int pos, char **buf, size_t bufsz)
1902 {
1903 u32 i;
1904 u32 base; /* SRAM byte address of event log header */
1905 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1906 u32 ptr; /* SRAM byte address of log data */
1907 u32 ev, time, data; /* event log data */
1908 unsigned long reg_flags;
1909
1910 if (num_events == 0)
1911 return pos;
1912 if (priv->ucode_type == UCODE_INIT)
1913 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1914 else
1915 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1916
1917 if (mode == 0)
1918 event_size = 2 * sizeof(u32);
1919 else
1920 event_size = 3 * sizeof(u32);
1921
1922 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1923
1924 /* Make sure device is powered up for SRAM reads */
1925 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1926 iwl_grab_nic_access(priv);
1927
1928 /* Set starting address; reads will auto-increment */
1929 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1930 rmb();
1931
1932 /* "time" is actually "data" for mode 0 (no timestamp).
1933 * place event id # at far right for easier visual parsing. */
1934 for (i = 0; i < num_events; i++) {
1935 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1936 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1937 if (mode == 0) {
1938 /* data, ev */
1939 if (bufsz) {
1940 pos += scnprintf(*buf + pos, bufsz - pos,
1941 "EVT_LOG:0x%08x:%04u\n",
1942 time, ev);
1943 } else {
1944 trace_iwlwifi_dev_ucode_event(priv, 0,
1945 time, ev);
1946 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
1947 time, ev);
1948 }
1949 } else {
1950 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1951 if (bufsz) {
1952 pos += scnprintf(*buf + pos, bufsz - pos,
1953 "EVT_LOGT:%010u:0x%08x:%04u\n",
1954 time, data, ev);
1955 } else {
1956 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
1957 time, data, ev);
1958 trace_iwlwifi_dev_ucode_event(priv, time,
1959 data, ev);
1960 }
1961 }
1962 }
1963
1964 /* Allow device to power down */
1965 iwl_release_nic_access(priv);
1966 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
1967 return pos;
1968 }
1969
1970 /**
1971 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
1972 */
1973 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
1974 u32 num_wraps, u32 next_entry,
1975 u32 size, u32 mode,
1976 int pos, char **buf, size_t bufsz)
1977 {
1978 /*
1979 * display the newest DEFAULT_LOG_ENTRIES entries
1980 * i.e the entries just before the next ont that uCode would fill.
1981 */
1982 if (num_wraps) {
1983 if (next_entry < size) {
1984 pos = iwl_print_event_log(priv,
1985 capacity - (size - next_entry),
1986 size - next_entry, mode,
1987 pos, buf, bufsz);
1988 pos = iwl_print_event_log(priv, 0,
1989 next_entry, mode,
1990 pos, buf, bufsz);
1991 } else
1992 pos = iwl_print_event_log(priv, next_entry - size,
1993 size, mode, pos, buf, bufsz);
1994 } else {
1995 if (next_entry < size) {
1996 pos = iwl_print_event_log(priv, 0, next_entry,
1997 mode, pos, buf, bufsz);
1998 } else {
1999 pos = iwl_print_event_log(priv, next_entry - size,
2000 size, mode, pos, buf, bufsz);
2001 }
2002 }
2003 return pos;
2004 }
2005
2006 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2007
2008 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2009 char **buf, bool display)
2010 {
2011 u32 base; /* SRAM byte address of event log header */
2012 u32 capacity; /* event log capacity in # entries */
2013 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2014 u32 num_wraps; /* # times uCode wrapped to top of log */
2015 u32 next_entry; /* index of next entry to be written by uCode */
2016 u32 size; /* # entries that we'll print */
2017 int pos = 0;
2018 size_t bufsz = 0;
2019
2020 if (priv->ucode_type == UCODE_INIT)
2021 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2022 else
2023 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2024
2025 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2026 IWL_ERR(priv,
2027 "Invalid event log pointer 0x%08X for %s uCode\n",
2028 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2029 return -EINVAL;
2030 }
2031
2032 /* event log header */
2033 capacity = iwl_read_targ_mem(priv, base);
2034 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2035 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2036 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2037
2038 if (capacity > priv->cfg->max_event_log_size) {
2039 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2040 capacity, priv->cfg->max_event_log_size);
2041 capacity = priv->cfg->max_event_log_size;
2042 }
2043
2044 if (next_entry > priv->cfg->max_event_log_size) {
2045 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2046 next_entry, priv->cfg->max_event_log_size);
2047 next_entry = priv->cfg->max_event_log_size;
2048 }
2049
2050 size = num_wraps ? capacity : next_entry;
2051
2052 /* bail out if nothing in log */
2053 if (size == 0) {
2054 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2055 return pos;
2056 }
2057
2058 #ifdef CONFIG_IWLWIFI_DEBUG
2059 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2060 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2061 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2062 #else
2063 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2064 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2065 #endif
2066 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2067 size);
2068
2069 #ifdef CONFIG_IWLWIFI_DEBUG
2070 if (display) {
2071 if (full_log)
2072 bufsz = capacity * 48;
2073 else
2074 bufsz = size * 48;
2075 *buf = kmalloc(bufsz, GFP_KERNEL);
2076 if (!*buf)
2077 return -ENOMEM;
2078 }
2079 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2080 /*
2081 * if uCode has wrapped back to top of log,
2082 * start at the oldest entry,
2083 * i.e the next one that uCode would fill.
2084 */
2085 if (num_wraps)
2086 pos = iwl_print_event_log(priv, next_entry,
2087 capacity - next_entry, mode,
2088 pos, buf, bufsz);
2089 /* (then/else) start at top of log */
2090 pos = iwl_print_event_log(priv, 0,
2091 next_entry, mode, pos, buf, bufsz);
2092 } else
2093 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2094 next_entry, size, mode,
2095 pos, buf, bufsz);
2096 #else
2097 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2098 next_entry, size, mode,
2099 pos, buf, bufsz);
2100 #endif
2101 return pos;
2102 }
2103
2104 /**
2105 * iwl_alive_start - called after REPLY_ALIVE notification received
2106 * from protocol/runtime uCode (initialization uCode's
2107 * Alive gets handled by iwl_init_alive_start()).
2108 */
2109 static void iwl_alive_start(struct iwl_priv *priv)
2110 {
2111 int ret = 0;
2112
2113 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2114
2115 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2116 /* We had an error bringing up the hardware, so take it
2117 * all the way back down so we can try again */
2118 IWL_DEBUG_INFO(priv, "Alive failed.\n");
2119 goto restart;
2120 }
2121
2122 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2123 * This is a paranoid check, because we would not have gotten the
2124 * "runtime" alive if code weren't properly loaded. */
2125 if (iwl_verify_ucode(priv)) {
2126 /* Runtime instruction load was bad;
2127 * take it all the way back down so we can try again */
2128 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2129 goto restart;
2130 }
2131
2132 ret = priv->cfg->ops->lib->alive_notify(priv);
2133 if (ret) {
2134 IWL_WARN(priv,
2135 "Could not complete ALIVE transition [ntf]: %d\n", ret);
2136 goto restart;
2137 }
2138
2139 /* After the ALIVE response, we can send host commands to the uCode */
2140 set_bit(STATUS_ALIVE, &priv->status);
2141
2142 if (priv->cfg->ops->lib->recover_from_tx_stall) {
2143 /* Enable timer to monitor the driver queues */
2144 mod_timer(&priv->monitor_recover,
2145 jiffies +
2146 msecs_to_jiffies(priv->cfg->monitor_recover_period));
2147 }
2148
2149 if (iwl_is_rfkill(priv))
2150 return;
2151
2152 ieee80211_wake_queues(priv->hw);
2153
2154 priv->active_rate = IWL_RATES_MASK;
2155
2156 /* Configure Tx antenna selection based on H/W config */
2157 if (priv->cfg->ops->hcmd->set_tx_ant)
2158 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2159
2160 if (iwl_is_associated(priv)) {
2161 struct iwl_rxon_cmd *active_rxon =
2162 (struct iwl_rxon_cmd *)&priv->active_rxon;
2163 /* apply any changes in staging */
2164 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2165 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2166 } else {
2167 /* Initialize our rx_config data */
2168 iwl_connection_init_rx_config(priv, priv->iw_mode);
2169
2170 if (priv->cfg->ops->hcmd->set_rxon_chain)
2171 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2172
2173 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2174 }
2175
2176 /* Configure Bluetooth device coexistence support */
2177 iwl_send_bt_config(priv);
2178
2179 iwl_reset_run_time_calib(priv);
2180
2181 /* Configure the adapter for unassociated operation */
2182 iwlcore_commit_rxon(priv);
2183
2184 /* At this point, the NIC is initialized and operational */
2185 iwl_rf_kill_ct_config(priv);
2186
2187 iwl_leds_init(priv);
2188
2189 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2190 set_bit(STATUS_READY, &priv->status);
2191 wake_up_interruptible(&priv->wait_command_queue);
2192
2193 iwl_power_update_mode(priv, true);
2194 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2195
2196
2197 return;
2198
2199 restart:
2200 queue_work(priv->workqueue, &priv->restart);
2201 }
2202
2203 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2204
2205 static void __iwl_down(struct iwl_priv *priv)
2206 {
2207 unsigned long flags;
2208 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2209
2210 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2211
2212 if (!exit_pending)
2213 set_bit(STATUS_EXIT_PENDING, &priv->status);
2214
2215 iwl_clear_ucode_stations(priv, true);
2216
2217 /* Unblock any waiting calls */
2218 wake_up_interruptible_all(&priv->wait_command_queue);
2219
2220 /* Wipe out the EXIT_PENDING status bit if we are not actually
2221 * exiting the module */
2222 if (!exit_pending)
2223 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2224
2225 /* stop and reset the on-board processor */
2226 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2227
2228 /* tell the device to stop sending interrupts */
2229 spin_lock_irqsave(&priv->lock, flags);
2230 iwl_disable_interrupts(priv);
2231 spin_unlock_irqrestore(&priv->lock, flags);
2232 iwl_synchronize_irq(priv);
2233
2234 if (priv->mac80211_registered)
2235 ieee80211_stop_queues(priv->hw);
2236
2237 /* If we have not previously called iwl_init() then
2238 * clear all bits but the RF Kill bit and return */
2239 if (!iwl_is_init(priv)) {
2240 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2241 STATUS_RF_KILL_HW |
2242 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2243 STATUS_GEO_CONFIGURED |
2244 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2245 STATUS_EXIT_PENDING;
2246 goto exit;
2247 }
2248
2249 /* ...otherwise clear out all the status bits but the RF Kill
2250 * bit and continue taking the NIC down. */
2251 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2252 STATUS_RF_KILL_HW |
2253 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2254 STATUS_GEO_CONFIGURED |
2255 test_bit(STATUS_FW_ERROR, &priv->status) <<
2256 STATUS_FW_ERROR |
2257 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2258 STATUS_EXIT_PENDING;
2259
2260 /* device going down, Stop using ICT table */
2261 iwl_disable_ict(priv);
2262
2263 iwlagn_txq_ctx_stop(priv);
2264 iwlagn_rxq_stop(priv);
2265
2266 /* Power-down device's busmaster DMA clocks */
2267 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2268 udelay(5);
2269
2270 /* Make sure (redundant) we've released our request to stay awake */
2271 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2272
2273 /* Stop the device, and put it in low power state */
2274 priv->cfg->ops->lib->apm_ops.stop(priv);
2275
2276 exit:
2277 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2278
2279 if (priv->ibss_beacon)
2280 dev_kfree_skb(priv->ibss_beacon);
2281 priv->ibss_beacon = NULL;
2282
2283 /* clear out any free frames */
2284 iwl_clear_free_frames(priv);
2285 }
2286
2287 static void iwl_down(struct iwl_priv *priv)
2288 {
2289 mutex_lock(&priv->mutex);
2290 __iwl_down(priv);
2291 mutex_unlock(&priv->mutex);
2292
2293 iwl_cancel_deferred_work(priv);
2294 }
2295
2296 #define HW_READY_TIMEOUT (50)
2297
2298 static int iwl_set_hw_ready(struct iwl_priv *priv)
2299 {
2300 int ret = 0;
2301
2302 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2303 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2304
2305 /* See if we got it */
2306 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2307 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2308 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2309 HW_READY_TIMEOUT);
2310 if (ret != -ETIMEDOUT)
2311 priv->hw_ready = true;
2312 else
2313 priv->hw_ready = false;
2314
2315 IWL_DEBUG_INFO(priv, "hardware %s\n",
2316 (priv->hw_ready == 1) ? "ready" : "not ready");
2317 return ret;
2318 }
2319
2320 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2321 {
2322 int ret = 0;
2323
2324 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2325
2326 ret = iwl_set_hw_ready(priv);
2327 if (priv->hw_ready)
2328 return ret;
2329
2330 /* If HW is not ready, prepare the conditions to check again */
2331 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2332 CSR_HW_IF_CONFIG_REG_PREPARE);
2333
2334 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2335 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2336 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2337
2338 /* HW should be ready by now, check again. */
2339 if (ret != -ETIMEDOUT)
2340 iwl_set_hw_ready(priv);
2341
2342 return ret;
2343 }
2344
2345 #define MAX_HW_RESTARTS 5
2346
2347 static int __iwl_up(struct iwl_priv *priv)
2348 {
2349 int i;
2350 int ret;
2351
2352 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2353 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2354 return -EIO;
2355 }
2356
2357 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2358 IWL_ERR(priv, "ucode not available for device bringup\n");
2359 return -EIO;
2360 }
2361
2362 iwl_prepare_card_hw(priv);
2363
2364 if (!priv->hw_ready) {
2365 IWL_WARN(priv, "Exit HW not ready\n");
2366 return -EIO;
2367 }
2368
2369 /* If platform's RF_KILL switch is NOT set to KILL */
2370 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2371 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2372 else
2373 set_bit(STATUS_RF_KILL_HW, &priv->status);
2374
2375 if (iwl_is_rfkill(priv)) {
2376 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2377
2378 iwl_enable_interrupts(priv);
2379 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2380 return 0;
2381 }
2382
2383 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2384
2385 ret = iwlagn_hw_nic_init(priv);
2386 if (ret) {
2387 IWL_ERR(priv, "Unable to init nic\n");
2388 return ret;
2389 }
2390
2391 /* make sure rfkill handshake bits are cleared */
2392 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2393 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2394 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2395
2396 /* clear (again), then enable host interrupts */
2397 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2398 iwl_enable_interrupts(priv);
2399
2400 /* really make sure rfkill handshake bits are cleared */
2401 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2402 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2403
2404 /* Copy original ucode data image from disk into backup cache.
2405 * This will be used to initialize the on-board processor's
2406 * data SRAM for a clean start when the runtime program first loads. */
2407 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
2408 priv->ucode_data.len);
2409
2410 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2411
2412 /* load bootstrap state machine,
2413 * load bootstrap program into processor's memory,
2414 * prepare to load the "initialize" uCode */
2415 ret = priv->cfg->ops->lib->load_ucode(priv);
2416
2417 if (ret) {
2418 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2419 ret);
2420 continue;
2421 }
2422
2423 /* start card; "initialize" will load runtime ucode */
2424 iwl_nic_start(priv);
2425
2426 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
2427
2428 return 0;
2429 }
2430
2431 set_bit(STATUS_EXIT_PENDING, &priv->status);
2432 __iwl_down(priv);
2433 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2434
2435 /* tried to restart and config the device for as long as our
2436 * patience could withstand */
2437 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
2438 return -EIO;
2439 }
2440
2441
2442 /*****************************************************************************
2443 *
2444 * Workqueue callbacks
2445 *
2446 *****************************************************************************/
2447
2448 static void iwl_bg_init_alive_start(struct work_struct *data)
2449 {
2450 struct iwl_priv *priv =
2451 container_of(data, struct iwl_priv, init_alive_start.work);
2452
2453 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2454 return;
2455
2456 mutex_lock(&priv->mutex);
2457 priv->cfg->ops->lib->init_alive_start(priv);
2458 mutex_unlock(&priv->mutex);
2459 }
2460
2461 static void iwl_bg_alive_start(struct work_struct *data)
2462 {
2463 struct iwl_priv *priv =
2464 container_of(data, struct iwl_priv, alive_start.work);
2465
2466 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2467 return;
2468
2469 /* enable dram interrupt */
2470 iwl_reset_ict(priv);
2471
2472 mutex_lock(&priv->mutex);
2473 iwl_alive_start(priv);
2474 mutex_unlock(&priv->mutex);
2475 }
2476
2477 static void iwl_bg_run_time_calib_work(struct work_struct *work)
2478 {
2479 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2480 run_time_calib_work);
2481
2482 mutex_lock(&priv->mutex);
2483
2484 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2485 test_bit(STATUS_SCANNING, &priv->status)) {
2486 mutex_unlock(&priv->mutex);
2487 return;
2488 }
2489
2490 if (priv->start_calib) {
2491 iwl_chain_noise_calibration(priv, &priv->statistics);
2492
2493 iwl_sensitivity_calibration(priv, &priv->statistics);
2494 }
2495
2496 mutex_unlock(&priv->mutex);
2497 return;
2498 }
2499
2500 static void iwl_bg_restart(struct work_struct *data)
2501 {
2502 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2503
2504 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2505 return;
2506
2507 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2508 mutex_lock(&priv->mutex);
2509 priv->vif = NULL;
2510 priv->is_open = 0;
2511 mutex_unlock(&priv->mutex);
2512 iwl_down(priv);
2513 ieee80211_restart_hw(priv->hw);
2514 } else {
2515 iwl_down(priv);
2516
2517 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2518 return;
2519
2520 mutex_lock(&priv->mutex);
2521 __iwl_up(priv);
2522 mutex_unlock(&priv->mutex);
2523 }
2524 }
2525
2526 static void iwl_bg_rx_replenish(struct work_struct *data)
2527 {
2528 struct iwl_priv *priv =
2529 container_of(data, struct iwl_priv, rx_replenish);
2530
2531 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2532 return;
2533
2534 mutex_lock(&priv->mutex);
2535 iwlagn_rx_replenish(priv);
2536 mutex_unlock(&priv->mutex);
2537 }
2538
2539 #define IWL_DELAY_NEXT_SCAN (HZ*2)
2540
2541 void iwl_post_associate(struct iwl_priv *priv)
2542 {
2543 struct ieee80211_conf *conf = NULL;
2544 int ret = 0;
2545
2546 if (priv->iw_mode == NL80211_IFTYPE_AP) {
2547 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
2548 return;
2549 }
2550
2551 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2552 return;
2553
2554
2555 if (!priv->vif || !priv->is_open)
2556 return;
2557
2558 iwl_scan_cancel_timeout(priv, 200);
2559
2560 conf = ieee80211_get_hw_conf(priv->hw);
2561
2562 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2563 iwlcore_commit_rxon(priv);
2564
2565 iwl_setup_rxon_timing(priv);
2566 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
2567 sizeof(priv->rxon_timing), &priv->rxon_timing);
2568 if (ret)
2569 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
2570 "Attempting to continue.\n");
2571
2572 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2573
2574 iwl_set_rxon_ht(priv, &priv->current_ht_config);
2575
2576 if (priv->cfg->ops->hcmd->set_rxon_chain)
2577 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2578
2579 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2580
2581 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
2582 priv->assoc_id, priv->beacon_int);
2583
2584 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2585 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2586 else
2587 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2588
2589 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2590 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2591 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2592 else
2593 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2594
2595 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
2596 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2597
2598 }
2599
2600 iwlcore_commit_rxon(priv);
2601
2602 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
2603 priv->assoc_id, priv->active_rxon.bssid_addr);
2604
2605 switch (priv->iw_mode) {
2606 case NL80211_IFTYPE_STATION:
2607 break;
2608
2609 case NL80211_IFTYPE_ADHOC:
2610
2611 /* assume default assoc id */
2612 priv->assoc_id = 1;
2613
2614 iwl_add_local_station(priv, priv->bssid, true);
2615 iwl_send_beacon_cmd(priv);
2616
2617 break;
2618
2619 default:
2620 IWL_ERR(priv, "%s Should not be called in %d mode\n",
2621 __func__, priv->iw_mode);
2622 break;
2623 }
2624
2625 /* the chain noise calibration will enabled PM upon completion
2626 * If chain noise has already been run, then we need to enable
2627 * power management here */
2628 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
2629 iwl_power_update_mode(priv, false);
2630
2631 /* Enable Rx differential gain and sensitivity calibrations */
2632 iwl_chain_noise_reset(priv);
2633 priv->start_calib = 1;
2634
2635 }
2636
2637 /*****************************************************************************
2638 *
2639 * mac80211 entry point functions
2640 *
2641 *****************************************************************************/
2642
2643 #define UCODE_READY_TIMEOUT (4 * HZ)
2644
2645 /*
2646 * Not a mac80211 entry point function, but it fits in with all the
2647 * other mac80211 functions grouped here.
2648 */
2649 static int iwl_mac_setup_register(struct iwl_priv *priv)
2650 {
2651 int ret;
2652 struct ieee80211_hw *hw = priv->hw;
2653 hw->rate_control_algorithm = "iwl-agn-rs";
2654
2655 /* Tell mac80211 our characteristics */
2656 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2657 IEEE80211_HW_NOISE_DBM |
2658 IEEE80211_HW_AMPDU_AGGREGATION |
2659 IEEE80211_HW_SPECTRUM_MGMT;
2660
2661 if (!priv->cfg->broken_powersave)
2662 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2663 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2664
2665 if (priv->cfg->sku & IWL_SKU_N)
2666 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2667 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2668
2669 hw->sta_data_size = sizeof(struct iwl_station_priv);
2670 hw->wiphy->interface_modes =
2671 BIT(NL80211_IFTYPE_STATION) |
2672 BIT(NL80211_IFTYPE_ADHOC);
2673
2674 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
2675 WIPHY_FLAG_DISABLE_BEACON_HINTS;
2676
2677 /*
2678 * For now, disable PS by default because it affects
2679 * RX performance significantly.
2680 */
2681 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2682
2683 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2684 /* we create the 802.11 header and a zero-length SSID element */
2685 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
2686
2687 /* Default value; 4 EDCA QOS priorities */
2688 hw->queues = 4;
2689
2690 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2691
2692 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2693 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2694 &priv->bands[IEEE80211_BAND_2GHZ];
2695 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2696 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2697 &priv->bands[IEEE80211_BAND_5GHZ];
2698
2699 ret = ieee80211_register_hw(priv->hw);
2700 if (ret) {
2701 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2702 return ret;
2703 }
2704 priv->mac80211_registered = 1;
2705
2706 return 0;
2707 }
2708
2709
2710 static int iwl_mac_start(struct ieee80211_hw *hw)
2711 {
2712 struct iwl_priv *priv = hw->priv;
2713 int ret;
2714
2715 IWL_DEBUG_MAC80211(priv, "enter\n");
2716
2717 /* we should be verifying the device is ready to be opened */
2718 mutex_lock(&priv->mutex);
2719 ret = __iwl_up(priv);
2720 mutex_unlock(&priv->mutex);
2721
2722 if (ret)
2723 return ret;
2724
2725 if (iwl_is_rfkill(priv))
2726 goto out;
2727
2728 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
2729
2730 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
2731 * mac80211 will not be run successfully. */
2732 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2733 test_bit(STATUS_READY, &priv->status),
2734 UCODE_READY_TIMEOUT);
2735 if (!ret) {
2736 if (!test_bit(STATUS_READY, &priv->status)) {
2737 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
2738 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2739 return -ETIMEDOUT;
2740 }
2741 }
2742
2743 iwl_led_start(priv);
2744
2745 out:
2746 priv->is_open = 1;
2747 IWL_DEBUG_MAC80211(priv, "leave\n");
2748 return 0;
2749 }
2750
2751 static void iwl_mac_stop(struct ieee80211_hw *hw)
2752 {
2753 struct iwl_priv *priv = hw->priv;
2754
2755 IWL_DEBUG_MAC80211(priv, "enter\n");
2756
2757 if (!priv->is_open)
2758 return;
2759
2760 priv->is_open = 0;
2761
2762 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
2763 /* stop mac, cancel any scan request and clear
2764 * RXON_FILTER_ASSOC_MSK BIT
2765 */
2766 mutex_lock(&priv->mutex);
2767 iwl_scan_cancel_timeout(priv, 100);
2768 mutex_unlock(&priv->mutex);
2769 }
2770
2771 iwl_down(priv);
2772
2773 flush_workqueue(priv->workqueue);
2774
2775 /* enable interrupts again in order to receive rfkill changes */
2776 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2777 iwl_enable_interrupts(priv);
2778
2779 IWL_DEBUG_MAC80211(priv, "leave\n");
2780 }
2781
2782 static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2783 {
2784 struct iwl_priv *priv = hw->priv;
2785
2786 IWL_DEBUG_MACDUMP(priv, "enter\n");
2787
2788 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2789 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2790
2791 if (iwlagn_tx_skb(priv, skb))
2792 dev_kfree_skb_any(skb);
2793
2794 IWL_DEBUG_MACDUMP(priv, "leave\n");
2795 return NETDEV_TX_OK;
2796 }
2797
2798 void iwl_config_ap(struct iwl_priv *priv)
2799 {
2800 int ret = 0;
2801
2802 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2803 return;
2804
2805 /* The following should be done only at AP bring up */
2806 if (!iwl_is_associated(priv)) {
2807
2808 /* RXON - unassoc (to set timing command) */
2809 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2810 iwlcore_commit_rxon(priv);
2811
2812 /* RXON Timing */
2813 iwl_setup_rxon_timing(priv);
2814 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
2815 sizeof(priv->rxon_timing), &priv->rxon_timing);
2816 if (ret)
2817 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
2818 "Attempting to continue.\n");
2819
2820 /* AP has all antennas */
2821 priv->chain_noise_data.active_chains =
2822 priv->hw_params.valid_rx_ant;
2823 iwl_set_rxon_ht(priv, &priv->current_ht_config);
2824 if (priv->cfg->ops->hcmd->set_rxon_chain)
2825 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2826
2827 /* FIXME: what should be the assoc_id for AP? */
2828 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2829 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2830 priv->staging_rxon.flags |=
2831 RXON_FLG_SHORT_PREAMBLE_MSK;
2832 else
2833 priv->staging_rxon.flags &=
2834 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2835
2836 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2837 if (priv->assoc_capability &
2838 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2839 priv->staging_rxon.flags |=
2840 RXON_FLG_SHORT_SLOT_MSK;
2841 else
2842 priv->staging_rxon.flags &=
2843 ~RXON_FLG_SHORT_SLOT_MSK;
2844
2845 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
2846 priv->staging_rxon.flags &=
2847 ~RXON_FLG_SHORT_SLOT_MSK;
2848 }
2849 /* restore RXON assoc */
2850 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2851 iwlcore_commit_rxon(priv);
2852 iwl_add_bcast_station(priv);
2853 }
2854 iwl_send_beacon_cmd(priv);
2855
2856 /* FIXME - we need to add code here to detect a totally new
2857 * configuration, reset the AP, unassoc, rxon timing, assoc,
2858 * clear sta table, add BCAST sta... */
2859 }
2860
2861 static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
2862 struct ieee80211_vif *vif,
2863 struct ieee80211_key_conf *keyconf,
2864 struct ieee80211_sta *sta,
2865 u32 iv32, u16 *phase1key)
2866 {
2867
2868 struct iwl_priv *priv = hw->priv;
2869 IWL_DEBUG_MAC80211(priv, "enter\n");
2870
2871 iwl_update_tkip_key(priv, keyconf,
2872 sta ? sta->addr : iwl_bcast_addr,
2873 iv32, phase1key);
2874
2875 IWL_DEBUG_MAC80211(priv, "leave\n");
2876 }
2877
2878 static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2879 struct ieee80211_vif *vif,
2880 struct ieee80211_sta *sta,
2881 struct ieee80211_key_conf *key)
2882 {
2883 struct iwl_priv *priv = hw->priv;
2884 const u8 *addr;
2885 int ret;
2886 u8 sta_id;
2887 bool is_default_wep_key = false;
2888
2889 IWL_DEBUG_MAC80211(priv, "enter\n");
2890
2891 if (priv->cfg->mod_params->sw_crypto) {
2892 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
2893 return -EOPNOTSUPP;
2894 }
2895 addr = sta ? sta->addr : iwl_bcast_addr;
2896 sta_id = iwl_find_station(priv, addr);
2897 if (sta_id == IWL_INVALID_STATION) {
2898 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
2899 addr);
2900 return -EINVAL;
2901
2902 }
2903
2904 mutex_lock(&priv->mutex);
2905 iwl_scan_cancel_timeout(priv, 100);
2906
2907 /*
2908 * If we are getting WEP group key and we didn't receive any key mapping
2909 * so far, we are in legacy wep mode (group key only), otherwise we are
2910 * in 1X mode.
2911 * In legacy wep mode, we use another host command to the uCode.
2912 */
2913 if (key->alg == ALG_WEP && !sta && vif->type != NL80211_IFTYPE_AP) {
2914 if (cmd == SET_KEY)
2915 is_default_wep_key = !priv->key_mapping_key;
2916 else
2917 is_default_wep_key =
2918 (key->hw_key_idx == HW_KEY_DEFAULT);
2919 }
2920
2921 switch (cmd) {
2922 case SET_KEY:
2923 if (is_default_wep_key)
2924 ret = iwl_set_default_wep_key(priv, key);
2925 else
2926 ret = iwl_set_dynamic_key(priv, key, sta_id);
2927
2928 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
2929 break;
2930 case DISABLE_KEY:
2931 if (is_default_wep_key)
2932 ret = iwl_remove_default_wep_key(priv, key);
2933 else
2934 ret = iwl_remove_dynamic_key(priv, key, sta_id);
2935
2936 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
2937 break;
2938 default:
2939 ret = -EINVAL;
2940 }
2941
2942 mutex_unlock(&priv->mutex);
2943 IWL_DEBUG_MAC80211(priv, "leave\n");
2944
2945 return ret;
2946 }
2947
2948 static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
2949 struct ieee80211_vif *vif,
2950 enum ieee80211_ampdu_mlme_action action,
2951 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
2952 {
2953 struct iwl_priv *priv = hw->priv;
2954 int ret;
2955
2956 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
2957 sta->addr, tid);
2958
2959 if (!(priv->cfg->sku & IWL_SKU_N))
2960 return -EACCES;
2961
2962 switch (action) {
2963 case IEEE80211_AMPDU_RX_START:
2964 IWL_DEBUG_HT(priv, "start Rx\n");
2965 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
2966 case IEEE80211_AMPDU_RX_STOP:
2967 IWL_DEBUG_HT(priv, "stop Rx\n");
2968 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
2969 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2970 return 0;
2971 else
2972 return ret;
2973 case IEEE80211_AMPDU_TX_START:
2974 IWL_DEBUG_HT(priv, "start Tx\n");
2975 ret = iwlagn_tx_agg_start(priv, sta->addr, tid, ssn);
2976 if (ret == 0) {
2977 priv->_agn.agg_tids_count++;
2978 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
2979 priv->_agn.agg_tids_count);
2980 }
2981 return ret;
2982 case IEEE80211_AMPDU_TX_STOP:
2983 IWL_DEBUG_HT(priv, "stop Tx\n");
2984 ret = iwlagn_tx_agg_stop(priv, sta->addr, tid);
2985 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
2986 priv->_agn.agg_tids_count--;
2987 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
2988 priv->_agn.agg_tids_count);
2989 }
2990 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2991 return 0;
2992 else
2993 return ret;
2994 case IEEE80211_AMPDU_TX_OPERATIONAL:
2995 /* do nothing */
2996 return -EOPNOTSUPP;
2997 default:
2998 IWL_DEBUG_HT(priv, "unknown\n");
2999 return -EINVAL;
3000 break;
3001 }
3002 return 0;
3003 }
3004
3005 static int iwl_mac_get_stats(struct ieee80211_hw *hw,
3006 struct ieee80211_low_level_stats *stats)
3007 {
3008 struct iwl_priv *priv = hw->priv;
3009
3010 priv = hw->priv;
3011 IWL_DEBUG_MAC80211(priv, "enter\n");
3012 IWL_DEBUG_MAC80211(priv, "leave\n");
3013
3014 return 0;
3015 }
3016
3017 static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3018 struct ieee80211_vif *vif,
3019 enum sta_notify_cmd cmd,
3020 struct ieee80211_sta *sta)
3021 {
3022 struct iwl_priv *priv = hw->priv;
3023 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3024 int sta_id;
3025
3026 switch (cmd) {
3027 case STA_NOTIFY_SLEEP:
3028 WARN_ON(!sta_priv->client);
3029 sta_priv->asleep = true;
3030 if (atomic_read(&sta_priv->pending_frames) > 0)
3031 ieee80211_sta_block_awake(hw, sta, true);
3032 break;
3033 case STA_NOTIFY_AWAKE:
3034 WARN_ON(!sta_priv->client);
3035 if (!sta_priv->asleep)
3036 break;
3037 sta_priv->asleep = false;
3038 sta_id = iwl_find_station(priv, sta->addr);
3039 if (sta_id != IWL_INVALID_STATION)
3040 iwl_sta_modify_ps_wake(priv, sta_id);
3041 break;
3042 default:
3043 break;
3044 }
3045 }
3046
3047 static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3048 struct ieee80211_vif *vif,
3049 struct ieee80211_sta *sta)
3050 {
3051 struct iwl_priv *priv = hw->priv;
3052 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3053 bool is_ap = priv->iw_mode == NL80211_IFTYPE_STATION;
3054 int ret;
3055 u8 sta_id;
3056
3057 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3058 sta->addr);
3059
3060 atomic_set(&sta_priv->pending_frames, 0);
3061 if (vif->type == NL80211_IFTYPE_AP)
3062 sta_priv->client = true;
3063
3064 ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap,
3065 &sta_id);
3066 if (ret) {
3067 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3068 sta->addr, ret);
3069 /* Should we return success if return code is EEXIST ? */
3070 return ret;
3071 }
3072
3073 /* Initialize rate scaling */
3074 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3075 sta->addr);
3076 iwl_rs_rate_init(priv, sta, sta_id);
3077
3078 return ret;
3079 }
3080
3081 /*****************************************************************************
3082 *
3083 * sysfs attributes
3084 *
3085 *****************************************************************************/
3086
3087 #ifdef CONFIG_IWLWIFI_DEBUG
3088
3089 /*
3090 * The following adds a new attribute to the sysfs representation
3091 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
3092 * used for controlling the debug level.
3093 *
3094 * See the level definitions in iwl for details.
3095 *
3096 * The debug_level being managed using sysfs below is a per device debug
3097 * level that is used instead of the global debug level if it (the per
3098 * device debug level) is set.
3099 */
3100 static ssize_t show_debug_level(struct device *d,
3101 struct device_attribute *attr, char *buf)
3102 {
3103 struct iwl_priv *priv = dev_get_drvdata(d);
3104 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
3105 }
3106 static ssize_t store_debug_level(struct device *d,
3107 struct device_attribute *attr,
3108 const char *buf, size_t count)
3109 {
3110 struct iwl_priv *priv = dev_get_drvdata(d);
3111 unsigned long val;
3112 int ret;
3113
3114 ret = strict_strtoul(buf, 0, &val);
3115 if (ret)
3116 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
3117 else {
3118 priv->debug_level = val;
3119 if (iwl_alloc_traffic_mem(priv))
3120 IWL_ERR(priv,
3121 "Not enough memory to generate traffic log\n");
3122 }
3123 return strnlen(buf, count);
3124 }
3125
3126 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
3127 show_debug_level, store_debug_level);
3128
3129
3130 #endif /* CONFIG_IWLWIFI_DEBUG */
3131
3132
3133 static ssize_t show_temperature(struct device *d,
3134 struct device_attribute *attr, char *buf)
3135 {
3136 struct iwl_priv *priv = dev_get_drvdata(d);
3137
3138 if (!iwl_is_alive(priv))
3139 return -EAGAIN;
3140
3141 return sprintf(buf, "%d\n", priv->temperature);
3142 }
3143
3144 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
3145
3146 static ssize_t show_tx_power(struct device *d,
3147 struct device_attribute *attr, char *buf)
3148 {
3149 struct iwl_priv *priv = dev_get_drvdata(d);
3150
3151 if (!iwl_is_ready_rf(priv))
3152 return sprintf(buf, "off\n");
3153 else
3154 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
3155 }
3156
3157 static ssize_t store_tx_power(struct device *d,
3158 struct device_attribute *attr,
3159 const char *buf, size_t count)
3160 {
3161 struct iwl_priv *priv = dev_get_drvdata(d);
3162 unsigned long val;
3163 int ret;
3164
3165 ret = strict_strtoul(buf, 10, &val);
3166 if (ret)
3167 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
3168 else {
3169 ret = iwl_set_tx_power(priv, val, false);
3170 if (ret)
3171 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
3172 ret);
3173 else
3174 ret = count;
3175 }
3176 return ret;
3177 }
3178
3179 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
3180
3181 static ssize_t show_statistics(struct device *d,
3182 struct device_attribute *attr, char *buf)
3183 {
3184 struct iwl_priv *priv = dev_get_drvdata(d);
3185 u32 size = sizeof(struct iwl_notif_statistics);
3186 u32 len = 0, ofs = 0;
3187 u8 *data = (u8 *)&priv->statistics;
3188 int rc = 0;
3189
3190 if (!iwl_is_alive(priv))
3191 return -EAGAIN;
3192
3193 mutex_lock(&priv->mutex);
3194 rc = iwl_send_statistics_request(priv, CMD_SYNC, false);
3195 mutex_unlock(&priv->mutex);
3196
3197 if (rc) {
3198 len = sprintf(buf,
3199 "Error sending statistics request: 0x%08X\n", rc);
3200 return len;
3201 }
3202
3203 while (size && (PAGE_SIZE - len)) {
3204 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3205 PAGE_SIZE - len, 1);
3206 len = strlen(buf);
3207 if (PAGE_SIZE - len)
3208 buf[len++] = '\n';
3209
3210 ofs += 16;
3211 size -= min(size, 16U);
3212 }
3213
3214 return len;
3215 }
3216
3217 static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
3218
3219 static ssize_t show_rts_ht_protection(struct device *d,
3220 struct device_attribute *attr, char *buf)
3221 {
3222 struct iwl_priv *priv = dev_get_drvdata(d);
3223
3224 return sprintf(buf, "%s\n",
3225 priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
3226 }
3227
3228 static ssize_t store_rts_ht_protection(struct device *d,
3229 struct device_attribute *attr,
3230 const char *buf, size_t count)
3231 {
3232 struct iwl_priv *priv = dev_get_drvdata(d);
3233 unsigned long val;
3234 int ret;
3235
3236 ret = strict_strtoul(buf, 10, &val);
3237 if (ret)
3238 IWL_INFO(priv, "Input is not in decimal form.\n");
3239 else {
3240 if (!iwl_is_associated(priv))
3241 priv->cfg->use_rts_for_ht = val ? true : false;
3242 else
3243 IWL_ERR(priv, "Sta associated with AP - "
3244 "Change protection mechanism is not allowed\n");
3245 ret = count;
3246 }
3247 return ret;
3248 }
3249
3250 static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
3251 show_rts_ht_protection, store_rts_ht_protection);
3252
3253
3254 /*****************************************************************************
3255 *
3256 * driver setup and teardown
3257 *
3258 *****************************************************************************/
3259
3260 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3261 {
3262 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3263
3264 init_waitqueue_head(&priv->wait_command_queue);
3265
3266 INIT_WORK(&priv->restart, iwl_bg_restart);
3267 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3268 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3269 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3270 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3271 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3272
3273 iwl_setup_scan_deferred_work(priv);
3274
3275 if (priv->cfg->ops->lib->setup_deferred_work)
3276 priv->cfg->ops->lib->setup_deferred_work(priv);
3277
3278 init_timer(&priv->statistics_periodic);
3279 priv->statistics_periodic.data = (unsigned long)priv;
3280 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3281
3282 init_timer(&priv->ucode_trace);
3283 priv->ucode_trace.data = (unsigned long)priv;
3284 priv->ucode_trace.function = iwl_bg_ucode_trace;
3285
3286 if (priv->cfg->ops->lib->recover_from_tx_stall) {
3287 init_timer(&priv->monitor_recover);
3288 priv->monitor_recover.data = (unsigned long)priv;
3289 priv->monitor_recover.function =
3290 priv->cfg->ops->lib->recover_from_tx_stall;
3291 }
3292
3293 if (!priv->cfg->use_isr_legacy)
3294 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3295 iwl_irq_tasklet, (unsigned long)priv);
3296 else
3297 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3298 iwl_irq_tasklet_legacy, (unsigned long)priv);
3299 }
3300
3301 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3302 {
3303 if (priv->cfg->ops->lib->cancel_deferred_work)
3304 priv->cfg->ops->lib->cancel_deferred_work(priv);
3305
3306 cancel_delayed_work_sync(&priv->init_alive_start);
3307 cancel_delayed_work(&priv->scan_check);
3308 cancel_delayed_work(&priv->alive_start);
3309 cancel_work_sync(&priv->beacon_update);
3310 del_timer_sync(&priv->statistics_periodic);
3311 del_timer_sync(&priv->ucode_trace);
3312 if (priv->cfg->ops->lib->recover_from_tx_stall)
3313 del_timer_sync(&priv->monitor_recover);
3314 }
3315
3316 static void iwl_init_hw_rates(struct iwl_priv *priv,
3317 struct ieee80211_rate *rates)
3318 {
3319 int i;
3320
3321 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3322 rates[i].bitrate = iwl_rates[i].ieee * 5;
3323 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3324 rates[i].hw_value_short = i;
3325 rates[i].flags = 0;
3326 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3327 /*
3328 * If CCK != 1M then set short preamble rate flag.
3329 */
3330 rates[i].flags |=
3331 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3332 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3333 }
3334 }
3335 }
3336
3337 static int iwl_init_drv(struct iwl_priv *priv)
3338 {
3339 int ret;
3340
3341 priv->ibss_beacon = NULL;
3342
3343 spin_lock_init(&priv->sta_lock);
3344 spin_lock_init(&priv->hcmd_lock);
3345
3346 INIT_LIST_HEAD(&priv->free_frames);
3347
3348 mutex_init(&priv->mutex);
3349 mutex_init(&priv->sync_cmd_mutex);
3350
3351 priv->ieee_channels = NULL;
3352 priv->ieee_rates = NULL;
3353 priv->band = IEEE80211_BAND_2GHZ;
3354
3355 priv->iw_mode = NL80211_IFTYPE_STATION;
3356 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3357 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3358 priv->_agn.agg_tids_count = 0;
3359
3360 /* initialize force reset */
3361 priv->force_reset[IWL_RF_RESET].reset_duration =
3362 IWL_DELAY_NEXT_FORCE_RF_RESET;
3363 priv->force_reset[IWL_FW_RESET].reset_duration =
3364 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3365
3366 /* Choose which receivers/antennas to use */
3367 if (priv->cfg->ops->hcmd->set_rxon_chain)
3368 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3369
3370 iwl_init_scan_params(priv);
3371
3372 /* Set the tx_power_user_lmt to the lowest power level
3373 * this value will get overwritten by channel max power avg
3374 * from eeprom */
3375 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3376
3377 ret = iwl_init_channel_map(priv);
3378 if (ret) {
3379 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3380 goto err;
3381 }
3382
3383 ret = iwlcore_init_geos(priv);
3384 if (ret) {
3385 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3386 goto err_free_channel_map;
3387 }
3388 iwl_init_hw_rates(priv, priv->ieee_rates);
3389
3390 return 0;
3391
3392 err_free_channel_map:
3393 iwl_free_channel_map(priv);
3394 err:
3395 return ret;
3396 }
3397
3398 static void iwl_uninit_drv(struct iwl_priv *priv)
3399 {
3400 iwl_calib_free_results(priv);
3401 iwlcore_free_geos(priv);
3402 iwl_free_channel_map(priv);
3403 kfree(priv->scan);
3404 }
3405
3406 static struct attribute *iwl_sysfs_entries[] = {
3407 &dev_attr_statistics.attr,
3408 &dev_attr_temperature.attr,
3409 &dev_attr_tx_power.attr,
3410 &dev_attr_rts_ht_protection.attr,
3411 #ifdef CONFIG_IWLWIFI_DEBUG
3412 &dev_attr_debug_level.attr,
3413 #endif
3414 NULL
3415 };
3416
3417 static struct attribute_group iwl_attribute_group = {
3418 .name = NULL, /* put in device directory */
3419 .attrs = iwl_sysfs_entries,
3420 };
3421
3422 static struct ieee80211_ops iwl_hw_ops = {
3423 .tx = iwl_mac_tx,
3424 .start = iwl_mac_start,
3425 .stop = iwl_mac_stop,
3426 .add_interface = iwl_mac_add_interface,
3427 .remove_interface = iwl_mac_remove_interface,
3428 .config = iwl_mac_config,
3429 .configure_filter = iwl_configure_filter,
3430 .set_key = iwl_mac_set_key,
3431 .update_tkip_key = iwl_mac_update_tkip_key,
3432 .get_stats = iwl_mac_get_stats,
3433 .conf_tx = iwl_mac_conf_tx,
3434 .reset_tsf = iwl_mac_reset_tsf,
3435 .bss_info_changed = iwl_bss_info_changed,
3436 .ampdu_action = iwl_mac_ampdu_action,
3437 .hw_scan = iwl_mac_hw_scan,
3438 .sta_notify = iwl_mac_sta_notify,
3439 .sta_add = iwlagn_mac_sta_add,
3440 .sta_remove = iwl_mac_sta_remove,
3441 };
3442
3443 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3444 {
3445 int err = 0;
3446 struct iwl_priv *priv;
3447 struct ieee80211_hw *hw;
3448 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3449 unsigned long flags;
3450 u16 pci_cmd;
3451
3452 /************************
3453 * 1. Allocating HW data
3454 ************************/
3455
3456 /* Disabling hardware scan means that mac80211 will perform scans
3457 * "the hard way", rather than using device's scan. */
3458 if (cfg->mod_params->disable_hw_scan) {
3459 if (iwl_debug_level & IWL_DL_INFO)
3460 dev_printk(KERN_DEBUG, &(pdev->dev),
3461 "Disabling hw_scan\n");
3462 iwl_hw_ops.hw_scan = NULL;
3463 }
3464
3465 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
3466 if (!hw) {
3467 err = -ENOMEM;
3468 goto out;
3469 }
3470 priv = hw->priv;
3471 /* At this point both hw and priv are allocated. */
3472
3473 SET_IEEE80211_DEV(hw, &pdev->dev);
3474
3475 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
3476 priv->cfg = cfg;
3477 priv->pci_dev = pdev;
3478 priv->inta_mask = CSR_INI_SET_MASK;
3479
3480 #ifdef CONFIG_IWLWIFI_DEBUG
3481 atomic_set(&priv->restrict_refcnt, 0);
3482 #endif
3483 if (iwl_alloc_traffic_mem(priv))
3484 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
3485
3486 /**************************
3487 * 2. Initializing PCI bus
3488 **************************/
3489 if (pci_enable_device(pdev)) {
3490 err = -ENODEV;
3491 goto out_ieee80211_free_hw;
3492 }
3493
3494 pci_set_master(pdev);
3495
3496 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
3497 if (!err)
3498 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
3499 if (err) {
3500 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3501 if (!err)
3502 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3503 /* both attempts failed: */
3504 if (err) {
3505 IWL_WARN(priv, "No suitable DMA available.\n");
3506 goto out_pci_disable_device;
3507 }
3508 }
3509
3510 err = pci_request_regions(pdev, DRV_NAME);
3511 if (err)
3512 goto out_pci_disable_device;
3513
3514 pci_set_drvdata(pdev, priv);
3515
3516
3517 /***********************
3518 * 3. Read REV register
3519 ***********************/
3520 priv->hw_base = pci_iomap(pdev, 0, 0);
3521 if (!priv->hw_base) {
3522 err = -ENODEV;
3523 goto out_pci_release_regions;
3524 }
3525
3526 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
3527 (unsigned long long) pci_resource_len(pdev, 0));
3528 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
3529
3530 /* these spin locks will be used in apm_ops.init and EEPROM access
3531 * we should init now
3532 */
3533 spin_lock_init(&priv->reg_lock);
3534 spin_lock_init(&priv->lock);
3535
3536 /*
3537 * stop and reset the on-board processor just in case it is in a
3538 * strange state ... like being left stranded by a primary kernel
3539 * and this is now the kdump kernel trying to start up
3540 */
3541 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3542
3543 iwl_hw_detect(priv);
3544 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
3545 priv->cfg->name, priv->hw_rev);
3546
3547 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3548 * PCI Tx retries from interfering with C3 CPU state */
3549 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3550
3551 iwl_prepare_card_hw(priv);
3552 if (!priv->hw_ready) {
3553 IWL_WARN(priv, "Failed, HW not ready\n");
3554 goto out_iounmap;
3555 }
3556
3557 /*****************
3558 * 4. Read EEPROM
3559 *****************/
3560 /* Read the EEPROM */
3561 err = iwl_eeprom_init(priv);
3562 if (err) {
3563 IWL_ERR(priv, "Unable to init EEPROM\n");
3564 goto out_iounmap;
3565 }
3566 err = iwl_eeprom_check_version(priv);
3567 if (err)
3568 goto out_free_eeprom;
3569
3570 /* extract MAC Address */
3571 iwl_eeprom_get_mac(priv, priv->mac_addr);
3572 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
3573 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
3574
3575 /************************
3576 * 5. Setup HW constants
3577 ************************/
3578 if (iwl_set_hw_params(priv)) {
3579 IWL_ERR(priv, "failed to set hw parameters\n");
3580 goto out_free_eeprom;
3581 }
3582
3583 /*******************
3584 * 6. Setup priv
3585 *******************/
3586
3587 err = iwl_init_drv(priv);
3588 if (err)
3589 goto out_free_eeprom;
3590 /* At this point both hw and priv are initialized. */
3591
3592 /********************
3593 * 7. Setup services
3594 ********************/
3595 spin_lock_irqsave(&priv->lock, flags);
3596 iwl_disable_interrupts(priv);
3597 spin_unlock_irqrestore(&priv->lock, flags);
3598
3599 pci_enable_msi(priv->pci_dev);
3600
3601 iwl_alloc_isr_ict(priv);
3602 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
3603 IRQF_SHARED, DRV_NAME, priv);
3604 if (err) {
3605 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3606 goto out_disable_msi;
3607 }
3608 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
3609 if (err) {
3610 IWL_ERR(priv, "failed to create sysfs device attributes\n");
3611 goto out_free_irq;
3612 }
3613
3614 iwl_setup_deferred_work(priv);
3615 iwl_setup_rx_handlers(priv);
3616
3617 /*********************************************
3618 * 8. Enable interrupts and read RFKILL state
3619 *********************************************/
3620
3621 /* enable interrupts if needed: hw bug w/a */
3622 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3623 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3624 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3625 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3626 }
3627
3628 iwl_enable_interrupts(priv);
3629
3630 /* If platform's RF_KILL switch is NOT set to KILL */
3631 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3632 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3633 else
3634 set_bit(STATUS_RF_KILL_HW, &priv->status);
3635
3636 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3637 test_bit(STATUS_RF_KILL_HW, &priv->status));
3638
3639 iwl_power_initialize(priv);
3640 iwl_tt_initialize(priv);
3641
3642 err = iwl_request_firmware(priv, true);
3643 if (err)
3644 goto out_remove_sysfs;
3645
3646 return 0;
3647
3648 out_remove_sysfs:
3649 destroy_workqueue(priv->workqueue);
3650 priv->workqueue = NULL;
3651 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
3652 out_free_irq:
3653 free_irq(priv->pci_dev->irq, priv);
3654 iwl_free_isr_ict(priv);
3655 out_disable_msi:
3656 pci_disable_msi(priv->pci_dev);
3657 iwl_uninit_drv(priv);
3658 out_free_eeprom:
3659 iwl_eeprom_free(priv);
3660 out_iounmap:
3661 pci_iounmap(pdev, priv->hw_base);
3662 out_pci_release_regions:
3663 pci_set_drvdata(pdev, NULL);
3664 pci_release_regions(pdev);
3665 out_pci_disable_device:
3666 pci_disable_device(pdev);
3667 out_ieee80211_free_hw:
3668 iwl_free_traffic_mem(priv);
3669 ieee80211_free_hw(priv->hw);
3670 out:
3671 return err;
3672 }
3673
3674 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
3675 {
3676 struct iwl_priv *priv = pci_get_drvdata(pdev);
3677 unsigned long flags;
3678
3679 if (!priv)
3680 return;
3681
3682 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
3683
3684 iwl_dbgfs_unregister(priv);
3685 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
3686
3687 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3688 * to be called and iwl_down since we are removing the device
3689 * we need to set STATUS_EXIT_PENDING bit.
3690 */
3691 set_bit(STATUS_EXIT_PENDING, &priv->status);
3692 if (priv->mac80211_registered) {
3693 ieee80211_unregister_hw(priv->hw);
3694 priv->mac80211_registered = 0;
3695 } else {
3696 iwl_down(priv);
3697 }
3698
3699 /*
3700 * Make sure device is reset to low power before unloading driver.
3701 * This may be redundant with iwl_down(), but there are paths to
3702 * run iwl_down() without calling apm_ops.stop(), and there are
3703 * paths to avoid running iwl_down() at all before leaving driver.
3704 * This (inexpensive) call *makes sure* device is reset.
3705 */
3706 priv->cfg->ops->lib->apm_ops.stop(priv);
3707
3708 iwl_tt_exit(priv);
3709
3710 /* make sure we flush any pending irq or
3711 * tasklet for the driver
3712 */
3713 spin_lock_irqsave(&priv->lock, flags);
3714 iwl_disable_interrupts(priv);
3715 spin_unlock_irqrestore(&priv->lock, flags);
3716
3717 iwl_synchronize_irq(priv);
3718
3719 iwl_dealloc_ucode_pci(priv);
3720
3721 if (priv->rxq.bd)
3722 iwlagn_rx_queue_free(priv, &priv->rxq);
3723 iwlagn_hw_txq_ctx_free(priv);
3724
3725 iwl_eeprom_free(priv);
3726
3727
3728 /*netif_stop_queue(dev); */
3729 flush_workqueue(priv->workqueue);
3730
3731 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
3732 * priv->workqueue... so we can't take down the workqueue
3733 * until now... */
3734 destroy_workqueue(priv->workqueue);
3735 priv->workqueue = NULL;
3736 iwl_free_traffic_mem(priv);
3737
3738 free_irq(priv->pci_dev->irq, priv);
3739 pci_disable_msi(priv->pci_dev);
3740 pci_iounmap(pdev, priv->hw_base);
3741 pci_release_regions(pdev);
3742 pci_disable_device(pdev);
3743 pci_set_drvdata(pdev, NULL);
3744
3745 iwl_uninit_drv(priv);
3746
3747 iwl_free_isr_ict(priv);
3748
3749 if (priv->ibss_beacon)
3750 dev_kfree_skb(priv->ibss_beacon);
3751
3752 ieee80211_free_hw(priv->hw);
3753 }
3754
3755
3756 /*****************************************************************************
3757 *
3758 * driver and module entry point
3759 *
3760 *****************************************************************************/
3761
3762 /* Hardware specific file defines the PCI IDs table for that hardware module */
3763 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
3764 #ifdef CONFIG_IWL4965
3765 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3766 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
3767 #endif /* CONFIG_IWL4965 */
3768 #ifdef CONFIG_IWL5000
3769 /* 5100 Series WiFi */
3770 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
3771 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
3772 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
3773 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
3774 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
3775 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
3776 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
3777 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
3778 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
3779 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
3780 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
3781 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
3782 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
3783 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
3784 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
3785 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
3786 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
3787 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
3788 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
3789 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
3790 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
3791 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
3792 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
3793 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
3794
3795 /* 5300 Series WiFi */
3796 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
3797 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
3798 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
3799 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
3800 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
3801 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
3802 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
3803 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
3804 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
3805 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
3806 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
3807 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
3808
3809 /* 5350 Series WiFi/WiMax */
3810 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
3811 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
3812 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
3813
3814 /* 5150 Series Wifi/WiMax */
3815 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
3816 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
3817 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
3818 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
3819 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
3820 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
3821
3822 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
3823 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
3824 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
3825 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
3826
3827 /* 6x00 Series */
3828 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
3829 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
3830 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
3831 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
3832 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
3833 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
3834 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
3835 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
3836 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
3837 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
3838 {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000i_g2_2agn_cfg)},
3839
3840 /* 6x50 WiFi/WiMax Series */
3841 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
3842 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
3843 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
3844 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
3845 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
3846 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
3847
3848 /* 1000 Series WiFi */
3849 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
3850 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
3851 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
3852 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
3853 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
3854 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
3855 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
3856 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
3857 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
3858 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
3859 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
3860 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
3861 #endif /* CONFIG_IWL5000 */
3862
3863 {0}
3864 };
3865 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3866
3867 static struct pci_driver iwl_driver = {
3868 .name = DRV_NAME,
3869 .id_table = iwl_hw_card_ids,
3870 .probe = iwl_pci_probe,
3871 .remove = __devexit_p(iwl_pci_remove),
3872 #ifdef CONFIG_PM
3873 .suspend = iwl_pci_suspend,
3874 .resume = iwl_pci_resume,
3875 #endif
3876 };
3877
3878 static int __init iwl_init(void)
3879 {
3880
3881 int ret;
3882 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3883 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
3884
3885 ret = iwlagn_rate_control_register();
3886 if (ret) {
3887 printk(KERN_ERR DRV_NAME
3888 "Unable to register rate control algorithm: %d\n", ret);
3889 return ret;
3890 }
3891
3892 ret = pci_register_driver(&iwl_driver);
3893 if (ret) {
3894 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
3895 goto error_register;
3896 }
3897
3898 return ret;
3899
3900 error_register:
3901 iwlagn_rate_control_unregister();
3902 return ret;
3903 }
3904
3905 static void __exit iwl_exit(void)
3906 {
3907 pci_unregister_driver(&iwl_driver);
3908 iwlagn_rate_control_unregister();
3909 }
3910
3911 module_exit(iwl_exit);
3912 module_init(iwl_init);
3913
3914 #ifdef CONFIG_IWLWIFI_DEBUG
3915 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
3916 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
3917 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
3918 MODULE_PARM_DESC(debug, "debug output mask");
3919 #endif
3920
3921 module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
3922 MODULE_PARM_DESC(swcrypto50,
3923 "using crypto in software (default 0 [hardware]) (deprecated)");
3924 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
3925 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
3926 module_param_named(queues_num50,
3927 iwlagn_mod_params.num_of_queues, int, S_IRUGO);
3928 MODULE_PARM_DESC(queues_num50,
3929 "number of hw queues in 50xx series (deprecated)");
3930 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
3931 MODULE_PARM_DESC(queues_num, "number of hw queues.");
3932 module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
3933 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
3934 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
3935 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
3936 module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
3937 int, S_IRUGO);
3938 MODULE_PARM_DESC(amsdu_size_8K50,
3939 "enable 8K amsdu size in 50XX series (deprecated)");
3940 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
3941 int, S_IRUGO);
3942 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
3943 module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
3944 MODULE_PARM_DESC(fw_restart50,
3945 "restart firmware in case of error (deprecated)");
3946 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
3947 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
3948 module_param_named(
3949 disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
3950 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
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