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mac80211: Re-enable aggregation
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1 /******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Tomas Winkler <tomas.winkler@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <net/mac80211.h>
32
33 struct iwl_priv; /* FIXME: remove */
34 #include "iwl-debug.h"
35 #include "iwl-eeprom.h"
36 #include "iwl-dev.h" /* FIXME: remove */
37 #include "iwl-core.h"
38 #include "iwl-io.h"
39 #include "iwl-rfkill.h"
40 #include "iwl-power.h"
41
42
43 MODULE_DESCRIPTION("iwl core");
44 MODULE_VERSION(IWLWIFI_VERSION);
45 MODULE_AUTHOR(DRV_COPYRIGHT);
46 MODULE_LICENSE("GPL");
47
48 #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
49 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
50 IWL_RATE_SISO_##s##M_PLCP, \
51 IWL_RATE_MIMO2_##s##M_PLCP,\
52 IWL_RATE_MIMO3_##s##M_PLCP,\
53 IWL_RATE_##r##M_IEEE, \
54 IWL_RATE_##ip##M_INDEX, \
55 IWL_RATE_##in##M_INDEX, \
56 IWL_RATE_##rp##M_INDEX, \
57 IWL_RATE_##rn##M_INDEX, \
58 IWL_RATE_##pp##M_INDEX, \
59 IWL_RATE_##np##M_INDEX }
60
61 /*
62 * Parameter order:
63 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
64 *
65 * If there isn't a valid next or previous rate then INV is used which
66 * maps to IWL_RATE_INVALID
67 *
68 */
69 const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
70 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
71 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
72 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
73 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
74 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
75 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
76 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
77 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
78 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
79 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
80 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
81 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
82 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
83 /* FIXME:RS: ^^ should be INV (legacy) */
84 };
85 EXPORT_SYMBOL(iwl_rates);
86
87 /**
88 * translate ucode response to mac80211 tx status control values
89 */
90 void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
91 struct ieee80211_tx_info *info)
92 {
93 int rate_index;
94 struct ieee80211_tx_rate *r = &info->control.rates[0];
95
96 info->antenna_sel_tx =
97 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
98 if (rate_n_flags & RATE_MCS_HT_MSK)
99 r->flags |= IEEE80211_TX_RC_MCS;
100 if (rate_n_flags & RATE_MCS_GF_MSK)
101 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
102 if (rate_n_flags & RATE_MCS_FAT_MSK)
103 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
104 if (rate_n_flags & RATE_MCS_DUP_MSK)
105 r->flags |= IEEE80211_TX_RC_DUP_DATA;
106 if (rate_n_flags & RATE_MCS_SGI_MSK)
107 r->flags |= IEEE80211_TX_RC_SHORT_GI;
108 rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
109 if (info->band == IEEE80211_BAND_5GHZ)
110 rate_index -= IWL_FIRST_OFDM_RATE;
111 r->idx = rate_index;
112 }
113 EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
114
115 int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
116 {
117 int idx = 0;
118
119 /* HT rate format */
120 if (rate_n_flags & RATE_MCS_HT_MSK) {
121 idx = (rate_n_flags & 0xff);
122
123 if (idx >= IWL_RATE_MIMO2_6M_PLCP)
124 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
125
126 idx += IWL_FIRST_OFDM_RATE;
127 /* skip 9M not supported in ht*/
128 if (idx >= IWL_RATE_9M_INDEX)
129 idx += 1;
130 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
131 return idx;
132
133 /* legacy rate format, search for match in table */
134 } else {
135 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
136 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
137 return idx;
138 }
139
140 return -1;
141 }
142 EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
143
144 u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
145 {
146 int i;
147 u8 ind = ant;
148 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
149 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
150 if (priv->hw_params.valid_tx_ant & BIT(ind))
151 return ind;
152 }
153 return ant;
154 }
155
156 const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
157 EXPORT_SYMBOL(iwl_bcast_addr);
158
159
160 /* This function both allocates and initializes hw and priv. */
161 struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
162 struct ieee80211_ops *hw_ops)
163 {
164 struct iwl_priv *priv;
165
166 /* mac80211 allocates memory for this device instance, including
167 * space for this driver's private structure */
168 struct ieee80211_hw *hw =
169 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
170 if (hw == NULL) {
171 IWL_ERROR("Can not allocate network device\n");
172 goto out;
173 }
174
175 priv = hw->priv;
176 priv->hw = hw;
177
178 out:
179 return hw;
180 }
181 EXPORT_SYMBOL(iwl_alloc_all);
182
183 void iwl_hw_detect(struct iwl_priv *priv)
184 {
185 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
186 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
187 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
188 }
189 EXPORT_SYMBOL(iwl_hw_detect);
190
191 /* Tell nic where to find the "keep warm" buffer */
192 int iwl_kw_init(struct iwl_priv *priv)
193 {
194 unsigned long flags;
195 int ret;
196
197 spin_lock_irqsave(&priv->lock, flags);
198 ret = iwl_grab_nic_access(priv);
199 if (ret)
200 goto out;
201
202 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG,
203 priv->kw.dma_addr >> 4);
204 iwl_release_nic_access(priv);
205 out:
206 spin_unlock_irqrestore(&priv->lock, flags);
207 return ret;
208 }
209
210 int iwl_kw_alloc(struct iwl_priv *priv)
211 {
212 struct pci_dev *dev = priv->pci_dev;
213 struct iwl_kw *kw = &priv->kw;
214
215 kw->size = IWL_KW_SIZE;
216 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
217 if (!kw->v_addr)
218 return -ENOMEM;
219
220 return 0;
221 }
222
223 /**
224 * iwl_kw_free - Free the "keep warm" buffer
225 */
226 void iwl_kw_free(struct iwl_priv *priv)
227 {
228 struct pci_dev *dev = priv->pci_dev;
229 struct iwl_kw *kw = &priv->kw;
230
231 if (kw->v_addr) {
232 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
233 memset(kw, 0, sizeof(*kw));
234 }
235 }
236
237 int iwl_hw_nic_init(struct iwl_priv *priv)
238 {
239 unsigned long flags;
240 struct iwl_rx_queue *rxq = &priv->rxq;
241 int ret;
242
243 /* nic_init */
244 spin_lock_irqsave(&priv->lock, flags);
245 priv->cfg->ops->lib->apm_ops.init(priv);
246 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
247 spin_unlock_irqrestore(&priv->lock, flags);
248
249 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
250
251 priv->cfg->ops->lib->apm_ops.config(priv);
252
253 /* Allocate the RX queue, or reset if it is already allocated */
254 if (!rxq->bd) {
255 ret = iwl_rx_queue_alloc(priv);
256 if (ret) {
257 IWL_ERROR("Unable to initialize Rx queue\n");
258 return -ENOMEM;
259 }
260 } else
261 iwl_rx_queue_reset(priv, rxq);
262
263 iwl_rx_replenish(priv);
264
265 iwl_rx_init(priv, rxq);
266
267 spin_lock_irqsave(&priv->lock, flags);
268
269 rxq->need_update = 1;
270 iwl_rx_queue_update_write_ptr(priv, rxq);
271
272 spin_unlock_irqrestore(&priv->lock, flags);
273
274 /* Allocate and init all Tx and Command queues */
275 ret = iwl_txq_ctx_reset(priv);
276 if (ret)
277 return ret;
278
279 set_bit(STATUS_INIT, &priv->status);
280
281 return 0;
282 }
283 EXPORT_SYMBOL(iwl_hw_nic_init);
284
285 /**
286 * iwl_clear_stations_table - Clear the driver's station table
287 *
288 * NOTE: This does not clear or otherwise alter the device's station table.
289 */
290 void iwl_clear_stations_table(struct iwl_priv *priv)
291 {
292 unsigned long flags;
293
294 spin_lock_irqsave(&priv->sta_lock, flags);
295
296 if (iwl_is_alive(priv) &&
297 !test_bit(STATUS_EXIT_PENDING, &priv->status) &&
298 iwl_send_cmd_pdu_async(priv, REPLY_REMOVE_ALL_STA, 0, NULL, NULL))
299 IWL_ERROR("Couldn't clear the station table\n");
300
301 priv->num_stations = 0;
302 memset(priv->stations, 0, sizeof(priv->stations));
303
304 spin_unlock_irqrestore(&priv->sta_lock, flags);
305 }
306 EXPORT_SYMBOL(iwl_clear_stations_table);
307
308 void iwl_reset_qos(struct iwl_priv *priv)
309 {
310 u16 cw_min = 15;
311 u16 cw_max = 1023;
312 u8 aifs = 2;
313 u8 is_legacy = 0;
314 unsigned long flags;
315 int i;
316
317 spin_lock_irqsave(&priv->lock, flags);
318 priv->qos_data.qos_active = 0;
319
320 if (priv->iw_mode == NL80211_IFTYPE_ADHOC) {
321 if (priv->qos_data.qos_enable)
322 priv->qos_data.qos_active = 1;
323 if (!(priv->active_rate & 0xfff0)) {
324 cw_min = 31;
325 is_legacy = 1;
326 }
327 } else if (priv->iw_mode == NL80211_IFTYPE_AP) {
328 if (priv->qos_data.qos_enable)
329 priv->qos_data.qos_active = 1;
330 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
331 cw_min = 31;
332 is_legacy = 1;
333 }
334
335 if (priv->qos_data.qos_active)
336 aifs = 3;
337
338 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
339 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
340 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
341 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
342 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
343
344 if (priv->qos_data.qos_active) {
345 i = 1;
346 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
347 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
348 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
349 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
350 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
351
352 i = 2;
353 priv->qos_data.def_qos_parm.ac[i].cw_min =
354 cpu_to_le16((cw_min + 1) / 2 - 1);
355 priv->qos_data.def_qos_parm.ac[i].cw_max =
356 cpu_to_le16(cw_max);
357 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
358 if (is_legacy)
359 priv->qos_data.def_qos_parm.ac[i].edca_txop =
360 cpu_to_le16(6016);
361 else
362 priv->qos_data.def_qos_parm.ac[i].edca_txop =
363 cpu_to_le16(3008);
364 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
365
366 i = 3;
367 priv->qos_data.def_qos_parm.ac[i].cw_min =
368 cpu_to_le16((cw_min + 1) / 4 - 1);
369 priv->qos_data.def_qos_parm.ac[i].cw_max =
370 cpu_to_le16((cw_max + 1) / 2 - 1);
371 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
372 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
373 if (is_legacy)
374 priv->qos_data.def_qos_parm.ac[i].edca_txop =
375 cpu_to_le16(3264);
376 else
377 priv->qos_data.def_qos_parm.ac[i].edca_txop =
378 cpu_to_le16(1504);
379 } else {
380 for (i = 1; i < 4; i++) {
381 priv->qos_data.def_qos_parm.ac[i].cw_min =
382 cpu_to_le16(cw_min);
383 priv->qos_data.def_qos_parm.ac[i].cw_max =
384 cpu_to_le16(cw_max);
385 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
386 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
387 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
388 }
389 }
390 IWL_DEBUG_QOS("set QoS to default \n");
391
392 spin_unlock_irqrestore(&priv->lock, flags);
393 }
394 EXPORT_SYMBOL(iwl_reset_qos);
395
396 #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
397 #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
398 static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
399 struct ieee80211_sta_ht_cap *ht_info,
400 enum ieee80211_band band)
401 {
402 u16 max_bit_rate = 0;
403 u8 rx_chains_num = priv->hw_params.rx_chains_num;
404 u8 tx_chains_num = priv->hw_params.tx_chains_num;
405
406 ht_info->cap = 0;
407 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
408
409 ht_info->ht_supported = true;
410
411 ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
412 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
413 ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
414 (WLAN_HT_CAP_SM_PS_DISABLED << 2));
415
416 max_bit_rate = MAX_BIT_RATE_20_MHZ;
417 if (priv->hw_params.fat_channel & BIT(band)) {
418 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
419 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
420 ht_info->mcs.rx_mask[4] = 0x01;
421 max_bit_rate = MAX_BIT_RATE_40_MHZ;
422 }
423
424 if (priv->cfg->mod_params->amsdu_size_8K)
425 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
426
427 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
428 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
429
430 ht_info->mcs.rx_mask[0] = 0xFF;
431 if (rx_chains_num >= 2)
432 ht_info->mcs.rx_mask[1] = 0xFF;
433 if (rx_chains_num >= 3)
434 ht_info->mcs.rx_mask[2] = 0xFF;
435
436 /* Highest supported Rx data rate */
437 max_bit_rate *= rx_chains_num;
438 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
439 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
440
441 /* Tx MCS capabilities */
442 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
443 if (tx_chains_num != rx_chains_num) {
444 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
445 ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
446 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
447 }
448 }
449
450 static void iwlcore_init_hw_rates(struct iwl_priv *priv,
451 struct ieee80211_rate *rates)
452 {
453 int i;
454
455 for (i = 0; i < IWL_RATE_COUNT; i++) {
456 rates[i].bitrate = iwl_rates[i].ieee * 5;
457 rates[i].hw_value = i; /* Rate scaling will work on indexes */
458 rates[i].hw_value_short = i;
459 rates[i].flags = 0;
460 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
461 /*
462 * If CCK != 1M then set short preamble rate flag.
463 */
464 rates[i].flags |=
465 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
466 0 : IEEE80211_RATE_SHORT_PREAMBLE;
467 }
468 }
469 }
470
471 /**
472 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
473 */
474 static int iwlcore_init_geos(struct iwl_priv *priv)
475 {
476 struct iwl_channel_info *ch;
477 struct ieee80211_supported_band *sband;
478 struct ieee80211_channel *channels;
479 struct ieee80211_channel *geo_ch;
480 struct ieee80211_rate *rates;
481 int i = 0;
482
483 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
484 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
485 IWL_DEBUG_INFO("Geography modes already initialized.\n");
486 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
487 return 0;
488 }
489
490 channels = kzalloc(sizeof(struct ieee80211_channel) *
491 priv->channel_count, GFP_KERNEL);
492 if (!channels)
493 return -ENOMEM;
494
495 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
496 GFP_KERNEL);
497 if (!rates) {
498 kfree(channels);
499 return -ENOMEM;
500 }
501
502 /* 5.2GHz channels start after the 2.4GHz channels */
503 sband = &priv->bands[IEEE80211_BAND_5GHZ];
504 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
505 /* just OFDM */
506 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
507 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
508
509 if (priv->cfg->sku & IWL_SKU_N)
510 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
511 IEEE80211_BAND_5GHZ);
512
513 sband = &priv->bands[IEEE80211_BAND_2GHZ];
514 sband->channels = channels;
515 /* OFDM & CCK */
516 sband->bitrates = rates;
517 sband->n_bitrates = IWL_RATE_COUNT;
518
519 if (priv->cfg->sku & IWL_SKU_N)
520 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
521 IEEE80211_BAND_2GHZ);
522
523 priv->ieee_channels = channels;
524 priv->ieee_rates = rates;
525
526 iwlcore_init_hw_rates(priv, rates);
527
528 for (i = 0; i < priv->channel_count; i++) {
529 ch = &priv->channel_info[i];
530
531 /* FIXME: might be removed if scan is OK */
532 if (!is_channel_valid(ch))
533 continue;
534
535 if (is_channel_a_band(ch))
536 sband = &priv->bands[IEEE80211_BAND_5GHZ];
537 else
538 sband = &priv->bands[IEEE80211_BAND_2GHZ];
539
540 geo_ch = &sband->channels[sband->n_channels++];
541
542 geo_ch->center_freq =
543 ieee80211_channel_to_frequency(ch->channel);
544 geo_ch->max_power = ch->max_power_avg;
545 geo_ch->max_antenna_gain = 0xff;
546 geo_ch->hw_value = ch->channel;
547
548 if (is_channel_valid(ch)) {
549 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
550 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
551
552 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
553 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
554
555 if (ch->flags & EEPROM_CHANNEL_RADAR)
556 geo_ch->flags |= IEEE80211_CHAN_RADAR;
557
558 geo_ch->flags |= ch->fat_extension_channel;
559
560 if (ch->max_power_avg > priv->tx_power_channel_lmt)
561 priv->tx_power_channel_lmt = ch->max_power_avg;
562 } else {
563 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
564 }
565
566 /* Save flags for reg domain usage */
567 geo_ch->orig_flags = geo_ch->flags;
568
569 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
570 ch->channel, geo_ch->center_freq,
571 is_channel_a_band(ch) ? "5.2" : "2.4",
572 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
573 "restricted" : "valid",
574 geo_ch->flags);
575 }
576
577 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
578 priv->cfg->sku & IWL_SKU_A) {
579 printk(KERN_INFO DRV_NAME
580 ": Incorrectly detected BG card as ABG. Please send "
581 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
582 priv->pci_dev->device, priv->pci_dev->subsystem_device);
583 priv->cfg->sku &= ~IWL_SKU_A;
584 }
585
586 printk(KERN_INFO DRV_NAME
587 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
588 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
589 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
590
591
592 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
593
594 return 0;
595 }
596
597 /*
598 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
599 */
600 static void iwlcore_free_geos(struct iwl_priv *priv)
601 {
602 kfree(priv->ieee_channels);
603 kfree(priv->ieee_rates);
604 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
605 }
606
607 static bool is_single_rx_stream(struct iwl_priv *priv)
608 {
609 return !priv->current_ht_config.is_ht ||
610 ((priv->current_ht_config.mcs.rx_mask[1] == 0) &&
611 (priv->current_ht_config.mcs.rx_mask[2] == 0));
612 }
613
614 static u8 iwl_is_channel_extension(struct iwl_priv *priv,
615 enum ieee80211_band band,
616 u16 channel, u8 extension_chan_offset)
617 {
618 const struct iwl_channel_info *ch_info;
619
620 ch_info = iwl_get_channel_info(priv, band, channel);
621 if (!is_channel_valid(ch_info))
622 return 0;
623
624 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
625 return !(ch_info->fat_extension_channel &
626 IEEE80211_CHAN_NO_FAT_ABOVE);
627 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
628 return !(ch_info->fat_extension_channel &
629 IEEE80211_CHAN_NO_FAT_BELOW);
630
631 return 0;
632 }
633
634 u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
635 struct ieee80211_sta_ht_cap *sta_ht_inf)
636 {
637 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
638
639 if ((!iwl_ht_conf->is_ht) ||
640 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
641 (iwl_ht_conf->extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE))
642 return 0;
643
644 if (sta_ht_inf) {
645 if ((!sta_ht_inf->ht_supported) ||
646 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)))
647 return 0;
648 }
649
650 return iwl_is_channel_extension(priv, priv->band,
651 le16_to_cpu(priv->staging_rxon.channel),
652 iwl_ht_conf->extension_chan_offset);
653 }
654 EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
655
656 void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
657 {
658 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
659 u32 val;
660
661 if (!ht_info->is_ht) {
662 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
663 RXON_FLG_CHANNEL_MODE_PURE_40_MSK |
664 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
665 RXON_FLG_FAT_PROT_MSK |
666 RXON_FLG_HT_PROT_MSK);
667 return;
668 }
669
670 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
671 if (iwl_is_fat_tx_allowed(priv, NULL))
672 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
673 else
674 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
675 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
676
677 /* Note: control channel is opposite of extension channel */
678 switch (ht_info->extension_chan_offset) {
679 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
680 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
681 break;
682 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
683 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
684 break;
685 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
686 default:
687 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
688 break;
689 }
690
691 val = ht_info->ht_protection;
692
693 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
694
695 iwl_set_rxon_chain(priv);
696
697 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
698 "rxon flags 0x%X operation mode :0x%X "
699 "extension channel offset 0x%x\n",
700 ht_info->mcs.rx_mask[0],
701 ht_info->mcs.rx_mask[1],
702 ht_info->mcs.rx_mask[2],
703 le32_to_cpu(rxon->flags), ht_info->ht_protection,
704 ht_info->extension_chan_offset);
705 return;
706 }
707 EXPORT_SYMBOL(iwl_set_rxon_ht);
708
709 #define IWL_NUM_RX_CHAINS_MULTIPLE 3
710 #define IWL_NUM_RX_CHAINS_SINGLE 2
711 #define IWL_NUM_IDLE_CHAINS_DUAL 2
712 #define IWL_NUM_IDLE_CHAINS_SINGLE 1
713
714 /* Determine how many receiver/antenna chains to use.
715 * More provides better reception via diversity. Fewer saves power.
716 * MIMO (dual stream) requires at least 2, but works better with 3.
717 * This does not determine *which* chains to use, just how many.
718 */
719 static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
720 {
721 bool is_single = is_single_rx_stream(priv);
722 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
723
724 /* # of Rx chains to use when expecting MIMO. */
725 if (is_single || (!is_cam && (priv->current_ht_config.sm_ps ==
726 WLAN_HT_CAP_SM_PS_STATIC)))
727 return IWL_NUM_RX_CHAINS_SINGLE;
728 else
729 return IWL_NUM_RX_CHAINS_MULTIPLE;
730 }
731
732 static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
733 {
734 int idle_cnt;
735 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
736 /* # Rx chains when idling and maybe trying to save power */
737 switch (priv->current_ht_config.sm_ps) {
738 case WLAN_HT_CAP_SM_PS_STATIC:
739 case WLAN_HT_CAP_SM_PS_DYNAMIC:
740 idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
741 IWL_NUM_IDLE_CHAINS_SINGLE;
742 break;
743 case WLAN_HT_CAP_SM_PS_DISABLED:
744 idle_cnt = (is_cam) ? active_cnt : IWL_NUM_IDLE_CHAINS_SINGLE;
745 break;
746 case WLAN_HT_CAP_SM_PS_INVALID:
747 default:
748 IWL_ERROR("invalide mimo ps mode %d\n",
749 priv->current_ht_config.sm_ps);
750 WARN_ON(1);
751 idle_cnt = -1;
752 break;
753 }
754 return idle_cnt;
755 }
756
757 /* up to 4 chains */
758 static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
759 {
760 u8 res;
761 res = (chain_bitmap & BIT(0)) >> 0;
762 res += (chain_bitmap & BIT(1)) >> 1;
763 res += (chain_bitmap & BIT(2)) >> 2;
764 res += (chain_bitmap & BIT(4)) >> 4;
765 return res;
766 }
767
768 /**
769 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
770 *
771 * Selects how many and which Rx receivers/antennas/chains to use.
772 * This should not be used for scan command ... it puts data in wrong place.
773 */
774 void iwl_set_rxon_chain(struct iwl_priv *priv)
775 {
776 bool is_single = is_single_rx_stream(priv);
777 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
778 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
779 u32 active_chains;
780 u16 rx_chain;
781
782 /* Tell uCode which antennas are actually connected.
783 * Before first association, we assume all antennas are connected.
784 * Just after first association, iwl_chain_noise_calibration()
785 * checks which antennas actually *are* connected. */
786 if (priv->chain_noise_data.active_chains)
787 active_chains = priv->chain_noise_data.active_chains;
788 else
789 active_chains = priv->hw_params.valid_rx_ant;
790
791 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
792
793 /* How many receivers should we use? */
794 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
795 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
796
797
798 /* correct rx chain count according hw settings
799 * and chain noise calibration
800 */
801 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
802 if (valid_rx_cnt < active_rx_cnt)
803 active_rx_cnt = valid_rx_cnt;
804
805 if (valid_rx_cnt < idle_rx_cnt)
806 idle_rx_cnt = valid_rx_cnt;
807
808 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
809 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
810
811 priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
812
813 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
814 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
815 else
816 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
817
818 IWL_DEBUG_ASSOC("rx_chain=0x%X active=%d idle=%d\n",
819 priv->staging_rxon.rx_chain,
820 active_rx_cnt, idle_rx_cnt);
821
822 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
823 active_rx_cnt < idle_rx_cnt);
824 }
825 EXPORT_SYMBOL(iwl_set_rxon_chain);
826
827 /**
828 * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
829 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
830 * @channel: Any channel valid for the requested phymode
831
832 * In addition to setting the staging RXON, priv->phymode is also set.
833 *
834 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
835 * in the staging RXON flag structure based on the phymode
836 */
837 int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
838 {
839 enum ieee80211_band band = ch->band;
840 u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
841
842 if (!iwl_get_channel_info(priv, band, channel)) {
843 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
844 channel, band);
845 return -EINVAL;
846 }
847
848 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
849 (priv->band == band))
850 return 0;
851
852 priv->staging_rxon.channel = cpu_to_le16(channel);
853 if (band == IEEE80211_BAND_5GHZ)
854 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
855 else
856 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
857
858 priv->band = band;
859
860 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
861
862 return 0;
863 }
864 EXPORT_SYMBOL(iwl_set_rxon_channel);
865
866 int iwl_setup_mac(struct iwl_priv *priv)
867 {
868 int ret;
869 struct ieee80211_hw *hw = priv->hw;
870 hw->rate_control_algorithm = "iwl-agn-rs";
871
872 /* Tell mac80211 our characteristics */
873 hw->flags = IEEE80211_HW_SIGNAL_DBM |
874 IEEE80211_HW_NOISE_DBM |
875 IEEE80211_HW_AMPDU_AGGREGATION;
876 hw->wiphy->interface_modes =
877 BIT(NL80211_IFTYPE_AP) |
878 BIT(NL80211_IFTYPE_STATION) |
879 BIT(NL80211_IFTYPE_ADHOC);
880 /* Default value; 4 EDCA QOS priorities */
881 hw->queues = 4;
882 /* queues to support 11n aggregation */
883 if (priv->cfg->sku & IWL_SKU_N)
884 hw->ampdu_queues = priv->cfg->mod_params->num_of_ampdu_queues;
885
886 hw->conf.beacon_int = 100;
887 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
888
889 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
890 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
891 &priv->bands[IEEE80211_BAND_2GHZ];
892 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
893 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
894 &priv->bands[IEEE80211_BAND_5GHZ];
895
896 ret = ieee80211_register_hw(priv->hw);
897 if (ret) {
898 IWL_ERROR("Failed to register hw (error %d)\n", ret);
899 return ret;
900 }
901 priv->mac80211_registered = 1;
902
903 return 0;
904 }
905 EXPORT_SYMBOL(iwl_setup_mac);
906
907 int iwl_set_hw_params(struct iwl_priv *priv)
908 {
909 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
910 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
911 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
912 if (priv->cfg->mod_params->amsdu_size_8K)
913 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
914 else
915 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
916 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
917
918 if (priv->cfg->mod_params->disable_11n)
919 priv->cfg->sku &= ~IWL_SKU_N;
920
921 /* Device-specific setup */
922 return priv->cfg->ops->lib->set_hw_params(priv);
923 }
924 EXPORT_SYMBOL(iwl_set_hw_params);
925
926 int iwl_init_drv(struct iwl_priv *priv)
927 {
928 int ret;
929
930 priv->retry_rate = 1;
931 priv->ibss_beacon = NULL;
932
933 spin_lock_init(&priv->lock);
934 spin_lock_init(&priv->power_data.lock);
935 spin_lock_init(&priv->sta_lock);
936 spin_lock_init(&priv->hcmd_lock);
937
938 INIT_LIST_HEAD(&priv->free_frames);
939
940 mutex_init(&priv->mutex);
941
942 /* Clear the driver's (not device's) station table */
943 iwl_clear_stations_table(priv);
944
945 priv->data_retry_limit = -1;
946 priv->ieee_channels = NULL;
947 priv->ieee_rates = NULL;
948 priv->band = IEEE80211_BAND_2GHZ;
949
950 priv->iw_mode = NL80211_IFTYPE_STATION;
951
952 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
953
954 /* Choose which receivers/antennas to use */
955 iwl_set_rxon_chain(priv);
956 iwl_init_scan_params(priv);
957
958 if (priv->cfg->mod_params->enable_qos)
959 priv->qos_data.qos_enable = 1;
960
961 iwl_reset_qos(priv);
962
963 priv->qos_data.qos_active = 0;
964 priv->qos_data.qos_cap.val = 0;
965
966 priv->rates_mask = IWL_RATES_MASK;
967 /* If power management is turned on, default to AC mode */
968 priv->power_mode = IWL_POWER_AC;
969 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
970
971 ret = iwl_init_channel_map(priv);
972 if (ret) {
973 IWL_ERROR("initializing regulatory failed: %d\n", ret);
974 goto err;
975 }
976
977 ret = iwlcore_init_geos(priv);
978 if (ret) {
979 IWL_ERROR("initializing geos failed: %d\n", ret);
980 goto err_free_channel_map;
981 }
982
983 return 0;
984
985 err_free_channel_map:
986 iwl_free_channel_map(priv);
987 err:
988 return ret;
989 }
990 EXPORT_SYMBOL(iwl_init_drv);
991
992 int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
993 {
994 int ret = 0;
995 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
996 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
997 priv->tx_power_user_lmt);
998 return -EINVAL;
999 }
1000
1001 if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
1002 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
1003 priv->tx_power_user_lmt);
1004 return -EINVAL;
1005 }
1006
1007 if (priv->tx_power_user_lmt != tx_power)
1008 force = true;
1009
1010 priv->tx_power_user_lmt = tx_power;
1011
1012 if (force && priv->cfg->ops->lib->send_tx_power)
1013 ret = priv->cfg->ops->lib->send_tx_power(priv);
1014
1015 return ret;
1016 }
1017 EXPORT_SYMBOL(iwl_set_tx_power);
1018
1019 void iwl_uninit_drv(struct iwl_priv *priv)
1020 {
1021 iwl_calib_free_results(priv);
1022 iwlcore_free_geos(priv);
1023 iwl_free_channel_map(priv);
1024 kfree(priv->scan);
1025 }
1026 EXPORT_SYMBOL(iwl_uninit_drv);
1027
1028 int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
1029 {
1030 u32 stat_flags = 0;
1031 struct iwl_host_cmd cmd = {
1032 .id = REPLY_STATISTICS_CMD,
1033 .meta.flags = flags,
1034 .len = sizeof(stat_flags),
1035 .data = (u8 *) &stat_flags,
1036 };
1037 return iwl_send_cmd(priv, &cmd);
1038 }
1039 EXPORT_SYMBOL(iwl_send_statistics_request);
1040
1041 /**
1042 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
1043 * using sample data 100 bytes apart. If these sample points are good,
1044 * it's a pretty good bet that everything between them is good, too.
1045 */
1046 static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
1047 {
1048 u32 val;
1049 int ret = 0;
1050 u32 errcnt = 0;
1051 u32 i;
1052
1053 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1054
1055 ret = iwl_grab_nic_access(priv);
1056 if (ret)
1057 return ret;
1058
1059 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1060 /* read data comes through single port, auto-incr addr */
1061 /* NOTE: Use the debugless read so we don't flood kernel log
1062 * if IWL_DL_IO is set */
1063 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
1064 i + RTC_INST_LOWER_BOUND);
1065 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1066 if (val != le32_to_cpu(*image)) {
1067 ret = -EIO;
1068 errcnt++;
1069 if (errcnt >= 3)
1070 break;
1071 }
1072 }
1073
1074 iwl_release_nic_access(priv);
1075
1076 return ret;
1077 }
1078
1079 /**
1080 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
1081 * looking at all data.
1082 */
1083 static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
1084 u32 len)
1085 {
1086 u32 val;
1087 u32 save_len = len;
1088 int ret = 0;
1089 u32 errcnt;
1090
1091 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1092
1093 ret = iwl_grab_nic_access(priv);
1094 if (ret)
1095 return ret;
1096
1097 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
1098
1099 errcnt = 0;
1100 for (; len > 0; len -= sizeof(u32), image++) {
1101 /* read data comes through single port, auto-incr addr */
1102 /* NOTE: Use the debugless read so we don't flood kernel log
1103 * if IWL_DL_IO is set */
1104 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1105 if (val != le32_to_cpu(*image)) {
1106 IWL_ERROR("uCode INST section is invalid at "
1107 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1108 save_len - len, val, le32_to_cpu(*image));
1109 ret = -EIO;
1110 errcnt++;
1111 if (errcnt >= 20)
1112 break;
1113 }
1114 }
1115
1116 iwl_release_nic_access(priv);
1117
1118 if (!errcnt)
1119 IWL_DEBUG_INFO
1120 ("ucode image in INSTRUCTION memory is good\n");
1121
1122 return ret;
1123 }
1124
1125 /**
1126 * iwl_verify_ucode - determine which instruction image is in SRAM,
1127 * and verify its contents
1128 */
1129 int iwl_verify_ucode(struct iwl_priv *priv)
1130 {
1131 __le32 *image;
1132 u32 len;
1133 int ret;
1134
1135 /* Try bootstrap */
1136 image = (__le32 *)priv->ucode_boot.v_addr;
1137 len = priv->ucode_boot.len;
1138 ret = iwlcore_verify_inst_sparse(priv, image, len);
1139 if (!ret) {
1140 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1141 return 0;
1142 }
1143
1144 /* Try initialize */
1145 image = (__le32 *)priv->ucode_init.v_addr;
1146 len = priv->ucode_init.len;
1147 ret = iwlcore_verify_inst_sparse(priv, image, len);
1148 if (!ret) {
1149 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1150 return 0;
1151 }
1152
1153 /* Try runtime/protocol */
1154 image = (__le32 *)priv->ucode_code.v_addr;
1155 len = priv->ucode_code.len;
1156 ret = iwlcore_verify_inst_sparse(priv, image, len);
1157 if (!ret) {
1158 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1159 return 0;
1160 }
1161
1162 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1163
1164 /* Since nothing seems to match, show first several data entries in
1165 * instruction SRAM, so maybe visual inspection will give a clue.
1166 * Selection of bootstrap image (vs. other images) is arbitrary. */
1167 image = (__le32 *)priv->ucode_boot.v_addr;
1168 len = priv->ucode_boot.len;
1169 ret = iwl_verify_inst_full(priv, image, len);
1170
1171 return ret;
1172 }
1173 EXPORT_SYMBOL(iwl_verify_ucode);
1174
1175
1176 static const char *desc_lookup_text[] = {
1177 "OK",
1178 "FAIL",
1179 "BAD_PARAM",
1180 "BAD_CHECKSUM",
1181 "NMI_INTERRUPT_WDG",
1182 "SYSASSERT",
1183 "FATAL_ERROR",
1184 "BAD_COMMAND",
1185 "HW_ERROR_TUNE_LOCK",
1186 "HW_ERROR_TEMPERATURE",
1187 "ILLEGAL_CHAN_FREQ",
1188 "VCC_NOT_STABLE",
1189 "FH_ERROR",
1190 "NMI_INTERRUPT_HOST",
1191 "NMI_INTERRUPT_ACTION_PT",
1192 "NMI_INTERRUPT_UNKNOWN",
1193 "UCODE_VERSION_MISMATCH",
1194 "HW_ERROR_ABS_LOCK",
1195 "HW_ERROR_CAL_LOCK_FAIL",
1196 "NMI_INTERRUPT_INST_ACTION_PT",
1197 "NMI_INTERRUPT_DATA_ACTION_PT",
1198 "NMI_TRM_HW_ER",
1199 "NMI_INTERRUPT_TRM",
1200 "NMI_INTERRUPT_BREAK_POINT"
1201 "DEBUG_0",
1202 "DEBUG_1",
1203 "DEBUG_2",
1204 "DEBUG_3",
1205 "UNKNOWN"
1206 };
1207
1208 static const char *desc_lookup(int i)
1209 {
1210 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1211
1212 if (i < 0 || i > max)
1213 i = max;
1214
1215 return desc_lookup_text[i];
1216 }
1217
1218 #define ERROR_START_OFFSET (1 * sizeof(u32))
1219 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1220
1221 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1222 {
1223 u32 data2, line;
1224 u32 desc, time, count, base, data1;
1225 u32 blink1, blink2, ilink1, ilink2;
1226 int ret;
1227
1228 if (priv->ucode_type == UCODE_INIT)
1229 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1230 else
1231 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1232
1233 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1234 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
1235 return;
1236 }
1237
1238 ret = iwl_grab_nic_access(priv);
1239 if (ret) {
1240 IWL_WARNING("Can not read from adapter at this time.\n");
1241 return;
1242 }
1243
1244 count = iwl_read_targ_mem(priv, base);
1245
1246 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1247 IWL_ERROR("Start IWL Error Log Dump:\n");
1248 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
1249 }
1250
1251 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1252 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1253 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1254 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1255 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1256 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1257 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1258 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1259 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1260
1261 IWL_ERROR("Desc Time "
1262 "data1 data2 line\n");
1263 IWL_ERROR("%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
1264 desc_lookup(desc), desc, time, data1, data2, line);
1265 IWL_ERROR("blink1 blink2 ilink1 ilink2\n");
1266 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1267 ilink1, ilink2);
1268
1269 iwl_release_nic_access(priv);
1270 }
1271 EXPORT_SYMBOL(iwl_dump_nic_error_log);
1272
1273 #define EVENT_START_OFFSET (4 * sizeof(u32))
1274
1275 /**
1276 * iwl_print_event_log - Dump error event log to syslog
1277 *
1278 * NOTE: Must be called with iwl_grab_nic_access() already obtained!
1279 */
1280 static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1281 u32 num_events, u32 mode)
1282 {
1283 u32 i;
1284 u32 base; /* SRAM byte address of event log header */
1285 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1286 u32 ptr; /* SRAM byte address of log data */
1287 u32 ev, time, data; /* event log data */
1288
1289 if (num_events == 0)
1290 return;
1291 if (priv->ucode_type == UCODE_INIT)
1292 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1293 else
1294 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1295
1296 if (mode == 0)
1297 event_size = 2 * sizeof(u32);
1298 else
1299 event_size = 3 * sizeof(u32);
1300
1301 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1302
1303 /* "time" is actually "data" for mode 0 (no timestamp).
1304 * place event id # at far right for easier visual parsing. */
1305 for (i = 0; i < num_events; i++) {
1306 ev = iwl_read_targ_mem(priv, ptr);
1307 ptr += sizeof(u32);
1308 time = iwl_read_targ_mem(priv, ptr);
1309 ptr += sizeof(u32);
1310 if (mode == 0) {
1311 /* data, ev */
1312 IWL_ERROR("EVT_LOG:0x%08x:%04u\n", time, ev);
1313 } else {
1314 data = iwl_read_targ_mem(priv, ptr);
1315 ptr += sizeof(u32);
1316 IWL_ERROR("EVT_LOGT:%010u:0x%08x:%04u\n",
1317 time, data, ev);
1318 }
1319 }
1320 }
1321
1322 void iwl_dump_nic_event_log(struct iwl_priv *priv)
1323 {
1324 int ret;
1325 u32 base; /* SRAM byte address of event log header */
1326 u32 capacity; /* event log capacity in # entries */
1327 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1328 u32 num_wraps; /* # times uCode wrapped to top of log */
1329 u32 next_entry; /* index of next entry to be written by uCode */
1330 u32 size; /* # entries that we'll print */
1331
1332 if (priv->ucode_type == UCODE_INIT)
1333 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1334 else
1335 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1336
1337 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1338 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
1339 return;
1340 }
1341
1342 ret = iwl_grab_nic_access(priv);
1343 if (ret) {
1344 IWL_WARNING("Can not read from adapter at this time.\n");
1345 return;
1346 }
1347
1348 /* event log header */
1349 capacity = iwl_read_targ_mem(priv, base);
1350 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1351 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1352 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1353
1354 size = num_wraps ? capacity : next_entry;
1355
1356 /* bail out if nothing in log */
1357 if (size == 0) {
1358 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
1359 iwl_release_nic_access(priv);
1360 return;
1361 }
1362
1363 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
1364 size, num_wraps);
1365
1366 /* if uCode has wrapped back to top of log, start at the oldest entry,
1367 * i.e the next one that uCode would fill. */
1368 if (num_wraps)
1369 iwl_print_event_log(priv, next_entry,
1370 capacity - next_entry, mode);
1371 /* (then/else) start at top of log */
1372 iwl_print_event_log(priv, 0, next_entry, mode);
1373
1374 iwl_release_nic_access(priv);
1375 }
1376 EXPORT_SYMBOL(iwl_dump_nic_event_log);
1377
1378 void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1379 {
1380 struct iwl_ct_kill_config cmd;
1381 unsigned long flags;
1382 int ret = 0;
1383
1384 spin_lock_irqsave(&priv->lock, flags);
1385 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1386 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1387 spin_unlock_irqrestore(&priv->lock, flags);
1388
1389 cmd.critical_temperature_R =
1390 cpu_to_le32(priv->hw_params.ct_kill_threshold);
1391
1392 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1393 sizeof(cmd), &cmd);
1394 if (ret)
1395 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1396 else
1397 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
1398 "critical temperature is %d\n",
1399 cmd.critical_temperature_R);
1400 }
1401 EXPORT_SYMBOL(iwl_rf_kill_ct_config);
1402
1403 /*
1404 * CARD_STATE_CMD
1405 *
1406 * Use: Sets the device's internal card state to enable, disable, or halt
1407 *
1408 * When in the 'enable' state the card operates as normal.
1409 * When in the 'disable' state, the card enters into a low power mode.
1410 * When in the 'halt' state, the card is shut down and must be fully
1411 * restarted to come back on.
1412 */
1413 static int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
1414 {
1415 struct iwl_host_cmd cmd = {
1416 .id = REPLY_CARD_STATE_CMD,
1417 .len = sizeof(u32),
1418 .data = &flags,
1419 .meta.flags = meta_flag,
1420 };
1421
1422 return iwl_send_cmd(priv, &cmd);
1423 }
1424
1425 void iwl_radio_kill_sw_disable_radio(struct iwl_priv *priv)
1426 {
1427 unsigned long flags;
1428
1429 if (test_bit(STATUS_RF_KILL_SW, &priv->status))
1430 return;
1431
1432 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO OFF\n");
1433
1434 iwl_scan_cancel(priv);
1435 /* FIXME: This is a workaround for AP */
1436 if (priv->iw_mode != NL80211_IFTYPE_AP) {
1437 spin_lock_irqsave(&priv->lock, flags);
1438 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
1439 CSR_UCODE_SW_BIT_RFKILL);
1440 spin_unlock_irqrestore(&priv->lock, flags);
1441 /* call the host command only if no hw rf-kill set */
1442 if (!test_bit(STATUS_RF_KILL_HW, &priv->status) &&
1443 iwl_is_ready(priv))
1444 iwl_send_card_state(priv,
1445 CARD_STATE_CMD_DISABLE, 0);
1446 set_bit(STATUS_RF_KILL_SW, &priv->status);
1447 /* make sure mac80211 stop sending Tx frame */
1448 if (priv->mac80211_registered)
1449 ieee80211_stop_queues(priv->hw);
1450 }
1451 }
1452 EXPORT_SYMBOL(iwl_radio_kill_sw_disable_radio);
1453
1454 int iwl_radio_kill_sw_enable_radio(struct iwl_priv *priv)
1455 {
1456 unsigned long flags;
1457
1458 if (!test_bit(STATUS_RF_KILL_SW, &priv->status))
1459 return 0;
1460
1461 IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO ON\n");
1462
1463 spin_lock_irqsave(&priv->lock, flags);
1464 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1465
1466 /* If the driver is up it will receive CARD_STATE_NOTIFICATION
1467 * notification where it will clear SW rfkill status.
1468 * Setting it here would break the handler. Only if the
1469 * interface is down we can set here since we don't
1470 * receive any further notification.
1471 */
1472 if (!priv->is_open)
1473 clear_bit(STATUS_RF_KILL_SW, &priv->status);
1474 spin_unlock_irqrestore(&priv->lock, flags);
1475
1476 /* wake up ucode */
1477 msleep(10);
1478
1479 spin_lock_irqsave(&priv->lock, flags);
1480 iwl_read32(priv, CSR_UCODE_DRV_GP1);
1481 if (!iwl_grab_nic_access(priv))
1482 iwl_release_nic_access(priv);
1483 spin_unlock_irqrestore(&priv->lock, flags);
1484
1485 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
1486 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
1487 "disabled by HW switch\n");
1488 return 0;
1489 }
1490
1491 /* If the driver is already loaded, it will receive
1492 * CARD_STATE_NOTIFICATION notifications and the handler will
1493 * call restart to reload the driver.
1494 */
1495 return 1;
1496 }
1497 EXPORT_SYMBOL(iwl_radio_kill_sw_enable_radio);