drivers/net/wireless/iwlwifi/iwl-eeprom-read.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  22  * USA
  23  *
  24  * The full GNU General Public License is included in this distribution
  25  * in the file called COPYING.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30  *
  31  * BSD LICENSE
  32  *
  33  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
  34  * All rights reserved.
  35  *
  36  * Redistribution and use in source and binary forms, with or without
  37  * modification, are permitted provided that the following conditions
  38  * are met:
  39  *
  40  *  * Redistributions of source code must retain the above copyright
  41  *    notice, this list of conditions and the following disclaimer.
  42  *  * Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
  46  *  * Neither the name Intel Corporation nor the names of its
  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *****************************************************************************/
  62 #include <linux/types.h>
  63 #include <linux/slab.h>
  64 #include <linux/export.h>
  65
  66 #include "iwl-drv.h"
  67 #include "iwl-debug.h"
  68 #include "iwl-eeprom-read.h"
  69 #include "iwl-io.h"
  70 #include "iwl-prph.h"
  71 #include "iwl-csr.h"
  72
  73 /*
  74  * EEPROM access time values:
  75  *
  76  * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
  77  * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
  78  * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
  79  * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
  80  */
  81 #define IWL_EEPROM_ACCESS_TIMEOUT       5000 /* uSec */
  82
  83 #define IWL_EEPROM_SEM_TIMEOUT          10   /* microseconds */
  84 #define IWL_EEPROM_SEM_RETRY_LIMIT      1000 /* number of attempts (not time) */
  85
  86
  87 /*
  88  * The device's EEPROM semaphore prevents conflicts between driver and uCode
  89  * when accessing the EEPROM; each access is a series of pulses to/from the
  90  * EEPROM chip, not a single event, so even reads could conflict if they
  91  * weren't arbitrated by the semaphore.
  92  */
  93
  94 #define EEPROM_SEM_TIMEOUT 10           /* milliseconds */
  95 #define EEPROM_SEM_RETRY_LIMIT 1000     /* number of attempts (not time) */
  96
  97 static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans)
  98 {
  99         u16 count;
 100         int ret;
 101
 102         for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
 103                 /* Request semaphore */
 104                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 105                             CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
 106
 107                 /* See if we got it */
 108                 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 109                                 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
 110                                 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
 111                                 EEPROM_SEM_TIMEOUT);
 112                 if (ret >= 0) {
 113                         IWL_DEBUG_EEPROM(trans->dev,
 114                                          "Acquired semaphore after %d tries.\n",
 115                                          count+1);
 116                         return ret;
 117                 }
 118         }
 119
 120         return ret;
 121 }
 122
 123 static void iwl_eeprom_release_semaphore(struct iwl_trans *trans)
 124 {
 125         iwl_clear_bit(trans, CSR_HW_IF_CONFIG_REG,
 126                       CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
 127 }
 128
 129 static int iwl_eeprom_verify_signature(struct iwl_trans *trans, bool nvm_is_otp)
 130 {
 131         u32 gp = iwl_read32(trans, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
 132
 133         IWL_DEBUG_EEPROM(trans->dev, "EEPROM signature=0x%08x\n", gp);
 134
 135         switch (gp) {
 136         case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP:
 137                 if (!nvm_is_otp) {
 138                         IWL_ERR(trans, "EEPROM with bad signature: 0x%08x\n",
 139                                 gp);
 140                         return -ENOENT;
 141                 }
 142                 return 0;
 143         case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
 144         case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
 145                 if (nvm_is_otp) {
 146                         IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp);
 147                         return -ENOENT;
 148                 }
 149                 return 0;
 150         case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP:
 151         default:
 152                 IWL_ERR(trans,
 153                         "bad EEPROM/OTP signature, type=%s, EEPROM_GP=0x%08x\n",
 154                         nvm_is_otp ? "OTP" : "EEPROM", gp);
 155                 return -ENOENT;
 156         }
 157 }
 158
 159 /******************************************************************************
 160  *
 161  * OTP related functions
 162  *
 163 ******************************************************************************/
 164
 165 static void iwl_set_otp_access_absolute(struct iwl_trans *trans)
 166 {
 167         iwl_read32(trans, CSR_OTP_GP_REG);
 168
 169         iwl_clear_bit(trans, CSR_OTP_GP_REG,
 170                       CSR_OTP_GP_REG_OTP_ACCESS_MODE);
 171 }
 172
 173 static int iwl_nvm_is_otp(struct iwl_trans *trans)
 174 {
 175         u32 otpgp;
 176
 177         /* OTP only valid for CP/PP and after */
 178         switch (trans->hw_rev & CSR_HW_REV_TYPE_MSK) {
 179         case CSR_HW_REV_TYPE_NONE:
 180                 IWL_ERR(trans, "Unknown hardware type\n");
 181                 return -EIO;
 182         case CSR_HW_REV_TYPE_5300:
 183         case CSR_HW_REV_TYPE_5350:
 184         case CSR_HW_REV_TYPE_5100:
 185         case CSR_HW_REV_TYPE_5150:
 186                 return 0;
 187         default:
 188                 otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
 189                 if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
 190                         return 1;
 191                 return 0;
 192         }
 193 }
 194
 195 static int iwl_init_otp_access(struct iwl_trans *trans)
 196 {
 197         int ret;
 198
 199         /* Enable 40MHz radio clock */
 200         iwl_write32(trans, CSR_GP_CNTRL,
 201                     iwl_read32(trans, CSR_GP_CNTRL) |
 202                     CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 203
 204         /* wait for clock to be ready */
 205         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 206                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 207                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 208                            25000);
 209         if (ret < 0) {
 210                 IWL_ERR(trans, "Time out access OTP\n");
 211         } else {
 212                 iwl_set_bits_prph(trans, APMG_PS_CTRL_REG,
 213                                   APMG_PS_CTRL_VAL_RESET_REQ);
 214                 udelay(5);
 215                 iwl_clear_bits_prph(trans, APMG_PS_CTRL_REG,
 216                                     APMG_PS_CTRL_VAL_RESET_REQ);
 217
 218                 /*
 219                  * CSR auto clock gate disable bit -
 220                  * this is only applicable for HW with OTP shadow RAM
 221                  */
 222                 if (trans->cfg->base_params->shadow_ram_support)
 223                         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 224                                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 225         }
 226         return ret;
 227 }
 228
 229 static int iwl_read_otp_word(struct iwl_trans *trans, u16 addr,
 230                              __le16 *eeprom_data)
 231 {
 232         int ret = 0;
 233         u32 r;
 234         u32 otpgp;
 235
 236         iwl_write32(trans, CSR_EEPROM_REG,
 237                     CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
 238         ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
 239                                  CSR_EEPROM_REG_READ_VALID_MSK,
 240                                  CSR_EEPROM_REG_READ_VALID_MSK,
 241                                  IWL_EEPROM_ACCESS_TIMEOUT);
 242         if (ret < 0) {
 243                 IWL_ERR(trans, "Time out reading OTP[%d]\n", addr);
 244                 return ret;
 245         }
 246         r = iwl_read32(trans, CSR_EEPROM_REG);
 247         /* check for ECC errors: */
 248         otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
 249         if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
 250                 /* stop in this case */
 251                 /* set the uncorrectable OTP ECC bit for acknowledgement */
 252                 iwl_set_bit(trans, CSR_OTP_GP_REG,
 253                             CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
 254                 IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n");
 255                 return -EINVAL;
 256         }
 257         if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
 258                 /* continue in this case */
 259                 /* set the correctable OTP ECC bit for acknowledgement */
 260                 iwl_set_bit(trans, CSR_OTP_GP_REG,
 261                             CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
 262                 IWL_ERR(trans, "Correctable OTP ECC error, continue read\n");
 263         }
 264         *eeprom_data = cpu_to_le16(r >> 16);
 265         return 0;
 266 }
 267
 268 /*
 269  * iwl_is_otp_empty: check for empty OTP
 270  */
 271 static bool iwl_is_otp_empty(struct iwl_trans *trans)
 272 {
 273         u16 next_link_addr = 0;
 274         __le16 link_value;
 275         bool is_empty = false;
 276
 277         /* locate the beginning of OTP link list */
 278         if (!iwl_read_otp_word(trans, next_link_addr, &link_value)) {
 279                 if (!link_value) {
 280                         IWL_ERR(trans, "OTP is empty\n");
 281                         is_empty = true;
 282                 }
 283         } else {
 284                 IWL_ERR(trans, "Unable to read first block of OTP list.\n");
 285                 is_empty = true;
 286         }
 287
 288         return is_empty;
 289 }
 290
 291
 292 /*
 293  * iwl_find_otp_image: find EEPROM image in OTP
 294  *   finding the OTP block that contains the EEPROM image.
 295  *   the last valid block on the link list (the block _before_ the last block)
 296  *   is the block we should read and used to configure the device.
 297  *   If all the available OTP blocks are full, the last block will be the block
 298  *   we should read and used to configure the device.
 299  *   only perform this operation if shadow RAM is disabled
 300  */
 301 static int iwl_find_otp_image(struct iwl_trans *trans,
 302                                         u16 *validblockaddr)
 303 {
 304         u16 next_link_addr = 0, valid_addr;
 305         __le16 link_value = 0;
 306         int usedblocks = 0;
 307
 308         /* set addressing mode to absolute to traverse the link list */
 309         iwl_set_otp_access_absolute(trans);
 310
 311         /* checking for empty OTP or error */
 312         if (iwl_is_otp_empty(trans))
 313                 return -EINVAL;
 314
 315         /*
 316          * start traverse link list
 317          * until reach the max number of OTP blocks
 318          * different devices have different number of OTP blocks
 319          */
 320         do {
 321                 /* save current valid block address
 322                  * check for more block on the link list
 323                  */
 324                 valid_addr = next_link_addr;
 325                 next_link_addr = le16_to_cpu(link_value) * sizeof(u16);
 326                 IWL_DEBUG_EEPROM(trans->dev, "OTP blocks %d addr 0x%x\n",
 327                                  usedblocks, next_link_addr);
 328                 if (iwl_read_otp_word(trans, next_link_addr, &link_value))
 329                         return -EINVAL;
 330                 if (!link_value) {
 331                         /*
 332                          * reach the end of link list, return success and
 333                          * set address point to the starting address
 334                          * of the image
 335                          */
 336                         *validblockaddr = valid_addr;
 337                         /* skip first 2 bytes (link list pointer) */
 338                         *validblockaddr += 2;
 339                         return 0;
 340                 }
 341                 /* more in the link list, continue */
 342                 usedblocks++;
 343         } while (usedblocks <= trans->cfg->base_params->max_ll_items);
 344
 345         /* OTP has no valid blocks */
 346         IWL_DEBUG_EEPROM(trans->dev, "OTP has no valid blocks\n");
 347         return -EINVAL;
 348 }
 349
 350 /**
 351  * iwl_read_eeprom - read EEPROM contents
 352  *
 353  * Load the EEPROM contents from adapter and return it
 354  * and its size.
 355  *
 356  * NOTE:  This routine uses the non-debug IO access functions.
 357  */
 358 int iwl_read_eeprom(struct iwl_trans *trans, u8 **eeprom, size_t *eeprom_size)
 359 {
 360         __le16 *e;
 361         u32 gp = iwl_read32(trans, CSR_EEPROM_GP);
 362         int sz;
 363         int ret;
 364         u16 addr;
 365         u16 validblockaddr = 0;
 366         u16 cache_addr = 0;
 367         int nvm_is_otp;
 368
 369         if (!eeprom || !eeprom_size)
 370                 return -EINVAL;
 371
 372         nvm_is_otp = iwl_nvm_is_otp(trans);
 373         if (nvm_is_otp < 0)
 374                 return nvm_is_otp;
 375
 376         sz = trans->cfg->base_params->eeprom_size;
 377         IWL_DEBUG_EEPROM(trans->dev, "NVM size = %d\n", sz);
 378
 379         e = kmalloc(sz, GFP_KERNEL);
 380         if (!e)
 381                 return -ENOMEM;
 382
 383         ret = iwl_eeprom_verify_signature(trans, nvm_is_otp);
 384         if (ret < 0) {
 385                 IWL_ERR(trans, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
 386                 goto err_free;
 387         }
 388
 389         /* Make sure driver (instead of uCode) is allowed to read EEPROM */
 390         ret = iwl_eeprom_acquire_semaphore(trans);
 391         if (ret < 0) {
 392                 IWL_ERR(trans, "Failed to acquire EEPROM semaphore.\n");
 393                 goto err_free;
 394         }
 395
 396         if (nvm_is_otp) {
 397                 ret = iwl_init_otp_access(trans);
 398                 if (ret) {
 399                         IWL_ERR(trans, "Failed to initialize OTP access.\n");
 400                         goto err_unlock;
 401                 }
 402
 403                 iwl_write32(trans, CSR_EEPROM_GP,
 404                             iwl_read32(trans, CSR_EEPROM_GP) &
 405                             ~CSR_EEPROM_GP_IF_OWNER_MSK);
 406
 407                 iwl_set_bit(trans, CSR_OTP_GP_REG,
 408                             CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
 409                             CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
 410                 /* traversing the linked list if no shadow ram supported */
 411                 if (!trans->cfg->base_params->shadow_ram_support) {
 412                         ret = iwl_find_otp_image(trans, &validblockaddr);
 413                         if (ret)
 414                                 goto err_unlock;
 415                 }
 416                 for (addr = validblockaddr; addr < validblockaddr + sz;
 417                      addr += sizeof(u16)) {
 418                         __le16 eeprom_data;
 419
 420                         ret = iwl_read_otp_word(trans, addr, &eeprom_data);
 421                         if (ret)
 422                                 goto err_unlock;
 423                         e[cache_addr / 2] = eeprom_data;
 424                         cache_addr += sizeof(u16);
 425                 }
 426         } else {
 427                 /* eeprom is an array of 16bit values */
 428                 for (addr = 0; addr < sz; addr += sizeof(u16)) {
 429                         u32 r;
 430
 431                         iwl_write32(trans, CSR_EEPROM_REG,
 432                                     CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
 433
 434                         ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
 435                                            CSR_EEPROM_REG_READ_VALID_MSK,
 436                                            CSR_EEPROM_REG_READ_VALID_MSK,
 437                                            IWL_EEPROM_ACCESS_TIMEOUT);
 438                         if (ret < 0) {
 439                                 IWL_ERR(trans,
 440                                         "Time out reading EEPROM[%d]\n", addr);
 441                                 goto err_unlock;
 442                         }
 443                         r = iwl_read32(trans, CSR_EEPROM_REG);
 444                         e[addr / 2] = cpu_to_le16(r >> 16);
 445                 }
 446         }
 447
 448         IWL_DEBUG_EEPROM(trans->dev, "NVM Type: %s\n",
 449                          nvm_is_otp ? "OTP" : "EEPROM");
 450
 451         iwl_eeprom_release_semaphore(trans);
 452
 453         *eeprom_size = sz;
 454         *eeprom = (u8 *)e;
 455         return 0;
 456
 457  err_unlock:
 458         iwl_eeprom_release_semaphore(trans);
 459  err_free:
 460         kfree(e);
 461
 462         return ret;
 463 }
 464 IWL_EXPORT_SYMBOL(iwl_read_eeprom);