]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blob - drivers/net/wireless/iwlwifi/iwl-trans-pcie.c
projects / mirror_ubuntu-jammy-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
iwlwifi: process multiple frames per RXB
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / iwlwifi / iwl-trans-pcie.c
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
70
71 #include "iwl-trans.h"
72 #include "iwl-trans-pcie-int.h"
73 #include "iwl-csr.h"
74 #include "iwl-prph.h"
75 #include "iwl-shared.h"
76 #include "iwl-eeprom.h"
77 #include "iwl-agn-hw.h"
78
79 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
80
81 #define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie) \
82 (((1<<cfg(trans)->base_params->num_of_queues) - 1) &\
83 (~(1<<(trans_pcie)->cmd_queue)))
84
85 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
86 {
87 struct iwl_trans_pcie *trans_pcie =
88 IWL_TRANS_GET_PCIE_TRANS(trans);
89 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
90 struct device *dev = trans->dev;
91
92 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
93
94 spin_lock_init(&rxq->lock);
95
96 if (WARN_ON(rxq->bd || rxq->rb_stts))
97 return -EINVAL;
98
99 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
100 rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
101 &rxq->bd_dma, GFP_KERNEL);
102 if (!rxq->bd)
103 goto err_bd;
104
105 /*Allocate the driver's pointer to receive buffer status */
106 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
107 &rxq->rb_stts_dma, GFP_KERNEL);
108 if (!rxq->rb_stts)
109 goto err_rb_stts;
110
111 return 0;
112
113 err_rb_stts:
114 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
115 rxq->bd, rxq->bd_dma);
116 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
117 rxq->bd = NULL;
118 err_bd:
119 return -ENOMEM;
120 }
121
122 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
123 {
124 struct iwl_trans_pcie *trans_pcie =
125 IWL_TRANS_GET_PCIE_TRANS(trans);
126 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
127 int i;
128
129 /* Fill the rx_used queue with _all_ of the Rx buffers */
130 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
131 /* In the reset function, these buffers may have been allocated
132 * to an SKB, so we need to unmap and free potential storage */
133 if (rxq->pool[i].page != NULL) {
134 dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
135 PAGE_SIZE << hw_params(trans).rx_page_order,
136 DMA_FROM_DEVICE);
137 __free_pages(rxq->pool[i].page,
138 hw_params(trans).rx_page_order);
139 rxq->pool[i].page = NULL;
140 }
141 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
142 }
143 }
144
145 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
146 struct iwl_rx_queue *rxq)
147 {
148 u32 rb_size;
149 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
150 u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
151
152 if (iwlagn_mod_params.amsdu_size_8K)
153 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
154 else
155 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
156
157 /* Stop Rx DMA */
158 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
159
160 /* Reset driver's Rx queue write index */
161 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
162
163 /* Tell device where to find RBD circular buffer in DRAM */
164 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
165 (u32)(rxq->bd_dma >> 8));
166
167 /* Tell device where in DRAM to update its Rx status */
168 iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
169 rxq->rb_stts_dma >> 4);
170
171 /* Enable Rx DMA
172 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
173 * the credit mechanism in 5000 HW RX FIFO
174 * Direct rx interrupts to hosts
175 * Rx buffer size 4 or 8k
176 * RB timeout 0x10
177 * 256 RBDs
178 */
179 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
180 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
181 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
182 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
183 rb_size|
184 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
185 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
186
187 /* Set interrupt coalescing timer to default (2048 usecs) */
188 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
189 }
190
191 static int iwl_rx_init(struct iwl_trans *trans)
192 {
193 struct iwl_trans_pcie *trans_pcie =
194 IWL_TRANS_GET_PCIE_TRANS(trans);
195 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
196
197 int i, err;
198 unsigned long flags;
199
200 if (!rxq->bd) {
201 err = iwl_trans_rx_alloc(trans);
202 if (err)
203 return err;
204 }
205
206 spin_lock_irqsave(&rxq->lock, flags);
207 INIT_LIST_HEAD(&rxq->rx_free);
208 INIT_LIST_HEAD(&rxq->rx_used);
209
210 iwl_trans_rxq_free_rx_bufs(trans);
211
212 for (i = 0; i < RX_QUEUE_SIZE; i++)
213 rxq->queue[i] = NULL;
214
215 /* Set us so that we have processed and used all buffers, but have
216 * not restocked the Rx queue with fresh buffers */
217 rxq->read = rxq->write = 0;
218 rxq->write_actual = 0;
219 rxq->free_count = 0;
220 spin_unlock_irqrestore(&rxq->lock, flags);
221
222 iwlagn_rx_replenish(trans);
223
224 iwl_trans_rx_hw_init(trans, rxq);
225
226 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
227 rxq->need_update = 1;
228 iwl_rx_queue_update_write_ptr(trans, rxq);
229 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
230
231 return 0;
232 }
233
234 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
235 {
236 struct iwl_trans_pcie *trans_pcie =
237 IWL_TRANS_GET_PCIE_TRANS(trans);
238 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
239
240 unsigned long flags;
241
242 /*if rxq->bd is NULL, it means that nothing has been allocated,
243 * exit now */
244 if (!rxq->bd) {
245 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
246 return;
247 }
248
249 spin_lock_irqsave(&rxq->lock, flags);
250 iwl_trans_rxq_free_rx_bufs(trans);
251 spin_unlock_irqrestore(&rxq->lock, flags);
252
253 dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
254 rxq->bd, rxq->bd_dma);
255 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
256 rxq->bd = NULL;
257
258 if (rxq->rb_stts)
259 dma_free_coherent(trans->dev,
260 sizeof(struct iwl_rb_status),
261 rxq->rb_stts, rxq->rb_stts_dma);
262 else
263 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
264 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
265 rxq->rb_stts = NULL;
266 }
267
268 static int iwl_trans_rx_stop(struct iwl_trans *trans)
269 {
270
271 /* stop Rx DMA */
272 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
273 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
274 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
275 }
276
277 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
278 struct iwl_dma_ptr *ptr, size_t size)
279 {
280 if (WARN_ON(ptr->addr))
281 return -EINVAL;
282
283 ptr->addr = dma_alloc_coherent(trans->dev, size,
284 &ptr->dma, GFP_KERNEL);
285 if (!ptr->addr)
286 return -ENOMEM;
287 ptr->size = size;
288 return 0;
289 }
290
291 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
292 struct iwl_dma_ptr *ptr)
293 {
294 if (unlikely(!ptr->addr))
295 return;
296
297 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
298 memset(ptr, 0, sizeof(*ptr));
299 }
300
301 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
302 struct iwl_tx_queue *txq, int slots_num,
303 u32 txq_id)
304 {
305 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
306 int i;
307 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
308
309 if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
310 return -EINVAL;
311
312 txq->q.n_window = slots_num;
313
314 txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL);
315 txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL);
316
317 if (!txq->meta || !txq->cmd)
318 goto error;
319
320 if (txq_id == trans_pcie->cmd_queue)
321 for (i = 0; i < slots_num; i++) {
322 txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
323 GFP_KERNEL);
324 if (!txq->cmd[i])
325 goto error;
326 }
327
328 /* Alloc driver data array and TFD circular buffer */
329 /* Driver private data, only for Tx (not command) queues,
330 * not shared with device. */
331 if (txq_id != trans_pcie->cmd_queue) {
332 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]),
333 GFP_KERNEL);
334 if (!txq->skbs) {
335 IWL_ERR(trans, "kmalloc for auxiliary BD "
336 "structures failed\n");
337 goto error;
338 }
339 } else {
340 txq->skbs = NULL;
341 }
342
343 /* Circular buffer of transmit frame descriptors (TFDs),
344 * shared with device */
345 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
346 &txq->q.dma_addr, GFP_KERNEL);
347 if (!txq->tfds) {
348 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
349 goto error;
350 }
351 txq->q.id = txq_id;
352
353 return 0;
354 error:
355 kfree(txq->skbs);
356 txq->skbs = NULL;
357 /* since txq->cmd has been zeroed,
358 * all non allocated cmd[i] will be NULL */
359 if (txq->cmd && txq_id == trans_pcie->cmd_queue)
360 for (i = 0; i < slots_num; i++)
361 kfree(txq->cmd[i]);
362 kfree(txq->meta);
363 kfree(txq->cmd);
364 txq->meta = NULL;
365 txq->cmd = NULL;
366
367 return -ENOMEM;
368
369 }
370
371 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
372 int slots_num, u32 txq_id)
373 {
374 int ret;
375
376 txq->need_update = 0;
377 memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
378
379 /*
380 * For the default queues 0-3, set up the swq_id
381 * already -- all others need to get one later
382 * (if they need one at all).
383 */
384 if (txq_id < 4)
385 iwl_set_swq_id(txq, txq_id, txq_id);
386
387 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
388 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
389 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
390
391 /* Initialize queue's high/low-water marks, and head/tail indexes */
392 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
393 txq_id);
394 if (ret)
395 return ret;
396
397 spin_lock_init(&txq->lock);
398
399 /*
400 * Tell nic where to find circular buffer of Tx Frame Descriptors for
401 * given Tx queue, and enable the DMA channel used for that queue.
402 * Circular buffer (TFD queue in DRAM) physical base address */
403 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
404 txq->q.dma_addr >> 8);
405
406 return 0;
407 }
408
409 /**
410 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
411 */
412 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
413 {
414 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
415 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
416 struct iwl_queue *q = &txq->q;
417 enum dma_data_direction dma_dir;
418
419 if (!q->n_bd)
420 return;
421
422 /* In the command queue, all the TBs are mapped as BIDI
423 * so unmap them as such.
424 */
425 if (txq_id == trans_pcie->cmd_queue)
426 dma_dir = DMA_BIDIRECTIONAL;
427 else
428 dma_dir = DMA_TO_DEVICE;
429
430 spin_lock_bh(&txq->lock);
431 while (q->write_ptr != q->read_ptr) {
432 /* The read_ptr needs to bound by q->n_window */
433 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
434 dma_dir);
435 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
436 }
437 spin_unlock_bh(&txq->lock);
438 }
439
440 /**
441 * iwl_tx_queue_free - Deallocate DMA queue.
442 * @txq: Transmit queue to deallocate.
443 *
444 * Empty queue by removing and destroying all BD's.
445 * Free all buffers.
446 * 0-fill, but do not free "txq" descriptor structure.
447 */
448 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
449 {
450 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
451 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
452 struct device *dev = trans->dev;
453 int i;
454 if (WARN_ON(!txq))
455 return;
456
457 iwl_tx_queue_unmap(trans, txq_id);
458
459 /* De-alloc array of command/tx buffers */
460
461 if (txq_id == trans_pcie->cmd_queue)
462 for (i = 0; i < txq->q.n_window; i++)
463 kfree(txq->cmd[i]);
464
465 /* De-alloc circular buffer of TFDs */
466 if (txq->q.n_bd) {
467 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
468 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
469 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
470 }
471
472 /* De-alloc array of per-TFD driver data */
473 kfree(txq->skbs);
474 txq->skbs = NULL;
475
476 /* deallocate arrays */
477 kfree(txq->cmd);
478 kfree(txq->meta);
479 txq->cmd = NULL;
480 txq->meta = NULL;
481
482 /* 0-fill queue descriptor structure */
483 memset(txq, 0, sizeof(*txq));
484 }
485
486 /**
487 * iwl_trans_tx_free - Free TXQ Context
488 *
489 * Destroy all TX DMA queues and structures
490 */
491 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
492 {
493 int txq_id;
494 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
495
496 /* Tx queues */
497 if (trans_pcie->txq) {
498 for (txq_id = 0;
499 txq_id < cfg(trans)->base_params->num_of_queues; txq_id++)
500 iwl_tx_queue_free(trans, txq_id);
501 }
502
503 kfree(trans_pcie->txq);
504 trans_pcie->txq = NULL;
505
506 iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
507
508 iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
509 }
510
511 /**
512 * iwl_trans_tx_alloc - allocate TX context
513 * Allocate all Tx DMA structures and initialize them
514 *
515 * @param priv
516 * @return error code
517 */
518 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
519 {
520 int ret;
521 int txq_id, slots_num;
522 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
523
524 u16 scd_bc_tbls_size = cfg(trans)->base_params->num_of_queues *
525 sizeof(struct iwlagn_scd_bc_tbl);
526
527 /*It is not allowed to alloc twice, so warn when this happens.
528 * We cannot rely on the previous allocation, so free and fail */
529 if (WARN_ON(trans_pcie->txq)) {
530 ret = -EINVAL;
531 goto error;
532 }
533
534 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
535 scd_bc_tbls_size);
536 if (ret) {
537 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
538 goto error;
539 }
540
541 /* Alloc keep-warm buffer */
542 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
543 if (ret) {
544 IWL_ERR(trans, "Keep Warm allocation failed\n");
545 goto error;
546 }
547
548 trans_pcie->txq = kcalloc(cfg(trans)->base_params->num_of_queues,
549 sizeof(struct iwl_tx_queue), GFP_KERNEL);
550 if (!trans_pcie->txq) {
551 IWL_ERR(trans, "Not enough memory for txq\n");
552 ret = ENOMEM;
553 goto error;
554 }
555
556 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
557 for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
558 txq_id++) {
559 slots_num = (txq_id == trans_pcie->cmd_queue) ?
560 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
561 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
562 slots_num, txq_id);
563 if (ret) {
564 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
565 goto error;
566 }
567 }
568
569 return 0;
570
571 error:
572 iwl_trans_pcie_tx_free(trans);
573
574 return ret;
575 }
576 static int iwl_tx_init(struct iwl_trans *trans)
577 {
578 int ret;
579 int txq_id, slots_num;
580 unsigned long flags;
581 bool alloc = false;
582 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
583
584 if (!trans_pcie->txq) {
585 ret = iwl_trans_tx_alloc(trans);
586 if (ret)
587 goto error;
588 alloc = true;
589 }
590
591 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
592
593 /* Turn off all Tx DMA fifos */
594 iwl_write_prph(trans, SCD_TXFACT, 0);
595
596 /* Tell NIC where to find the "keep warm" buffer */
597 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
598 trans_pcie->kw.dma >> 4);
599
600 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
601
602 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
603 for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
604 txq_id++) {
605 slots_num = (txq_id == trans_pcie->cmd_queue) ?
606 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
607 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
608 slots_num, txq_id);
609 if (ret) {
610 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
611 goto error;
612 }
613 }
614
615 return 0;
616 error:
617 /*Upon error, free only if we allocated something */
618 if (alloc)
619 iwl_trans_pcie_tx_free(trans);
620 return ret;
621 }
622
623 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
624 {
625 /*
626 * (for documentation purposes)
627 * to set power to V_AUX, do:
628
629 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
630 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
631 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
632 ~APMG_PS_CTRL_MSK_PWR_SRC);
633 */
634
635 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
636 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
637 ~APMG_PS_CTRL_MSK_PWR_SRC);
638 }
639
640 /* PCI registers */
641 #define PCI_CFG_RETRY_TIMEOUT 0x041
642 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
643 #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
644
645 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
646 {
647 int pos;
648 u16 pci_lnk_ctl;
649 struct iwl_trans_pcie *trans_pcie =
650 IWL_TRANS_GET_PCIE_TRANS(trans);
651
652 struct pci_dev *pci_dev = trans_pcie->pci_dev;
653
654 pos = pci_pcie_cap(pci_dev);
655 pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
656 return pci_lnk_ctl;
657 }
658
659 static void iwl_apm_config(struct iwl_trans *trans)
660 {
661 /*
662 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
663 * Check if BIOS (or OS) enabled L1-ASPM on this device.
664 * If so (likely), disable L0S, so device moves directly L0->L1;
665 * costs negligible amount of power savings.
666 * If not (unlikely), enable L0S, so there is at least some
667 * power savings, even without L1.
668 */
669 u16 lctl = iwl_pciexp_link_ctrl(trans);
670
671 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
672 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
673 /* L1-ASPM enabled; disable(!) L0S */
674 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
675 dev_printk(KERN_INFO, trans->dev,
676 "L1 Enabled; Disabling L0S\n");
677 } else {
678 /* L1-ASPM disabled; enable(!) L0S */
679 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
680 dev_printk(KERN_INFO, trans->dev,
681 "L1 Disabled; Enabling L0S\n");
682 }
683 trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
684 }
685
686 /*
687 * Start up NIC's basic functionality after it has been reset
688 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
689 * NOTE: This does not load uCode nor start the embedded processor
690 */
691 static int iwl_apm_init(struct iwl_trans *trans)
692 {
693 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
694 int ret = 0;
695 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
696
697 /*
698 * Use "set_bit" below rather than "write", to preserve any hardware
699 * bits already set by default after reset.
700 */
701
702 /* Disable L0S exit timer (platform NMI Work/Around) */
703 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
704 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
705
706 /*
707 * Disable L0s without affecting L1;
708 * don't wait for ICH L0s (ICH bug W/A)
709 */
710 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
711 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
712
713 /* Set FH wait threshold to maximum (HW error during stress W/A) */
714 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
715
716 /*
717 * Enable HAP INTA (interrupt from management bus) to
718 * wake device's PCI Express link L1a -> L0s
719 */
720 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
721 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
722
723 iwl_apm_config(trans);
724
725 /* Configure analog phase-lock-loop before activating to D0A */
726 if (cfg(trans)->base_params->pll_cfg_val)
727 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
728 cfg(trans)->base_params->pll_cfg_val);
729
730 /*
731 * Set "initialization complete" bit to move adapter from
732 * D0U* --> D0A* (powered-up active) state.
733 */
734 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
735
736 /*
737 * Wait for clock stabilization; once stabilized, access to
738 * device-internal resources is supported, e.g. iwl_write_prph()
739 * and accesses to uCode SRAM.
740 */
741 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
742 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
743 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
744 if (ret < 0) {
745 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
746 goto out;
747 }
748
749 /*
750 * Enable DMA clock and wait for it to stabilize.
751 *
752 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
753 * do not disable clocks. This preserves any hardware bits already
754 * set by default in "CLK_CTRL_REG" after reset.
755 */
756 iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
757 udelay(20);
758
759 /* Disable L1-Active */
760 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
761 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
762
763 set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
764
765 out:
766 return ret;
767 }
768
769 static int iwl_apm_stop_master(struct iwl_trans *trans)
770 {
771 int ret = 0;
772
773 /* stop device's busmaster DMA activity */
774 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
775
776 ret = iwl_poll_bit(trans, CSR_RESET,
777 CSR_RESET_REG_FLAG_MASTER_DISABLED,
778 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
779 if (ret)
780 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
781
782 IWL_DEBUG_INFO(trans, "stop master\n");
783
784 return ret;
785 }
786
787 static void iwl_apm_stop(struct iwl_trans *trans)
788 {
789 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
790 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
791
792 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
793
794 /* Stop device's DMA activity */
795 iwl_apm_stop_master(trans);
796
797 /* Reset the entire device */
798 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
799
800 udelay(10);
801
802 /*
803 * Clear "initialization complete" bit to move adapter from
804 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
805 */
806 iwl_clear_bit(trans, CSR_GP_CNTRL,
807 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
808 }
809
810 static int iwl_nic_init(struct iwl_trans *trans)
811 {
812 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
813 unsigned long flags;
814
815 /* nic_init */
816 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
817 iwl_apm_init(trans);
818
819 /* Set interrupt coalescing calibration timer to default (512 usecs) */
820 iwl_write8(trans, CSR_INT_COALESCING,
821 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
822
823 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
824
825 iwl_set_pwr_vmain(trans);
826
827 iwl_op_mode_nic_config(trans->op_mode);
828
829 #ifndef CONFIG_IWLWIFI_IDI
830 /* Allocate the RX queue, or reset if it is already allocated */
831 iwl_rx_init(trans);
832 #endif
833
834 /* Allocate or reset and init all Tx and Command queues */
835 if (iwl_tx_init(trans))
836 return -ENOMEM;
837
838 if (cfg(trans)->base_params->shadow_reg_enable) {
839 /* enable shadow regs in HW */
840 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
841 0x800FFFFF);
842 }
843
844 return 0;
845 }
846
847 #define HW_READY_TIMEOUT (50)
848
849 /* Note: returns poll_bit return value, which is >= 0 if success */
850 static int iwl_set_hw_ready(struct iwl_trans *trans)
851 {
852 int ret;
853
854 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
855 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
856
857 /* See if we got it */
858 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
859 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
860 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
861 HW_READY_TIMEOUT);
862
863 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
864 return ret;
865 }
866
867 /* Note: returns standard 0/-ERROR code */
868 static int iwl_prepare_card_hw(struct iwl_trans *trans)
869 {
870 int ret;
871
872 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
873
874 ret = iwl_set_hw_ready(trans);
875 /* If the card is ready, exit 0 */
876 if (ret >= 0)
877 return 0;
878
879 /* If HW is not ready, prepare the conditions to check again */
880 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
881 CSR_HW_IF_CONFIG_REG_PREPARE);
882
883 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
884 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
885 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
886
887 if (ret < 0)
888 return ret;
889
890 /* HW should be ready by now, check again. */
891 ret = iwl_set_hw_ready(trans);
892 if (ret >= 0)
893 return 0;
894 return ret;
895 }
896
897 #define IWL_AC_UNSET -1
898
899 struct queue_to_fifo_ac {
900 s8 fifo, ac;
901 };
902
903 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
904 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
905 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
906 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
907 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
908 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
909 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
910 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
911 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
912 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
913 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
914 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
915 };
916
917 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
918 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
919 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
920 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
921 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
922 { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
923 { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
924 { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
925 { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
926 { IWL_TX_FIFO_BE_IPAN, 2, },
927 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
928 { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
929 };
930
931 static const u8 iwlagn_bss_ac_to_fifo[] = {
932 IWL_TX_FIFO_VO,
933 IWL_TX_FIFO_VI,
934 IWL_TX_FIFO_BE,
935 IWL_TX_FIFO_BK,
936 };
937 static const u8 iwlagn_bss_ac_to_queue[] = {
938 0, 1, 2, 3,
939 };
940 static const u8 iwlagn_pan_ac_to_fifo[] = {
941 IWL_TX_FIFO_VO_IPAN,
942 IWL_TX_FIFO_VI_IPAN,
943 IWL_TX_FIFO_BE_IPAN,
944 IWL_TX_FIFO_BK_IPAN,
945 };
946 static const u8 iwlagn_pan_ac_to_queue[] = {
947 7, 6, 5, 4,
948 };
949
950 /*
951 * ucode
952 */
953 static int iwl_load_section(struct iwl_trans *trans, u8 section_num,
954 const struct fw_desc *section)
955 {
956 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
957 dma_addr_t phy_addr = section->p_addr;
958 u32 byte_cnt = section->len;
959 u32 dst_addr = section->offset;
960 int ret;
961
962 trans_pcie->ucode_write_complete = false;
963
964 iwl_write_direct32(trans,
965 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
966 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
967
968 iwl_write_direct32(trans,
969 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
970
971 iwl_write_direct32(trans,
972 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
973 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
974
975 iwl_write_direct32(trans,
976 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
977 (iwl_get_dma_hi_addr(phy_addr)
978 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
979
980 iwl_write_direct32(trans,
981 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
982 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
983 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
984 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
985
986 iwl_write_direct32(trans,
987 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
988 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
989 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
990 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
991
992 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
993 section_num);
994 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
995 trans_pcie->ucode_write_complete, 5 * HZ);
996 if (!ret) {
997 IWL_ERR(trans, "Could not load the [%d] uCode section\n",
998 section_num);
999 return -ETIMEDOUT;
1000 }
1001
1002 return 0;
1003 }
1004
1005 static int iwl_load_given_ucode(struct iwl_trans *trans,
1006 const struct fw_img *image)
1007 {
1008 int ret = 0;
1009 int i;
1010
1011 for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
1012 if (!image->sec[i].p_addr)
1013 break;
1014
1015 ret = iwl_load_section(trans, i, &image->sec[i]);
1016 if (ret)
1017 return ret;
1018 }
1019
1020 /* Remove all resets to allow NIC to operate */
1021 iwl_write32(trans, CSR_RESET, 0);
1022
1023 return 0;
1024 }
1025
1026 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1027 const struct fw_img *fw)
1028 {
1029 int ret;
1030 struct iwl_trans_pcie *trans_pcie =
1031 IWL_TRANS_GET_PCIE_TRANS(trans);
1032 bool hw_rfkill;
1033
1034 trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
1035 trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
1036
1037 trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
1038 trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
1039
1040 trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
1041 trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
1042
1043 /* This may fail if AMT took ownership of the device */
1044 if (iwl_prepare_card_hw(trans)) {
1045 IWL_WARN(trans, "Exit HW not ready\n");
1046 return -EIO;
1047 }
1048
1049 /* If platform's RF_KILL switch is NOT set to KILL */
1050 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1051 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1052 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1053
1054 if (hw_rfkill) {
1055 iwl_enable_rfkill_int(trans);
1056 return -ERFKILL;
1057 }
1058
1059 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1060
1061 ret = iwl_nic_init(trans);
1062 if (ret) {
1063 IWL_ERR(trans, "Unable to init nic\n");
1064 return ret;
1065 }
1066
1067 /* make sure rfkill handshake bits are cleared */
1068 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1069 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1070 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1071
1072 /* clear (again), then enable host interrupts */
1073 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1074 iwl_enable_interrupts(trans);
1075
1076 /* really make sure rfkill handshake bits are cleared */
1077 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1078 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1079
1080 /* Load the given image to the HW */
1081 return iwl_load_given_ucode(trans, fw);
1082 }
1083
1084 /*
1085 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1086 * must be called under the irq lock and with MAC access
1087 */
1088 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1089 {
1090 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1091 IWL_TRANS_GET_PCIE_TRANS(trans);
1092
1093 lockdep_assert_held(&trans_pcie->irq_lock);
1094
1095 iwl_write_prph(trans, SCD_TXFACT, mask);
1096 }
1097
1098 static void iwl_tx_start(struct iwl_trans *trans)
1099 {
1100 const struct queue_to_fifo_ac *queue_to_fifo;
1101 struct iwl_trans_pcie *trans_pcie =
1102 IWL_TRANS_GET_PCIE_TRANS(trans);
1103 u32 a;
1104 unsigned long flags;
1105 int i, chan;
1106 u32 reg_val;
1107
1108 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1109
1110 trans_pcie->scd_base_addr =
1111 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1112 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1113 /* reset conext data memory */
1114 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1115 a += 4)
1116 iwl_write_targ_mem(trans, a, 0);
1117 /* reset tx status memory */
1118 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1119 a += 4)
1120 iwl_write_targ_mem(trans, a, 0);
1121 for (; a < trans_pcie->scd_base_addr +
1122 SCD_TRANS_TBL_OFFSET_QUEUE(
1123 cfg(trans)->base_params->num_of_queues);
1124 a += 4)
1125 iwl_write_targ_mem(trans, a, 0);
1126
1127 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1128 trans_pcie->scd_bc_tbls.dma >> 10);
1129
1130 /* Enable DMA channel */
1131 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1132 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1133 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1134 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1135
1136 /* Update FH chicken bits */
1137 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1138 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1139 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1140
1141 iwl_write_prph(trans, SCD_QUEUECHAIN_SEL,
1142 SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie));
1143 iwl_write_prph(trans, SCD_AGGR_SEL, 0);
1144
1145 /* initiate the queues */
1146 for (i = 0; i < cfg(trans)->base_params->num_of_queues; i++) {
1147 iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
1148 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
1149 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1150 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
1151 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1152 SCD_CONTEXT_QUEUE_OFFSET(i) +
1153 sizeof(u32),
1154 ((SCD_WIN_SIZE <<
1155 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1156 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1157 ((SCD_FRAME_LIMIT <<
1158 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1159 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1160 }
1161
1162 iwl_write_prph(trans, SCD_INTERRUPT_MASK,
1163 IWL_MASK(0, cfg(trans)->base_params->num_of_queues));
1164
1165 /* Activate all Tx DMA/FIFO channels */
1166 iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1167
1168 /* map queues to FIFOs */
1169 if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1170 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
1171 else
1172 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
1173
1174 iwl_trans_set_wr_ptrs(trans, trans_pcie->cmd_queue, 0);
1175
1176 /* make sure all queue are not stopped */
1177 memset(&trans_pcie->queue_stopped[0], 0,
1178 sizeof(trans_pcie->queue_stopped));
1179 for (i = 0; i < 4; i++)
1180 atomic_set(&trans_pcie->queue_stop_count[i], 0);
1181
1182 /* reset to 0 to enable all the queue first */
1183 trans_pcie->txq_ctx_active_msk = 0;
1184
1185 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
1186 IWLAGN_FIRST_AMPDU_QUEUE);
1187 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
1188 IWLAGN_FIRST_AMPDU_QUEUE);
1189
1190 for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
1191 int fifo = queue_to_fifo[i].fifo;
1192 int ac = queue_to_fifo[i].ac;
1193
1194 iwl_txq_ctx_activate(trans_pcie, i);
1195
1196 if (fifo == IWL_TX_FIFO_UNUSED)
1197 continue;
1198
1199 if (ac != IWL_AC_UNSET)
1200 iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
1201 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
1202 fifo, 0);
1203 }
1204
1205 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1206
1207 /* Enable L1-Active */
1208 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1209 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1210 }
1211
1212 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1213 {
1214 iwl_reset_ict(trans);
1215 iwl_tx_start(trans);
1216 }
1217
1218 /**
1219 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1220 */
1221 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1222 {
1223 int ch, txq_id, ret;
1224 unsigned long flags;
1225 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1226
1227 /* Turn off all Tx DMA fifos */
1228 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1229
1230 iwl_trans_txq_set_sched(trans, 0);
1231
1232 /* Stop each Tx DMA channel, and wait for it to be idle */
1233 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1234 iwl_write_direct32(trans,
1235 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1236 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1237 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
1238 1000);
1239 if (ret < 0)
1240 IWL_ERR(trans, "Failing on timeout while stopping"
1241 " DMA channel %d [0x%08x]", ch,
1242 iwl_read_direct32(trans,
1243 FH_TSSR_TX_STATUS_REG));
1244 }
1245 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1246
1247 if (!trans_pcie->txq) {
1248 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
1249 return 0;
1250 }
1251
1252 /* Unmap DMA from host system and free skb's */
1253 for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
1254 txq_id++)
1255 iwl_tx_queue_unmap(trans, txq_id);
1256
1257 return 0;
1258 }
1259
1260 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1261 {
1262 unsigned long flags;
1263 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1264
1265 /* tell the device to stop sending interrupts */
1266 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1267 iwl_disable_interrupts(trans);
1268 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1269
1270 /* device going down, Stop using ICT table */
1271 iwl_disable_ict(trans);
1272
1273 /*
1274 * If a HW restart happens during firmware loading,
1275 * then the firmware loading might call this function
1276 * and later it might be called again due to the
1277 * restart. So don't process again if the device is
1278 * already dead.
1279 */
1280 if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
1281 iwl_trans_tx_stop(trans);
1282 #ifndef CONFIG_IWLWIFI_IDI
1283 iwl_trans_rx_stop(trans);
1284 #endif
1285 /* Power-down device's busmaster DMA clocks */
1286 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1287 APMG_CLK_VAL_DMA_CLK_RQT);
1288 udelay(5);
1289 }
1290
1291 /* Make sure (redundant) we've released our request to stay awake */
1292 iwl_clear_bit(trans, CSR_GP_CNTRL,
1293 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1294
1295 /* Stop the device, and put it in low power state */
1296 iwl_apm_stop(trans);
1297
1298 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1299 * Clean again the interrupt here
1300 */
1301 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1302 iwl_disable_interrupts(trans);
1303 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1304
1305 /* wait to make sure we flush pending tasklet*/
1306 synchronize_irq(trans_pcie->irq);
1307 tasklet_kill(&trans_pcie->irq_tasklet);
1308
1309 cancel_work_sync(&trans_pcie->rx_replenish);
1310
1311 /* stop and reset the on-board processor */
1312 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1313 }
1314
1315 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1316 {
1317 /* let the ucode operate on its own */
1318 iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1319 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1320
1321 iwl_disable_interrupts(trans);
1322 iwl_clear_bit(trans, CSR_GP_CNTRL,
1323 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1324 }
1325
1326 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1327 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1328 u8 sta_id, u8 tid)
1329 {
1330 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1331 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1332 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1333 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1334 struct iwl_cmd_meta *out_meta;
1335 struct iwl_tx_queue *txq;
1336 struct iwl_queue *q;
1337
1338 dma_addr_t phys_addr = 0;
1339 dma_addr_t txcmd_phys;
1340 dma_addr_t scratch_phys;
1341 u16 len, firstlen, secondlen;
1342 u8 wait_write_ptr = 0;
1343 u8 txq_id;
1344 bool is_agg = false;
1345 __le16 fc = hdr->frame_control;
1346 u8 hdr_len = ieee80211_hdrlen(fc);
1347 u16 __maybe_unused wifi_seq;
1348
1349 /*
1350 * Send this frame after DTIM -- there's a special queue
1351 * reserved for this for contexts that support AP mode.
1352 */
1353 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1354 txq_id = trans_pcie->mcast_queue[ctx];
1355
1356 /*
1357 * The microcode will clear the more data
1358 * bit in the last frame it transmits.
1359 */
1360 hdr->frame_control |=
1361 cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1362 } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1363 txq_id = IWL_AUX_QUEUE;
1364 else
1365 txq_id =
1366 trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1367
1368 /* aggregation is on for this <sta,tid> */
1369 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
1370 WARN_ON(tid >= IWL_MAX_TID_COUNT);
1371 txq_id = trans_pcie->agg_txq[sta_id][tid];
1372 is_agg = true;
1373 }
1374
1375 txq = &trans_pcie->txq[txq_id];
1376 q = &txq->q;
1377
1378 spin_lock(&txq->lock);
1379
1380 /* In AGG mode, the index in the ring must correspond to the WiFi
1381 * sequence number. This is a HW requirements to help the SCD to parse
1382 * the BA.
1383 * Check here that the packets are in the right place on the ring.
1384 */
1385 #ifdef CONFIG_IWLWIFI_DEBUG
1386 wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1387 WARN_ONCE(is_agg && ((wifi_seq & 0xff) != q->write_ptr),
1388 "Q: %d WiFi Seq %d tfdNum %d",
1389 txq_id, wifi_seq, q->write_ptr);
1390 #endif
1391
1392 /* Set up driver data for this TFD */
1393 txq->skbs[q->write_ptr] = skb;
1394 txq->cmd[q->write_ptr] = dev_cmd;
1395
1396 dev_cmd->hdr.cmd = REPLY_TX;
1397 dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1398 INDEX_TO_SEQ(q->write_ptr)));
1399
1400 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1401 out_meta = &txq->meta[q->write_ptr];
1402
1403 /*
1404 * Use the first empty entry in this queue's command buffer array
1405 * to contain the Tx command and MAC header concatenated together
1406 * (payload data will be in another buffer).
1407 * Size of this varies, due to varying MAC header length.
1408 * If end is not dword aligned, we'll have 2 extra bytes at the end
1409 * of the MAC header (device reads on dword boundaries).
1410 * We'll tell device about this padding later.
1411 */
1412 len = sizeof(struct iwl_tx_cmd) +
1413 sizeof(struct iwl_cmd_header) + hdr_len;
1414 firstlen = (len + 3) & ~3;
1415
1416 /* Tell NIC about any 2-byte padding after MAC header */
1417 if (firstlen != len)
1418 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1419
1420 /* Physical address of this Tx command's header (not MAC header!),
1421 * within command buffer array. */
1422 txcmd_phys = dma_map_single(trans->dev,
1423 &dev_cmd->hdr, firstlen,
1424 DMA_BIDIRECTIONAL);
1425 if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1426 goto out_err;
1427 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1428 dma_unmap_len_set(out_meta, len, firstlen);
1429
1430 if (!ieee80211_has_morefrags(fc)) {
1431 txq->need_update = 1;
1432 } else {
1433 wait_write_ptr = 1;
1434 txq->need_update = 0;
1435 }
1436
1437 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1438 * if any (802.11 null frames have no payload). */
1439 secondlen = skb->len - hdr_len;
1440 if (secondlen > 0) {
1441 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1442 secondlen, DMA_TO_DEVICE);
1443 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1444 dma_unmap_single(trans->dev,
1445 dma_unmap_addr(out_meta, mapping),
1446 dma_unmap_len(out_meta, len),
1447 DMA_BIDIRECTIONAL);
1448 goto out_err;
1449 }
1450 }
1451
1452 /* Attach buffers to TFD */
1453 iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1454 if (secondlen > 0)
1455 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1456 secondlen, 0);
1457
1458 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1459 offsetof(struct iwl_tx_cmd, scratch);
1460
1461 /* take back ownership of DMA buffer to enable update */
1462 dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1463 DMA_BIDIRECTIONAL);
1464 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1465 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1466
1467 IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1468 le16_to_cpu(dev_cmd->hdr.sequence));
1469 IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1470
1471 /* Set up entry for this TFD in Tx byte-count array */
1472 iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1473
1474 dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1475 DMA_BIDIRECTIONAL);
1476
1477 trace_iwlwifi_dev_tx(trans->dev,
1478 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1479 sizeof(struct iwl_tfd),
1480 &dev_cmd->hdr, firstlen,
1481 skb->data + hdr_len, secondlen);
1482
1483 /* Tell device the write index *just past* this latest filled TFD */
1484 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1485 iwl_txq_update_write_ptr(trans, txq);
1486
1487 /*
1488 * At this point the frame is "transmitted" successfully
1489 * and we will get a TX status notification eventually,
1490 * regardless of the value of ret. "ret" only indicates
1491 * whether or not we should update the write pointer.
1492 */
1493 if (iwl_queue_space(q) < q->high_mark) {
1494 if (wait_write_ptr) {
1495 txq->need_update = 1;
1496 iwl_txq_update_write_ptr(trans, txq);
1497 } else {
1498 iwl_stop_queue(trans, txq);
1499 }
1500 }
1501 spin_unlock(&txq->lock);
1502 return 0;
1503 out_err:
1504 spin_unlock(&txq->lock);
1505 return -1;
1506 }
1507
1508 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1509 {
1510 struct iwl_trans_pcie *trans_pcie =
1511 IWL_TRANS_GET_PCIE_TRANS(trans);
1512 int err;
1513 bool hw_rfkill;
1514
1515 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1516
1517 if (!trans_pcie->irq_requested) {
1518 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1519 iwl_irq_tasklet, (unsigned long)trans);
1520
1521 iwl_alloc_isr_ict(trans);
1522
1523 err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED,
1524 DRV_NAME, trans);
1525 if (err) {
1526 IWL_ERR(trans, "Error allocating IRQ %d\n",
1527 trans_pcie->irq);
1528 goto error;
1529 }
1530
1531 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1532 trans_pcie->irq_requested = true;
1533 }
1534
1535 err = iwl_prepare_card_hw(trans);
1536 if (err) {
1537 IWL_ERR(trans, "Error while preparing HW: %d", err);
1538 goto err_free_irq;
1539 }
1540
1541 iwl_apm_init(trans);
1542
1543 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1544 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1545 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1546
1547 return err;
1548
1549 err_free_irq:
1550 free_irq(trans_pcie->irq, trans);
1551 error:
1552 iwl_free_isr_ict(trans);
1553 tasklet_kill(&trans_pcie->irq_tasklet);
1554 return err;
1555 }
1556
1557 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans)
1558 {
1559 iwl_apm_stop(trans);
1560
1561 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1562
1563 /* Even if we stop the HW, we still want the RF kill interrupt */
1564 iwl_enable_rfkill_int(trans);
1565 }
1566
1567 static int iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1568 int txq_id, int ssn, struct sk_buff_head *skbs)
1569 {
1570 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1571 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1572 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1573 int tfd_num = ssn & (txq->q.n_bd - 1);
1574 int freed = 0;
1575
1576 spin_lock(&txq->lock);
1577
1578 txq->time_stamp = jiffies;
1579
1580 if (unlikely(txq_id >= IWLAGN_FIRST_AMPDU_QUEUE &&
1581 tid != IWL_TID_NON_QOS &&
1582 txq_id != trans_pcie->agg_txq[sta_id][tid])) {
1583 /*
1584 * FIXME: this is a uCode bug which need to be addressed,
1585 * log the information and return for now.
1586 * Since it is can possibly happen very often and in order
1587 * not to fill the syslog, don't use IWL_ERR or IWL_WARN
1588 */
1589 IWL_DEBUG_TX_QUEUES(trans, "Bad queue mapping txq_id %d, "
1590 "agg_txq[sta_id[tid] %d", txq_id,
1591 trans_pcie->agg_txq[sta_id][tid]);
1592 spin_unlock(&txq->lock);
1593 return 1;
1594 }
1595
1596 if (txq->q.read_ptr != tfd_num) {
1597 IWL_DEBUG_TX_REPLY(trans, "[Q %d | AC %d] %d -> %d (%d)\n",
1598 txq_id, iwl_get_queue_ac(txq), txq->q.read_ptr,
1599 tfd_num, ssn);
1600 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1601 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1602 iwl_wake_queue(trans, txq);
1603 }
1604
1605 spin_unlock(&txq->lock);
1606 return 0;
1607 }
1608
1609 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1610 {
1611 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1612 }
1613
1614 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1615 {
1616 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1617 }
1618
1619 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1620 {
1621 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1622 }
1623
1624 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1625 const struct iwl_trans_config *trans_cfg)
1626 {
1627 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1628
1629 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1630 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1631 trans_pcie->n_no_reclaim_cmds = 0;
1632 else
1633 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1634 if (trans_pcie->n_no_reclaim_cmds)
1635 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1636 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1637 }
1638
1639 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1640 {
1641 struct iwl_trans_pcie *trans_pcie =
1642 IWL_TRANS_GET_PCIE_TRANS(trans);
1643
1644 iwl_trans_pcie_tx_free(trans);
1645 #ifndef CONFIG_IWLWIFI_IDI
1646 iwl_trans_pcie_rx_free(trans);
1647 #endif
1648 if (trans_pcie->irq_requested == true) {
1649 free_irq(trans_pcie->irq, trans);
1650 iwl_free_isr_ict(trans);
1651 }
1652
1653 pci_disable_msi(trans_pcie->pci_dev);
1654 iounmap(trans_pcie->hw_base);
1655 pci_release_regions(trans_pcie->pci_dev);
1656 pci_disable_device(trans_pcie->pci_dev);
1657
1658 trans->shrd->trans = NULL;
1659 kfree(trans);
1660 }
1661
1662 #ifdef CONFIG_PM_SLEEP
1663 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1664 {
1665 return 0;
1666 }
1667
1668 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1669 {
1670 bool hw_rfkill;
1671
1672 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1673 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1674
1675 if (hw_rfkill)
1676 iwl_enable_rfkill_int(trans);
1677 else
1678 iwl_enable_interrupts(trans);
1679
1680 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1681
1682 return 0;
1683 }
1684 #endif /* CONFIG_PM_SLEEP */
1685
1686 #define IWL_FLUSH_WAIT_MS 2000
1687
1688 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1689 {
1690 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1691 struct iwl_tx_queue *txq;
1692 struct iwl_queue *q;
1693 int cnt;
1694 unsigned long now = jiffies;
1695 int ret = 0;
1696
1697 /* waiting for all the tx frames complete might take a while */
1698 for (cnt = 0; cnt < cfg(trans)->base_params->num_of_queues; cnt++) {
1699 if (cnt == trans_pcie->cmd_queue)
1700 continue;
1701 txq = &trans_pcie->txq[cnt];
1702 q = &txq->q;
1703 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1704 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1705 msleep(1);
1706
1707 if (q->read_ptr != q->write_ptr) {
1708 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1709 ret = -ETIMEDOUT;
1710 break;
1711 }
1712 }
1713 return ret;
1714 }
1715
1716 /*
1717 * On every watchdog tick we check (latest) time stamp. If it does not
1718 * change during timeout period and queue is not empty we reset firmware.
1719 */
1720 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1721 {
1722 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1723 struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1724 struct iwl_queue *q = &txq->q;
1725 unsigned long timeout;
1726
1727 if (q->read_ptr == q->write_ptr) {
1728 txq->time_stamp = jiffies;
1729 return 0;
1730 }
1731
1732 timeout = txq->time_stamp +
1733 msecs_to_jiffies(hw_params(trans).wd_timeout);
1734
1735 if (time_after(jiffies, timeout)) {
1736 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1737 hw_params(trans).wd_timeout);
1738 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1739 q->read_ptr, q->write_ptr);
1740 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
1741 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt))
1742 & (TFD_QUEUE_SIZE_MAX - 1),
1743 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1744 return 1;
1745 }
1746
1747 return 0;
1748 }
1749
1750 static const char *get_fh_string(int cmd)
1751 {
1752 switch (cmd) {
1753 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1754 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1755 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1756 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1757 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1758 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1759 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1760 IWL_CMD(FH_TSSR_TX_STATUS_REG);
1761 IWL_CMD(FH_TSSR_TX_ERROR_REG);
1762 default:
1763 return "UNKNOWN";
1764 }
1765 }
1766
1767 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1768 {
1769 int i;
1770 #ifdef CONFIG_IWLWIFI_DEBUG
1771 int pos = 0;
1772 size_t bufsz = 0;
1773 #endif
1774 static const u32 fh_tbl[] = {
1775 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1776 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1777 FH_RSCSR_CHNL0_WPTR,
1778 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1779 FH_MEM_RSSR_SHARED_CTRL_REG,
1780 FH_MEM_RSSR_RX_STATUS_REG,
1781 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1782 FH_TSSR_TX_STATUS_REG,
1783 FH_TSSR_TX_ERROR_REG
1784 };
1785 #ifdef CONFIG_IWLWIFI_DEBUG
1786 if (display) {
1787 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1788 *buf = kmalloc(bufsz, GFP_KERNEL);
1789 if (!*buf)
1790 return -ENOMEM;
1791 pos += scnprintf(*buf + pos, bufsz - pos,
1792 "FH register values:\n");
1793 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1794 pos += scnprintf(*buf + pos, bufsz - pos,
1795 " %34s: 0X%08x\n",
1796 get_fh_string(fh_tbl[i]),
1797 iwl_read_direct32(trans, fh_tbl[i]));
1798 }
1799 return pos;
1800 }
1801 #endif
1802 IWL_ERR(trans, "FH register values:\n");
1803 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1804 IWL_ERR(trans, " %34s: 0X%08x\n",
1805 get_fh_string(fh_tbl[i]),
1806 iwl_read_direct32(trans, fh_tbl[i]));
1807 }
1808 return 0;
1809 }
1810
1811 static const char *get_csr_string(int cmd)
1812 {
1813 switch (cmd) {
1814 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1815 IWL_CMD(CSR_INT_COALESCING);
1816 IWL_CMD(CSR_INT);
1817 IWL_CMD(CSR_INT_MASK);
1818 IWL_CMD(CSR_FH_INT_STATUS);
1819 IWL_CMD(CSR_GPIO_IN);
1820 IWL_CMD(CSR_RESET);
1821 IWL_CMD(CSR_GP_CNTRL);
1822 IWL_CMD(CSR_HW_REV);
1823 IWL_CMD(CSR_EEPROM_REG);
1824 IWL_CMD(CSR_EEPROM_GP);
1825 IWL_CMD(CSR_OTP_GP_REG);
1826 IWL_CMD(CSR_GIO_REG);
1827 IWL_CMD(CSR_GP_UCODE_REG);
1828 IWL_CMD(CSR_GP_DRIVER_REG);
1829 IWL_CMD(CSR_UCODE_DRV_GP1);
1830 IWL_CMD(CSR_UCODE_DRV_GP2);
1831 IWL_CMD(CSR_LED_REG);
1832 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1833 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1834 IWL_CMD(CSR_ANA_PLL_CFG);
1835 IWL_CMD(CSR_HW_REV_WA_REG);
1836 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1837 default:
1838 return "UNKNOWN";
1839 }
1840 }
1841
1842 void iwl_dump_csr(struct iwl_trans *trans)
1843 {
1844 int i;
1845 static const u32 csr_tbl[] = {
1846 CSR_HW_IF_CONFIG_REG,
1847 CSR_INT_COALESCING,
1848 CSR_INT,
1849 CSR_INT_MASK,
1850 CSR_FH_INT_STATUS,
1851 CSR_GPIO_IN,
1852 CSR_RESET,
1853 CSR_GP_CNTRL,
1854 CSR_HW_REV,
1855 CSR_EEPROM_REG,
1856 CSR_EEPROM_GP,
1857 CSR_OTP_GP_REG,
1858 CSR_GIO_REG,
1859 CSR_GP_UCODE_REG,
1860 CSR_GP_DRIVER_REG,
1861 CSR_UCODE_DRV_GP1,
1862 CSR_UCODE_DRV_GP2,
1863 CSR_LED_REG,
1864 CSR_DRAM_INT_TBL_REG,
1865 CSR_GIO_CHICKEN_BITS,
1866 CSR_ANA_PLL_CFG,
1867 CSR_HW_REV_WA_REG,
1868 CSR_DBG_HPET_MEM_REG
1869 };
1870 IWL_ERR(trans, "CSR values:\n");
1871 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1872 "CSR_INT_PERIODIC_REG)\n");
1873 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1874 IWL_ERR(trans, " %25s: 0X%08x\n",
1875 get_csr_string(csr_tbl[i]),
1876 iwl_read32(trans, csr_tbl[i]));
1877 }
1878 }
1879
1880 #ifdef CONFIG_IWLWIFI_DEBUGFS
1881 /* create and remove of files */
1882 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1883 if (!debugfs_create_file(#name, mode, parent, trans, \
1884 &iwl_dbgfs_##name##_ops)) \
1885 return -ENOMEM; \
1886 } while (0)
1887
1888 /* file operation */
1889 #define DEBUGFS_READ_FUNC(name) \
1890 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1891 char __user *user_buf, \
1892 size_t count, loff_t *ppos);
1893
1894 #define DEBUGFS_WRITE_FUNC(name) \
1895 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1896 const char __user *user_buf, \
1897 size_t count, loff_t *ppos);
1898
1899
1900 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1901 {
1902 file->private_data = inode->i_private;
1903 return 0;
1904 }
1905
1906 #define DEBUGFS_READ_FILE_OPS(name) \
1907 DEBUGFS_READ_FUNC(name); \
1908 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1909 .read = iwl_dbgfs_##name##_read, \
1910 .open = iwl_dbgfs_open_file_generic, \
1911 .llseek = generic_file_llseek, \
1912 };
1913
1914 #define DEBUGFS_WRITE_FILE_OPS(name) \
1915 DEBUGFS_WRITE_FUNC(name); \
1916 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1917 .write = iwl_dbgfs_##name##_write, \
1918 .open = iwl_dbgfs_open_file_generic, \
1919 .llseek = generic_file_llseek, \
1920 };
1921
1922 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1923 DEBUGFS_READ_FUNC(name); \
1924 DEBUGFS_WRITE_FUNC(name); \
1925 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1926 .write = iwl_dbgfs_##name##_write, \
1927 .read = iwl_dbgfs_##name##_read, \
1928 .open = iwl_dbgfs_open_file_generic, \
1929 .llseek = generic_file_llseek, \
1930 };
1931
1932 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1933 char __user *user_buf,
1934 size_t count, loff_t *ppos)
1935 {
1936 struct iwl_trans *trans = file->private_data;
1937 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1938 struct iwl_tx_queue *txq;
1939 struct iwl_queue *q;
1940 char *buf;
1941 int pos = 0;
1942 int cnt;
1943 int ret;
1944 size_t bufsz;
1945
1946 bufsz = sizeof(char) * 64 * cfg(trans)->base_params->num_of_queues;
1947
1948 if (!trans_pcie->txq) {
1949 IWL_ERR(trans, "txq not ready\n");
1950 return -EAGAIN;
1951 }
1952 buf = kzalloc(bufsz, GFP_KERNEL);
1953 if (!buf)
1954 return -ENOMEM;
1955
1956 for (cnt = 0; cnt < cfg(trans)->base_params->num_of_queues; cnt++) {
1957 txq = &trans_pcie->txq[cnt];
1958 q = &txq->q;
1959 pos += scnprintf(buf + pos, bufsz - pos,
1960 "hwq %.2d: read=%u write=%u stop=%d"
1961 " swq_id=%#.2x (ac %d/hwq %d)\n",
1962 cnt, q->read_ptr, q->write_ptr,
1963 !!test_bit(cnt, trans_pcie->queue_stopped),
1964 txq->swq_id, txq->swq_id & 3,
1965 (txq->swq_id >> 2) & 0x1f);
1966 if (cnt >= 4)
1967 continue;
1968 /* for the ACs, display the stop count too */
1969 pos += scnprintf(buf + pos, bufsz - pos,
1970 " stop-count: %d\n",
1971 atomic_read(&trans_pcie->queue_stop_count[cnt]));
1972 }
1973 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1974 kfree(buf);
1975 return ret;
1976 }
1977
1978 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1979 char __user *user_buf,
1980 size_t count, loff_t *ppos) {
1981 struct iwl_trans *trans = file->private_data;
1982 struct iwl_trans_pcie *trans_pcie =
1983 IWL_TRANS_GET_PCIE_TRANS(trans);
1984 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1985 char buf[256];
1986 int pos = 0;
1987 const size_t bufsz = sizeof(buf);
1988
1989 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1990 rxq->read);
1991 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1992 rxq->write);
1993 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1994 rxq->free_count);
1995 if (rxq->rb_stts) {
1996 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1997 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1998 } else {
1999 pos += scnprintf(buf + pos, bufsz - pos,
2000 "closed_rb_num: Not Allocated\n");
2001 }
2002 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2003 }
2004
2005 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
2006 char __user *user_buf,
2007 size_t count, loff_t *ppos)
2008 {
2009 struct iwl_trans *trans = file->private_data;
2010 char *buf;
2011 int pos = 0;
2012 ssize_t ret = -ENOMEM;
2013
2014 ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
2015 if (buf) {
2016 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2017 kfree(buf);
2018 }
2019 return ret;
2020 }
2021
2022 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
2023 const char __user *user_buf,
2024 size_t count, loff_t *ppos)
2025 {
2026 struct iwl_trans *trans = file->private_data;
2027 u32 event_log_flag;
2028 char buf[8];
2029 int buf_size;
2030
2031 memset(buf, 0, sizeof(buf));
2032 buf_size = min(count, sizeof(buf) - 1);
2033 if (copy_from_user(buf, user_buf, buf_size))
2034 return -EFAULT;
2035 if (sscanf(buf, "%d", &event_log_flag) != 1)
2036 return -EFAULT;
2037 if (event_log_flag == 1)
2038 iwl_dump_nic_event_log(trans, true, NULL, false);
2039
2040 return count;
2041 }
2042
2043 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2044 char __user *user_buf,
2045 size_t count, loff_t *ppos) {
2046
2047 struct iwl_trans *trans = file->private_data;
2048 struct iwl_trans_pcie *trans_pcie =
2049 IWL_TRANS_GET_PCIE_TRANS(trans);
2050 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2051
2052 int pos = 0;
2053 char *buf;
2054 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2055 ssize_t ret;
2056
2057 buf = kzalloc(bufsz, GFP_KERNEL);
2058 if (!buf) {
2059 IWL_ERR(trans, "Can not allocate Buffer\n");
2060 return -ENOMEM;
2061 }
2062
2063 pos += scnprintf(buf + pos, bufsz - pos,
2064 "Interrupt Statistics Report:\n");
2065
2066 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2067 isr_stats->hw);
2068 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2069 isr_stats->sw);
2070 if (isr_stats->sw || isr_stats->hw) {
2071 pos += scnprintf(buf + pos, bufsz - pos,
2072 "\tLast Restarting Code: 0x%X\n",
2073 isr_stats->err_code);
2074 }
2075 #ifdef CONFIG_IWLWIFI_DEBUG
2076 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2077 isr_stats->sch);
2078 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2079 isr_stats->alive);
2080 #endif
2081 pos += scnprintf(buf + pos, bufsz - pos,
2082 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2083
2084 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2085 isr_stats->ctkill);
2086
2087 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2088 isr_stats->wakeup);
2089
2090 pos += scnprintf(buf + pos, bufsz - pos,
2091 "Rx command responses:\t\t %u\n", isr_stats->rx);
2092
2093 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2094 isr_stats->tx);
2095
2096 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2097 isr_stats->unhandled);
2098
2099 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2100 kfree(buf);
2101 return ret;
2102 }
2103
2104 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2105 const char __user *user_buf,
2106 size_t count, loff_t *ppos)
2107 {
2108 struct iwl_trans *trans = file->private_data;
2109 struct iwl_trans_pcie *trans_pcie =
2110 IWL_TRANS_GET_PCIE_TRANS(trans);
2111 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2112
2113 char buf[8];
2114 int buf_size;
2115 u32 reset_flag;
2116
2117 memset(buf, 0, sizeof(buf));
2118 buf_size = min(count, sizeof(buf) - 1);
2119 if (copy_from_user(buf, user_buf, buf_size))
2120 return -EFAULT;
2121 if (sscanf(buf, "%x", &reset_flag) != 1)
2122 return -EFAULT;
2123 if (reset_flag == 0)
2124 memset(isr_stats, 0, sizeof(*isr_stats));
2125
2126 return count;
2127 }
2128
2129 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2130 const char __user *user_buf,
2131 size_t count, loff_t *ppos)
2132 {
2133 struct iwl_trans *trans = file->private_data;
2134 char buf[8];
2135 int buf_size;
2136 int csr;
2137
2138 memset(buf, 0, sizeof(buf));
2139 buf_size = min(count, sizeof(buf) - 1);
2140 if (copy_from_user(buf, user_buf, buf_size))
2141 return -EFAULT;
2142 if (sscanf(buf, "%d", &csr) != 1)
2143 return -EFAULT;
2144
2145 iwl_dump_csr(trans);
2146
2147 return count;
2148 }
2149
2150 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2151 char __user *user_buf,
2152 size_t count, loff_t *ppos)
2153 {
2154 struct iwl_trans *trans = file->private_data;
2155 char *buf;
2156 int pos = 0;
2157 ssize_t ret = -EFAULT;
2158
2159 ret = pos = iwl_dump_fh(trans, &buf, true);
2160 if (buf) {
2161 ret = simple_read_from_buffer(user_buf,
2162 count, ppos, buf, pos);
2163 kfree(buf);
2164 }
2165
2166 return ret;
2167 }
2168
2169 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
2170 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2171 DEBUGFS_READ_FILE_OPS(fh_reg);
2172 DEBUGFS_READ_FILE_OPS(rx_queue);
2173 DEBUGFS_READ_FILE_OPS(tx_queue);
2174 DEBUGFS_WRITE_FILE_OPS(csr);
2175
2176 /*
2177 * Create the debugfs files and directories
2178 *
2179 */
2180 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2181 struct dentry *dir)
2182 {
2183 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2184 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2185 DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
2186 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2187 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2188 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2189 return 0;
2190 }
2191 #else
2192 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2193 struct dentry *dir)
2194 { return 0; }
2195
2196 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2197
2198 const struct iwl_trans_ops trans_ops_pcie = {
2199 .start_hw = iwl_trans_pcie_start_hw,
2200 .stop_hw = iwl_trans_pcie_stop_hw,
2201 .fw_alive = iwl_trans_pcie_fw_alive,
2202 .start_fw = iwl_trans_pcie_start_fw,
2203 .stop_device = iwl_trans_pcie_stop_device,
2204
2205 .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2206
2207 .send_cmd = iwl_trans_pcie_send_cmd,
2208
2209 .tx = iwl_trans_pcie_tx,
2210 .reclaim = iwl_trans_pcie_reclaim,
2211
2212 .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
2213 .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
2214 .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
2215
2216 .free = iwl_trans_pcie_free,
2217
2218 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2219
2220 .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2221 .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
2222
2223 #ifdef CONFIG_PM_SLEEP
2224 .suspend = iwl_trans_pcie_suspend,
2225 .resume = iwl_trans_pcie_resume,
2226 #endif
2227 .write8 = iwl_trans_pcie_write8,
2228 .write32 = iwl_trans_pcie_write32,
2229 .read32 = iwl_trans_pcie_read32,
2230 .configure = iwl_trans_pcie_configure,
2231 };
2232
2233 struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
2234 struct pci_dev *pdev,
2235 const struct pci_device_id *ent)
2236 {
2237 struct iwl_trans_pcie *trans_pcie;
2238 struct iwl_trans *trans;
2239 u16 pci_cmd;
2240 int err;
2241
2242 trans = kzalloc(sizeof(struct iwl_trans) +
2243 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2244
2245 if (WARN_ON(!trans))
2246 return NULL;
2247
2248 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2249
2250 trans->ops = &trans_ops_pcie;
2251 trans->shrd = shrd;
2252 trans_pcie->trans = trans;
2253 spin_lock_init(&trans_pcie->irq_lock);
2254 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2255
2256 /* W/A - seems to solve weird behavior. We need to remove this if we
2257 * don't want to stay in L1 all the time. This wastes a lot of power */
2258 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2259 PCIE_LINK_STATE_CLKPM);
2260
2261 if (pci_enable_device(pdev)) {
2262 err = -ENODEV;
2263 goto out_no_pci;
2264 }
2265
2266 pci_set_master(pdev);
2267
2268 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2269 if (!err)
2270 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2271 if (err) {
2272 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2273 if (!err)
2274 err = pci_set_consistent_dma_mask(pdev,
2275 DMA_BIT_MASK(32));
2276 /* both attempts failed: */
2277 if (err) {
2278 dev_printk(KERN_ERR, &pdev->dev,
2279 "No suitable DMA available.\n");
2280 goto out_pci_disable_device;
2281 }
2282 }
2283
2284 err = pci_request_regions(pdev, DRV_NAME);
2285 if (err) {
2286 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2287 goto out_pci_disable_device;
2288 }
2289
2290 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2291 if (!trans_pcie->hw_base) {
2292 dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed");
2293 err = -ENODEV;
2294 goto out_pci_release_regions;
2295 }
2296
2297 dev_printk(KERN_INFO, &pdev->dev,
2298 "pci_resource_len = 0x%08llx\n",
2299 (unsigned long long) pci_resource_len(pdev, 0));
2300 dev_printk(KERN_INFO, &pdev->dev,
2301 "pci_resource_base = %p\n", trans_pcie->hw_base);
2302
2303 dev_printk(KERN_INFO, &pdev->dev,
2304 "HW Revision ID = 0x%X\n", pdev->revision);
2305
2306 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2307 * PCI Tx retries from interfering with C3 CPU state */
2308 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2309
2310 err = pci_enable_msi(pdev);
2311 if (err)
2312 dev_printk(KERN_ERR, &pdev->dev,
2313 "pci_enable_msi failed(0X%x)", err);
2314
2315 trans->dev = &pdev->dev;
2316 trans_pcie->irq = pdev->irq;
2317 trans_pcie->pci_dev = pdev;
2318 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2319 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2320 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2321 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2322
2323 /* TODO: Move this away, not needed if not MSI */
2324 /* enable rfkill interrupt: hw bug w/a */
2325 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2326 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2327 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2328 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2329 }
2330
2331 /* Initialize the wait queue for commands */
2332 init_waitqueue_head(&trans->wait_command_queue);
2333
2334 return trans;
2335
2336 out_pci_release_regions:
2337 pci_release_regions(pdev);
2338 out_pci_disable_device:
2339 pci_disable_device(pdev);
2340 out_no_pci:
2341 kfree(trans);
2342 return NULL;
2343 }
2344
Ubuntu Jammy Linux kernel mirror