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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / iwlwifi / iwl-trans-pcie.c
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
70
71 #include "iwl-trans.h"
72 #include "iwl-trans-pcie-int.h"
73 #include "iwl-csr.h"
74 #include "iwl-prph.h"
75 #include "iwl-shared.h"
76 #include "iwl-eeprom.h"
77 #include "iwl-agn-hw.h"
78 #include "iwl-core.h"
79
80 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
81 {
82 struct iwl_trans_pcie *trans_pcie =
83 IWL_TRANS_GET_PCIE_TRANS(trans);
84 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
85 struct device *dev = trans->dev;
86
87 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
88
89 spin_lock_init(&rxq->lock);
90
91 if (WARN_ON(rxq->bd || rxq->rb_stts))
92 return -EINVAL;
93
94 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
95 rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
96 &rxq->bd_dma, GFP_KERNEL);
97 if (!rxq->bd)
98 goto err_bd;
99
100 /*Allocate the driver's pointer to receive buffer status */
101 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
102 &rxq->rb_stts_dma, GFP_KERNEL);
103 if (!rxq->rb_stts)
104 goto err_rb_stts;
105
106 return 0;
107
108 err_rb_stts:
109 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
110 rxq->bd, rxq->bd_dma);
111 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
112 rxq->bd = NULL;
113 err_bd:
114 return -ENOMEM;
115 }
116
117 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
118 {
119 struct iwl_trans_pcie *trans_pcie =
120 IWL_TRANS_GET_PCIE_TRANS(trans);
121 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
122 int i;
123
124 /* Fill the rx_used queue with _all_ of the Rx buffers */
125 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
126 /* In the reset function, these buffers may have been allocated
127 * to an SKB, so we need to unmap and free potential storage */
128 if (rxq->pool[i].page != NULL) {
129 dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
130 PAGE_SIZE << hw_params(trans).rx_page_order,
131 DMA_FROM_DEVICE);
132 __free_pages(rxq->pool[i].page,
133 hw_params(trans).rx_page_order);
134 rxq->pool[i].page = NULL;
135 }
136 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
137 }
138 }
139
140 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
141 struct iwl_rx_queue *rxq)
142 {
143 u32 rb_size;
144 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
145 u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
146
147 if (iwlagn_mod_params.amsdu_size_8K)
148 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
149 else
150 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
151
152 /* Stop Rx DMA */
153 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
154
155 /* Reset driver's Rx queue write index */
156 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
157
158 /* Tell device where to find RBD circular buffer in DRAM */
159 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
160 (u32)(rxq->bd_dma >> 8));
161
162 /* Tell device where in DRAM to update its Rx status */
163 iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
164 rxq->rb_stts_dma >> 4);
165
166 /* Enable Rx DMA
167 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
168 * the credit mechanism in 5000 HW RX FIFO
169 * Direct rx interrupts to hosts
170 * Rx buffer size 4 or 8k
171 * RB timeout 0x10
172 * 256 RBDs
173 */
174 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
175 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
176 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
177 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
178 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
179 rb_size|
180 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
181 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
182
183 /* Set interrupt coalescing timer to default (2048 usecs) */
184 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
185 }
186
187 static int iwl_rx_init(struct iwl_trans *trans)
188 {
189 struct iwl_trans_pcie *trans_pcie =
190 IWL_TRANS_GET_PCIE_TRANS(trans);
191 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
192
193 int i, err;
194 unsigned long flags;
195
196 if (!rxq->bd) {
197 err = iwl_trans_rx_alloc(trans);
198 if (err)
199 return err;
200 }
201
202 spin_lock_irqsave(&rxq->lock, flags);
203 INIT_LIST_HEAD(&rxq->rx_free);
204 INIT_LIST_HEAD(&rxq->rx_used);
205
206 iwl_trans_rxq_free_rx_bufs(trans);
207
208 for (i = 0; i < RX_QUEUE_SIZE; i++)
209 rxq->queue[i] = NULL;
210
211 /* Set us so that we have processed and used all buffers, but have
212 * not restocked the Rx queue with fresh buffers */
213 rxq->read = rxq->write = 0;
214 rxq->write_actual = 0;
215 rxq->free_count = 0;
216 spin_unlock_irqrestore(&rxq->lock, flags);
217
218 iwlagn_rx_replenish(trans);
219
220 iwl_trans_rx_hw_init(trans, rxq);
221
222 spin_lock_irqsave(&trans->shrd->lock, flags);
223 rxq->need_update = 1;
224 iwl_rx_queue_update_write_ptr(trans, rxq);
225 spin_unlock_irqrestore(&trans->shrd->lock, flags);
226
227 return 0;
228 }
229
230 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
231 {
232 struct iwl_trans_pcie *trans_pcie =
233 IWL_TRANS_GET_PCIE_TRANS(trans);
234 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
235
236 unsigned long flags;
237
238 /*if rxq->bd is NULL, it means that nothing has been allocated,
239 * exit now */
240 if (!rxq->bd) {
241 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
242 return;
243 }
244
245 spin_lock_irqsave(&rxq->lock, flags);
246 iwl_trans_rxq_free_rx_bufs(trans);
247 spin_unlock_irqrestore(&rxq->lock, flags);
248
249 dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
250 rxq->bd, rxq->bd_dma);
251 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
252 rxq->bd = NULL;
253
254 if (rxq->rb_stts)
255 dma_free_coherent(trans->dev,
256 sizeof(struct iwl_rb_status),
257 rxq->rb_stts, rxq->rb_stts_dma);
258 else
259 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
260 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
261 rxq->rb_stts = NULL;
262 }
263
264 static int iwl_trans_rx_stop(struct iwl_trans *trans)
265 {
266
267 /* stop Rx DMA */
268 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
269 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
270 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
271 }
272
273 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
274 struct iwl_dma_ptr *ptr, size_t size)
275 {
276 if (WARN_ON(ptr->addr))
277 return -EINVAL;
278
279 ptr->addr = dma_alloc_coherent(trans->dev, size,
280 &ptr->dma, GFP_KERNEL);
281 if (!ptr->addr)
282 return -ENOMEM;
283 ptr->size = size;
284 return 0;
285 }
286
287 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
288 struct iwl_dma_ptr *ptr)
289 {
290 if (unlikely(!ptr->addr))
291 return;
292
293 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
294 memset(ptr, 0, sizeof(*ptr));
295 }
296
297 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
298 struct iwl_tx_queue *txq, int slots_num,
299 u32 txq_id)
300 {
301 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
302 int i;
303
304 if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
305 return -EINVAL;
306
307 txq->q.n_window = slots_num;
308
309 txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL);
310 txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL);
311
312 if (!txq->meta || !txq->cmd)
313 goto error;
314
315 if (txq_id == trans->shrd->cmd_queue)
316 for (i = 0; i < slots_num; i++) {
317 txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
318 GFP_KERNEL);
319 if (!txq->cmd[i])
320 goto error;
321 }
322
323 /* Alloc driver data array and TFD circular buffer */
324 /* Driver private data, only for Tx (not command) queues,
325 * not shared with device. */
326 if (txq_id != trans->shrd->cmd_queue) {
327 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]),
328 GFP_KERNEL);
329 if (!txq->skbs) {
330 IWL_ERR(trans, "kmalloc for auxiliary BD "
331 "structures failed\n");
332 goto error;
333 }
334 } else {
335 txq->skbs = NULL;
336 }
337
338 /* Circular buffer of transmit frame descriptors (TFDs),
339 * shared with device */
340 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
341 &txq->q.dma_addr, GFP_KERNEL);
342 if (!txq->tfds) {
343 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
344 goto error;
345 }
346 txq->q.id = txq_id;
347
348 return 0;
349 error:
350 kfree(txq->skbs);
351 txq->skbs = NULL;
352 /* since txq->cmd has been zeroed,
353 * all non allocated cmd[i] will be NULL */
354 if (txq->cmd && txq_id == trans->shrd->cmd_queue)
355 for (i = 0; i < slots_num; i++)
356 kfree(txq->cmd[i]);
357 kfree(txq->meta);
358 kfree(txq->cmd);
359 txq->meta = NULL;
360 txq->cmd = NULL;
361
362 return -ENOMEM;
363
364 }
365
366 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
367 int slots_num, u32 txq_id)
368 {
369 int ret;
370
371 txq->need_update = 0;
372 memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
373
374 /*
375 * For the default queues 0-3, set up the swq_id
376 * already -- all others need to get one later
377 * (if they need one at all).
378 */
379 if (txq_id < 4)
380 iwl_set_swq_id(txq, txq_id, txq_id);
381
382 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
383 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
384 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
385
386 /* Initialize queue's high/low-water marks, and head/tail indexes */
387 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
388 txq_id);
389 if (ret)
390 return ret;
391
392 /*
393 * Tell nic where to find circular buffer of Tx Frame Descriptors for
394 * given Tx queue, and enable the DMA channel used for that queue.
395 * Circular buffer (TFD queue in DRAM) physical base address */
396 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
397 txq->q.dma_addr >> 8);
398
399 return 0;
400 }
401
402 /**
403 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
404 */
405 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
406 {
407 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
408 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
409 struct iwl_queue *q = &txq->q;
410 enum dma_data_direction dma_dir;
411 unsigned long flags;
412 spinlock_t *lock;
413
414 if (!q->n_bd)
415 return;
416
417 /* In the command queue, all the TBs are mapped as BIDI
418 * so unmap them as such.
419 */
420 if (txq_id == trans->shrd->cmd_queue) {
421 dma_dir = DMA_BIDIRECTIONAL;
422 lock = &trans->hcmd_lock;
423 } else {
424 dma_dir = DMA_TO_DEVICE;
425 lock = &trans->shrd->sta_lock;
426 }
427
428 spin_lock_irqsave(lock, flags);
429 while (q->write_ptr != q->read_ptr) {
430 /* The read_ptr needs to bound by q->n_window */
431 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
432 dma_dir);
433 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
434 }
435 spin_unlock_irqrestore(lock, flags);
436 }
437
438 /**
439 * iwl_tx_queue_free - Deallocate DMA queue.
440 * @txq: Transmit queue to deallocate.
441 *
442 * Empty queue by removing and destroying all BD's.
443 * Free all buffers.
444 * 0-fill, but do not free "txq" descriptor structure.
445 */
446 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
447 {
448 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
449 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
450 struct device *dev = trans->dev;
451 int i;
452 if (WARN_ON(!txq))
453 return;
454
455 iwl_tx_queue_unmap(trans, txq_id);
456
457 /* De-alloc array of command/tx buffers */
458
459 if (txq_id == trans->shrd->cmd_queue)
460 for (i = 0; i < txq->q.n_window; i++)
461 kfree(txq->cmd[i]);
462
463 /* De-alloc circular buffer of TFDs */
464 if (txq->q.n_bd) {
465 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
466 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
467 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
468 }
469
470 /* De-alloc array of per-TFD driver data */
471 kfree(txq->skbs);
472 txq->skbs = NULL;
473
474 /* deallocate arrays */
475 kfree(txq->cmd);
476 kfree(txq->meta);
477 txq->cmd = NULL;
478 txq->meta = NULL;
479
480 /* 0-fill queue descriptor structure */
481 memset(txq, 0, sizeof(*txq));
482 }
483
484 /**
485 * iwl_trans_tx_free - Free TXQ Context
486 *
487 * Destroy all TX DMA queues and structures
488 */
489 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
490 {
491 int txq_id;
492 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
493
494 /* Tx queues */
495 if (trans_pcie->txq) {
496 for (txq_id = 0;
497 txq_id < hw_params(trans).max_txq_num; txq_id++)
498 iwl_tx_queue_free(trans, txq_id);
499 }
500
501 kfree(trans_pcie->txq);
502 trans_pcie->txq = NULL;
503
504 iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
505
506 iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
507 }
508
509 /**
510 * iwl_trans_tx_alloc - allocate TX context
511 * Allocate all Tx DMA structures and initialize them
512 *
513 * @param priv
514 * @return error code
515 */
516 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
517 {
518 int ret;
519 int txq_id, slots_num;
520 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
521
522 u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
523 sizeof(struct iwlagn_scd_bc_tbl);
524
525 /*It is not allowed to alloc twice, so warn when this happens.
526 * We cannot rely on the previous allocation, so free and fail */
527 if (WARN_ON(trans_pcie->txq)) {
528 ret = -EINVAL;
529 goto error;
530 }
531
532 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
533 scd_bc_tbls_size);
534 if (ret) {
535 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
536 goto error;
537 }
538
539 /* Alloc keep-warm buffer */
540 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
541 if (ret) {
542 IWL_ERR(trans, "Keep Warm allocation failed\n");
543 goto error;
544 }
545
546 trans_pcie->txq = kcalloc(hw_params(trans).max_txq_num,
547 sizeof(struct iwl_tx_queue), GFP_KERNEL);
548 if (!trans_pcie->txq) {
549 IWL_ERR(trans, "Not enough memory for txq\n");
550 ret = ENOMEM;
551 goto error;
552 }
553
554 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
555 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
556 slots_num = (txq_id == trans->shrd->cmd_queue) ?
557 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
558 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
559 slots_num, txq_id);
560 if (ret) {
561 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
562 goto error;
563 }
564 }
565
566 return 0;
567
568 error:
569 iwl_trans_pcie_tx_free(trans);
570
571 return ret;
572 }
573 static int iwl_tx_init(struct iwl_trans *trans)
574 {
575 int ret;
576 int txq_id, slots_num;
577 unsigned long flags;
578 bool alloc = false;
579 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
580
581 if (!trans_pcie->txq) {
582 ret = iwl_trans_tx_alloc(trans);
583 if (ret)
584 goto error;
585 alloc = true;
586 }
587
588 spin_lock_irqsave(&trans->shrd->lock, flags);
589
590 /* Turn off all Tx DMA fifos */
591 iwl_write_prph(trans, SCD_TXFACT, 0);
592
593 /* Tell NIC where to find the "keep warm" buffer */
594 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
595 trans_pcie->kw.dma >> 4);
596
597 spin_unlock_irqrestore(&trans->shrd->lock, flags);
598
599 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
600 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
601 slots_num = (txq_id == trans->shrd->cmd_queue) ?
602 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
603 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
604 slots_num, txq_id);
605 if (ret) {
606 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
607 goto error;
608 }
609 }
610
611 return 0;
612 error:
613 /*Upon error, free only if we allocated something */
614 if (alloc)
615 iwl_trans_pcie_tx_free(trans);
616 return ret;
617 }
618
619 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
620 {
621 /*
622 * (for documentation purposes)
623 * to set power to V_AUX, do:
624
625 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
626 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
627 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
628 ~APMG_PS_CTRL_MSK_PWR_SRC);
629 */
630
631 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
632 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
633 ~APMG_PS_CTRL_MSK_PWR_SRC);
634 }
635
636 /* PCI registers */
637 #define PCI_CFG_RETRY_TIMEOUT 0x041
638 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
639 #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
640
641 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
642 {
643 int pos;
644 u16 pci_lnk_ctl;
645 struct iwl_trans_pcie *trans_pcie =
646 IWL_TRANS_GET_PCIE_TRANS(trans);
647
648 struct pci_dev *pci_dev = trans_pcie->pci_dev;
649
650 pos = pci_pcie_cap(pci_dev);
651 pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
652 return pci_lnk_ctl;
653 }
654
655 static void iwl_apm_config(struct iwl_trans *trans)
656 {
657 /*
658 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
659 * Check if BIOS (or OS) enabled L1-ASPM on this device.
660 * If so (likely), disable L0S, so device moves directly L0->L1;
661 * costs negligible amount of power savings.
662 * If not (unlikely), enable L0S, so there is at least some
663 * power savings, even without L1.
664 */
665 u16 lctl = iwl_pciexp_link_ctrl(trans);
666
667 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
668 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
669 /* L1-ASPM enabled; disable(!) L0S */
670 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
671 dev_printk(KERN_INFO, trans->dev,
672 "L1 Enabled; Disabling L0S\n");
673 } else {
674 /* L1-ASPM disabled; enable(!) L0S */
675 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
676 dev_printk(KERN_INFO, trans->dev,
677 "L1 Disabled; Enabling L0S\n");
678 }
679 trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
680 }
681
682 /*
683 * Start up NIC's basic functionality after it has been reset
684 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
685 * NOTE: This does not load uCode nor start the embedded processor
686 */
687 static int iwl_apm_init(struct iwl_trans *trans)
688 {
689 int ret = 0;
690 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
691
692 /*
693 * Use "set_bit" below rather than "write", to preserve any hardware
694 * bits already set by default after reset.
695 */
696
697 /* Disable L0S exit timer (platform NMI Work/Around) */
698 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
699 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
700
701 /*
702 * Disable L0s without affecting L1;
703 * don't wait for ICH L0s (ICH bug W/A)
704 */
705 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
706 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
707
708 /* Set FH wait threshold to maximum (HW error during stress W/A) */
709 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
710
711 /*
712 * Enable HAP INTA (interrupt from management bus) to
713 * wake device's PCI Express link L1a -> L0s
714 */
715 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
716 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
717
718 iwl_apm_config(trans);
719
720 /* Configure analog phase-lock-loop before activating to D0A */
721 if (cfg(trans)->base_params->pll_cfg_val)
722 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
723 cfg(trans)->base_params->pll_cfg_val);
724
725 /*
726 * Set "initialization complete" bit to move adapter from
727 * D0U* --> D0A* (powered-up active) state.
728 */
729 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
730
731 /*
732 * Wait for clock stabilization; once stabilized, access to
733 * device-internal resources is supported, e.g. iwl_write_prph()
734 * and accesses to uCode SRAM.
735 */
736 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
737 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
738 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
739 if (ret < 0) {
740 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
741 goto out;
742 }
743
744 /*
745 * Enable DMA clock and wait for it to stabilize.
746 *
747 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
748 * do not disable clocks. This preserves any hardware bits already
749 * set by default in "CLK_CTRL_REG" after reset.
750 */
751 iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
752 udelay(20);
753
754 /* Disable L1-Active */
755 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
756 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
757
758 set_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
759
760 out:
761 return ret;
762 }
763
764 static int iwl_apm_stop_master(struct iwl_trans *trans)
765 {
766 int ret = 0;
767
768 /* stop device's busmaster DMA activity */
769 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
770
771 ret = iwl_poll_bit(trans, CSR_RESET,
772 CSR_RESET_REG_FLAG_MASTER_DISABLED,
773 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
774 if (ret)
775 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
776
777 IWL_DEBUG_INFO(trans, "stop master\n");
778
779 return ret;
780 }
781
782 static void iwl_apm_stop(struct iwl_trans *trans)
783 {
784 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
785
786 clear_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
787
788 /* Stop device's DMA activity */
789 iwl_apm_stop_master(trans);
790
791 /* Reset the entire device */
792 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
793
794 udelay(10);
795
796 /*
797 * Clear "initialization complete" bit to move adapter from
798 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
799 */
800 iwl_clear_bit(trans, CSR_GP_CNTRL,
801 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
802 }
803
804 static int iwl_nic_init(struct iwl_trans *trans)
805 {
806 unsigned long flags;
807
808 /* nic_init */
809 spin_lock_irqsave(&trans->shrd->lock, flags);
810 iwl_apm_init(trans);
811
812 /* Set interrupt coalescing calibration timer to default (512 usecs) */
813 iwl_write8(trans, CSR_INT_COALESCING,
814 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
815
816 spin_unlock_irqrestore(&trans->shrd->lock, flags);
817
818 iwl_set_pwr_vmain(trans);
819
820 iwl_nic_config(priv(trans));
821
822 #ifndef CONFIG_IWLWIFI_IDI
823 /* Allocate the RX queue, or reset if it is already allocated */
824 iwl_rx_init(trans);
825 #endif
826
827 /* Allocate or reset and init all Tx and Command queues */
828 if (iwl_tx_init(trans))
829 return -ENOMEM;
830
831 if (hw_params(trans).shadow_reg_enable) {
832 /* enable shadow regs in HW */
833 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
834 0x800FFFFF);
835 }
836
837 set_bit(STATUS_INIT, &trans->shrd->status);
838
839 return 0;
840 }
841
842 #define HW_READY_TIMEOUT (50)
843
844 /* Note: returns poll_bit return value, which is >= 0 if success */
845 static int iwl_set_hw_ready(struct iwl_trans *trans)
846 {
847 int ret;
848
849 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
850 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
851
852 /* See if we got it */
853 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
854 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
855 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
856 HW_READY_TIMEOUT);
857
858 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
859 return ret;
860 }
861
862 /* Note: returns standard 0/-ERROR code */
863 static int iwl_prepare_card_hw(struct iwl_trans *trans)
864 {
865 int ret;
866
867 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
868
869 ret = iwl_set_hw_ready(trans);
870 /* If the card is ready, exit 0 */
871 if (ret >= 0)
872 return 0;
873
874 /* If HW is not ready, prepare the conditions to check again */
875 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
876 CSR_HW_IF_CONFIG_REG_PREPARE);
877
878 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
879 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
880 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
881
882 if (ret < 0)
883 return ret;
884
885 /* HW should be ready by now, check again. */
886 ret = iwl_set_hw_ready(trans);
887 if (ret >= 0)
888 return 0;
889 return ret;
890 }
891
892 #define IWL_AC_UNSET -1
893
894 struct queue_to_fifo_ac {
895 s8 fifo, ac;
896 };
897
898 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
899 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
900 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
901 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
902 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
903 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
904 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
905 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
906 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
907 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
908 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
909 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
910 };
911
912 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
913 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
914 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
915 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
916 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
917 { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
918 { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
919 { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
920 { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
921 { IWL_TX_FIFO_BE_IPAN, 2, },
922 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
923 { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
924 };
925
926 static const u8 iwlagn_bss_ac_to_fifo[] = {
927 IWL_TX_FIFO_VO,
928 IWL_TX_FIFO_VI,
929 IWL_TX_FIFO_BE,
930 IWL_TX_FIFO_BK,
931 };
932 static const u8 iwlagn_bss_ac_to_queue[] = {
933 0, 1, 2, 3,
934 };
935 static const u8 iwlagn_pan_ac_to_fifo[] = {
936 IWL_TX_FIFO_VO_IPAN,
937 IWL_TX_FIFO_VI_IPAN,
938 IWL_TX_FIFO_BE_IPAN,
939 IWL_TX_FIFO_BK_IPAN,
940 };
941 static const u8 iwlagn_pan_ac_to_queue[] = {
942 7, 6, 5, 4,
943 };
944
945 /*
946 * ucode
947 */
948 static int iwl_load_section(struct iwl_trans *trans, const char *name,
949 struct fw_desc *image, u32 dst_addr)
950 {
951 dma_addr_t phy_addr = image->p_addr;
952 u32 byte_cnt = image->len;
953 int ret;
954
955 trans->ucode_write_complete = 0;
956
957 iwl_write_direct32(trans,
958 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
959 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
960
961 iwl_write_direct32(trans,
962 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
963
964 iwl_write_direct32(trans,
965 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
966 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
967
968 iwl_write_direct32(trans,
969 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
970 (iwl_get_dma_hi_addr(phy_addr)
971 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
972
973 iwl_write_direct32(trans,
974 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
975 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
976 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
977 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
978
979 iwl_write_direct32(trans,
980 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
981 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
982 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
983 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
984
985 IWL_DEBUG_FW(trans, "%s uCode section being loaded...\n", name);
986 ret = wait_event_timeout(trans->shrd->wait_command_queue,
987 trans->ucode_write_complete, 5 * HZ);
988 if (!ret) {
989 IWL_ERR(trans, "Could not load the %s uCode section\n",
990 name);
991 return -ETIMEDOUT;
992 }
993
994 return 0;
995 }
996
997 static int iwl_load_given_ucode(struct iwl_trans *trans, struct fw_img *image)
998 {
999 int ret = 0;
1000
1001 ret = iwl_load_section(trans, "INST", &image->code,
1002 IWLAGN_RTC_INST_LOWER_BOUND);
1003 if (ret)
1004 return ret;
1005
1006 ret = iwl_load_section(trans, "DATA", &image->data,
1007 IWLAGN_RTC_DATA_LOWER_BOUND);
1008 if (ret)
1009 return ret;
1010
1011 /* Remove all resets to allow NIC to operate */
1012 iwl_write32(trans, CSR_RESET, 0);
1013
1014 return 0;
1015 }
1016
1017 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, struct fw_img *fw)
1018 {
1019 int ret;
1020 struct iwl_trans_pcie *trans_pcie =
1021 IWL_TRANS_GET_PCIE_TRANS(trans);
1022
1023 trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
1024 trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
1025 trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
1026
1027 trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
1028 trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
1029
1030 trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
1031 trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
1032
1033 if ((hw_params(trans).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
1034 iwl_prepare_card_hw(trans)) {
1035 IWL_WARN(trans, "Exit HW not ready\n");
1036 return -EIO;
1037 }
1038
1039 /* If platform's RF_KILL switch is NOT set to KILL */
1040 if (iwl_read32(trans, CSR_GP_CNTRL) &
1041 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
1042 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1043 else
1044 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1045
1046 if (iwl_is_rfkill(trans->shrd)) {
1047 iwl_set_hw_rfkill_state(priv(trans), true);
1048 iwl_enable_interrupts(trans);
1049 return -ERFKILL;
1050 }
1051
1052 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1053
1054 ret = iwl_nic_init(trans);
1055 if (ret) {
1056 IWL_ERR(trans, "Unable to init nic\n");
1057 return ret;
1058 }
1059
1060 /* make sure rfkill handshake bits are cleared */
1061 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1062 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1063 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1064
1065 /* clear (again), then enable host interrupts */
1066 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1067 iwl_enable_interrupts(trans);
1068
1069 /* really make sure rfkill handshake bits are cleared */
1070 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1071 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1072
1073 /* Load the given image to the HW */
1074 iwl_load_given_ucode(trans, fw);
1075
1076 return 0;
1077 }
1078
1079 /*
1080 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1081 * must be called under priv->shrd->lock and mac access
1082 */
1083 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1084 {
1085 iwl_write_prph(trans, SCD_TXFACT, mask);
1086 }
1087
1088 static void iwl_tx_start(struct iwl_trans *trans)
1089 {
1090 const struct queue_to_fifo_ac *queue_to_fifo;
1091 struct iwl_trans_pcie *trans_pcie =
1092 IWL_TRANS_GET_PCIE_TRANS(trans);
1093 u32 a;
1094 unsigned long flags;
1095 int i, chan;
1096 u32 reg_val;
1097
1098 spin_lock_irqsave(&trans->shrd->lock, flags);
1099
1100 trans_pcie->scd_base_addr =
1101 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1102 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1103 /* reset conext data memory */
1104 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1105 a += 4)
1106 iwl_write_targ_mem(trans, a, 0);
1107 /* reset tx status memory */
1108 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1109 a += 4)
1110 iwl_write_targ_mem(trans, a, 0);
1111 for (; a < trans_pcie->scd_base_addr +
1112 SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
1113 a += 4)
1114 iwl_write_targ_mem(trans, a, 0);
1115
1116 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1117 trans_pcie->scd_bc_tbls.dma >> 10);
1118
1119 /* Enable DMA channel */
1120 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1121 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1122 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1123 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1124
1125 /* Update FH chicken bits */
1126 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1127 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1128 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1129
1130 iwl_write_prph(trans, SCD_QUEUECHAIN_SEL,
1131 SCD_QUEUECHAIN_SEL_ALL(trans));
1132 iwl_write_prph(trans, SCD_AGGR_SEL, 0);
1133
1134 /* initiate the queues */
1135 for (i = 0; i < hw_params(trans).max_txq_num; i++) {
1136 iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
1137 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
1138 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1139 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
1140 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1141 SCD_CONTEXT_QUEUE_OFFSET(i) +
1142 sizeof(u32),
1143 ((SCD_WIN_SIZE <<
1144 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1145 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1146 ((SCD_FRAME_LIMIT <<
1147 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1148 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1149 }
1150
1151 iwl_write_prph(trans, SCD_INTERRUPT_MASK,
1152 IWL_MASK(0, hw_params(trans).max_txq_num));
1153
1154 /* Activate all Tx DMA/FIFO channels */
1155 iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1156
1157 /* map queues to FIFOs */
1158 if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1159 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
1160 else
1161 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
1162
1163 iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
1164
1165 /* make sure all queue are not stopped */
1166 memset(&trans_pcie->queue_stopped[0], 0,
1167 sizeof(trans_pcie->queue_stopped));
1168 for (i = 0; i < 4; i++)
1169 atomic_set(&trans_pcie->queue_stop_count[i], 0);
1170
1171 /* reset to 0 to enable all the queue first */
1172 trans_pcie->txq_ctx_active_msk = 0;
1173
1174 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
1175 IWLAGN_FIRST_AMPDU_QUEUE);
1176 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
1177 IWLAGN_FIRST_AMPDU_QUEUE);
1178
1179 for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
1180 int fifo = queue_to_fifo[i].fifo;
1181 int ac = queue_to_fifo[i].ac;
1182
1183 iwl_txq_ctx_activate(trans_pcie, i);
1184
1185 if (fifo == IWL_TX_FIFO_UNUSED)
1186 continue;
1187
1188 if (ac != IWL_AC_UNSET)
1189 iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
1190 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
1191 fifo, 0);
1192 }
1193
1194 spin_unlock_irqrestore(&trans->shrd->lock, flags);
1195
1196 /* Enable L1-Active */
1197 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1198 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1199 }
1200
1201 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1202 {
1203 iwl_reset_ict(trans);
1204 iwl_tx_start(trans);
1205 }
1206
1207 /**
1208 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1209 */
1210 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1211 {
1212 int ch, txq_id;
1213 unsigned long flags;
1214 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1215
1216 /* Turn off all Tx DMA fifos */
1217 spin_lock_irqsave(&trans->shrd->lock, flags);
1218
1219 iwl_trans_txq_set_sched(trans, 0);
1220
1221 /* Stop each Tx DMA channel, and wait for it to be idle */
1222 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1223 iwl_write_direct32(trans,
1224 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1225 if (iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1226 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
1227 1000))
1228 IWL_ERR(trans, "Failing on timeout while stopping"
1229 " DMA channel %d [0x%08x]", ch,
1230 iwl_read_direct32(trans,
1231 FH_TSSR_TX_STATUS_REG));
1232 }
1233 spin_unlock_irqrestore(&trans->shrd->lock, flags);
1234
1235 if (!trans_pcie->txq) {
1236 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
1237 return 0;
1238 }
1239
1240 /* Unmap DMA from host system and free skb's */
1241 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
1242 iwl_tx_queue_unmap(trans, txq_id);
1243
1244 return 0;
1245 }
1246
1247 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1248 {
1249 unsigned long flags;
1250 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1251
1252 /* tell the device to stop sending interrupts */
1253 spin_lock_irqsave(&trans->shrd->lock, flags);
1254 iwl_disable_interrupts(trans);
1255 spin_unlock_irqrestore(&trans->shrd->lock, flags);
1256
1257 /* device going down, Stop using ICT table */
1258 iwl_disable_ict(trans);
1259
1260 /*
1261 * If a HW restart happens during firmware loading,
1262 * then the firmware loading might call this function
1263 * and later it might be called again due to the
1264 * restart. So don't process again if the device is
1265 * already dead.
1266 */
1267 if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
1268 iwl_trans_tx_stop(trans);
1269 #ifndef CONFIG_IWLWIFI_IDI
1270 iwl_trans_rx_stop(trans);
1271 #endif
1272 /* Power-down device's busmaster DMA clocks */
1273 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1274 APMG_CLK_VAL_DMA_CLK_RQT);
1275 udelay(5);
1276 }
1277
1278 /* Make sure (redundant) we've released our request to stay awake */
1279 iwl_clear_bit(trans, CSR_GP_CNTRL,
1280 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1281
1282 /* Stop the device, and put it in low power state */
1283 iwl_apm_stop(trans);
1284
1285 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1286 * Clean again the interrupt here
1287 */
1288 spin_lock_irqsave(&trans->shrd->lock, flags);
1289 iwl_disable_interrupts(trans);
1290 spin_unlock_irqrestore(&trans->shrd->lock, flags);
1291
1292 /* wait to make sure we flush pending tasklet*/
1293 synchronize_irq(trans->irq);
1294 tasklet_kill(&trans_pcie->irq_tasklet);
1295
1296 /* stop and reset the on-board processor */
1297 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1298 }
1299
1300 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1301 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1302 u8 sta_id, u8 tid)
1303 {
1304 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1305 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1306 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1307 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1308 struct iwl_cmd_meta *out_meta;
1309 struct iwl_tx_queue *txq;
1310 struct iwl_queue *q;
1311
1312 dma_addr_t phys_addr = 0;
1313 dma_addr_t txcmd_phys;
1314 dma_addr_t scratch_phys;
1315 u16 len, firstlen, secondlen;
1316 u8 wait_write_ptr = 0;
1317 u8 txq_id;
1318 bool is_agg = false;
1319 __le16 fc = hdr->frame_control;
1320 u8 hdr_len = ieee80211_hdrlen(fc);
1321 u16 __maybe_unused wifi_seq;
1322
1323 /*
1324 * Send this frame after DTIM -- there's a special queue
1325 * reserved for this for contexts that support AP mode.
1326 */
1327 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1328 txq_id = trans_pcie->mcast_queue[ctx];
1329
1330 /*
1331 * The microcode will clear the more data
1332 * bit in the last frame it transmits.
1333 */
1334 hdr->frame_control |=
1335 cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1336 } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1337 txq_id = IWL_AUX_QUEUE;
1338 else
1339 txq_id =
1340 trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1341
1342 /* aggregation is on for this <sta,tid> */
1343 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
1344 WARN_ON(tid >= IWL_MAX_TID_COUNT);
1345 txq_id = trans_pcie->agg_txq[sta_id][tid];
1346 is_agg = true;
1347 }
1348
1349 txq = &trans_pcie->txq[txq_id];
1350 q = &txq->q;
1351
1352 /* In AGG mode, the index in the ring must correspond to the WiFi
1353 * sequence number. This is a HW requirements to help the SCD to parse
1354 * the BA.
1355 * Check here that the packets are in the right place on the ring.
1356 */
1357 #ifdef CONFIG_IWLWIFI_DEBUG
1358 wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1359 WARN_ONCE(is_agg && ((wifi_seq & 0xff) != q->write_ptr),
1360 "Q: %d WiFi Seq %d tfdNum %d",
1361 txq_id, wifi_seq, q->write_ptr);
1362 #endif
1363
1364 /* Set up driver data for this TFD */
1365 txq->skbs[q->write_ptr] = skb;
1366 txq->cmd[q->write_ptr] = dev_cmd;
1367
1368 dev_cmd->hdr.cmd = REPLY_TX;
1369 dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1370 INDEX_TO_SEQ(q->write_ptr)));
1371
1372 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1373 out_meta = &txq->meta[q->write_ptr];
1374
1375 /*
1376 * Use the first empty entry in this queue's command buffer array
1377 * to contain the Tx command and MAC header concatenated together
1378 * (payload data will be in another buffer).
1379 * Size of this varies, due to varying MAC header length.
1380 * If end is not dword aligned, we'll have 2 extra bytes at the end
1381 * of the MAC header (device reads on dword boundaries).
1382 * We'll tell device about this padding later.
1383 */
1384 len = sizeof(struct iwl_tx_cmd) +
1385 sizeof(struct iwl_cmd_header) + hdr_len;
1386 firstlen = (len + 3) & ~3;
1387
1388 /* Tell NIC about any 2-byte padding after MAC header */
1389 if (firstlen != len)
1390 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1391
1392 /* Physical address of this Tx command's header (not MAC header!),
1393 * within command buffer array. */
1394 txcmd_phys = dma_map_single(trans->dev,
1395 &dev_cmd->hdr, firstlen,
1396 DMA_BIDIRECTIONAL);
1397 if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1398 return -1;
1399 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1400 dma_unmap_len_set(out_meta, len, firstlen);
1401
1402 if (!ieee80211_has_morefrags(fc)) {
1403 txq->need_update = 1;
1404 } else {
1405 wait_write_ptr = 1;
1406 txq->need_update = 0;
1407 }
1408
1409 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1410 * if any (802.11 null frames have no payload). */
1411 secondlen = skb->len - hdr_len;
1412 if (secondlen > 0) {
1413 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1414 secondlen, DMA_TO_DEVICE);
1415 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1416 dma_unmap_single(trans->dev,
1417 dma_unmap_addr(out_meta, mapping),
1418 dma_unmap_len(out_meta, len),
1419 DMA_BIDIRECTIONAL);
1420 return -1;
1421 }
1422 }
1423
1424 /* Attach buffers to TFD */
1425 iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1426 if (secondlen > 0)
1427 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1428 secondlen, 0);
1429
1430 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1431 offsetof(struct iwl_tx_cmd, scratch);
1432
1433 /* take back ownership of DMA buffer to enable update */
1434 dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1435 DMA_BIDIRECTIONAL);
1436 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1437 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1438
1439 IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1440 le16_to_cpu(dev_cmd->hdr.sequence));
1441 IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1442 iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1443 iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1444
1445 /* Set up entry for this TFD in Tx byte-count array */
1446 iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1447
1448 dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1449 DMA_BIDIRECTIONAL);
1450
1451 trace_iwlwifi_dev_tx(priv(trans),
1452 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1453 sizeof(struct iwl_tfd),
1454 &dev_cmd->hdr, firstlen,
1455 skb->data + hdr_len, secondlen);
1456
1457 /* Tell device the write index *just past* this latest filled TFD */
1458 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1459 iwl_txq_update_write_ptr(trans, txq);
1460
1461 /*
1462 * At this point the frame is "transmitted" successfully
1463 * and we will get a TX status notification eventually,
1464 * regardless of the value of ret. "ret" only indicates
1465 * whether or not we should update the write pointer.
1466 */
1467 if (iwl_queue_space(q) < q->high_mark) {
1468 if (wait_write_ptr) {
1469 txq->need_update = 1;
1470 iwl_txq_update_write_ptr(trans, txq);
1471 } else {
1472 iwl_stop_queue(trans, txq, "Queue is full");
1473 }
1474 }
1475 return 0;
1476 }
1477
1478 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1479 {
1480 struct iwl_trans_pcie *trans_pcie =
1481 IWL_TRANS_GET_PCIE_TRANS(trans);
1482 int err;
1483
1484 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1485
1486 if (!trans_pcie->irq_requested) {
1487 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1488 iwl_irq_tasklet, (unsigned long)trans);
1489
1490 iwl_alloc_isr_ict(trans);
1491
1492 err = request_irq(trans->irq, iwl_isr_ict, IRQF_SHARED,
1493 DRV_NAME, trans);
1494 if (err) {
1495 IWL_ERR(trans, "Error allocating IRQ %d\n",
1496 trans->irq);
1497 goto error;
1498 }
1499
1500 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1501 trans_pcie->irq_requested = true;
1502 }
1503
1504 err = iwl_prepare_card_hw(trans);
1505 if (err) {
1506 IWL_ERR(trans, "Error while preparing HW: %d", err);
1507 goto err_free_irq;
1508 }
1509
1510 iwl_apm_init(trans);
1511
1512 /* If platform's RF_KILL switch is NOT set to KILL */
1513 if (iwl_read32(trans,
1514 CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
1515 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1516 else
1517 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1518
1519 iwl_set_hw_rfkill_state(priv(trans),
1520 test_bit(STATUS_RF_KILL_HW,
1521 &trans->shrd->status));
1522
1523 return err;
1524
1525 err_free_irq:
1526 free_irq(trans->irq, trans);
1527 error:
1528 iwl_free_isr_ict(trans);
1529 tasklet_kill(&trans_pcie->irq_tasklet);
1530 return err;
1531 }
1532
1533 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans)
1534 {
1535 iwl_apm_stop(trans);
1536
1537 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1538
1539 /* Even if we stop the HW, we still want the RF kill interrupt */
1540 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
1541 iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
1542 }
1543
1544 static int iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1545 int txq_id, int ssn, u32 status,
1546 struct sk_buff_head *skbs)
1547 {
1548 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1549 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1550 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1551 int tfd_num = ssn & (txq->q.n_bd - 1);
1552 int freed = 0;
1553
1554 txq->time_stamp = jiffies;
1555
1556 if (unlikely(txq_id >= IWLAGN_FIRST_AMPDU_QUEUE &&
1557 tid != IWL_TID_NON_QOS &&
1558 txq_id != trans_pcie->agg_txq[sta_id][tid])) {
1559 /*
1560 * FIXME: this is a uCode bug which need to be addressed,
1561 * log the information and return for now.
1562 * Since it is can possibly happen very often and in order
1563 * not to fill the syslog, don't use IWL_ERR or IWL_WARN
1564 */
1565 IWL_DEBUG_TX_QUEUES(trans, "Bad queue mapping txq_id %d, "
1566 "agg_txq[sta_id[tid] %d", txq_id,
1567 trans_pcie->agg_txq[sta_id][tid]);
1568 return 1;
1569 }
1570
1571 if (txq->q.read_ptr != tfd_num) {
1572 IWL_DEBUG_TX_REPLY(trans, "[Q %d | AC %d] %d -> %d (%d)\n",
1573 txq_id, iwl_get_queue_ac(txq), txq->q.read_ptr,
1574 tfd_num, ssn);
1575 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1576 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1577 (!txq->sched_retry ||
1578 status != TX_STATUS_FAIL_PASSIVE_NO_RX))
1579 iwl_wake_queue(trans, txq, "Packets reclaimed");
1580 }
1581 return 0;
1582 }
1583
1584 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1585 {
1586 iowrite8(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1587 }
1588
1589 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1590 {
1591 iowrite32(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1592 }
1593
1594 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1595 {
1596 u32 val = ioread32(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1597 return val;
1598 }
1599
1600 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1601 {
1602 struct iwl_trans_pcie *trans_pcie =
1603 IWL_TRANS_GET_PCIE_TRANS(trans);
1604
1605 iwl_calib_free_results(trans);
1606 iwl_trans_pcie_tx_free(trans);
1607 #ifndef CONFIG_IWLWIFI_IDI
1608 iwl_trans_pcie_rx_free(trans);
1609 #endif
1610 if (trans_pcie->irq_requested == true) {
1611 free_irq(trans->irq, trans);
1612 iwl_free_isr_ict(trans);
1613 }
1614
1615 pci_disable_msi(trans_pcie->pci_dev);
1616 pci_iounmap(trans_pcie->pci_dev, trans_pcie->hw_base);
1617 pci_release_regions(trans_pcie->pci_dev);
1618 pci_disable_device(trans_pcie->pci_dev);
1619
1620 trans->shrd->trans = NULL;
1621 kfree(trans);
1622 }
1623
1624 #ifdef CONFIG_PM_SLEEP
1625 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1626 {
1627 /*
1628 * This function is called when system goes into suspend state
1629 * mac80211 will call iwlagn_mac_stop() from the mac80211 suspend
1630 * function first but since iwlagn_mac_stop() has no knowledge of
1631 * who the caller is,
1632 * it will not call apm_ops.stop() to stop the DMA operation.
1633 * Calling apm_ops.stop here to make sure we stop the DMA.
1634 *
1635 * But of course ... if we have configured WoWLAN then we did other
1636 * things already :-)
1637 */
1638 if (!trans->shrd->wowlan) {
1639 iwl_apm_stop(trans);
1640 } else {
1641 iwl_disable_interrupts(trans);
1642 iwl_clear_bit(trans, CSR_GP_CNTRL,
1643 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1644 }
1645
1646 return 0;
1647 }
1648
1649 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1650 {
1651 bool hw_rfkill = false;
1652
1653 iwl_enable_interrupts(trans);
1654
1655 if (!(iwl_read32(trans, CSR_GP_CNTRL) &
1656 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1657 hw_rfkill = true;
1658
1659 if (hw_rfkill)
1660 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1661 else
1662 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1663
1664 iwl_set_hw_rfkill_state(priv(trans), hw_rfkill);
1665
1666 return 0;
1667 }
1668 #endif /* CONFIG_PM_SLEEP */
1669
1670 static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans,
1671 enum iwl_rxon_context_id ctx,
1672 const char *msg)
1673 {
1674 u8 ac, txq_id;
1675 struct iwl_trans_pcie *trans_pcie =
1676 IWL_TRANS_GET_PCIE_TRANS(trans);
1677
1678 for (ac = 0; ac < AC_NUM; ac++) {
1679 txq_id = trans_pcie->ac_to_queue[ctx][ac];
1680 IWL_DEBUG_TX_QUEUES(trans, "Queue Status: Q[%d] %s\n",
1681 ac,
1682 (atomic_read(&trans_pcie->queue_stop_count[ac]) > 0)
1683 ? "stopped" : "awake");
1684 iwl_wake_queue(trans, &trans_pcie->txq[txq_id], msg);
1685 }
1686 }
1687
1688 static void iwl_trans_pcie_stop_queue(struct iwl_trans *trans, int txq_id,
1689 const char *msg)
1690 {
1691 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1692
1693 iwl_stop_queue(trans, &trans_pcie->txq[txq_id], msg);
1694 }
1695
1696 #define IWL_FLUSH_WAIT_MS 2000
1697
1698 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1699 {
1700 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1701 struct iwl_tx_queue *txq;
1702 struct iwl_queue *q;
1703 int cnt;
1704 unsigned long now = jiffies;
1705 int ret = 0;
1706
1707 /* waiting for all the tx frames complete might take a while */
1708 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1709 if (cnt == trans->shrd->cmd_queue)
1710 continue;
1711 txq = &trans_pcie->txq[cnt];
1712 q = &txq->q;
1713 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1714 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1715 msleep(1);
1716
1717 if (q->read_ptr != q->write_ptr) {
1718 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1719 ret = -ETIMEDOUT;
1720 break;
1721 }
1722 }
1723 return ret;
1724 }
1725
1726 /*
1727 * On every watchdog tick we check (latest) time stamp. If it does not
1728 * change during timeout period and queue is not empty we reset firmware.
1729 */
1730 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1731 {
1732 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1733 struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1734 struct iwl_queue *q = &txq->q;
1735 unsigned long timeout;
1736
1737 if (q->read_ptr == q->write_ptr) {
1738 txq->time_stamp = jiffies;
1739 return 0;
1740 }
1741
1742 timeout = txq->time_stamp +
1743 msecs_to_jiffies(hw_params(trans).wd_timeout);
1744
1745 if (time_after(jiffies, timeout)) {
1746 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1747 hw_params(trans).wd_timeout);
1748 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1749 q->read_ptr, q->write_ptr);
1750 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
1751 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt))
1752 & (TFD_QUEUE_SIZE_MAX - 1),
1753 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1754 return 1;
1755 }
1756
1757 return 0;
1758 }
1759
1760 static const char *get_fh_string(int cmd)
1761 {
1762 switch (cmd) {
1763 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1764 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1765 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1766 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1767 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1768 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1769 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1770 IWL_CMD(FH_TSSR_TX_STATUS_REG);
1771 IWL_CMD(FH_TSSR_TX_ERROR_REG);
1772 default:
1773 return "UNKNOWN";
1774 }
1775 }
1776
1777 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1778 {
1779 int i;
1780 #ifdef CONFIG_IWLWIFI_DEBUG
1781 int pos = 0;
1782 size_t bufsz = 0;
1783 #endif
1784 static const u32 fh_tbl[] = {
1785 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1786 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1787 FH_RSCSR_CHNL0_WPTR,
1788 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1789 FH_MEM_RSSR_SHARED_CTRL_REG,
1790 FH_MEM_RSSR_RX_STATUS_REG,
1791 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1792 FH_TSSR_TX_STATUS_REG,
1793 FH_TSSR_TX_ERROR_REG
1794 };
1795 #ifdef CONFIG_IWLWIFI_DEBUG
1796 if (display) {
1797 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1798 *buf = kmalloc(bufsz, GFP_KERNEL);
1799 if (!*buf)
1800 return -ENOMEM;
1801 pos += scnprintf(*buf + pos, bufsz - pos,
1802 "FH register values:\n");
1803 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1804 pos += scnprintf(*buf + pos, bufsz - pos,
1805 " %34s: 0X%08x\n",
1806 get_fh_string(fh_tbl[i]),
1807 iwl_read_direct32(trans, fh_tbl[i]));
1808 }
1809 return pos;
1810 }
1811 #endif
1812 IWL_ERR(trans, "FH register values:\n");
1813 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1814 IWL_ERR(trans, " %34s: 0X%08x\n",
1815 get_fh_string(fh_tbl[i]),
1816 iwl_read_direct32(trans, fh_tbl[i]));
1817 }
1818 return 0;
1819 }
1820
1821 static const char *get_csr_string(int cmd)
1822 {
1823 switch (cmd) {
1824 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1825 IWL_CMD(CSR_INT_COALESCING);
1826 IWL_CMD(CSR_INT);
1827 IWL_CMD(CSR_INT_MASK);
1828 IWL_CMD(CSR_FH_INT_STATUS);
1829 IWL_CMD(CSR_GPIO_IN);
1830 IWL_CMD(CSR_RESET);
1831 IWL_CMD(CSR_GP_CNTRL);
1832 IWL_CMD(CSR_HW_REV);
1833 IWL_CMD(CSR_EEPROM_REG);
1834 IWL_CMD(CSR_EEPROM_GP);
1835 IWL_CMD(CSR_OTP_GP_REG);
1836 IWL_CMD(CSR_GIO_REG);
1837 IWL_CMD(CSR_GP_UCODE_REG);
1838 IWL_CMD(CSR_GP_DRIVER_REG);
1839 IWL_CMD(CSR_UCODE_DRV_GP1);
1840 IWL_CMD(CSR_UCODE_DRV_GP2);
1841 IWL_CMD(CSR_LED_REG);
1842 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1843 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1844 IWL_CMD(CSR_ANA_PLL_CFG);
1845 IWL_CMD(CSR_HW_REV_WA_REG);
1846 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1847 default:
1848 return "UNKNOWN";
1849 }
1850 }
1851
1852 void iwl_dump_csr(struct iwl_trans *trans)
1853 {
1854 int i;
1855 static const u32 csr_tbl[] = {
1856 CSR_HW_IF_CONFIG_REG,
1857 CSR_INT_COALESCING,
1858 CSR_INT,
1859 CSR_INT_MASK,
1860 CSR_FH_INT_STATUS,
1861 CSR_GPIO_IN,
1862 CSR_RESET,
1863 CSR_GP_CNTRL,
1864 CSR_HW_REV,
1865 CSR_EEPROM_REG,
1866 CSR_EEPROM_GP,
1867 CSR_OTP_GP_REG,
1868 CSR_GIO_REG,
1869 CSR_GP_UCODE_REG,
1870 CSR_GP_DRIVER_REG,
1871 CSR_UCODE_DRV_GP1,
1872 CSR_UCODE_DRV_GP2,
1873 CSR_LED_REG,
1874 CSR_DRAM_INT_TBL_REG,
1875 CSR_GIO_CHICKEN_BITS,
1876 CSR_ANA_PLL_CFG,
1877 CSR_HW_REV_WA_REG,
1878 CSR_DBG_HPET_MEM_REG
1879 };
1880 IWL_ERR(trans, "CSR values:\n");
1881 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1882 "CSR_INT_PERIODIC_REG)\n");
1883 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1884 IWL_ERR(trans, " %25s: 0X%08x\n",
1885 get_csr_string(csr_tbl[i]),
1886 iwl_read32(trans, csr_tbl[i]));
1887 }
1888 }
1889
1890 #ifdef CONFIG_IWLWIFI_DEBUGFS
1891 /* create and remove of files */
1892 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1893 if (!debugfs_create_file(#name, mode, parent, trans, \
1894 &iwl_dbgfs_##name##_ops)) \
1895 return -ENOMEM; \
1896 } while (0)
1897
1898 /* file operation */
1899 #define DEBUGFS_READ_FUNC(name) \
1900 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1901 char __user *user_buf, \
1902 size_t count, loff_t *ppos);
1903
1904 #define DEBUGFS_WRITE_FUNC(name) \
1905 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1906 const char __user *user_buf, \
1907 size_t count, loff_t *ppos);
1908
1909
1910 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1911 {
1912 file->private_data = inode->i_private;
1913 return 0;
1914 }
1915
1916 #define DEBUGFS_READ_FILE_OPS(name) \
1917 DEBUGFS_READ_FUNC(name); \
1918 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1919 .read = iwl_dbgfs_##name##_read, \
1920 .open = iwl_dbgfs_open_file_generic, \
1921 .llseek = generic_file_llseek, \
1922 };
1923
1924 #define DEBUGFS_WRITE_FILE_OPS(name) \
1925 DEBUGFS_WRITE_FUNC(name); \
1926 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1927 .write = iwl_dbgfs_##name##_write, \
1928 .open = iwl_dbgfs_open_file_generic, \
1929 .llseek = generic_file_llseek, \
1930 };
1931
1932 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1933 DEBUGFS_READ_FUNC(name); \
1934 DEBUGFS_WRITE_FUNC(name); \
1935 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1936 .write = iwl_dbgfs_##name##_write, \
1937 .read = iwl_dbgfs_##name##_read, \
1938 .open = iwl_dbgfs_open_file_generic, \
1939 .llseek = generic_file_llseek, \
1940 };
1941
1942 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1943 char __user *user_buf,
1944 size_t count, loff_t *ppos)
1945 {
1946 struct iwl_trans *trans = file->private_data;
1947 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1948 struct iwl_tx_queue *txq;
1949 struct iwl_queue *q;
1950 char *buf;
1951 int pos = 0;
1952 int cnt;
1953 int ret;
1954 const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1955
1956 if (!trans_pcie->txq) {
1957 IWL_ERR(trans, "txq not ready\n");
1958 return -EAGAIN;
1959 }
1960 buf = kzalloc(bufsz, GFP_KERNEL);
1961 if (!buf)
1962 return -ENOMEM;
1963
1964 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1965 txq = &trans_pcie->txq[cnt];
1966 q = &txq->q;
1967 pos += scnprintf(buf + pos, bufsz - pos,
1968 "hwq %.2d: read=%u write=%u stop=%d"
1969 " swq_id=%#.2x (ac %d/hwq %d)\n",
1970 cnt, q->read_ptr, q->write_ptr,
1971 !!test_bit(cnt, trans_pcie->queue_stopped),
1972 txq->swq_id, txq->swq_id & 3,
1973 (txq->swq_id >> 2) & 0x1f);
1974 if (cnt >= 4)
1975 continue;
1976 /* for the ACs, display the stop count too */
1977 pos += scnprintf(buf + pos, bufsz - pos,
1978 " stop-count: %d\n",
1979 atomic_read(&trans_pcie->queue_stop_count[cnt]));
1980 }
1981 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1982 kfree(buf);
1983 return ret;
1984 }
1985
1986 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1987 char __user *user_buf,
1988 size_t count, loff_t *ppos) {
1989 struct iwl_trans *trans = file->private_data;
1990 struct iwl_trans_pcie *trans_pcie =
1991 IWL_TRANS_GET_PCIE_TRANS(trans);
1992 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1993 char buf[256];
1994 int pos = 0;
1995 const size_t bufsz = sizeof(buf);
1996
1997 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1998 rxq->read);
1999 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
2000 rxq->write);
2001 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
2002 rxq->free_count);
2003 if (rxq->rb_stts) {
2004 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
2005 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
2006 } else {
2007 pos += scnprintf(buf + pos, bufsz - pos,
2008 "closed_rb_num: Not Allocated\n");
2009 }
2010 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2011 }
2012
2013 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
2014 char __user *user_buf,
2015 size_t count, loff_t *ppos)
2016 {
2017 struct iwl_trans *trans = file->private_data;
2018 char *buf;
2019 int pos = 0;
2020 ssize_t ret = -ENOMEM;
2021
2022 ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
2023 if (buf) {
2024 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2025 kfree(buf);
2026 }
2027 return ret;
2028 }
2029
2030 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
2031 const char __user *user_buf,
2032 size_t count, loff_t *ppos)
2033 {
2034 struct iwl_trans *trans = file->private_data;
2035 u32 event_log_flag;
2036 char buf[8];
2037 int buf_size;
2038
2039 memset(buf, 0, sizeof(buf));
2040 buf_size = min(count, sizeof(buf) - 1);
2041 if (copy_from_user(buf, user_buf, buf_size))
2042 return -EFAULT;
2043 if (sscanf(buf, "%d", &event_log_flag) != 1)
2044 return -EFAULT;
2045 if (event_log_flag == 1)
2046 iwl_dump_nic_event_log(trans, true, NULL, false);
2047
2048 return count;
2049 }
2050
2051 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2052 char __user *user_buf,
2053 size_t count, loff_t *ppos) {
2054
2055 struct iwl_trans *trans = file->private_data;
2056 struct iwl_trans_pcie *trans_pcie =
2057 IWL_TRANS_GET_PCIE_TRANS(trans);
2058 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2059
2060 int pos = 0;
2061 char *buf;
2062 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2063 ssize_t ret;
2064
2065 buf = kzalloc(bufsz, GFP_KERNEL);
2066 if (!buf) {
2067 IWL_ERR(trans, "Can not allocate Buffer\n");
2068 return -ENOMEM;
2069 }
2070
2071 pos += scnprintf(buf + pos, bufsz - pos,
2072 "Interrupt Statistics Report:\n");
2073
2074 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2075 isr_stats->hw);
2076 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2077 isr_stats->sw);
2078 if (isr_stats->sw || isr_stats->hw) {
2079 pos += scnprintf(buf + pos, bufsz - pos,
2080 "\tLast Restarting Code: 0x%X\n",
2081 isr_stats->err_code);
2082 }
2083 #ifdef CONFIG_IWLWIFI_DEBUG
2084 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2085 isr_stats->sch);
2086 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2087 isr_stats->alive);
2088 #endif
2089 pos += scnprintf(buf + pos, bufsz - pos,
2090 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2091
2092 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2093 isr_stats->ctkill);
2094
2095 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2096 isr_stats->wakeup);
2097
2098 pos += scnprintf(buf + pos, bufsz - pos,
2099 "Rx command responses:\t\t %u\n", isr_stats->rx);
2100
2101 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2102 isr_stats->tx);
2103
2104 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2105 isr_stats->unhandled);
2106
2107 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2108 kfree(buf);
2109 return ret;
2110 }
2111
2112 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2113 const char __user *user_buf,
2114 size_t count, loff_t *ppos)
2115 {
2116 struct iwl_trans *trans = file->private_data;
2117 struct iwl_trans_pcie *trans_pcie =
2118 IWL_TRANS_GET_PCIE_TRANS(trans);
2119 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2120
2121 char buf[8];
2122 int buf_size;
2123 u32 reset_flag;
2124
2125 memset(buf, 0, sizeof(buf));
2126 buf_size = min(count, sizeof(buf) - 1);
2127 if (copy_from_user(buf, user_buf, buf_size))
2128 return -EFAULT;
2129 if (sscanf(buf, "%x", &reset_flag) != 1)
2130 return -EFAULT;
2131 if (reset_flag == 0)
2132 memset(isr_stats, 0, sizeof(*isr_stats));
2133
2134 return count;
2135 }
2136
2137 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2138 const char __user *user_buf,
2139 size_t count, loff_t *ppos)
2140 {
2141 struct iwl_trans *trans = file->private_data;
2142 char buf[8];
2143 int buf_size;
2144 int csr;
2145
2146 memset(buf, 0, sizeof(buf));
2147 buf_size = min(count, sizeof(buf) - 1);
2148 if (copy_from_user(buf, user_buf, buf_size))
2149 return -EFAULT;
2150 if (sscanf(buf, "%d", &csr) != 1)
2151 return -EFAULT;
2152
2153 iwl_dump_csr(trans);
2154
2155 return count;
2156 }
2157
2158 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2159 char __user *user_buf,
2160 size_t count, loff_t *ppos)
2161 {
2162 struct iwl_trans *trans = file->private_data;
2163 char *buf;
2164 int pos = 0;
2165 ssize_t ret = -EFAULT;
2166
2167 ret = pos = iwl_dump_fh(trans, &buf, true);
2168 if (buf) {
2169 ret = simple_read_from_buffer(user_buf,
2170 count, ppos, buf, pos);
2171 kfree(buf);
2172 }
2173
2174 return ret;
2175 }
2176
2177 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
2178 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2179 DEBUGFS_READ_FILE_OPS(fh_reg);
2180 DEBUGFS_READ_FILE_OPS(rx_queue);
2181 DEBUGFS_READ_FILE_OPS(tx_queue);
2182 DEBUGFS_WRITE_FILE_OPS(csr);
2183
2184 /*
2185 * Create the debugfs files and directories
2186 *
2187 */
2188 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2189 struct dentry *dir)
2190 {
2191 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2192 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2193 DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
2194 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2195 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2196 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2197 return 0;
2198 }
2199 #else
2200 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2201 struct dentry *dir)
2202 { return 0; }
2203
2204 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2205
2206 const struct iwl_trans_ops trans_ops_pcie = {
2207 .start_hw = iwl_trans_pcie_start_hw,
2208 .stop_hw = iwl_trans_pcie_stop_hw,
2209 .fw_alive = iwl_trans_pcie_fw_alive,
2210 .start_fw = iwl_trans_pcie_start_fw,
2211 .stop_device = iwl_trans_pcie_stop_device,
2212
2213 .wake_any_queue = iwl_trans_pcie_wake_any_queue,
2214
2215 .send_cmd = iwl_trans_pcie_send_cmd,
2216
2217 .tx = iwl_trans_pcie_tx,
2218 .reclaim = iwl_trans_pcie_reclaim,
2219
2220 .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
2221 .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
2222 .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
2223
2224 .free = iwl_trans_pcie_free,
2225 .stop_queue = iwl_trans_pcie_stop_queue,
2226
2227 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2228
2229 .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2230 .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
2231
2232 #ifdef CONFIG_PM_SLEEP
2233 .suspend = iwl_trans_pcie_suspend,
2234 .resume = iwl_trans_pcie_resume,
2235 #endif
2236 .write8 = iwl_trans_pcie_write8,
2237 .write32 = iwl_trans_pcie_write32,
2238 .read32 = iwl_trans_pcie_read32,
2239 };
2240
2241 struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
2242 struct pci_dev *pdev,
2243 const struct pci_device_id *ent)
2244 {
2245 struct iwl_trans_pcie *trans_pcie;
2246 struct iwl_trans *trans;
2247 u16 pci_cmd;
2248 int err;
2249
2250 trans = kzalloc(sizeof(struct iwl_trans) +
2251 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2252
2253 if (WARN_ON(!trans))
2254 return NULL;
2255
2256 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2257
2258 trans->ops = &trans_ops_pcie;
2259 trans->shrd = shrd;
2260 trans_pcie->trans = trans;
2261 spin_lock_init(&trans->hcmd_lock);
2262
2263 /* W/A - seems to solve weird behavior. We need to remove this if we
2264 * don't want to stay in L1 all the time. This wastes a lot of power */
2265 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2266 PCIE_LINK_STATE_CLKPM);
2267
2268 if (pci_enable_device(pdev)) {
2269 err = -ENODEV;
2270 goto out_no_pci;
2271 }
2272
2273 pci_set_master(pdev);
2274
2275 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2276 if (!err)
2277 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2278 if (err) {
2279 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2280 if (!err)
2281 err = pci_set_consistent_dma_mask(pdev,
2282 DMA_BIT_MASK(32));
2283 /* both attempts failed: */
2284 if (err) {
2285 dev_printk(KERN_ERR, &pdev->dev,
2286 "No suitable DMA available.\n");
2287 goto out_pci_disable_device;
2288 }
2289 }
2290
2291 err = pci_request_regions(pdev, DRV_NAME);
2292 if (err) {
2293 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2294 goto out_pci_disable_device;
2295 }
2296
2297 trans_pcie->hw_base = pci_iomap(pdev, 0, 0);
2298 if (!trans_pcie->hw_base) {
2299 dev_printk(KERN_ERR, &pdev->dev, "pci_iomap failed");
2300 err = -ENODEV;
2301 goto out_pci_release_regions;
2302 }
2303
2304 dev_printk(KERN_INFO, &pdev->dev,
2305 "pci_resource_len = 0x%08llx\n",
2306 (unsigned long long) pci_resource_len(pdev, 0));
2307 dev_printk(KERN_INFO, &pdev->dev,
2308 "pci_resource_base = %p\n", trans_pcie->hw_base);
2309
2310 dev_printk(KERN_INFO, &pdev->dev,
2311 "HW Revision ID = 0x%X\n", pdev->revision);
2312
2313 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2314 * PCI Tx retries from interfering with C3 CPU state */
2315 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2316
2317 err = pci_enable_msi(pdev);
2318 if (err)
2319 dev_printk(KERN_ERR, &pdev->dev,
2320 "pci_enable_msi failed(0X%x)", err);
2321
2322 trans->dev = &pdev->dev;
2323 trans->irq = pdev->irq;
2324 trans_pcie->pci_dev = pdev;
2325 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2326 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2327 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2328 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2329
2330 /* TODO: Move this away, not needed if not MSI */
2331 /* enable rfkill interrupt: hw bug w/a */
2332 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2333 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2334 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2335 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2336 }
2337
2338 return trans;
2339
2340 out_pci_release_regions:
2341 pci_release_regions(pdev);
2342 out_pci_disable_device:
2343 pci_disable_device(pdev);
2344 out_no_pci:
2345 kfree(trans);
2346 return NULL;
2347 }
2348
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