drivers/net/wireless/iwlwifi/pcie/internal.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
   4  * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
   5  *
   6  * Portions of this file are derived from the ipw3945 project, as well
   7  * as portions of the ieee80211 subsystem header files.
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * this program; if not, write to the Free Software Foundation, Inc.,
  20  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  21  *
  22  * The full GNU General Public License is included in this distribution in the
  23  * file called LICENSE.
  24  *
  25  * Contact Information:
  26  *  Intel Linux Wireless <ilw@linux.intel.com>
  27  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  28  *
  29  *****************************************************************************/
  30 #ifndef __iwl_trans_int_pcie_h__
  31 #define __iwl_trans_int_pcie_h__
  32
  33 #include <linux/spinlock.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/skbuff.h>
  36 #include <linux/wait.h>
  37 #include <linux/pci.h>
  38 #include <linux/timer.h>
  39
  40 #include "iwl-fh.h"
  41 #include "iwl-csr.h"
  42 #include "iwl-trans.h"
  43 #include "iwl-debug.h"
  44 #include "iwl-io.h"
  45 #include "iwl-op-mode.h"
  46
  47 struct iwl_host_cmd;
  48
  49 /*This file includes the declaration that are internal to the
  50  * trans_pcie layer */
  51
  52 struct iwl_rx_mem_buffer {
  53         dma_addr_t page_dma;
  54         struct page *page;
  55         struct list_head list;
  56 };
  57
  58 /**
  59  * struct isr_statistics - interrupt statistics
  60  *
  61  */
  62 struct isr_statistics {
  63         u32 hw;
  64         u32 sw;
  65         u32 err_code;
  66         u32 sch;
  67         u32 alive;
  68         u32 rfkill;
  69         u32 ctkill;
  70         u32 wakeup;
  71         u32 rx;
  72         u32 tx;
  73         u32 unhandled;
  74 };
  75
  76 /**
  77  * struct iwl_rxq - Rx queue
  78  * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
  79  * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
  80  * @pool:
  81  * @queue:
  82  * @read: Shared index to newest available Rx buffer
  83  * @write: Shared index to oldest written Rx packet
  84  * @free_count: Number of pre-allocated buffers in rx_free
  85  * @write_actual:
  86  * @rx_free: list of free SKBs for use
  87  * @rx_used: List of Rx buffers with no SKB
  88  * @need_update: flag to indicate we need to update read/write index
  89  * @rb_stts: driver's pointer to receive buffer status
  90  * @rb_stts_dma: bus address of receive buffer status
  91  * @lock:
  92  *
  93  * NOTE:  rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
  94  */
  95 struct iwl_rxq {
  96         __le32 *bd;
  97         dma_addr_t bd_dma;
  98         struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
  99         struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
 100         u32 read;
 101         u32 write;
 102         u32 free_count;
 103         u32 write_actual;
 104         struct list_head rx_free;
 105         struct list_head rx_used;
 106         bool need_update;
 107         struct iwl_rb_status *rb_stts;
 108         dma_addr_t rb_stts_dma;
 109         spinlock_t lock;
 110 };
 111
 112 struct iwl_dma_ptr {
 113         dma_addr_t dma;
 114         void *addr;
 115         size_t size;
 116 };
 117
 118 /**
 119  * iwl_queue_inc_wrap - increment queue index, wrap back to beginning
 120  * @index -- current index
 121  */
 122 static inline int iwl_queue_inc_wrap(int index)
 123 {
 124         return ++index & (TFD_QUEUE_SIZE_MAX - 1);
 125 }
 126
 127 /**
 128  * iwl_queue_dec_wrap - decrement queue index, wrap back to end
 129  * @index -- current index
 130  */
 131 static inline int iwl_queue_dec_wrap(int index)
 132 {
 133         return --index & (TFD_QUEUE_SIZE_MAX - 1);
 134 }
 135
 136 struct iwl_cmd_meta {
 137         /* only for SYNC commands, iff the reply skb is wanted */
 138         struct iwl_host_cmd *source;
 139         u32 flags;
 140 };
 141
 142 /*
 143  * Generic queue structure
 144  *
 145  * Contains common data for Rx and Tx queues.
 146  *
 147  * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware
 148  * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless
 149  * there might be HW changes in the future). For the normal TX
 150  * queues, n_window, which is the size of the software queue data
 151  * is also 256; however, for the command queue, n_window is only
 152  * 32 since we don't need so many commands pending. Since the HW
 153  * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. As a result,
 154  * the software buffers (in the variables @meta, @txb in struct
 155  * iwl_txq) only have 32 entries, while the HW buffers (@tfds in
 156  * the same struct) have 256.
 157  * This means that we end up with the following:
 158  *  HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
 159  *  SW entries:           | 0      | ... | 31          |
 160  * where N is a number between 0 and 7. This means that the SW
 161  * data is a window overlayed over the HW queue.
 162  */
 163 struct iwl_queue {
 164         int write_ptr;       /* 1-st empty entry (index) host_w*/
 165         int read_ptr;         /* last used entry (index) host_r*/
 166         /* use for monitoring and recovering the stuck queue */
 167         dma_addr_t dma_addr;   /* physical addr for BD's */
 168         int n_window;          /* safe queue window */
 169         u32 id;
 170         int low_mark;          /* low watermark, resume queue if free
 171                                 * space more than this */
 172         int high_mark;         /* high watermark, stop queue if free
 173                                 * space less than this */
 174 };
 175
 176 #define TFD_TX_CMD_SLOTS 256
 177 #define TFD_CMD_SLOTS 32
 178
 179 /*
 180  * The FH will write back to the first TB only, so we need
 181  * to copy some data into the buffer regardless of whether
 182  * it should be mapped or not. This indicates how big the
 183  * first TB must be to include the scratch buffer. Since
 184  * the scratch is 4 bytes at offset 12, it's 16 now. If we
 185  * make it bigger then allocations will be bigger and copy
 186  * slower, so that's probably not useful.
 187  */
 188 #define IWL_HCMD_SCRATCHBUF_SIZE        16
 189
 190 struct iwl_pcie_txq_entry {
 191         struct iwl_device_cmd *cmd;
 192         struct sk_buff *skb;
 193         /* buffer to free after command completes */
 194         const void *free_buf;
 195         struct iwl_cmd_meta meta;
 196 };
 197
 198 struct iwl_pcie_txq_scratch_buf {
 199         struct iwl_cmd_header hdr;
 200         u8 buf[8];
 201         __le32 scratch;
 202 };
 203
 204 /**
 205  * struct iwl_txq - Tx Queue for DMA
 206  * @q: generic Rx/Tx queue descriptor
 207  * @tfds: transmit frame descriptors (DMA memory)
 208  * @scratchbufs: start of command headers, including scratch buffers, for
 209  *      the writeback -- this is DMA memory and an array holding one buffer
 210  *      for each command on the queue
 211  * @scratchbufs_dma: DMA address for the scratchbufs start
 212  * @entries: transmit entries (driver state)
 213  * @lock: queue lock
 214  * @stuck_timer: timer that fires if queue gets stuck
 215  * @trans_pcie: pointer back to transport (for timer)
 216  * @need_update: indicates need to update read/write index
 217  * @active: stores if queue is active
 218  * @ampdu: true if this queue is an ampdu queue for an specific RA/TID
 219  *
 220  * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
 221  * descriptors) and required locking structures.
 222  */
 223 struct iwl_txq {
 224         struct iwl_queue q;
 225         struct iwl_tfd *tfds;
 226         struct iwl_pcie_txq_scratch_buf *scratchbufs;
 227         dma_addr_t scratchbufs_dma;
 228         struct iwl_pcie_txq_entry *entries;
 229         spinlock_t lock;
 230         struct timer_list stuck_timer;
 231         struct iwl_trans_pcie *trans_pcie;
 232         bool need_update;
 233         u8 active;
 234         bool ampdu;
 235 };
 236
 237 static inline dma_addr_t
 238 iwl_pcie_get_scratchbuf_dma(struct iwl_txq *txq, int idx)
 239 {
 240         return txq->scratchbufs_dma +
 241                sizeof(struct iwl_pcie_txq_scratch_buf) * idx;
 242 }
 243
 244 /**
 245  * struct iwl_trans_pcie - PCIe transport specific data
 246  * @rxq: all the RX queue data
 247  * @rx_replenish: work that will be called when buffers need to be allocated
 248  * @drv - pointer to iwl_drv
 249  * @trans: pointer to the generic transport area
 250  * @scd_base_addr: scheduler sram base address in SRAM
 251  * @scd_bc_tbls: pointer to the byte count table of the scheduler
 252  * @kw: keep warm address
 253  * @pci_dev: basic pci-network driver stuff
 254  * @hw_base: pci hardware address support
 255  * @ucode_write_complete: indicates that the ucode has been copied.
 256  * @ucode_write_waitq: wait queue for uCode load
 257  * @cmd_queue - command queue number
 258  * @rx_buf_size_8k: 8 kB RX buffer size
 259  * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes)
 260  * @rx_page_order: page order for receive buffer size
 261  * @wd_timeout: queue watchdog timeout (jiffies)
 262  * @reg_lock: protect hw register access
 263  * @cmd_in_flight: true when we have a host command in flight
 264  * @fw_mon_phys: physical address of the buffer for the firmware monitor
 265  * @fw_mon_page: points to the first page of the buffer for the firmware monitor
 266  * @fw_mon_size: size of the buffer for the firmware monitor
 267  */
 268 struct iwl_trans_pcie {
 269         struct iwl_rxq rxq;
 270         struct work_struct rx_replenish;
 271         struct iwl_trans *trans;
 272         struct iwl_drv *drv;
 273
 274         struct net_device napi_dev;
 275         struct napi_struct napi;
 276
 277         /* INT ICT Table */
 278         __le32 *ict_tbl;
 279         dma_addr_t ict_tbl_dma;
 280         int ict_index;
 281         bool use_ict;
 282         struct isr_statistics isr_stats;
 283
 284         spinlock_t irq_lock;
 285         u32 inta_mask;
 286         u32 scd_base_addr;
 287         struct iwl_dma_ptr scd_bc_tbls;
 288         struct iwl_dma_ptr kw;
 289
 290         struct iwl_txq *txq;
 291         unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
 292         unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
 293
 294         /* PCI bus related data */
 295         struct pci_dev *pci_dev;
 296         void __iomem *hw_base;
 297
 298         bool ucode_write_complete;
 299         wait_queue_head_t ucode_write_waitq;
 300         wait_queue_head_t wait_command_queue;
 301
 302         u8 cmd_queue;
 303         u8 cmd_fifo;
 304         u8 n_no_reclaim_cmds;
 305         u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
 306
 307         bool rx_buf_size_8k;
 308         bool bc_table_dword;
 309         u32 rx_page_order;
 310
 311         const char *const *command_names;
 312
 313         /* queue watchdog */
 314         unsigned long wd_timeout;
 315
 316         /*protect hw register */
 317         spinlock_t reg_lock;
 318         bool cmd_in_flight;
 319
 320         dma_addr_t fw_mon_phys;
 321         struct page *fw_mon_page;
 322         u32 fw_mon_size;
 323 };
 324
 325 #define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
 326         ((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific))
 327
 328 static inline struct iwl_trans *
 329 iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
 330 {
 331         return container_of((void *)trans_pcie, struct iwl_trans,
 332                             trans_specific);
 333 }
 334
 335 /*
 336  * Convention: trans API functions: iwl_trans_pcie_XXX
 337  *      Other functions: iwl_pcie_XXX
 338  */
 339 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
 340                                        const struct pci_device_id *ent,
 341                                        const struct iwl_cfg *cfg);
 342 void iwl_trans_pcie_free(struct iwl_trans *trans);
 343
 344 /*****************************************************
 345 * RX
 346 ******************************************************/
 347 int iwl_pcie_rx_init(struct iwl_trans *trans);
 348 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id);
 349 int iwl_pcie_rx_stop(struct iwl_trans *trans);
 350 void iwl_pcie_rx_free(struct iwl_trans *trans);
 351
 352 /*****************************************************
 353 * ICT - interrupt handling
 354 ******************************************************/
 355 irqreturn_t iwl_pcie_isr(int irq, void *data);
 356 int iwl_pcie_alloc_ict(struct iwl_trans *trans);
 357 void iwl_pcie_free_ict(struct iwl_trans *trans);
 358 void iwl_pcie_reset_ict(struct iwl_trans *trans);
 359 void iwl_pcie_disable_ict(struct iwl_trans *trans);
 360
 361 /*****************************************************
 362 * TX / HCMD
 363 ******************************************************/
 364 int iwl_pcie_tx_init(struct iwl_trans *trans);
 365 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr);
 366 int iwl_pcie_tx_stop(struct iwl_trans *trans);
 367 void iwl_pcie_tx_free(struct iwl_trans *trans);
 368 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn,
 369                                const struct iwl_trans_txq_scd_cfg *cfg);
 370 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue,
 371                                 bool configure_scd);
 372 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
 373                       struct iwl_device_cmd *dev_cmd, int txq_id);
 374 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans);
 375 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
 376 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
 377                             struct iwl_rx_cmd_buffer *rxb, int handler_status);
 378 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
 379                             struct sk_buff_head *skbs);
 380 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);
 381
 382 static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 383 {
 384         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 385
 386         return le16_to_cpu(tb->hi_n_len) >> 4;
 387 }
 388
 389 /*****************************************************
 390 * Error handling
 391 ******************************************************/
 392 void iwl_pcie_dump_csr(struct iwl_trans *trans);
 393
 394 /*****************************************************
 395 * Helpers
 396 ******************************************************/
 397 static inline void iwl_disable_interrupts(struct iwl_trans *trans)
 398 {
 399         clear_bit(STATUS_INT_ENABLED, &trans->status);
 400
 401         /* disable interrupts from uCode/NIC to host */
 402         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
 403
 404         /* acknowledge/clear/reset any interrupts still pending
 405          * from uCode or flow handler (Rx/Tx DMA) */
 406         iwl_write32(trans, CSR_INT, 0xffffffff);
 407         iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
 408         IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
 409 }
 410
 411 static inline void iwl_enable_interrupts(struct iwl_trans *trans)
 412 {
 413         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 414
 415         IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
 416         set_bit(STATUS_INT_ENABLED, &trans->status);
 417         trans_pcie->inta_mask = CSR_INI_SET_MASK;
 418         iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
 419 }
 420
 421 static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
 422 {
 423         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 424
 425         IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
 426         trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL;
 427         iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
 428 }
 429
 430 static inline void iwl_wake_queue(struct iwl_trans *trans,
 431                                   struct iwl_txq *txq)
 432 {
 433         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 434
 435         if (test_and_clear_bit(txq->q.id, trans_pcie->queue_stopped)) {
 436                 IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->q.id);
 437                 iwl_op_mode_queue_not_full(trans->op_mode, txq->q.id);
 438         }
 439 }
 440
 441 static inline void iwl_stop_queue(struct iwl_trans *trans,
 442                                   struct iwl_txq *txq)
 443 {
 444         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 445
 446         if (!test_and_set_bit(txq->q.id, trans_pcie->queue_stopped)) {
 447                 iwl_op_mode_queue_full(trans->op_mode, txq->q.id);
 448                 IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->q.id);
 449         } else
 450                 IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n",
 451                                     txq->q.id);
 452 }
 453
 454 static inline bool iwl_queue_used(const struct iwl_queue *q, int i)
 455 {
 456         return q->write_ptr >= q->read_ptr ?
 457                 (i >= q->read_ptr && i < q->write_ptr) :
 458                 !(i < q->read_ptr && i >= q->write_ptr);
 459 }
 460
 461 static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
 462 {
 463         return index & (q->n_window - 1);
 464 }
 465
 466 static inline const char *get_cmd_string(struct iwl_trans_pcie *trans_pcie,
 467                                          u8 cmd)
 468 {
 469         if (!trans_pcie->command_names || !trans_pcie->command_names[cmd])
 470                 return "UNKNOWN";
 471         return trans_pcie->command_names[cmd];
 472 }
 473
 474 static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
 475 {
 476         return !(iwl_read32(trans, CSR_GP_CNTRL) &
 477                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
 478 }
 479
 480 static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
 481                                                   u32 reg, u32 mask, u32 value)
 482 {
 483         u32 v;
 484
 485 #ifdef CONFIG_IWLWIFI_DEBUG
 486         WARN_ON_ONCE(value & ~mask);
 487 #endif
 488
 489         v = iwl_read32(trans, reg);
 490         v &= ~mask;
 491         v |= value;
 492         iwl_write32(trans, reg, v);
 493 }
 494
 495 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
 496                                               u32 reg, u32 mask)
 497 {
 498         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
 499 }
 500
 501 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
 502                                             u32 reg, u32 mask)
 503 {
 504         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
 505 }
 506
 507 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state);
 508
 509 #endif /* __iwl_trans_int_pcie_h__ */