1 /******************************************************************************
3 * Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #include <linux/sched.h>
30 #include <linux/wait.h>
31 #include <linux/gfp.h>
36 #include "iwl-op-mode.h"
38 /******************************************************************************
42 ******************************************************************************/
45 * Rx theory of operation
47 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
48 * each of which point to Receive Buffers to be filled by the NIC. These get
49 * used not only for Rx frames, but for any command response or notification
50 * from the NIC. The driver and NIC manage the Rx buffers by means
51 * of indexes into the circular buffer.
54 * The host/firmware share two index registers for managing the Rx buffers.
56 * The READ index maps to the first position that the firmware may be writing
57 * to -- the driver can read up to (but not including) this position and get
59 * The READ index is managed by the firmware once the card is enabled.
61 * The WRITE index maps to the last position the driver has read from -- the
62 * position preceding WRITE is the last slot the firmware can place a packet.
64 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
67 * During initialization, the host sets up the READ queue position to the first
68 * INDEX position, and WRITE to the last (READ - 1 wrapped)
70 * When the firmware places a packet in a buffer, it will advance the READ index
71 * and fire the RX interrupt. The driver can then query the READ index and
72 * process as many packets as possible, moving the WRITE index forward as it
73 * resets the Rx queue buffers with new memory.
75 * The management in the driver is as follows:
76 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
77 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
78 * to replenish the iwl->rxq->rx_free.
79 * + In iwl_pcie_rx_replenish (scheduled) if 'processed' != 'read' then the
80 * iwl->rxq is replenished and the READ INDEX is updated (updating the
81 * 'processed' and 'read' driver indexes as well)
82 * + A received packet is processed and handed to the kernel network stack,
83 * detached from the iwl->rxq. The driver 'processed' index is updated.
84 * + The Host/Firmware iwl->rxq is replenished at irq thread time from the
85 * rx_free list. If there are no allocated buffers in iwl->rxq->rx_free,
86 * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.
87 * If there were enough free buffers and RX_STALLED is set it is cleared.
92 * iwl_rxq_alloc() Allocates rx_free
93 * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls
94 * iwl_pcie_rxq_restock
95 * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx
96 * queue, updates firmware pointers, and updates
97 * the WRITE index. If insufficient rx_free buffers
98 * are available, schedules iwl_pcie_rx_replenish
100 * -- enable interrupts --
101 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
102 * READ INDEX, detaching the SKB from the pool.
103 * Moves the packet buffer from queue to rx_used.
104 * Calls iwl_pcie_rxq_restock to refill any empty
111 * iwl_rxq_space - Return number of free slots available in queue.
113 static int iwl_rxq_space(const struct iwl_rxq
*rxq
)
115 /* Make sure RX_QUEUE_SIZE is a power of 2 */
116 BUILD_BUG_ON(RX_QUEUE_SIZE
& (RX_QUEUE_SIZE
- 1));
119 * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity
120 * between empty and completely full queues.
121 * The following is equivalent to modulo by RX_QUEUE_SIZE and is well
122 * defined for negative dividends.
124 return (rxq
->read
- rxq
->write
- 1) & (RX_QUEUE_SIZE
- 1);
128 * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
130 static inline __le32
iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr
)
132 return cpu_to_le32((u32
)(dma_addr
>> 8));
136 * iwl_pcie_rx_stop - stops the Rx DMA
138 int iwl_pcie_rx_stop(struct iwl_trans
*trans
)
140 iwl_write_direct32(trans
, FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
141 return iwl_poll_direct_bit(trans
, FH_MEM_RSSR_RX_STATUS_REG
,
142 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE
, 1000);
146 * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
148 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans
*trans
,
154 spin_lock_irqsave(&rxq
->lock
, flags
);
156 if (rxq
->need_update
== 0)
159 if (trans
->cfg
->base_params
->shadow_reg_enable
) {
160 /* shadow register enabled */
161 /* Device expects a multiple of 8 */
162 rxq
->write_actual
= (rxq
->write
& ~0x7);
163 iwl_write32(trans
, FH_RSCSR_CHNL0_WPTR
, rxq
->write_actual
);
165 struct iwl_trans_pcie
*trans_pcie
=
166 IWL_TRANS_GET_PCIE_TRANS(trans
);
168 /* If power-saving is in use, make sure device is awake */
169 if (test_bit(STATUS_TPOWER_PMI
, &trans_pcie
->status
)) {
170 reg
= iwl_read32(trans
, CSR_UCODE_DRV_GP1
);
172 if (reg
& CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP
) {
173 IWL_DEBUG_INFO(trans
,
174 "Rx queue requesting wakeup,"
175 " GP1 = 0x%x\n", reg
);
176 iwl_set_bit(trans
, CSR_GP_CNTRL
,
177 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
181 rxq
->write_actual
= (rxq
->write
& ~0x7);
182 iwl_write_direct32(trans
, FH_RSCSR_CHNL0_WPTR
,
185 /* Else device is assumed to be awake */
187 /* Device expects a multiple of 8 */
188 rxq
->write_actual
= (rxq
->write
& ~0x7);
189 iwl_write_direct32(trans
, FH_RSCSR_CHNL0_WPTR
,
193 rxq
->need_update
= 0;
196 spin_unlock_irqrestore(&rxq
->lock
, flags
);
200 * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
202 * If there are slots in the RX queue that need to be restocked,
203 * and we have free pre-allocated buffers, fill the ranks as much
204 * as we can, pulling from rx_free.
206 * This moves the 'write' index forward to catch up with 'processed', and
207 * also updates the memory address in the firmware to reference the new
210 static void iwl_pcie_rxq_restock(struct iwl_trans
*trans
)
212 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
213 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
;
214 struct iwl_rx_mem_buffer
*rxb
;
218 * If the device isn't enabled - not need to try to add buffers...
219 * This can happen when we stop the device and still have an interrupt
220 * pending. We stop the APM before we sync the interrupts because we
221 * have to (see comment there). On the other hand, since the APM is
222 * stopped, we cannot access the HW (in particular not prph).
223 * So don't try to restock if the APM has been already stopped.
225 if (!test_bit(STATUS_DEVICE_ENABLED
, &trans_pcie
->status
))
228 spin_lock_irqsave(&rxq
->lock
, flags
);
229 while ((iwl_rxq_space(rxq
) > 0) && (rxq
->free_count
)) {
230 /* The overwritten rxb must be a used one */
231 rxb
= rxq
->queue
[rxq
->write
];
232 BUG_ON(rxb
&& rxb
->page
);
234 /* Get next free Rx buffer, remove from free list */
235 rxb
= list_first_entry(&rxq
->rx_free
, struct iwl_rx_mem_buffer
,
237 list_del(&rxb
->list
);
239 /* Point to Rx buffer via next RBD in circular buffer */
240 rxq
->bd
[rxq
->write
] = iwl_pcie_dma_addr2rbd_ptr(rxb
->page_dma
);
241 rxq
->queue
[rxq
->write
] = rxb
;
242 rxq
->write
= (rxq
->write
+ 1) & RX_QUEUE_MASK
;
245 spin_unlock_irqrestore(&rxq
->lock
, flags
);
246 /* If the pre-allocated buffer pool is dropping low, schedule to
248 if (rxq
->free_count
<= RX_LOW_WATERMARK
)
249 schedule_work(&trans_pcie
->rx_replenish
);
251 /* If we've added more space for the firmware to place data, tell it.
252 * Increment device's write pointer in multiples of 8. */
253 if (rxq
->write_actual
!= (rxq
->write
& ~0x7)) {
254 spin_lock_irqsave(&rxq
->lock
, flags
);
255 rxq
->need_update
= 1;
256 spin_unlock_irqrestore(&rxq
->lock
, flags
);
257 iwl_pcie_rxq_inc_wr_ptr(trans
, rxq
);
262 * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
264 * A used RBD is an Rx buffer that has been given to the stack. To use it again
265 * a page must be allocated and the RBD must point to the page. This function
266 * doesn't change the HW pointer but handles the list of pages that is used by
267 * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
270 static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans
*trans
, gfp_t priority
)
272 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
273 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
;
274 struct iwl_rx_mem_buffer
*rxb
;
277 gfp_t gfp_mask
= priority
;
280 spin_lock_irqsave(&rxq
->lock
, flags
);
281 if (list_empty(&rxq
->rx_used
)) {
282 spin_unlock_irqrestore(&rxq
->lock
, flags
);
285 spin_unlock_irqrestore(&rxq
->lock
, flags
);
287 if (rxq
->free_count
> RX_LOW_WATERMARK
)
288 gfp_mask
|= __GFP_NOWARN
;
290 if (trans_pcie
->rx_page_order
> 0)
291 gfp_mask
|= __GFP_COMP
;
293 /* Alloc a new receive buffer */
294 page
= alloc_pages(gfp_mask
, trans_pcie
->rx_page_order
);
297 IWL_DEBUG_INFO(trans
, "alloc_pages failed, "
299 trans_pcie
->rx_page_order
);
301 if ((rxq
->free_count
<= RX_LOW_WATERMARK
) &&
303 IWL_CRIT(trans
, "Failed to alloc_pages with %s."
304 "Only %u free buffers remaining.\n",
305 priority
== GFP_ATOMIC
?
306 "GFP_ATOMIC" : "GFP_KERNEL",
308 /* We don't reschedule replenish work here -- we will
309 * call the restock method and if it still needs
310 * more buffers it will schedule replenish */
314 spin_lock_irqsave(&rxq
->lock
, flags
);
316 if (list_empty(&rxq
->rx_used
)) {
317 spin_unlock_irqrestore(&rxq
->lock
, flags
);
318 __free_pages(page
, trans_pcie
->rx_page_order
);
321 rxb
= list_first_entry(&rxq
->rx_used
, struct iwl_rx_mem_buffer
,
323 list_del(&rxb
->list
);
324 spin_unlock_irqrestore(&rxq
->lock
, flags
);
328 /* Get physical address of the RB */
330 dma_map_page(trans
->dev
, page
, 0,
331 PAGE_SIZE
<< trans_pcie
->rx_page_order
,
333 if (dma_mapping_error(trans
->dev
, rxb
->page_dma
)) {
335 spin_lock_irqsave(&rxq
->lock
, flags
);
336 list_add(&rxb
->list
, &rxq
->rx_used
);
337 spin_unlock_irqrestore(&rxq
->lock
, flags
);
338 __free_pages(page
, trans_pcie
->rx_page_order
);
341 /* dma address must be no more than 36 bits */
342 BUG_ON(rxb
->page_dma
& ~DMA_BIT_MASK(36));
343 /* and also 256 byte aligned! */
344 BUG_ON(rxb
->page_dma
& DMA_BIT_MASK(8));
346 spin_lock_irqsave(&rxq
->lock
, flags
);
348 list_add_tail(&rxb
->list
, &rxq
->rx_free
);
351 spin_unlock_irqrestore(&rxq
->lock
, flags
);
355 static void iwl_pcie_rxq_free_rbs(struct iwl_trans
*trans
)
357 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
358 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
;
361 lockdep_assert_held(&rxq
->lock
);
363 for (i
= 0; i
< RX_FREE_BUFFERS
+ RX_QUEUE_SIZE
; i
++) {
364 if (!rxq
->pool
[i
].page
)
366 dma_unmap_page(trans
->dev
, rxq
->pool
[i
].page_dma
,
367 PAGE_SIZE
<< trans_pcie
->rx_page_order
,
369 __free_pages(rxq
->pool
[i
].page
, trans_pcie
->rx_page_order
);
370 rxq
->pool
[i
].page
= NULL
;
375 * iwl_pcie_rx_replenish - Move all used buffers from rx_used to rx_free
377 * When moving to rx_free an page is allocated for the slot.
379 * Also restock the Rx queue via iwl_pcie_rxq_restock.
380 * This is called as a scheduled work item (except for during initialization)
382 static void iwl_pcie_rx_replenish(struct iwl_trans
*trans
)
384 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
387 iwl_pcie_rxq_alloc_rbs(trans
, GFP_KERNEL
);
389 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
390 iwl_pcie_rxq_restock(trans
);
391 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
394 static void iwl_pcie_rx_replenish_now(struct iwl_trans
*trans
)
396 iwl_pcie_rxq_alloc_rbs(trans
, GFP_ATOMIC
);
398 iwl_pcie_rxq_restock(trans
);
401 static void iwl_pcie_rx_replenish_work(struct work_struct
*data
)
403 struct iwl_trans_pcie
*trans_pcie
=
404 container_of(data
, struct iwl_trans_pcie
, rx_replenish
);
406 iwl_pcie_rx_replenish(trans_pcie
->trans
);
409 static int iwl_pcie_rx_alloc(struct iwl_trans
*trans
)
411 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
412 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
;
413 struct device
*dev
= trans
->dev
;
415 memset(&trans_pcie
->rxq
, 0, sizeof(trans_pcie
->rxq
));
417 spin_lock_init(&rxq
->lock
);
419 if (WARN_ON(rxq
->bd
|| rxq
->rb_stts
))
422 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
423 rxq
->bd
= dma_zalloc_coherent(dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
424 &rxq
->bd_dma
, GFP_KERNEL
);
428 /*Allocate the driver's pointer to receive buffer status */
429 rxq
->rb_stts
= dma_zalloc_coherent(dev
, sizeof(*rxq
->rb_stts
),
430 &rxq
->rb_stts_dma
, GFP_KERNEL
);
437 dma_free_coherent(dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
438 rxq
->bd
, rxq
->bd_dma
);
445 static void iwl_pcie_rx_hw_init(struct iwl_trans
*trans
, struct iwl_rxq
*rxq
)
447 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
449 const u32 rfdnlog
= RX_QUEUE_SIZE_LOG
; /* 256 RBDs */
451 if (trans_pcie
->rx_buf_size_8k
)
452 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K
;
454 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K
;
457 iwl_write_direct32(trans
, FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
458 /* reset and flush pointers */
459 iwl_write_direct32(trans
, FH_MEM_RCSR_CHNL0_RBDCB_WPTR
, 0);
460 iwl_write_direct32(trans
, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ
, 0);
461 iwl_write_direct32(trans
, FH_RSCSR_CHNL0_RDPTR
, 0);
463 /* Reset driver's Rx queue write index */
464 iwl_write_direct32(trans
, FH_RSCSR_CHNL0_RBDCB_WPTR_REG
, 0);
466 /* Tell device where to find RBD circular buffer in DRAM */
467 iwl_write_direct32(trans
, FH_RSCSR_CHNL0_RBDCB_BASE_REG
,
468 (u32
)(rxq
->bd_dma
>> 8));
470 /* Tell device where in DRAM to update its Rx status */
471 iwl_write_direct32(trans
, FH_RSCSR_CHNL0_STTS_WPTR_REG
,
472 rxq
->rb_stts_dma
>> 4);
475 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
476 * the credit mechanism in 5000 HW RX FIFO
477 * Direct rx interrupts to hosts
478 * Rx buffer size 4 or 8k
482 iwl_write_direct32(trans
, FH_MEM_RCSR_CHNL0_CONFIG_REG
,
483 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL
|
484 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY
|
485 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL
|
487 (RX_RB_TIMEOUT
<< FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS
)|
488 (rfdnlog
<< FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS
));
490 /* Set interrupt coalescing timer to default (2048 usecs) */
491 iwl_write8(trans
, CSR_INT_COALESCING
, IWL_HOST_INT_TIMEOUT_DEF
);
493 /* W/A for interrupt coalescing bug in 7260 and 3160 */
494 if (trans
->cfg
->host_interrupt_operation_mode
)
495 iwl_set_bit(trans
, CSR_INT_COALESCING
, IWL_HOST_INT_OPER_MODE
);
498 static void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq
*rxq
)
502 lockdep_assert_held(&rxq
->lock
);
504 INIT_LIST_HEAD(&rxq
->rx_free
);
505 INIT_LIST_HEAD(&rxq
->rx_used
);
508 for (i
= 0; i
< RX_FREE_BUFFERS
+ RX_QUEUE_SIZE
; i
++)
509 list_add(&rxq
->pool
[i
].list
, &rxq
->rx_used
);
512 int iwl_pcie_rx_init(struct iwl_trans
*trans
)
514 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
515 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
;
520 err
= iwl_pcie_rx_alloc(trans
);
525 spin_lock_irqsave(&rxq
->lock
, flags
);
527 INIT_WORK(&trans_pcie
->rx_replenish
, iwl_pcie_rx_replenish_work
);
529 /* free all first - we might be reconfigured for a different size */
530 iwl_pcie_rxq_free_rbs(trans
);
531 iwl_pcie_rx_init_rxb_lists(rxq
);
533 for (i
= 0; i
< RX_QUEUE_SIZE
; i
++)
534 rxq
->queue
[i
] = NULL
;
536 /* Set us so that we have processed and used all buffers, but have
537 * not restocked the Rx queue with fresh buffers */
538 rxq
->read
= rxq
->write
= 0;
539 rxq
->write_actual
= 0;
540 memset(rxq
->rb_stts
, 0, sizeof(*rxq
->rb_stts
));
541 spin_unlock_irqrestore(&rxq
->lock
, flags
);
543 iwl_pcie_rx_replenish(trans
);
545 iwl_pcie_rx_hw_init(trans
, rxq
);
547 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
548 rxq
->need_update
= 1;
549 iwl_pcie_rxq_inc_wr_ptr(trans
, rxq
);
550 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
555 void iwl_pcie_rx_free(struct iwl_trans
*trans
)
557 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
558 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
;
561 /*if rxq->bd is NULL, it means that nothing has been allocated,
564 IWL_DEBUG_INFO(trans
, "Free NULL rx context\n");
568 cancel_work_sync(&trans_pcie
->rx_replenish
);
570 spin_lock_irqsave(&rxq
->lock
, flags
);
571 iwl_pcie_rxq_free_rbs(trans
);
572 spin_unlock_irqrestore(&rxq
->lock
, flags
);
574 dma_free_coherent(trans
->dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
575 rxq
->bd
, rxq
->bd_dma
);
580 dma_free_coherent(trans
->dev
,
581 sizeof(struct iwl_rb_status
),
582 rxq
->rb_stts
, rxq
->rb_stts_dma
);
584 IWL_DEBUG_INFO(trans
, "Free rxq->rb_stts which is NULL\n");
585 rxq
->rb_stts_dma
= 0;
589 static void iwl_pcie_rx_handle_rb(struct iwl_trans
*trans
,
590 struct iwl_rx_mem_buffer
*rxb
)
592 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
593 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
;
594 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
596 bool page_stolen
= false;
597 int max_len
= PAGE_SIZE
<< trans_pcie
->rx_page_order
;
603 dma_unmap_page(trans
->dev
, rxb
->page_dma
, max_len
, DMA_FROM_DEVICE
);
605 while (offset
+ sizeof(u32
) + sizeof(struct iwl_cmd_header
) < max_len
) {
606 struct iwl_rx_packet
*pkt
;
607 struct iwl_device_cmd
*cmd
;
610 int index
, cmd_index
, err
, len
;
611 struct iwl_rx_cmd_buffer rxcb
= {
613 ._rx_page_order
= trans_pcie
->rx_page_order
,
615 ._page_stolen
= false,
619 pkt
= rxb_addr(&rxcb
);
621 if (pkt
->len_n_flags
== cpu_to_le32(FH_RSCSR_FRAME_INVALID
))
624 IWL_DEBUG_RX(trans
, "cmd at offset %d: %s (0x%.2x)\n",
625 rxcb
._offset
, get_cmd_string(trans_pcie
, pkt
->hdr
.cmd
),
628 len
= le32_to_cpu(pkt
->len_n_flags
) & FH_RSCSR_FRAME_SIZE_MSK
;
629 len
+= sizeof(u32
); /* account for status word */
630 trace_iwlwifi_dev_rx(trans
->dev
, trans
, pkt
, len
);
631 trace_iwlwifi_dev_rx_data(trans
->dev
, trans
, pkt
, len
);
633 /* Reclaim a command buffer only if this packet is a response
634 * to a (driver-originated) command.
635 * If the packet (e.g. Rx frame) originated from uCode,
636 * there is no command buffer to reclaim.
637 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
638 * but apparently a few don't get set; catch them here. */
639 reclaim
= !(pkt
->hdr
.sequence
& SEQ_RX_FRAME
);
643 for (i
= 0; i
< trans_pcie
->n_no_reclaim_cmds
; i
++) {
644 if (trans_pcie
->no_reclaim_cmds
[i
] ==
652 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
653 index
= SEQ_TO_INDEX(sequence
);
654 cmd_index
= get_cmd_index(&txq
->q
, index
);
657 cmd
= txq
->entries
[cmd_index
].cmd
;
661 err
= iwl_op_mode_rx(trans
->op_mode
, &rxcb
, cmd
);
664 kfree(txq
->entries
[cmd_index
].free_buf
);
665 txq
->entries
[cmd_index
].free_buf
= NULL
;
669 * After here, we should always check rxcb._page_stolen,
670 * if it is true then one of the handlers took the page.
674 /* Invoke any callbacks, transfer the buffer to caller,
675 * and fire off the (possibly) blocking
676 * iwl_trans_send_cmd()
677 * as we reclaim the driver command queue */
678 if (!rxcb
._page_stolen
)
679 iwl_pcie_hcmd_complete(trans
, &rxcb
, err
);
681 IWL_WARN(trans
, "Claim null rxb?\n");
684 page_stolen
|= rxcb
._page_stolen
;
685 offset
+= ALIGN(len
, FH_RSCSR_FRAME_ALIGN
);
688 /* page was stolen from us -- free our reference */
690 __free_pages(rxb
->page
, trans_pcie
->rx_page_order
);
694 /* Reuse the page if possible. For notification packets and
695 * SKBs that fail to Rx correctly, add them back into the
696 * rx_free list for reuse later. */
697 spin_lock_irqsave(&rxq
->lock
, flags
);
698 if (rxb
->page
!= NULL
) {
700 dma_map_page(trans
->dev
, rxb
->page
, 0,
701 PAGE_SIZE
<< trans_pcie
->rx_page_order
,
703 if (dma_mapping_error(trans
->dev
, rxb
->page_dma
)) {
705 * free the page(s) as well to not break
706 * the invariant that the items on the used
707 * list have no page(s)
709 __free_pages(rxb
->page
, trans_pcie
->rx_page_order
);
711 list_add_tail(&rxb
->list
, &rxq
->rx_used
);
713 list_add_tail(&rxb
->list
, &rxq
->rx_free
);
717 list_add_tail(&rxb
->list
, &rxq
->rx_used
);
718 spin_unlock_irqrestore(&rxq
->lock
, flags
);
722 * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
724 static void iwl_pcie_rx_handle(struct iwl_trans
*trans
)
726 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
727 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
;
733 /* uCode's read index (stored in shared DRAM) indicates the last Rx
734 * buffer that the driver may process (last buffer filled by ucode). */
735 r
= le16_to_cpu(ACCESS_ONCE(rxq
->rb_stts
->closed_rb_num
)) & 0x0FFF;
738 /* Rx interrupt, but nothing sent from uCode */
740 IWL_DEBUG_RX(trans
, "HW = SW = %d\n", r
);
742 /* calculate total frames need to be restock after handling RX */
743 total_empty
= r
- rxq
->write_actual
;
745 total_empty
+= RX_QUEUE_SIZE
;
747 if (total_empty
> (RX_QUEUE_SIZE
/ 2))
751 struct iwl_rx_mem_buffer
*rxb
;
754 rxq
->queue
[i
] = NULL
;
756 IWL_DEBUG_RX(trans
, "rxbuf: HW = %d, SW = %d (%p)\n",
758 iwl_pcie_rx_handle_rb(trans
, rxb
);
760 i
= (i
+ 1) & RX_QUEUE_MASK
;
761 /* If there are a lot of unused frames,
762 * restock the Rx queue so ucode wont assert. */
767 iwl_pcie_rx_replenish_now(trans
);
773 /* Backtrack one entry */
776 iwl_pcie_rx_replenish_now(trans
);
778 iwl_pcie_rxq_restock(trans
);
782 * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
784 static void iwl_pcie_irq_handle_error(struct iwl_trans
*trans
)
786 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
788 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
789 if (trans
->cfg
->internal_wimax_coex
&&
790 (!(iwl_read_prph(trans
, APMG_CLK_CTRL_REG
) &
791 APMS_CLK_VAL_MRB_FUNC_MODE
) ||
792 (iwl_read_prph(trans
, APMG_PS_CTRL_REG
) &
793 APMG_PS_CTRL_VAL_RESET_REQ
))) {
794 clear_bit(STATUS_HCMD_ACTIVE
, &trans_pcie
->status
);
795 iwl_op_mode_wimax_active(trans
->op_mode
);
796 wake_up(&trans_pcie
->wait_command_queue
);
800 iwl_pcie_dump_csr(trans
);
801 iwl_dump_fh(trans
, NULL
);
803 /* set the ERROR bit before we wake up the caller */
804 set_bit(STATUS_FW_ERROR
, &trans_pcie
->status
);
805 clear_bit(STATUS_HCMD_ACTIVE
, &trans_pcie
->status
);
806 wake_up(&trans_pcie
->wait_command_queue
);
809 iwl_nic_error(trans
);
813 irqreturn_t
iwl_pcie_irq_handler(int irq
, void *dev_id
)
815 struct iwl_trans
*trans
= dev_id
;
816 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
817 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
823 lock_map_acquire(&trans
->sync_cmd_lockdep_map
);
825 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
827 /* Ack/clear/reset pending uCode interrupts.
828 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
830 /* There is a hardware bug in the interrupt mask function that some
831 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
832 * they are disabled in the CSR_INT_MASK register. Furthermore the
833 * ICT interrupt handling mechanism has another bug that might cause
834 * these unmasked interrupts fail to be detected. We workaround the
835 * hardware bugs here by ACKing all the possible interrupts so that
836 * interrupt coalescing can still be achieved.
838 iwl_write32(trans
, CSR_INT
,
839 trans_pcie
->inta
| ~trans_pcie
->inta_mask
);
841 inta
= trans_pcie
->inta
;
843 if (iwl_have_debug_level(IWL_DL_ISR
))
844 IWL_DEBUG_ISR(trans
, "inta 0x%08x, enabled 0x%08x\n",
845 inta
, iwl_read32(trans
, CSR_INT_MASK
));
847 /* saved interrupt in inta variable now we can reset trans_pcie->inta */
848 trans_pcie
->inta
= 0;
850 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
852 /* Now service all interrupt bits discovered above. */
853 if (inta
& CSR_INT_BIT_HW_ERR
) {
854 IWL_ERR(trans
, "Hardware error detected. Restarting.\n");
856 /* Tell the device to stop sending interrupts */
857 iwl_disable_interrupts(trans
);
860 iwl_pcie_irq_handle_error(trans
);
862 handled
|= CSR_INT_BIT_HW_ERR
;
867 if (iwl_have_debug_level(IWL_DL_ISR
)) {
868 /* NIC fires this, but we don't use it, redundant with WAKEUP */
869 if (inta
& CSR_INT_BIT_SCD
) {
871 "Scheduler finished to transmit the frame/frames.\n");
875 /* Alive notification via Rx interrupt will do the real work */
876 if (inta
& CSR_INT_BIT_ALIVE
) {
877 IWL_DEBUG_ISR(trans
, "Alive interrupt\n");
882 /* Safely ignore these bits for debug checks below */
883 inta
&= ~(CSR_INT_BIT_SCD
| CSR_INT_BIT_ALIVE
);
885 /* HW RF KILL switch toggled */
886 if (inta
& CSR_INT_BIT_RF_KILL
) {
889 hw_rfkill
= iwl_is_rfkill_set(trans
);
890 IWL_WARN(trans
, "RF_KILL bit toggled to %s.\n",
891 hw_rfkill
? "disable radio" : "enable radio");
895 iwl_op_mode_hw_rf_kill(trans
->op_mode
, hw_rfkill
);
897 set_bit(STATUS_RFKILL
, &trans_pcie
->status
);
898 if (test_and_clear_bit(STATUS_HCMD_ACTIVE
,
899 &trans_pcie
->status
))
900 IWL_DEBUG_RF_KILL(trans
,
901 "Rfkill while SYNC HCMD in flight\n");
902 wake_up(&trans_pcie
->wait_command_queue
);
904 clear_bit(STATUS_RFKILL
, &trans_pcie
->status
);
907 handled
|= CSR_INT_BIT_RF_KILL
;
910 /* Chip got too hot and stopped itself */
911 if (inta
& CSR_INT_BIT_CT_KILL
) {
912 IWL_ERR(trans
, "Microcode CT kill error detected.\n");
914 handled
|= CSR_INT_BIT_CT_KILL
;
917 /* Error detected by uCode */
918 if (inta
& CSR_INT_BIT_SW_ERR
) {
919 IWL_ERR(trans
, "Microcode SW error detected. "
920 " Restarting 0x%X.\n", inta
);
922 iwl_pcie_irq_handle_error(trans
);
923 handled
|= CSR_INT_BIT_SW_ERR
;
926 /* uCode wakes up after power-down sleep */
927 if (inta
& CSR_INT_BIT_WAKEUP
) {
928 IWL_DEBUG_ISR(trans
, "Wakeup interrupt\n");
929 iwl_pcie_rxq_inc_wr_ptr(trans
, &trans_pcie
->rxq
);
930 for (i
= 0; i
< trans
->cfg
->base_params
->num_of_queues
; i
++)
931 iwl_pcie_txq_inc_wr_ptr(trans
, &trans_pcie
->txq
[i
]);
935 handled
|= CSR_INT_BIT_WAKEUP
;
938 /* All uCode command responses, including Tx command responses,
939 * Rx "responses" (frame-received notification), and other
940 * notifications from uCode come through here*/
941 if (inta
& (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
|
942 CSR_INT_BIT_RX_PERIODIC
)) {
943 IWL_DEBUG_ISR(trans
, "Rx interrupt\n");
944 if (inta
& (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
)) {
945 handled
|= (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
);
946 iwl_write32(trans
, CSR_FH_INT_STATUS
,
949 if (inta
& CSR_INT_BIT_RX_PERIODIC
) {
950 handled
|= CSR_INT_BIT_RX_PERIODIC
;
952 CSR_INT
, CSR_INT_BIT_RX_PERIODIC
);
954 /* Sending RX interrupt require many steps to be done in the
956 * 1- write interrupt to current index in ICT table.
958 * 3- update RX shared data to indicate last write index.
960 * This could lead to RX race, driver could receive RX interrupt
961 * but the shared data changes does not reflect this;
962 * periodic interrupt will detect any dangling Rx activity.
965 /* Disable periodic interrupt; we use it as just a one-shot. */
966 iwl_write8(trans
, CSR_INT_PERIODIC_REG
,
967 CSR_INT_PERIODIC_DIS
);
969 iwl_pcie_rx_handle(trans
);
972 * Enable periodic interrupt in 8 msec only if we received
973 * real RX interrupt (instead of just periodic int), to catch
974 * any dangling Rx interrupt. If it was just the periodic
975 * interrupt, there was no dangling Rx activity, and no need
976 * to extend the periodic interrupt; one-shot is enough.
978 if (inta
& (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
))
979 iwl_write8(trans
, CSR_INT_PERIODIC_REG
,
980 CSR_INT_PERIODIC_ENA
);
985 /* This "Tx" DMA channel is used only for loading uCode */
986 if (inta
& CSR_INT_BIT_FH_TX
) {
987 iwl_write32(trans
, CSR_FH_INT_STATUS
, CSR_FH_INT_TX_MASK
);
988 IWL_DEBUG_ISR(trans
, "uCode load interrupt\n");
990 handled
|= CSR_INT_BIT_FH_TX
;
991 /* Wake up uCode load routine, now that load is complete */
992 trans_pcie
->ucode_write_complete
= true;
993 wake_up(&trans_pcie
->ucode_write_waitq
);
996 if (inta
& ~handled
) {
997 IWL_ERR(trans
, "Unhandled INTA bits 0x%08x\n", inta
& ~handled
);
998 isr_stats
->unhandled
++;
1001 if (inta
& ~(trans_pcie
->inta_mask
)) {
1002 IWL_WARN(trans
, "Disabled INTA bits 0x%08x were pending\n",
1003 inta
& ~trans_pcie
->inta_mask
);
1006 /* Re-enable all interrupts */
1007 /* only Re-enable if disabled by irq */
1008 if (test_bit(STATUS_INT_ENABLED
, &trans_pcie
->status
))
1009 iwl_enable_interrupts(trans
);
1010 /* Re-enable RF_KILL if it occurred */
1011 else if (handled
& CSR_INT_BIT_RF_KILL
)
1012 iwl_enable_rfkill_int(trans
);
1015 lock_map_release(&trans
->sync_cmd_lockdep_map
);
1019 /******************************************************************************
1023 ******************************************************************************/
1025 /* a device (PCI-E) page is 4096 bytes long */
1026 #define ICT_SHIFT 12
1027 #define ICT_SIZE (1 << ICT_SHIFT)
1028 #define ICT_COUNT (ICT_SIZE / sizeof(u32))
1030 /* Free dram table */
1031 void iwl_pcie_free_ict(struct iwl_trans
*trans
)
1033 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1035 if (trans_pcie
->ict_tbl
) {
1036 dma_free_coherent(trans
->dev
, ICT_SIZE
,
1037 trans_pcie
->ict_tbl
,
1038 trans_pcie
->ict_tbl_dma
);
1039 trans_pcie
->ict_tbl
= NULL
;
1040 trans_pcie
->ict_tbl_dma
= 0;
1045 * allocate dram shared table, it is an aligned memory
1046 * block of ICT_SIZE.
1047 * also reset all data related to ICT table interrupt.
1049 int iwl_pcie_alloc_ict(struct iwl_trans
*trans
)
1051 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1053 trans_pcie
->ict_tbl
=
1054 dma_alloc_coherent(trans
->dev
, ICT_SIZE
,
1055 &trans_pcie
->ict_tbl_dma
,
1057 if (!trans_pcie
->ict_tbl
)
1060 /* just an API sanity check ... it is guaranteed to be aligned */
1061 if (WARN_ON(trans_pcie
->ict_tbl_dma
& (ICT_SIZE
- 1))) {
1062 iwl_pcie_free_ict(trans
);
1066 IWL_DEBUG_ISR(trans
, "ict dma addr %Lx\n",
1067 (unsigned long long)trans_pcie
->ict_tbl_dma
);
1069 IWL_DEBUG_ISR(trans
, "ict vir addr %p\n", trans_pcie
->ict_tbl
);
1071 /* reset table and index to all 0 */
1072 memset(trans_pcie
->ict_tbl
, 0, ICT_SIZE
);
1073 trans_pcie
->ict_index
= 0;
1075 /* add periodic RX interrupt */
1076 trans_pcie
->inta_mask
|= CSR_INT_BIT_RX_PERIODIC
;
1080 /* Device is going up inform it about using ICT interrupt table,
1081 * also we need to tell the driver to start using ICT interrupt.
1083 void iwl_pcie_reset_ict(struct iwl_trans
*trans
)
1085 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1087 unsigned long flags
;
1089 if (!trans_pcie
->ict_tbl
)
1092 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
1093 iwl_disable_interrupts(trans
);
1095 memset(trans_pcie
->ict_tbl
, 0, ICT_SIZE
);
1097 val
= trans_pcie
->ict_tbl_dma
>> ICT_SHIFT
;
1099 val
|= CSR_DRAM_INT_TBL_ENABLE
;
1100 val
|= CSR_DRAM_INIT_TBL_WRAP_CHECK
;
1102 IWL_DEBUG_ISR(trans
, "CSR_DRAM_INT_TBL_REG =0x%x\n", val
);
1104 iwl_write32(trans
, CSR_DRAM_INT_TBL_REG
, val
);
1105 trans_pcie
->use_ict
= true;
1106 trans_pcie
->ict_index
= 0;
1107 iwl_write32(trans
, CSR_INT
, trans_pcie
->inta_mask
);
1108 iwl_enable_interrupts(trans
);
1109 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
1112 /* Device is going down disable ict interrupt usage */
1113 void iwl_pcie_disable_ict(struct iwl_trans
*trans
)
1115 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1116 unsigned long flags
;
1118 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
1119 trans_pcie
->use_ict
= false;
1120 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
1123 /* legacy (non-ICT) ISR. Assumes that trans_pcie->irq_lock is held */
1124 static irqreturn_t
iwl_pcie_isr(int irq
, void *data
)
1126 struct iwl_trans
*trans
= data
;
1127 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1128 u32 inta
, inta_mask
;
1129 irqreturn_t ret
= IRQ_NONE
;
1131 lockdep_assert_held(&trans_pcie
->irq_lock
);
1133 trace_iwlwifi_dev_irq(trans
->dev
);
1135 /* Disable (but don't clear!) interrupts here to avoid
1136 * back-to-back ISRs and sporadic interrupts from our NIC.
1137 * If we have something to service, the irq thread will re-enable ints.
1138 * If we *don't* have something, we'll re-enable before leaving here. */
1139 inta_mask
= iwl_read32(trans
, CSR_INT_MASK
);
1140 iwl_write32(trans
, CSR_INT_MASK
, 0x00000000);
1142 /* Discover which interrupts are active/pending */
1143 inta
= iwl_read32(trans
, CSR_INT
);
1145 if (inta
& (~inta_mask
)) {
1146 IWL_DEBUG_ISR(trans
,
1147 "We got a masked interrupt (0x%08x)...Ack and ignore\n",
1148 inta
& (~inta_mask
));
1149 iwl_write32(trans
, CSR_INT
, inta
& (~inta_mask
));
1153 /* Ignore interrupt if there's nothing in NIC to service.
1154 * This may be due to IRQ shared with another device,
1155 * or due to sporadic interrupts thrown from our NIC. */
1157 IWL_DEBUG_ISR(trans
, "Ignore interrupt, inta == 0\n");
1161 if ((inta
== 0xFFFFFFFF) || ((inta
& 0xFFFFFFF0) == 0xa5a5a5a0)) {
1162 /* Hardware disappeared. It might have already raised
1164 IWL_WARN(trans
, "HARDWARE GONE?? INTA == 0x%08x\n", inta
);
1168 if (iwl_have_debug_level(IWL_DL_ISR
))
1169 IWL_DEBUG_ISR(trans
,
1170 "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1172 iwl_read32(trans
, CSR_FH_INT_STATUS
));
1174 trans_pcie
->inta
|= inta
;
1175 /* the thread will service interrupts and re-enable them */
1177 return IRQ_WAKE_THREAD
;
1182 /* re-enable interrupts here since we don't have anything to service. */
1183 /* only Re-enable if disabled by irq and no schedules tasklet. */
1184 if (test_bit(STATUS_INT_ENABLED
, &trans_pcie
->status
) &&
1186 iwl_enable_interrupts(trans
);
1191 /* interrupt handler using ict table, with this interrupt driver will
1192 * stop using INTA register to get device's interrupt, reading this register
1193 * is expensive, device will write interrupts in ICT dram table, increment
1194 * index then will fire interrupt to driver, driver will OR all ICT table
1195 * entries from current index up to table entry with 0 value. the result is
1196 * the interrupt we need to service, driver will set the entries back to 0 and
1199 irqreturn_t
iwl_pcie_isr_ict(int irq
, void *data
)
1201 struct iwl_trans
*trans
= data
;
1202 struct iwl_trans_pcie
*trans_pcie
;
1206 unsigned long flags
;
1207 irqreturn_t ret
= IRQ_NONE
;
1212 trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1214 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
1216 /* dram interrupt table not set yet,
1217 * use legacy interrupt.
1219 if (unlikely(!trans_pcie
->use_ict
)) {
1220 ret
= iwl_pcie_isr(irq
, data
);
1221 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
1225 trace_iwlwifi_dev_irq(trans
->dev
);
1227 /* Disable (but don't clear!) interrupts here to avoid
1228 * back-to-back ISRs and sporadic interrupts from our NIC.
1229 * If we have something to service, the tasklet will re-enable ints.
1230 * If we *don't* have something, we'll re-enable before leaving here.
1232 iwl_write32(trans
, CSR_INT_MASK
, 0x00000000);
1234 /* Ignore interrupt if there's nothing in NIC to service.
1235 * This may be due to IRQ shared with another device,
1236 * or due to sporadic interrupts thrown from our NIC. */
1237 read
= le32_to_cpu(trans_pcie
->ict_tbl
[trans_pcie
->ict_index
]);
1238 trace_iwlwifi_dev_ict_read(trans
->dev
, trans_pcie
->ict_index
, read
);
1240 IWL_DEBUG_ISR(trans
, "Ignore interrupt, inta == 0\n");
1245 * Collect all entries up to the first 0, starting from ict_index;
1246 * note we already read at ict_index.
1250 IWL_DEBUG_ISR(trans
, "ICT index %d value 0x%08X\n",
1251 trans_pcie
->ict_index
, read
);
1252 trans_pcie
->ict_tbl
[trans_pcie
->ict_index
] = 0;
1253 trans_pcie
->ict_index
=
1254 iwl_queue_inc_wrap(trans_pcie
->ict_index
, ICT_COUNT
);
1256 read
= le32_to_cpu(trans_pcie
->ict_tbl
[trans_pcie
->ict_index
]);
1257 trace_iwlwifi_dev_ict_read(trans
->dev
, trans_pcie
->ict_index
,
1261 /* We should not get this value, just ignore it. */
1262 if (val
== 0xffffffff)
1266 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1267 * (bit 15 before shifting it to 31) to clear when using interrupt
1268 * coalescing. fortunately, bits 18 and 19 stay set when this happens
1269 * so we use them to decide on the real state of the Rx bit.
1270 * In order words, bit 15 is set if bit 18 or bit 19 are set.
1275 inta
= (0xff & val
) | ((0xff00 & val
) << 16);
1276 IWL_DEBUG_ISR(trans
, "ISR inta 0x%08x, enabled(sw) 0x%08x ict 0x%08x\n",
1277 inta
, trans_pcie
->inta_mask
, val
);
1278 if (iwl_have_debug_level(IWL_DL_ISR
))
1279 IWL_DEBUG_ISR(trans
, "enabled(hw) 0x%08x\n",
1280 iwl_read32(trans
, CSR_INT_MASK
));
1282 inta
&= trans_pcie
->inta_mask
;
1283 trans_pcie
->inta
|= inta
;
1285 /* iwl_pcie_tasklet() will service interrupts and re-enable them */
1287 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
1288 return IRQ_WAKE_THREAD
;
1294 /* re-enable interrupts here since we don't have anything to service.
1295 * only Re-enable if disabled by irq.
1297 if (test_bit(STATUS_INT_ENABLED
, &trans_pcie
->status
) &&
1299 iwl_enable_interrupts(trans
);
1301 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);