1 /******************************************************************************
3 * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #include <linux/sched.h>
30 #include <linux/wait.h>
31 #include <linux/gfp.h>
36 #include "iwl-op-mode.h"
38 /******************************************************************************
42 ******************************************************************************/
45 * Rx theory of operation
47 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
48 * each of which point to Receive Buffers to be filled by the NIC. These get
49 * used not only for Rx frames, but for any command response or notification
50 * from the NIC. The driver and NIC manage the Rx buffers by means
51 * of indexes into the circular buffer.
54 * The host/firmware share two index registers for managing the Rx buffers.
56 * The READ index maps to the first position that the firmware may be writing
57 * to -- the driver can read up to (but not including) this position and get
59 * The READ index is managed by the firmware once the card is enabled.
61 * The WRITE index maps to the last position the driver has read from -- the
62 * position preceding WRITE is the last slot the firmware can place a packet.
64 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
67 * During initialization, the host sets up the READ queue position to the first
68 * INDEX position, and WRITE to the last (READ - 1 wrapped)
70 * When the firmware places a packet in a buffer, it will advance the READ index
71 * and fire the RX interrupt. The driver can then query the READ index and
72 * process as many packets as possible, moving the WRITE index forward as it
73 * resets the Rx queue buffers with new memory.
75 * The management in the driver is as follows:
76 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
77 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
78 * to replenish the iwl->rxq->rx_free.
79 * + In iwl_pcie_rx_replenish (scheduled) if 'processed' != 'read' then the
80 * iwl->rxq is replenished and the READ INDEX is updated (updating the
81 * 'processed' and 'read' driver indexes as well)
82 * + A received packet is processed and handed to the kernel network stack,
83 * detached from the iwl->rxq. The driver 'processed' index is updated.
84 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
85 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
86 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
87 * were enough free buffers and RX_STALLED is set it is cleared.
92 * iwl_rxq_alloc() Allocates rx_free
93 * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls
94 * iwl_pcie_rxq_restock
95 * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx
96 * queue, updates firmware pointers, and updates
97 * the WRITE index. If insufficient rx_free buffers
98 * are available, schedules iwl_pcie_rx_replenish
100 * -- enable interrupts --
101 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
102 * READ INDEX, detaching the SKB from the pool.
103 * Moves the packet buffer from queue to rx_used.
104 * Calls iwl_pcie_rxq_restock to refill any empty
111 * iwl_rxq_space - Return number of free slots available in queue.
113 static int iwl_rxq_space(const struct iwl_rxq
*q
)
115 int s
= q
->read
- q
->write
;
118 /* keep some buffer to not confuse full and empty queue */
126 * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
128 static inline __le32
iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr
)
130 return cpu_to_le32((u32
)(dma_addr
>> 8));
133 int iwl_pcie_rx_stop(struct iwl_trans
*trans
)
137 iwl_write_direct32(trans
, FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
138 return iwl_poll_direct_bit(trans
, FH_MEM_RSSR_RX_STATUS_REG
,
139 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE
, 1000);
143 * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
144 * TODO - could be made static
146 void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans
*trans
, struct iwl_rxq
*q
)
151 spin_lock_irqsave(&q
->lock
, flags
);
153 if (q
->need_update
== 0)
156 if (trans
->cfg
->base_params
->shadow_reg_enable
) {
157 /* shadow register enabled */
158 /* Device expects a multiple of 8 */
159 q
->write_actual
= (q
->write
& ~0x7);
160 iwl_write32(trans
, FH_RSCSR_CHNL0_WPTR
, q
->write_actual
);
162 struct iwl_trans_pcie
*trans_pcie
=
163 IWL_TRANS_GET_PCIE_TRANS(trans
);
165 /* If power-saving is in use, make sure device is awake */
166 if (test_bit(STATUS_TPOWER_PMI
, &trans_pcie
->status
)) {
167 reg
= iwl_read32(trans
, CSR_UCODE_DRV_GP1
);
169 if (reg
& CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP
) {
170 IWL_DEBUG_INFO(trans
,
171 "Rx queue requesting wakeup,"
172 " GP1 = 0x%x\n", reg
);
173 iwl_set_bit(trans
, CSR_GP_CNTRL
,
174 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
178 q
->write_actual
= (q
->write
& ~0x7);
179 iwl_write_direct32(trans
, FH_RSCSR_CHNL0_WPTR
,
182 /* Else device is assumed to be awake */
184 /* Device expects a multiple of 8 */
185 q
->write_actual
= (q
->write
& ~0x7);
186 iwl_write_direct32(trans
, FH_RSCSR_CHNL0_WPTR
,
193 spin_unlock_irqrestore(&q
->lock
, flags
);
197 * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
199 * If there are slots in the RX queue that need to be restocked,
200 * and we have free pre-allocated buffers, fill the ranks as much
201 * as we can, pulling from rx_free.
203 * This moves the 'write' index forward to catch up with 'processed', and
204 * also updates the memory address in the firmware to reference the new
207 static void iwl_pcie_rxq_restock(struct iwl_trans
*trans
)
209 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
210 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
;
211 struct iwl_rx_mem_buffer
*rxb
;
215 * If the device isn't enabled - not need to try to add buffers...
216 * This can happen when we stop the device and still have an interrupt
217 * pending. We stop the APM before we sync the interrupts / tasklets
218 * because we have to (see comment there). On the other hand, since
219 * the APM is stopped, we cannot access the HW (in particular not prph).
220 * So don't try to restock if the APM has been already stopped.
222 if (!test_bit(STATUS_DEVICE_ENABLED
, &trans_pcie
->status
))
225 spin_lock_irqsave(&rxq
->lock
, flags
);
226 while ((iwl_rxq_space(rxq
) > 0) && (rxq
->free_count
)) {
227 /* The overwritten rxb must be a used one */
228 rxb
= rxq
->queue
[rxq
->write
];
229 BUG_ON(rxb
&& rxb
->page
);
231 /* Get next free Rx buffer, remove from free list */
232 rxb
= list_first_entry(&rxq
->rx_free
, struct iwl_rx_mem_buffer
,
234 list_del(&rxb
->list
);
236 /* Point to Rx buffer via next RBD in circular buffer */
237 rxq
->bd
[rxq
->write
] = iwl_pcie_dma_addr2rbd_ptr(rxb
->page_dma
);
238 rxq
->queue
[rxq
->write
] = rxb
;
239 rxq
->write
= (rxq
->write
+ 1) & RX_QUEUE_MASK
;
242 spin_unlock_irqrestore(&rxq
->lock
, flags
);
243 /* If the pre-allocated buffer pool is dropping low, schedule to
245 if (rxq
->free_count
<= RX_LOW_WATERMARK
)
246 schedule_work(&trans_pcie
->rx_replenish
);
248 /* If we've added more space for the firmware to place data, tell it.
249 * Increment device's write pointer in multiples of 8. */
250 if (rxq
->write_actual
!= (rxq
->write
& ~0x7)) {
251 spin_lock_irqsave(&rxq
->lock
, flags
);
252 rxq
->need_update
= 1;
253 spin_unlock_irqrestore(&rxq
->lock
, flags
);
254 iwl_pcie_rxq_inc_wr_ptr(trans
, rxq
);
259 * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
261 * A used RBD is an Rx buffer that has been given to the stack. To use it again
262 * a page must be allocated and the RBD must point to the page. This function
263 * doesn't change the HW pointer but handles the list of pages that is used by
264 * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
267 static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans
*trans
, gfp_t priority
)
269 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
270 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
;
271 struct iwl_rx_mem_buffer
*rxb
;
274 gfp_t gfp_mask
= priority
;
277 spin_lock_irqsave(&rxq
->lock
, flags
);
278 if (list_empty(&rxq
->rx_used
)) {
279 spin_unlock_irqrestore(&rxq
->lock
, flags
);
282 spin_unlock_irqrestore(&rxq
->lock
, flags
);
284 if (rxq
->free_count
> RX_LOW_WATERMARK
)
285 gfp_mask
|= __GFP_NOWARN
;
287 if (trans_pcie
->rx_page_order
> 0)
288 gfp_mask
|= __GFP_COMP
;
290 /* Alloc a new receive buffer */
291 page
= alloc_pages(gfp_mask
, trans_pcie
->rx_page_order
);
294 IWL_DEBUG_INFO(trans
, "alloc_pages failed, "
296 trans_pcie
->rx_page_order
);
298 if ((rxq
->free_count
<= RX_LOW_WATERMARK
) &&
300 IWL_CRIT(trans
, "Failed to alloc_pages with %s."
301 "Only %u free buffers remaining.\n",
302 priority
== GFP_ATOMIC
?
303 "GFP_ATOMIC" : "GFP_KERNEL",
305 /* We don't reschedule replenish work here -- we will
306 * call the restock method and if it still needs
307 * more buffers it will schedule replenish */
311 spin_lock_irqsave(&rxq
->lock
, flags
);
313 if (list_empty(&rxq
->rx_used
)) {
314 spin_unlock_irqrestore(&rxq
->lock
, flags
);
315 __free_pages(page
, trans_pcie
->rx_page_order
);
318 rxb
= list_first_entry(&rxq
->rx_used
, struct iwl_rx_mem_buffer
,
320 list_del(&rxb
->list
);
321 spin_unlock_irqrestore(&rxq
->lock
, flags
);
325 /* Get physical address of the RB */
327 dma_map_page(trans
->dev
, page
, 0,
328 PAGE_SIZE
<< trans_pcie
->rx_page_order
,
330 /* dma address must be no more than 36 bits */
331 BUG_ON(rxb
->page_dma
& ~DMA_BIT_MASK(36));
332 /* and also 256 byte aligned! */
333 BUG_ON(rxb
->page_dma
& DMA_BIT_MASK(8));
335 spin_lock_irqsave(&rxq
->lock
, flags
);
337 list_add_tail(&rxb
->list
, &rxq
->rx_free
);
340 spin_unlock_irqrestore(&rxq
->lock
, flags
);
344 static void iwl_pcie_rxq_free_rbs(struct iwl_trans
*trans
)
346 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
347 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
;
350 /* Fill the rx_used queue with _all_ of the Rx buffers */
351 for (i
= 0; i
< RX_FREE_BUFFERS
+ RX_QUEUE_SIZE
; i
++) {
352 /* In the reset function, these buffers may have been allocated
353 * to an SKB, so we need to unmap and free potential storage */
354 if (rxq
->pool
[i
].page
!= NULL
) {
355 dma_unmap_page(trans
->dev
, rxq
->pool
[i
].page_dma
,
356 PAGE_SIZE
<< trans_pcie
->rx_page_order
,
358 __free_pages(rxq
->pool
[i
].page
,
359 trans_pcie
->rx_page_order
);
360 rxq
->pool
[i
].page
= NULL
;
362 list_add_tail(&rxq
->pool
[i
].list
, &rxq
->rx_used
);
367 * iwl_pcie_rx_replenish - Move all used buffers from rx_used to rx_free
369 * When moving to rx_free an page is allocated for the slot.
371 * Also restock the Rx queue via iwl_pcie_rxq_restock.
372 * This is called as a scheduled work item (except for during initialization)
374 static void iwl_pcie_rx_replenish(struct iwl_trans
*trans
)
376 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
379 iwl_pcie_rxq_alloc_rbs(trans
, GFP_KERNEL
);
381 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
382 iwl_pcie_rxq_restock(trans
);
383 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
386 static void iwl_pcie_rx_replenish_now(struct iwl_trans
*trans
)
388 iwl_pcie_rxq_alloc_rbs(trans
, GFP_ATOMIC
);
390 iwl_pcie_rxq_restock(trans
);
393 static void iwl_pcie_rx_replenish_work(struct work_struct
*data
)
395 struct iwl_trans_pcie
*trans_pcie
=
396 container_of(data
, struct iwl_trans_pcie
, rx_replenish
);
398 iwl_pcie_rx_replenish(trans_pcie
->trans
);
401 static int iwl_pcie_rx_alloc(struct iwl_trans
*trans
)
403 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
404 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
;
405 struct device
*dev
= trans
->dev
;
407 memset(&trans_pcie
->rxq
, 0, sizeof(trans_pcie
->rxq
));
409 spin_lock_init(&rxq
->lock
);
411 if (WARN_ON(rxq
->bd
|| rxq
->rb_stts
))
414 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
415 rxq
->bd
= dma_zalloc_coherent(dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
416 &rxq
->bd_dma
, GFP_KERNEL
);
420 /*Allocate the driver's pointer to receive buffer status */
421 rxq
->rb_stts
= dma_zalloc_coherent(dev
, sizeof(*rxq
->rb_stts
),
422 &rxq
->rb_stts_dma
, GFP_KERNEL
);
429 dma_free_coherent(dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
430 rxq
->bd
, rxq
->bd_dma
);
431 memset(&rxq
->bd_dma
, 0, sizeof(rxq
->bd_dma
));
437 static void iwl_pcie_rx_hw_init(struct iwl_trans
*trans
, struct iwl_rxq
*rxq
)
439 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
441 const u32 rfdnlog
= RX_QUEUE_SIZE_LOG
; /* 256 RBDs */
443 /* FIXME: RX_RB_TIMEOUT for all devices? */
444 u32 rb_timeout
= RX_RB_TIMEOUT
;
446 if (trans_pcie
->rx_buf_size_8k
)
447 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K
;
449 rb_size
= FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K
;
452 iwl_write_direct32(trans
, FH_MEM_RCSR_CHNL0_CONFIG_REG
, 0);
454 /* Reset driver's Rx queue write index */
455 iwl_write_direct32(trans
, FH_RSCSR_CHNL0_RBDCB_WPTR_REG
, 0);
457 /* Tell device where to find RBD circular buffer in DRAM */
458 iwl_write_direct32(trans
, FH_RSCSR_CHNL0_RBDCB_BASE_REG
,
459 (u32
)(rxq
->bd_dma
>> 8));
461 /* Tell device where in DRAM to update its Rx status */
462 iwl_write_direct32(trans
, FH_RSCSR_CHNL0_STTS_WPTR_REG
,
463 rxq
->rb_stts_dma
>> 4);
466 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
467 * the credit mechanism in 5000 HW RX FIFO
468 * Direct rx interrupts to hosts
469 * Rx buffer size 4 or 8k
473 iwl_write_direct32(trans
, FH_MEM_RCSR_CHNL0_CONFIG_REG
,
474 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL
|
475 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY
|
476 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL
|
478 (rb_timeout
<< FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS
)|
479 (rfdnlog
<< FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS
));
481 /* Set interrupt coalescing timer to default (2048 usecs) */
482 iwl_write8(trans
, CSR_INT_COALESCING
, IWL_HOST_INT_TIMEOUT_DEF
);
485 int iwl_pcie_rx_init(struct iwl_trans
*trans
)
487 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
488 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
;
494 err
= iwl_pcie_rx_alloc(trans
);
499 spin_lock_irqsave(&rxq
->lock
, flags
);
500 INIT_LIST_HEAD(&rxq
->rx_free
);
501 INIT_LIST_HEAD(&rxq
->rx_used
);
503 INIT_WORK(&trans_pcie
->rx_replenish
,
504 iwl_pcie_rx_replenish_work
);
506 iwl_pcie_rxq_free_rbs(trans
);
508 for (i
= 0; i
< RX_QUEUE_SIZE
; i
++)
509 rxq
->queue
[i
] = NULL
;
511 /* Set us so that we have processed and used all buffers, but have
512 * not restocked the Rx queue with fresh buffers */
513 rxq
->read
= rxq
->write
= 0;
514 rxq
->write_actual
= 0;
516 spin_unlock_irqrestore(&rxq
->lock
, flags
);
518 iwl_pcie_rx_replenish(trans
);
520 iwl_pcie_rx_hw_init(trans
, rxq
);
522 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
523 rxq
->need_update
= 1;
524 iwl_pcie_rxq_inc_wr_ptr(trans
, rxq
);
525 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
530 void iwl_pcie_rx_free(struct iwl_trans
*trans
)
532 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
533 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
;
536 /*if rxq->bd is NULL, it means that nothing has been allocated,
539 IWL_DEBUG_INFO(trans
, "Free NULL rx context\n");
543 spin_lock_irqsave(&rxq
->lock
, flags
);
544 iwl_pcie_rxq_free_rbs(trans
);
545 spin_unlock_irqrestore(&rxq
->lock
, flags
);
547 dma_free_coherent(trans
->dev
, sizeof(__le32
) * RX_QUEUE_SIZE
,
548 rxq
->bd
, rxq
->bd_dma
);
549 memset(&rxq
->bd_dma
, 0, sizeof(rxq
->bd_dma
));
553 dma_free_coherent(trans
->dev
,
554 sizeof(struct iwl_rb_status
),
555 rxq
->rb_stts
, rxq
->rb_stts_dma
);
557 IWL_DEBUG_INFO(trans
, "Free rxq->rb_stts which is NULL\n");
558 memset(&rxq
->rb_stts_dma
, 0, sizeof(rxq
->rb_stts_dma
));
562 static void iwl_pcie_rx_handle_rb(struct iwl_trans
*trans
,
563 struct iwl_rx_mem_buffer
*rxb
)
565 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
566 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
;
567 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
569 bool page_stolen
= false;
570 int max_len
= PAGE_SIZE
<< trans_pcie
->rx_page_order
;
576 dma_unmap_page(trans
->dev
, rxb
->page_dma
, max_len
, DMA_FROM_DEVICE
);
578 while (offset
+ sizeof(u32
) + sizeof(struct iwl_cmd_header
) < max_len
) {
579 struct iwl_rx_packet
*pkt
;
580 struct iwl_device_cmd
*cmd
;
583 int index
, cmd_index
, err
, len
;
584 struct iwl_rx_cmd_buffer rxcb
= {
587 ._page_stolen
= false,
591 pkt
= rxb_addr(&rxcb
);
593 if (pkt
->len_n_flags
== cpu_to_le32(FH_RSCSR_FRAME_INVALID
))
596 IWL_DEBUG_RX(trans
, "cmd at offset %d: %s (0x%.2x)\n",
597 rxcb
._offset
, get_cmd_string(trans_pcie
, pkt
->hdr
.cmd
),
600 len
= le32_to_cpu(pkt
->len_n_flags
) & FH_RSCSR_FRAME_SIZE_MSK
;
601 len
+= sizeof(u32
); /* account for status word */
602 trace_iwlwifi_dev_rx(trans
->dev
, trans
, pkt
, len
);
603 trace_iwlwifi_dev_rx_data(trans
->dev
, trans
, pkt
, len
);
605 /* Reclaim a command buffer only if this packet is a response
606 * to a (driver-originated) command.
607 * If the packet (e.g. Rx frame) originated from uCode,
608 * there is no command buffer to reclaim.
609 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
610 * but apparently a few don't get set; catch them here. */
611 reclaim
= !(pkt
->hdr
.sequence
& SEQ_RX_FRAME
);
615 for (i
= 0; i
< trans_pcie
->n_no_reclaim_cmds
; i
++) {
616 if (trans_pcie
->no_reclaim_cmds
[i
] ==
624 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
625 index
= SEQ_TO_INDEX(sequence
);
626 cmd_index
= get_cmd_index(&txq
->q
, index
);
629 struct iwl_pcie_txq_entry
*ent
;
630 ent
= &txq
->entries
[cmd_index
];
632 WARN_ON_ONCE(!cmd
&& ent
->meta
.flags
& CMD_WANT_HCMD
);
637 err
= iwl_op_mode_rx(trans
->op_mode
, &rxcb
, cmd
);
640 /* The original command isn't needed any more */
641 kfree(txq
->entries
[cmd_index
].copy_cmd
);
642 txq
->entries
[cmd_index
].copy_cmd
= NULL
;
643 /* nor is the duplicated part of the command */
644 kfree(txq
->entries
[cmd_index
].free_buf
);
645 txq
->entries
[cmd_index
].free_buf
= NULL
;
649 * After here, we should always check rxcb._page_stolen,
650 * if it is true then one of the handlers took the page.
654 /* Invoke any callbacks, transfer the buffer to caller,
655 * and fire off the (possibly) blocking
656 * iwl_trans_send_cmd()
657 * as we reclaim the driver command queue */
658 if (!rxcb
._page_stolen
)
659 iwl_pcie_hcmd_complete(trans
, &rxcb
, err
);
661 IWL_WARN(trans
, "Claim null rxb?\n");
664 page_stolen
|= rxcb
._page_stolen
;
665 offset
+= ALIGN(len
, FH_RSCSR_FRAME_ALIGN
);
668 /* page was stolen from us -- free our reference */
670 __free_pages(rxb
->page
, trans_pcie
->rx_page_order
);
674 /* Reuse the page if possible. For notification packets and
675 * SKBs that fail to Rx correctly, add them back into the
676 * rx_free list for reuse later. */
677 spin_lock_irqsave(&rxq
->lock
, flags
);
678 if (rxb
->page
!= NULL
) {
680 dma_map_page(trans
->dev
, rxb
->page
, 0,
681 PAGE_SIZE
<< trans_pcie
->rx_page_order
,
683 list_add_tail(&rxb
->list
, &rxq
->rx_free
);
686 list_add_tail(&rxb
->list
, &rxq
->rx_used
);
687 spin_unlock_irqrestore(&rxq
->lock
, flags
);
691 * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
693 static void iwl_pcie_rx_handle(struct iwl_trans
*trans
)
695 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
696 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
;
702 /* uCode's read index (stored in shared DRAM) indicates the last Rx
703 * buffer that the driver may process (last buffer filled by ucode). */
704 r
= le16_to_cpu(rxq
->rb_stts
->closed_rb_num
) & 0x0FFF;
707 /* Rx interrupt, but nothing sent from uCode */
709 IWL_DEBUG_RX(trans
, "HW = SW = %d\n", r
);
711 /* calculate total frames need to be restock after handling RX */
712 total_empty
= r
- rxq
->write_actual
;
714 total_empty
+= RX_QUEUE_SIZE
;
716 if (total_empty
> (RX_QUEUE_SIZE
/ 2))
720 struct iwl_rx_mem_buffer
*rxb
;
723 rxq
->queue
[i
] = NULL
;
725 IWL_DEBUG_RX(trans
, "rxbuf: HW = %d, SW = %d (%p)\n",
727 iwl_pcie_rx_handle_rb(trans
, rxb
);
729 i
= (i
+ 1) & RX_QUEUE_MASK
;
730 /* If there are a lot of unused frames,
731 * restock the Rx queue so ucode wont assert. */
736 iwl_pcie_rx_replenish_now(trans
);
742 /* Backtrack one entry */
745 iwl_pcie_rx_replenish_now(trans
);
747 iwl_pcie_rxq_restock(trans
);
751 * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
753 static void iwl_pcie_irq_handle_error(struct iwl_trans
*trans
)
755 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
757 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
758 if (trans
->cfg
->internal_wimax_coex
&&
759 (!(iwl_read_prph(trans
, APMG_CLK_CTRL_REG
) &
760 APMS_CLK_VAL_MRB_FUNC_MODE
) ||
761 (iwl_read_prph(trans
, APMG_PS_CTRL_REG
) &
762 APMG_PS_CTRL_VAL_RESET_REQ
))) {
763 clear_bit(STATUS_HCMD_ACTIVE
, &trans_pcie
->status
);
764 iwl_op_mode_wimax_active(trans
->op_mode
);
765 wake_up(&trans_pcie
->wait_command_queue
);
769 iwl_pcie_dump_csr(trans
);
770 iwl_pcie_dump_fh(trans
, NULL
);
772 set_bit(STATUS_FW_ERROR
, &trans_pcie
->status
);
773 clear_bit(STATUS_HCMD_ACTIVE
, &trans_pcie
->status
);
774 wake_up(&trans_pcie
->wait_command_queue
);
776 iwl_op_mode_nic_error(trans
->op_mode
);
779 /* tasklet for iwlagn interrupt */
780 void iwl_pcie_tasklet(struct iwl_trans
*trans
)
782 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
783 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
788 #ifdef CONFIG_IWLWIFI_DEBUG
792 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
794 /* Ack/clear/reset pending uCode interrupts.
795 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
797 /* There is a hardware bug in the interrupt mask function that some
798 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
799 * they are disabled in the CSR_INT_MASK register. Furthermore the
800 * ICT interrupt handling mechanism has another bug that might cause
801 * these unmasked interrupts fail to be detected. We workaround the
802 * hardware bugs here by ACKing all the possible interrupts so that
803 * interrupt coalescing can still be achieved.
805 iwl_write32(trans
, CSR_INT
,
806 trans_pcie
->inta
| ~trans_pcie
->inta_mask
);
808 inta
= trans_pcie
->inta
;
810 #ifdef CONFIG_IWLWIFI_DEBUG
811 if (iwl_have_debug_level(IWL_DL_ISR
)) {
813 inta_mask
= iwl_read32(trans
, CSR_INT_MASK
);
814 IWL_DEBUG_ISR(trans
, "inta 0x%08x, enabled 0x%08x\n",
819 /* saved interrupt in inta variable now we can reset trans_pcie->inta */
820 trans_pcie
->inta
= 0;
822 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
824 /* Now service all interrupt bits discovered above. */
825 if (inta
& CSR_INT_BIT_HW_ERR
) {
826 IWL_ERR(trans
, "Hardware error detected. Restarting.\n");
828 /* Tell the device to stop sending interrupts */
829 iwl_disable_interrupts(trans
);
832 iwl_pcie_irq_handle_error(trans
);
834 handled
|= CSR_INT_BIT_HW_ERR
;
839 #ifdef CONFIG_IWLWIFI_DEBUG
840 if (iwl_have_debug_level(IWL_DL_ISR
)) {
841 /* NIC fires this, but we don't use it, redundant with WAKEUP */
842 if (inta
& CSR_INT_BIT_SCD
) {
843 IWL_DEBUG_ISR(trans
, "Scheduler finished to transmit "
844 "the frame/frames.\n");
848 /* Alive notification via Rx interrupt will do the real work */
849 if (inta
& CSR_INT_BIT_ALIVE
) {
850 IWL_DEBUG_ISR(trans
, "Alive interrupt\n");
855 /* Safely ignore these bits for debug checks below */
856 inta
&= ~(CSR_INT_BIT_SCD
| CSR_INT_BIT_ALIVE
);
858 /* HW RF KILL switch toggled */
859 if (inta
& CSR_INT_BIT_RF_KILL
) {
862 hw_rfkill
= iwl_is_rfkill_set(trans
);
863 IWL_WARN(trans
, "RF_KILL bit toggled to %s.\n",
864 hw_rfkill
? "disable radio" : "enable radio");
868 iwl_op_mode_hw_rf_kill(trans
->op_mode
, hw_rfkill
);
870 set_bit(STATUS_RFKILL
, &trans_pcie
->status
);
871 if (test_and_clear_bit(STATUS_HCMD_ACTIVE
,
872 &trans_pcie
->status
))
873 IWL_DEBUG_RF_KILL(trans
,
874 "Rfkill while SYNC HCMD in flight\n");
875 wake_up(&trans_pcie
->wait_command_queue
);
877 clear_bit(STATUS_RFKILL
, &trans_pcie
->status
);
880 handled
|= CSR_INT_BIT_RF_KILL
;
883 /* Chip got too hot and stopped itself */
884 if (inta
& CSR_INT_BIT_CT_KILL
) {
885 IWL_ERR(trans
, "Microcode CT kill error detected.\n");
887 handled
|= CSR_INT_BIT_CT_KILL
;
890 /* Error detected by uCode */
891 if (inta
& CSR_INT_BIT_SW_ERR
) {
892 IWL_ERR(trans
, "Microcode SW error detected. "
893 " Restarting 0x%X.\n", inta
);
895 iwl_pcie_irq_handle_error(trans
);
896 handled
|= CSR_INT_BIT_SW_ERR
;
899 /* uCode wakes up after power-down sleep */
900 if (inta
& CSR_INT_BIT_WAKEUP
) {
901 IWL_DEBUG_ISR(trans
, "Wakeup interrupt\n");
902 iwl_pcie_rxq_inc_wr_ptr(trans
, &trans_pcie
->rxq
);
903 for (i
= 0; i
< trans
->cfg
->base_params
->num_of_queues
; i
++)
904 iwl_pcie_txq_inc_wr_ptr(trans
, &trans_pcie
->txq
[i
]);
908 handled
|= CSR_INT_BIT_WAKEUP
;
911 /* All uCode command responses, including Tx command responses,
912 * Rx "responses" (frame-received notification), and other
913 * notifications from uCode come through here*/
914 if (inta
& (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
|
915 CSR_INT_BIT_RX_PERIODIC
)) {
916 IWL_DEBUG_ISR(trans
, "Rx interrupt\n");
917 if (inta
& (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
)) {
918 handled
|= (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
);
919 iwl_write32(trans
, CSR_FH_INT_STATUS
,
922 if (inta
& CSR_INT_BIT_RX_PERIODIC
) {
923 handled
|= CSR_INT_BIT_RX_PERIODIC
;
925 CSR_INT
, CSR_INT_BIT_RX_PERIODIC
);
927 /* Sending RX interrupt require many steps to be done in the
929 * 1- write interrupt to current index in ICT table.
931 * 3- update RX shared data to indicate last write index.
933 * This could lead to RX race, driver could receive RX interrupt
934 * but the shared data changes does not reflect this;
935 * periodic interrupt will detect any dangling Rx activity.
938 /* Disable periodic interrupt; we use it as just a one-shot. */
939 iwl_write8(trans
, CSR_INT_PERIODIC_REG
,
940 CSR_INT_PERIODIC_DIS
);
942 iwl_pcie_rx_handle(trans
);
945 * Enable periodic interrupt in 8 msec only if we received
946 * real RX interrupt (instead of just periodic int), to catch
947 * any dangling Rx interrupt. If it was just the periodic
948 * interrupt, there was no dangling Rx activity, and no need
949 * to extend the periodic interrupt; one-shot is enough.
951 if (inta
& (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
))
952 iwl_write8(trans
, CSR_INT_PERIODIC_REG
,
953 CSR_INT_PERIODIC_ENA
);
958 /* This "Tx" DMA channel is used only for loading uCode */
959 if (inta
& CSR_INT_BIT_FH_TX
) {
960 iwl_write32(trans
, CSR_FH_INT_STATUS
, CSR_FH_INT_TX_MASK
);
961 IWL_DEBUG_ISR(trans
, "uCode load interrupt\n");
963 handled
|= CSR_INT_BIT_FH_TX
;
964 /* Wake up uCode load routine, now that load is complete */
965 trans_pcie
->ucode_write_complete
= true;
966 wake_up(&trans_pcie
->ucode_write_waitq
);
969 if (inta
& ~handled
) {
970 IWL_ERR(trans
, "Unhandled INTA bits 0x%08x\n", inta
& ~handled
);
971 isr_stats
->unhandled
++;
974 if (inta
& ~(trans_pcie
->inta_mask
)) {
975 IWL_WARN(trans
, "Disabled INTA bits 0x%08x were pending\n",
976 inta
& ~trans_pcie
->inta_mask
);
979 /* Re-enable all interrupts */
980 /* only Re-enable if disabled by irq */
981 if (test_bit(STATUS_INT_ENABLED
, &trans_pcie
->status
))
982 iwl_enable_interrupts(trans
);
983 /* Re-enable RF_KILL if it occurred */
984 else if (handled
& CSR_INT_BIT_RF_KILL
)
985 iwl_enable_rfkill_int(trans
);
988 /******************************************************************************
992 ******************************************************************************/
994 /* a device (PCI-E) page is 4096 bytes long */
996 #define ICT_SIZE (1 << ICT_SHIFT)
997 #define ICT_COUNT (ICT_SIZE / sizeof(u32))
999 /* Free dram table */
1000 void iwl_pcie_free_ict(struct iwl_trans
*trans
)
1002 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1004 if (trans_pcie
->ict_tbl
) {
1005 dma_free_coherent(trans
->dev
, ICT_SIZE
,
1006 trans_pcie
->ict_tbl
,
1007 trans_pcie
->ict_tbl_dma
);
1008 trans_pcie
->ict_tbl
= NULL
;
1009 trans_pcie
->ict_tbl_dma
= 0;
1014 * allocate dram shared table, it is an aligned memory
1015 * block of ICT_SIZE.
1016 * also reset all data related to ICT table interrupt.
1018 int iwl_pcie_alloc_ict(struct iwl_trans
*trans
)
1020 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1022 trans_pcie
->ict_tbl
=
1023 dma_alloc_coherent(trans
->dev
, ICT_SIZE
,
1024 &trans_pcie
->ict_tbl_dma
,
1026 if (!trans_pcie
->ict_tbl
)
1029 /* just an API sanity check ... it is guaranteed to be aligned */
1030 if (WARN_ON(trans_pcie
->ict_tbl_dma
& (ICT_SIZE
- 1))) {
1031 iwl_pcie_free_ict(trans
);
1035 IWL_DEBUG_ISR(trans
, "ict dma addr %Lx\n",
1036 (unsigned long long)trans_pcie
->ict_tbl_dma
);
1038 IWL_DEBUG_ISR(trans
, "ict vir addr %p\n", trans_pcie
->ict_tbl
);
1040 /* reset table and index to all 0 */
1041 memset(trans_pcie
->ict_tbl
, 0, ICT_SIZE
);
1042 trans_pcie
->ict_index
= 0;
1044 /* add periodic RX interrupt */
1045 trans_pcie
->inta_mask
|= CSR_INT_BIT_RX_PERIODIC
;
1049 /* Device is going up inform it about using ICT interrupt table,
1050 * also we need to tell the driver to start using ICT interrupt.
1052 void iwl_pcie_reset_ict(struct iwl_trans
*trans
)
1054 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1056 unsigned long flags
;
1058 if (!trans_pcie
->ict_tbl
)
1061 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
1062 iwl_disable_interrupts(trans
);
1064 memset(trans_pcie
->ict_tbl
, 0, ICT_SIZE
);
1066 val
= trans_pcie
->ict_tbl_dma
>> ICT_SHIFT
;
1068 val
|= CSR_DRAM_INT_TBL_ENABLE
;
1069 val
|= CSR_DRAM_INIT_TBL_WRAP_CHECK
;
1071 IWL_DEBUG_ISR(trans
, "CSR_DRAM_INT_TBL_REG =0x%x\n", val
);
1073 iwl_write32(trans
, CSR_DRAM_INT_TBL_REG
, val
);
1074 trans_pcie
->use_ict
= true;
1075 trans_pcie
->ict_index
= 0;
1076 iwl_write32(trans
, CSR_INT
, trans_pcie
->inta_mask
);
1077 iwl_enable_interrupts(trans
);
1078 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
1081 /* Device is going down disable ict interrupt usage */
1082 void iwl_pcie_disable_ict(struct iwl_trans
*trans
)
1084 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1085 unsigned long flags
;
1087 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
1088 trans_pcie
->use_ict
= false;
1089 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
1092 /* legacy (non-ICT) ISR. Assumes that trans_pcie->irq_lock is held */
1093 static irqreturn_t
iwl_pcie_isr(int irq
, void *data
)
1095 struct iwl_trans
*trans
= data
;
1096 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1097 u32 inta
, inta_mask
;
1098 #ifdef CONFIG_IWLWIFI_DEBUG
1102 lockdep_assert_held(&trans_pcie
->irq_lock
);
1104 trace_iwlwifi_dev_irq(trans
->dev
);
1106 /* Disable (but don't clear!) interrupts here to avoid
1107 * back-to-back ISRs and sporadic interrupts from our NIC.
1108 * If we have something to service, the tasklet will re-enable ints.
1109 * If we *don't* have something, we'll re-enable before leaving here. */
1110 inta_mask
= iwl_read32(trans
, CSR_INT_MASK
); /* just for debug */
1111 iwl_write32(trans
, CSR_INT_MASK
, 0x00000000);
1113 /* Discover which interrupts are active/pending */
1114 inta
= iwl_read32(trans
, CSR_INT
);
1116 /* Ignore interrupt if there's nothing in NIC to service.
1117 * This may be due to IRQ shared with another device,
1118 * or due to sporadic interrupts thrown from our NIC. */
1120 IWL_DEBUG_ISR(trans
, "Ignore interrupt, inta == 0\n");
1124 if ((inta
== 0xFFFFFFFF) || ((inta
& 0xFFFFFFF0) == 0xa5a5a5a0)) {
1125 /* Hardware disappeared. It might have already raised
1127 IWL_WARN(trans
, "HARDWARE GONE?? INTA == 0x%08x\n", inta
);
1131 #ifdef CONFIG_IWLWIFI_DEBUG
1132 if (iwl_have_debug_level(IWL_DL_ISR
)) {
1133 inta_fh
= iwl_read32(trans
, CSR_FH_INT_STATUS
);
1134 IWL_DEBUG_ISR(trans
, "ISR inta 0x%08x, enabled 0x%08x, "
1135 "fh 0x%08x\n", inta
, inta_mask
, inta_fh
);
1139 trans_pcie
->inta
|= inta
;
1140 /* iwl_pcie_tasklet() will service interrupts and re-enable them */
1142 tasklet_schedule(&trans_pcie
->irq_tasklet
);
1143 else if (test_bit(STATUS_INT_ENABLED
, &trans_pcie
->status
) &&
1145 iwl_enable_interrupts(trans
);
1148 /* re-enable interrupts here since we don't have anything to service. */
1149 /* only Re-enable if disabled by irq and no schedules tasklet. */
1150 if (test_bit(STATUS_INT_ENABLED
, &trans_pcie
->status
) &&
1152 iwl_enable_interrupts(trans
);
1157 /* interrupt handler using ict table, with this interrupt driver will
1158 * stop using INTA register to get device's interrupt, reading this register
1159 * is expensive, device will write interrupts in ICT dram table, increment
1160 * index then will fire interrupt to driver, driver will OR all ICT table
1161 * entries from current index up to table entry with 0 value. the result is
1162 * the interrupt we need to service, driver will set the entries back to 0 and
1165 irqreturn_t
iwl_pcie_isr_ict(int irq
, void *data
)
1167 struct iwl_trans
*trans
= data
;
1168 struct iwl_trans_pcie
*trans_pcie
;
1169 u32 inta
, inta_mask
;
1172 unsigned long flags
;
1177 trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1179 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
1181 /* dram interrupt table not set yet,
1182 * use legacy interrupt.
1184 if (unlikely(!trans_pcie
->use_ict
)) {
1185 irqreturn_t ret
= iwl_pcie_isr(irq
, data
);
1186 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
1190 trace_iwlwifi_dev_irq(trans
->dev
);
1193 /* Disable (but don't clear!) interrupts here to avoid
1194 * back-to-back ISRs and sporadic interrupts from our NIC.
1195 * If we have something to service, the tasklet will re-enable ints.
1196 * If we *don't* have something, we'll re-enable before leaving here.
1198 inta_mask
= iwl_read32(trans
, CSR_INT_MASK
); /* just for debug */
1199 iwl_write32(trans
, CSR_INT_MASK
, 0x00000000);
1202 /* Ignore interrupt if there's nothing in NIC to service.
1203 * This may be due to IRQ shared with another device,
1204 * or due to sporadic interrupts thrown from our NIC. */
1205 read
= le32_to_cpu(trans_pcie
->ict_tbl
[trans_pcie
->ict_index
]);
1206 trace_iwlwifi_dev_ict_read(trans
->dev
, trans_pcie
->ict_index
, read
);
1208 IWL_DEBUG_ISR(trans
, "Ignore interrupt, inta == 0\n");
1213 * Collect all entries up to the first 0, starting from ict_index;
1214 * note we already read at ict_index.
1218 IWL_DEBUG_ISR(trans
, "ICT index %d value 0x%08X\n",
1219 trans_pcie
->ict_index
, read
);
1220 trans_pcie
->ict_tbl
[trans_pcie
->ict_index
] = 0;
1221 trans_pcie
->ict_index
=
1222 iwl_queue_inc_wrap(trans_pcie
->ict_index
, ICT_COUNT
);
1224 read
= le32_to_cpu(trans_pcie
->ict_tbl
[trans_pcie
->ict_index
]);
1225 trace_iwlwifi_dev_ict_read(trans
->dev
, trans_pcie
->ict_index
,
1229 /* We should not get this value, just ignore it. */
1230 if (val
== 0xffffffff)
1234 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1235 * (bit 15 before shifting it to 31) to clear when using interrupt
1236 * coalescing. fortunately, bits 18 and 19 stay set when this happens
1237 * so we use them to decide on the real state of the Rx bit.
1238 * In order words, bit 15 is set if bit 18 or bit 19 are set.
1243 inta
= (0xff & val
) | ((0xff00 & val
) << 16);
1244 IWL_DEBUG_ISR(trans
, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1245 inta
, inta_mask
, val
);
1247 inta
&= trans_pcie
->inta_mask
;
1248 trans_pcie
->inta
|= inta
;
1250 /* iwl_pcie_tasklet() will service interrupts and re-enable them */
1252 tasklet_schedule(&trans_pcie
->irq_tasklet
);
1253 else if (test_bit(STATUS_INT_ENABLED
, &trans_pcie
->status
) &&
1254 !trans_pcie
->inta
) {
1255 /* Allow interrupt if was disabled by this handler and
1256 * no tasklet was schedules, We should not enable interrupt,
1257 * tasklet will enable it.
1259 iwl_enable_interrupts(trans
);
1262 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
1266 /* re-enable interrupts here since we don't have anything to service.
1267 * only Re-enable if disabled by irq.
1269 if (test_bit(STATUS_INT_ENABLED
, &trans_pcie
->status
) &&
1271 iwl_enable_interrupts(trans
);
1273 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);