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iwlwifi: s/txq_agg_disable/txq_disable
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / iwlwifi / pcie / trans.c
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
70
71 #include "iwl-drv.h"
72 #include "iwl-trans.h"
73 #include "iwl-csr.h"
74 #include "iwl-prph.h"
75 #include "iwl-agn-hw.h"
76 #include "internal.h"
77 /* FIXME: need to abstract out TX command (once we know what it looks like) */
78 #include "dvm/commands.h"
79
80 #define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie) \
81 (((1<<trans->cfg->base_params->num_of_queues) - 1) &\
82 (~(1<<(trans_pcie)->cmd_queue)))
83
84 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
85 {
86 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
87 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
88 struct device *dev = trans->dev;
89
90 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
91
92 spin_lock_init(&rxq->lock);
93
94 if (WARN_ON(rxq->bd || rxq->rb_stts))
95 return -EINVAL;
96
97 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
98 rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
99 &rxq->bd_dma, GFP_KERNEL);
100 if (!rxq->bd)
101 goto err_bd;
102
103 /*Allocate the driver's pointer to receive buffer status */
104 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
105 &rxq->rb_stts_dma, GFP_KERNEL);
106 if (!rxq->rb_stts)
107 goto err_rb_stts;
108
109 return 0;
110
111 err_rb_stts:
112 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
113 rxq->bd, rxq->bd_dma);
114 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
115 rxq->bd = NULL;
116 err_bd:
117 return -ENOMEM;
118 }
119
120 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
121 {
122 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
123 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
124 int i;
125
126 /* Fill the rx_used queue with _all_ of the Rx buffers */
127 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
128 /* In the reset function, these buffers may have been allocated
129 * to an SKB, so we need to unmap and free potential storage */
130 if (rxq->pool[i].page != NULL) {
131 dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
132 PAGE_SIZE << trans_pcie->rx_page_order,
133 DMA_FROM_DEVICE);
134 __free_pages(rxq->pool[i].page,
135 trans_pcie->rx_page_order);
136 rxq->pool[i].page = NULL;
137 }
138 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
139 }
140 }
141
142 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
143 struct iwl_rx_queue *rxq)
144 {
145 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
146 u32 rb_size;
147 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
148 u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
149
150 if (trans_pcie->rx_buf_size_8k)
151 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
152 else
153 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
154
155 /* Stop Rx DMA */
156 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
157
158 /* Reset driver's Rx queue write index */
159 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
160
161 /* Tell device where to find RBD circular buffer in DRAM */
162 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
163 (u32)(rxq->bd_dma >> 8));
164
165 /* Tell device where in DRAM to update its Rx status */
166 iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
167 rxq->rb_stts_dma >> 4);
168
169 /* Enable Rx DMA
170 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
171 * the credit mechanism in 5000 HW RX FIFO
172 * Direct rx interrupts to hosts
173 * Rx buffer size 4 or 8k
174 * RB timeout 0x10
175 * 256 RBDs
176 */
177 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
178 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
179 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
180 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
181 rb_size|
182 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
183 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
184
185 /* Set interrupt coalescing timer to default (2048 usecs) */
186 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
187 }
188
189 static int iwl_rx_init(struct iwl_trans *trans)
190 {
191 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
192 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
193
194 int i, err;
195 unsigned long flags;
196
197 if (!rxq->bd) {
198 err = iwl_trans_rx_alloc(trans);
199 if (err)
200 return err;
201 }
202
203 spin_lock_irqsave(&rxq->lock, flags);
204 INIT_LIST_HEAD(&rxq->rx_free);
205 INIT_LIST_HEAD(&rxq->rx_used);
206
207 iwl_trans_rxq_free_rx_bufs(trans);
208
209 for (i = 0; i < RX_QUEUE_SIZE; i++)
210 rxq->queue[i] = NULL;
211
212 /* Set us so that we have processed and used all buffers, but have
213 * not restocked the Rx queue with fresh buffers */
214 rxq->read = rxq->write = 0;
215 rxq->write_actual = 0;
216 rxq->free_count = 0;
217 spin_unlock_irqrestore(&rxq->lock, flags);
218
219 iwlagn_rx_replenish(trans);
220
221 iwl_trans_rx_hw_init(trans, rxq);
222
223 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
224 rxq->need_update = 1;
225 iwl_rx_queue_update_write_ptr(trans, rxq);
226 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
227
228 return 0;
229 }
230
231 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
232 {
233 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
234 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
235 unsigned long flags;
236
237 /*if rxq->bd is NULL, it means that nothing has been allocated,
238 * exit now */
239 if (!rxq->bd) {
240 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
241 return;
242 }
243
244 spin_lock_irqsave(&rxq->lock, flags);
245 iwl_trans_rxq_free_rx_bufs(trans);
246 spin_unlock_irqrestore(&rxq->lock, flags);
247
248 dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
249 rxq->bd, rxq->bd_dma);
250 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
251 rxq->bd = NULL;
252
253 if (rxq->rb_stts)
254 dma_free_coherent(trans->dev,
255 sizeof(struct iwl_rb_status),
256 rxq->rb_stts, rxq->rb_stts_dma);
257 else
258 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
259 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
260 rxq->rb_stts = NULL;
261 }
262
263 static int iwl_trans_rx_stop(struct iwl_trans *trans)
264 {
265
266 /* stop Rx DMA */
267 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
268 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
269 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
270 }
271
272 static int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
273 struct iwl_dma_ptr *ptr, size_t size)
274 {
275 if (WARN_ON(ptr->addr))
276 return -EINVAL;
277
278 ptr->addr = dma_alloc_coherent(trans->dev, size,
279 &ptr->dma, GFP_KERNEL);
280 if (!ptr->addr)
281 return -ENOMEM;
282 ptr->size = size;
283 return 0;
284 }
285
286 static void iwlagn_free_dma_ptr(struct iwl_trans *trans,
287 struct iwl_dma_ptr *ptr)
288 {
289 if (unlikely(!ptr->addr))
290 return;
291
292 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
293 memset(ptr, 0, sizeof(*ptr));
294 }
295
296 static void iwl_trans_pcie_queue_stuck_timer(unsigned long data)
297 {
298 struct iwl_tx_queue *txq = (void *)data;
299 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
300 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
301
302 spin_lock(&txq->lock);
303 /* check if triggered erroneously */
304 if (txq->q.read_ptr == txq->q.write_ptr) {
305 spin_unlock(&txq->lock);
306 return;
307 }
308 spin_unlock(&txq->lock);
309
310
311 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
312 jiffies_to_msecs(trans_pcie->wd_timeout));
313 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
314 txq->q.read_ptr, txq->q.write_ptr);
315 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
316 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq->q.id))
317 & (TFD_QUEUE_SIZE_MAX - 1),
318 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq->q.id)));
319
320 iwl_op_mode_nic_error(trans->op_mode);
321 }
322
323 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
324 struct iwl_tx_queue *txq, int slots_num,
325 u32 txq_id)
326 {
327 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
328 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
329 int i;
330
331 if (WARN_ON(txq->entries || txq->tfds))
332 return -EINVAL;
333
334 setup_timer(&txq->stuck_timer, iwl_trans_pcie_queue_stuck_timer,
335 (unsigned long)txq);
336 txq->trans_pcie = trans_pcie;
337
338 txq->q.n_window = slots_num;
339
340 txq->entries = kcalloc(slots_num,
341 sizeof(struct iwl_pcie_tx_queue_entry),
342 GFP_KERNEL);
343
344 if (!txq->entries)
345 goto error;
346
347 if (txq_id == trans_pcie->cmd_queue)
348 for (i = 0; i < slots_num; i++) {
349 txq->entries[i].cmd =
350 kmalloc(sizeof(struct iwl_device_cmd),
351 GFP_KERNEL);
352 if (!txq->entries[i].cmd)
353 goto error;
354 }
355
356 /* Circular buffer of transmit frame descriptors (TFDs),
357 * shared with device */
358 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
359 &txq->q.dma_addr, GFP_KERNEL);
360 if (!txq->tfds) {
361 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
362 goto error;
363 }
364 txq->q.id = txq_id;
365
366 return 0;
367 error:
368 if (txq->entries && txq_id == trans_pcie->cmd_queue)
369 for (i = 0; i < slots_num; i++)
370 kfree(txq->entries[i].cmd);
371 kfree(txq->entries);
372 txq->entries = NULL;
373
374 return -ENOMEM;
375
376 }
377
378 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
379 int slots_num, u32 txq_id)
380 {
381 int ret;
382
383 txq->need_update = 0;
384
385 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
386 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
387 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
388
389 /* Initialize queue's high/low-water marks, and head/tail indexes */
390 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
391 txq_id);
392 if (ret)
393 return ret;
394
395 spin_lock_init(&txq->lock);
396
397 /*
398 * Tell nic where to find circular buffer of Tx Frame Descriptors for
399 * given Tx queue, and enable the DMA channel used for that queue.
400 * Circular buffer (TFD queue in DRAM) physical base address */
401 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
402 txq->q.dma_addr >> 8);
403
404 return 0;
405 }
406
407 /**
408 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
409 */
410 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
411 {
412 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
413 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
414 struct iwl_queue *q = &txq->q;
415 enum dma_data_direction dma_dir;
416
417 if (!q->n_bd)
418 return;
419
420 /* In the command queue, all the TBs are mapped as BIDI
421 * so unmap them as such.
422 */
423 if (txq_id == trans_pcie->cmd_queue)
424 dma_dir = DMA_BIDIRECTIONAL;
425 else
426 dma_dir = DMA_TO_DEVICE;
427
428 spin_lock_bh(&txq->lock);
429 while (q->write_ptr != q->read_ptr) {
430 iwl_txq_free_tfd(trans, txq, dma_dir);
431 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
432 }
433 spin_unlock_bh(&txq->lock);
434 }
435
436 /**
437 * iwl_tx_queue_free - Deallocate DMA queue.
438 * @txq: Transmit queue to deallocate.
439 *
440 * Empty queue by removing and destroying all BD's.
441 * Free all buffers.
442 * 0-fill, but do not free "txq" descriptor structure.
443 */
444 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
445 {
446 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
447 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
448 struct device *dev = trans->dev;
449 int i;
450
451 if (WARN_ON(!txq))
452 return;
453
454 iwl_tx_queue_unmap(trans, txq_id);
455
456 /* De-alloc array of command/tx buffers */
457
458 if (txq_id == trans_pcie->cmd_queue)
459 for (i = 0; i < txq->q.n_window; i++)
460 kfree(txq->entries[i].cmd);
461
462 /* De-alloc circular buffer of TFDs */
463 if (txq->q.n_bd) {
464 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
465 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
466 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
467 }
468
469 kfree(txq->entries);
470 txq->entries = NULL;
471
472 del_timer_sync(&txq->stuck_timer);
473
474 /* 0-fill queue descriptor structure */
475 memset(txq, 0, sizeof(*txq));
476 }
477
478 /**
479 * iwl_trans_tx_free - Free TXQ Context
480 *
481 * Destroy all TX DMA queues and structures
482 */
483 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
484 {
485 int txq_id;
486 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
487
488 /* Tx queues */
489 if (trans_pcie->txq) {
490 for (txq_id = 0;
491 txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
492 iwl_tx_queue_free(trans, txq_id);
493 }
494
495 kfree(trans_pcie->txq);
496 trans_pcie->txq = NULL;
497
498 iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
499
500 iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
501 }
502
503 /**
504 * iwl_trans_tx_alloc - allocate TX context
505 * Allocate all Tx DMA structures and initialize them
506 *
507 * @param priv
508 * @return error code
509 */
510 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
511 {
512 int ret;
513 int txq_id, slots_num;
514 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
515
516 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
517 sizeof(struct iwlagn_scd_bc_tbl);
518
519 /*It is not allowed to alloc twice, so warn when this happens.
520 * We cannot rely on the previous allocation, so free and fail */
521 if (WARN_ON(trans_pcie->txq)) {
522 ret = -EINVAL;
523 goto error;
524 }
525
526 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
527 scd_bc_tbls_size);
528 if (ret) {
529 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
530 goto error;
531 }
532
533 /* Alloc keep-warm buffer */
534 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
535 if (ret) {
536 IWL_ERR(trans, "Keep Warm allocation failed\n");
537 goto error;
538 }
539
540 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
541 sizeof(struct iwl_tx_queue), GFP_KERNEL);
542 if (!trans_pcie->txq) {
543 IWL_ERR(trans, "Not enough memory for txq\n");
544 ret = ENOMEM;
545 goto error;
546 }
547
548 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
549 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
550 txq_id++) {
551 slots_num = (txq_id == trans_pcie->cmd_queue) ?
552 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
553 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
554 slots_num, txq_id);
555 if (ret) {
556 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
557 goto error;
558 }
559 }
560
561 return 0;
562
563 error:
564 iwl_trans_pcie_tx_free(trans);
565
566 return ret;
567 }
568 static int iwl_tx_init(struct iwl_trans *trans)
569 {
570 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
571 int ret;
572 int txq_id, slots_num;
573 unsigned long flags;
574 bool alloc = false;
575
576 if (!trans_pcie->txq) {
577 ret = iwl_trans_tx_alloc(trans);
578 if (ret)
579 goto error;
580 alloc = true;
581 }
582
583 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
584
585 /* Turn off all Tx DMA fifos */
586 iwl_write_prph(trans, SCD_TXFACT, 0);
587
588 /* Tell NIC where to find the "keep warm" buffer */
589 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
590 trans_pcie->kw.dma >> 4);
591
592 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
593
594 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
595 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
596 txq_id++) {
597 slots_num = (txq_id == trans_pcie->cmd_queue) ?
598 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
599 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
600 slots_num, txq_id);
601 if (ret) {
602 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
603 goto error;
604 }
605 }
606
607 return 0;
608 error:
609 /*Upon error, free only if we allocated something */
610 if (alloc)
611 iwl_trans_pcie_tx_free(trans);
612 return ret;
613 }
614
615 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
616 {
617 /*
618 * (for documentation purposes)
619 * to set power to V_AUX, do:
620
621 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
622 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
623 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
624 ~APMG_PS_CTRL_MSK_PWR_SRC);
625 */
626
627 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
628 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
629 ~APMG_PS_CTRL_MSK_PWR_SRC);
630 }
631
632 /* PCI registers */
633 #define PCI_CFG_RETRY_TIMEOUT 0x041
634 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
635 #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
636
637 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
638 {
639 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
640 int pos;
641 u16 pci_lnk_ctl;
642
643 struct pci_dev *pci_dev = trans_pcie->pci_dev;
644
645 pos = pci_pcie_cap(pci_dev);
646 pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
647 return pci_lnk_ctl;
648 }
649
650 static void iwl_apm_config(struct iwl_trans *trans)
651 {
652 /*
653 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
654 * Check if BIOS (or OS) enabled L1-ASPM on this device.
655 * If so (likely), disable L0S, so device moves directly L0->L1;
656 * costs negligible amount of power savings.
657 * If not (unlikely), enable L0S, so there is at least some
658 * power savings, even without L1.
659 */
660 u16 lctl = iwl_pciexp_link_ctrl(trans);
661
662 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
663 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
664 /* L1-ASPM enabled; disable(!) L0S */
665 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
666 dev_printk(KERN_INFO, trans->dev,
667 "L1 Enabled; Disabling L0S\n");
668 } else {
669 /* L1-ASPM disabled; enable(!) L0S */
670 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
671 dev_printk(KERN_INFO, trans->dev,
672 "L1 Disabled; Enabling L0S\n");
673 }
674 trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
675 }
676
677 /*
678 * Start up NIC's basic functionality after it has been reset
679 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
680 * NOTE: This does not load uCode nor start the embedded processor
681 */
682 static int iwl_apm_init(struct iwl_trans *trans)
683 {
684 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
685 int ret = 0;
686 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
687
688 /*
689 * Use "set_bit" below rather than "write", to preserve any hardware
690 * bits already set by default after reset.
691 */
692
693 /* Disable L0S exit timer (platform NMI Work/Around) */
694 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
695 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
696
697 /*
698 * Disable L0s without affecting L1;
699 * don't wait for ICH L0s (ICH bug W/A)
700 */
701 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
702 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
703
704 /* Set FH wait threshold to maximum (HW error during stress W/A) */
705 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
706
707 /*
708 * Enable HAP INTA (interrupt from management bus) to
709 * wake device's PCI Express link L1a -> L0s
710 */
711 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
712 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
713
714 iwl_apm_config(trans);
715
716 /* Configure analog phase-lock-loop before activating to D0A */
717 if (trans->cfg->base_params->pll_cfg_val)
718 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
719 trans->cfg->base_params->pll_cfg_val);
720
721 /*
722 * Set "initialization complete" bit to move adapter from
723 * D0U* --> D0A* (powered-up active) state.
724 */
725 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
726
727 /*
728 * Wait for clock stabilization; once stabilized, access to
729 * device-internal resources is supported, e.g. iwl_write_prph()
730 * and accesses to uCode SRAM.
731 */
732 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
733 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
734 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
735 if (ret < 0) {
736 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
737 goto out;
738 }
739
740 /*
741 * Enable DMA clock and wait for it to stabilize.
742 *
743 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
744 * do not disable clocks. This preserves any hardware bits already
745 * set by default in "CLK_CTRL_REG" after reset.
746 */
747 iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
748 udelay(20);
749
750 /* Disable L1-Active */
751 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
752 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
753
754 set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
755
756 out:
757 return ret;
758 }
759
760 static int iwl_apm_stop_master(struct iwl_trans *trans)
761 {
762 int ret = 0;
763
764 /* stop device's busmaster DMA activity */
765 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
766
767 ret = iwl_poll_bit(trans, CSR_RESET,
768 CSR_RESET_REG_FLAG_MASTER_DISABLED,
769 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
770 if (ret)
771 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
772
773 IWL_DEBUG_INFO(trans, "stop master\n");
774
775 return ret;
776 }
777
778 static void iwl_apm_stop(struct iwl_trans *trans)
779 {
780 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
781 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
782
783 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
784
785 /* Stop device's DMA activity */
786 iwl_apm_stop_master(trans);
787
788 /* Reset the entire device */
789 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
790
791 udelay(10);
792
793 /*
794 * Clear "initialization complete" bit to move adapter from
795 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
796 */
797 iwl_clear_bit(trans, CSR_GP_CNTRL,
798 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
799 }
800
801 static int iwl_nic_init(struct iwl_trans *trans)
802 {
803 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
804 unsigned long flags;
805
806 /* nic_init */
807 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
808 iwl_apm_init(trans);
809
810 /* Set interrupt coalescing calibration timer to default (512 usecs) */
811 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
812
813 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
814
815 iwl_set_pwr_vmain(trans);
816
817 iwl_op_mode_nic_config(trans->op_mode);
818
819 #ifndef CONFIG_IWLWIFI_IDI
820 /* Allocate the RX queue, or reset if it is already allocated */
821 iwl_rx_init(trans);
822 #endif
823
824 /* Allocate or reset and init all Tx and Command queues */
825 if (iwl_tx_init(trans))
826 return -ENOMEM;
827
828 if (trans->cfg->base_params->shadow_reg_enable) {
829 /* enable shadow regs in HW */
830 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
831 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
832 }
833
834 return 0;
835 }
836
837 #define HW_READY_TIMEOUT (50)
838
839 /* Note: returns poll_bit return value, which is >= 0 if success */
840 static int iwl_set_hw_ready(struct iwl_trans *trans)
841 {
842 int ret;
843
844 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
845 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
846
847 /* See if we got it */
848 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
849 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
850 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
851 HW_READY_TIMEOUT);
852
853 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
854 return ret;
855 }
856
857 /* Note: returns standard 0/-ERROR code */
858 static int iwl_prepare_card_hw(struct iwl_trans *trans)
859 {
860 int ret;
861
862 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
863
864 ret = iwl_set_hw_ready(trans);
865 /* If the card is ready, exit 0 */
866 if (ret >= 0)
867 return 0;
868
869 /* If HW is not ready, prepare the conditions to check again */
870 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
871 CSR_HW_IF_CONFIG_REG_PREPARE);
872
873 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
874 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
875 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
876
877 if (ret < 0)
878 return ret;
879
880 /* HW should be ready by now, check again. */
881 ret = iwl_set_hw_ready(trans);
882 if (ret >= 0)
883 return 0;
884 return ret;
885 }
886
887 /*
888 * ucode
889 */
890 static int iwl_load_section(struct iwl_trans *trans, u8 section_num,
891 const struct fw_desc *section)
892 {
893 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
894 dma_addr_t phy_addr = section->p_addr;
895 u32 byte_cnt = section->len;
896 u32 dst_addr = section->offset;
897 int ret;
898
899 trans_pcie->ucode_write_complete = false;
900
901 iwl_write_direct32(trans,
902 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
903 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
904
905 iwl_write_direct32(trans,
906 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
907 dst_addr);
908
909 iwl_write_direct32(trans,
910 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
911 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
912
913 iwl_write_direct32(trans,
914 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
915 (iwl_get_dma_hi_addr(phy_addr)
916 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
917
918 iwl_write_direct32(trans,
919 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
920 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
921 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
922 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
923
924 iwl_write_direct32(trans,
925 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
926 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
927 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
928 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
929
930 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
931 section_num);
932 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
933 trans_pcie->ucode_write_complete, 5 * HZ);
934 if (!ret) {
935 IWL_ERR(trans, "Could not load the [%d] uCode section\n",
936 section_num);
937 return -ETIMEDOUT;
938 }
939
940 return 0;
941 }
942
943 static int iwl_load_given_ucode(struct iwl_trans *trans,
944 const struct fw_img *image)
945 {
946 int ret = 0;
947 int i;
948
949 for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
950 if (!image->sec[i].p_addr)
951 break;
952
953 ret = iwl_load_section(trans, i, &image->sec[i]);
954 if (ret)
955 return ret;
956 }
957
958 /* Remove all resets to allow NIC to operate */
959 iwl_write32(trans, CSR_RESET, 0);
960
961 return 0;
962 }
963
964 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
965 const struct fw_img *fw)
966 {
967 int ret;
968 bool hw_rfkill;
969
970 /* This may fail if AMT took ownership of the device */
971 if (iwl_prepare_card_hw(trans)) {
972 IWL_WARN(trans, "Exit HW not ready\n");
973 return -EIO;
974 }
975
976 iwl_enable_rfkill_int(trans);
977
978 /* If platform's RF_KILL switch is NOT set to KILL */
979 hw_rfkill = iwl_is_rfkill_set(trans);
980 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
981 if (hw_rfkill)
982 return -ERFKILL;
983
984 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
985
986 ret = iwl_nic_init(trans);
987 if (ret) {
988 IWL_ERR(trans, "Unable to init nic\n");
989 return ret;
990 }
991
992 /* make sure rfkill handshake bits are cleared */
993 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
994 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
995 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
996
997 /* clear (again), then enable host interrupts */
998 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
999 iwl_enable_interrupts(trans);
1000
1001 /* really make sure rfkill handshake bits are cleared */
1002 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1003 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1004
1005 /* Load the given image to the HW */
1006 return iwl_load_given_ucode(trans, fw);
1007 }
1008
1009 /*
1010 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1011 * must be called under the irq lock and with MAC access
1012 */
1013 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1014 {
1015 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1016 IWL_TRANS_GET_PCIE_TRANS(trans);
1017
1018 lockdep_assert_held(&trans_pcie->irq_lock);
1019
1020 iwl_write_prph(trans, SCD_TXFACT, mask);
1021 }
1022
1023 static void iwl_tx_start(struct iwl_trans *trans)
1024 {
1025 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1026 u32 a;
1027 unsigned long flags;
1028 int i, chan;
1029 u32 reg_val;
1030
1031 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1032
1033 /* make sure all queue are not stopped/used */
1034 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
1035 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
1036
1037 trans_pcie->scd_base_addr =
1038 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1039 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1040 /* reset conext data memory */
1041 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1042 a += 4)
1043 iwl_write_targ_mem(trans, a, 0);
1044 /* reset tx status memory */
1045 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1046 a += 4)
1047 iwl_write_targ_mem(trans, a, 0);
1048 for (; a < trans_pcie->scd_base_addr +
1049 SCD_TRANS_TBL_OFFSET_QUEUE(
1050 trans->cfg->base_params->num_of_queues);
1051 a += 4)
1052 iwl_write_targ_mem(trans, a, 0);
1053
1054 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1055 trans_pcie->scd_bc_tbls.dma >> 10);
1056
1057 iwl_write_prph(trans, SCD_QUEUECHAIN_SEL,
1058 SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie));
1059 iwl_write_prph(trans, SCD_AGGR_SEL, 0);
1060
1061 /* initiate the queues */
1062 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
1063 iwl_trans_set_wr_ptrs(trans, i, 0);
1064 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1065 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
1066 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1067 SCD_CONTEXT_QUEUE_OFFSET(i) +
1068 sizeof(u32),
1069 ((SCD_WIN_SIZE <<
1070 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1071 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1072 ((SCD_FRAME_LIMIT <<
1073 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1074 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1075 }
1076
1077 for (i = 0; i < trans_pcie->n_q_to_fifo; i++) {
1078 int fifo = trans_pcie->setup_q_to_fifo[i];
1079
1080 set_bit(i, trans_pcie->queue_used);
1081
1082 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
1083 fifo, true);
1084 }
1085
1086 /* Activate all Tx DMA/FIFO channels */
1087 iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1088
1089 /* Enable DMA channel */
1090 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1091 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1092 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1093 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1094
1095 /* Update FH chicken bits */
1096 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1097 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1098 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1099
1100 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1101
1102 /* Enable L1-Active */
1103 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1104 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1105 }
1106
1107 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1108 {
1109 iwl_reset_ict(trans);
1110 iwl_tx_start(trans);
1111 }
1112
1113 /**
1114 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1115 */
1116 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1117 {
1118 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1119 int ch, txq_id, ret;
1120 unsigned long flags;
1121
1122 /* Turn off all Tx DMA fifos */
1123 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1124
1125 iwl_trans_txq_set_sched(trans, 0);
1126
1127 /* Stop each Tx DMA channel, and wait for it to be idle */
1128 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1129 iwl_write_direct32(trans,
1130 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1131 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1132 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000);
1133 if (ret < 0)
1134 IWL_ERR(trans,
1135 "Failing on timeout while stopping DMA channel %d [0x%08x]",
1136 ch,
1137 iwl_read_direct32(trans,
1138 FH_TSSR_TX_STATUS_REG));
1139 }
1140 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1141
1142 if (!trans_pcie->txq) {
1143 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
1144 return 0;
1145 }
1146
1147 /* Unmap DMA from host system and free skb's */
1148 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
1149 txq_id++)
1150 iwl_tx_queue_unmap(trans, txq_id);
1151
1152 return 0;
1153 }
1154
1155 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1156 {
1157 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1158 unsigned long flags;
1159
1160 /* tell the device to stop sending interrupts */
1161 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1162 iwl_disable_interrupts(trans);
1163 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1164
1165 /* device going down, Stop using ICT table */
1166 iwl_disable_ict(trans);
1167
1168 /*
1169 * If a HW restart happens during firmware loading,
1170 * then the firmware loading might call this function
1171 * and later it might be called again due to the
1172 * restart. So don't process again if the device is
1173 * already dead.
1174 */
1175 if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
1176 iwl_trans_tx_stop(trans);
1177 #ifndef CONFIG_IWLWIFI_IDI
1178 iwl_trans_rx_stop(trans);
1179 #endif
1180 /* Power-down device's busmaster DMA clocks */
1181 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1182 APMG_CLK_VAL_DMA_CLK_RQT);
1183 udelay(5);
1184 }
1185
1186 /* Make sure (redundant) we've released our request to stay awake */
1187 iwl_clear_bit(trans, CSR_GP_CNTRL,
1188 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1189
1190 /* Stop the device, and put it in low power state */
1191 iwl_apm_stop(trans);
1192
1193 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1194 * Clean again the interrupt here
1195 */
1196 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1197 iwl_disable_interrupts(trans);
1198 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1199
1200 iwl_enable_rfkill_int(trans);
1201
1202 /* wait to make sure we flush pending tasklet*/
1203 synchronize_irq(trans_pcie->irq);
1204 tasklet_kill(&trans_pcie->irq_tasklet);
1205
1206 cancel_work_sync(&trans_pcie->rx_replenish);
1207
1208 /* stop and reset the on-board processor */
1209 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1210
1211 /* clear all status bits */
1212 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1213 clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
1214 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
1215 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1216 }
1217
1218 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1219 {
1220 /* let the ucode operate on its own */
1221 iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1222 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1223
1224 iwl_disable_interrupts(trans);
1225 iwl_clear_bit(trans, CSR_GP_CNTRL,
1226 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1227 }
1228
1229 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1230 struct iwl_device_cmd *dev_cmd, int txq_id)
1231 {
1232 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1233 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1234 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1235 struct iwl_cmd_meta *out_meta;
1236 struct iwl_tx_queue *txq;
1237 struct iwl_queue *q;
1238 dma_addr_t phys_addr = 0;
1239 dma_addr_t txcmd_phys;
1240 dma_addr_t scratch_phys;
1241 u16 len, firstlen, secondlen;
1242 u8 wait_write_ptr = 0;
1243 __le16 fc = hdr->frame_control;
1244 u8 hdr_len = ieee80211_hdrlen(fc);
1245 u16 __maybe_unused wifi_seq;
1246
1247 txq = &trans_pcie->txq[txq_id];
1248 q = &txq->q;
1249
1250 if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) {
1251 WARN_ON_ONCE(1);
1252 return -EINVAL;
1253 }
1254
1255 spin_lock(&txq->lock);
1256
1257 /* Set up driver data for this TFD */
1258 txq->entries[q->write_ptr].skb = skb;
1259 txq->entries[q->write_ptr].cmd = dev_cmd;
1260
1261 dev_cmd->hdr.cmd = REPLY_TX;
1262 dev_cmd->hdr.sequence =
1263 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1264 INDEX_TO_SEQ(q->write_ptr)));
1265
1266 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1267 out_meta = &txq->entries[q->write_ptr].meta;
1268
1269 /*
1270 * Use the first empty entry in this queue's command buffer array
1271 * to contain the Tx command and MAC header concatenated together
1272 * (payload data will be in another buffer).
1273 * Size of this varies, due to varying MAC header length.
1274 * If end is not dword aligned, we'll have 2 extra bytes at the end
1275 * of the MAC header (device reads on dword boundaries).
1276 * We'll tell device about this padding later.
1277 */
1278 len = sizeof(struct iwl_tx_cmd) +
1279 sizeof(struct iwl_cmd_header) + hdr_len;
1280 firstlen = (len + 3) & ~3;
1281
1282 /* Tell NIC about any 2-byte padding after MAC header */
1283 if (firstlen != len)
1284 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1285
1286 /* Physical address of this Tx command's header (not MAC header!),
1287 * within command buffer array. */
1288 txcmd_phys = dma_map_single(trans->dev,
1289 &dev_cmd->hdr, firstlen,
1290 DMA_BIDIRECTIONAL);
1291 if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1292 goto out_err;
1293 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1294 dma_unmap_len_set(out_meta, len, firstlen);
1295
1296 if (!ieee80211_has_morefrags(fc)) {
1297 txq->need_update = 1;
1298 } else {
1299 wait_write_ptr = 1;
1300 txq->need_update = 0;
1301 }
1302
1303 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1304 * if any (802.11 null frames have no payload). */
1305 secondlen = skb->len - hdr_len;
1306 if (secondlen > 0) {
1307 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1308 secondlen, DMA_TO_DEVICE);
1309 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1310 dma_unmap_single(trans->dev,
1311 dma_unmap_addr(out_meta, mapping),
1312 dma_unmap_len(out_meta, len),
1313 DMA_BIDIRECTIONAL);
1314 goto out_err;
1315 }
1316 }
1317
1318 /* Attach buffers to TFD */
1319 iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1320 if (secondlen > 0)
1321 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1322 secondlen, 0);
1323
1324 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1325 offsetof(struct iwl_tx_cmd, scratch);
1326
1327 /* take back ownership of DMA buffer to enable update */
1328 dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1329 DMA_BIDIRECTIONAL);
1330 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1331 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1332
1333 IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1334 le16_to_cpu(dev_cmd->hdr.sequence));
1335 IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1336
1337 /* Set up entry for this TFD in Tx byte-count array */
1338 iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1339
1340 dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1341 DMA_BIDIRECTIONAL);
1342
1343 trace_iwlwifi_dev_tx(trans->dev,
1344 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1345 sizeof(struct iwl_tfd),
1346 &dev_cmd->hdr, firstlen,
1347 skb->data + hdr_len, secondlen);
1348
1349 /* start timer if queue currently empty */
1350 if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout)
1351 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1352
1353 /* Tell device the write index *just past* this latest filled TFD */
1354 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1355 iwl_txq_update_write_ptr(trans, txq);
1356
1357 /*
1358 * At this point the frame is "transmitted" successfully
1359 * and we will get a TX status notification eventually,
1360 * regardless of the value of ret. "ret" only indicates
1361 * whether or not we should update the write pointer.
1362 */
1363 if (iwl_queue_space(q) < q->high_mark) {
1364 if (wait_write_ptr) {
1365 txq->need_update = 1;
1366 iwl_txq_update_write_ptr(trans, txq);
1367 } else {
1368 iwl_stop_queue(trans, txq);
1369 }
1370 }
1371 spin_unlock(&txq->lock);
1372 return 0;
1373 out_err:
1374 spin_unlock(&txq->lock);
1375 return -1;
1376 }
1377
1378 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1379 {
1380 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1381 int err;
1382 bool hw_rfkill;
1383
1384 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1385
1386 if (!trans_pcie->irq_requested) {
1387 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1388 iwl_irq_tasklet, (unsigned long)trans);
1389
1390 iwl_alloc_isr_ict(trans);
1391
1392 err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED,
1393 DRV_NAME, trans);
1394 if (err) {
1395 IWL_ERR(trans, "Error allocating IRQ %d\n",
1396 trans_pcie->irq);
1397 goto error;
1398 }
1399
1400 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1401 trans_pcie->irq_requested = true;
1402 }
1403
1404 err = iwl_prepare_card_hw(trans);
1405 if (err) {
1406 IWL_ERR(trans, "Error while preparing HW: %d", err);
1407 goto err_free_irq;
1408 }
1409
1410 iwl_apm_init(trans);
1411
1412 /* From now on, the op_mode will be kept updated about RF kill state */
1413 iwl_enable_rfkill_int(trans);
1414
1415 hw_rfkill = iwl_is_rfkill_set(trans);
1416 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1417
1418 return err;
1419
1420 err_free_irq:
1421 free_irq(trans_pcie->irq, trans);
1422 error:
1423 iwl_free_isr_ict(trans);
1424 tasklet_kill(&trans_pcie->irq_tasklet);
1425 return err;
1426 }
1427
1428 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
1429 bool op_mode_leaving)
1430 {
1431 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1432 bool hw_rfkill;
1433 unsigned long flags;
1434
1435 iwl_apm_stop(trans);
1436
1437 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1438 iwl_disable_interrupts(trans);
1439 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1440
1441 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1442
1443 if (!op_mode_leaving) {
1444 /*
1445 * Even if we stop the HW, we still want the RF kill
1446 * interrupt
1447 */
1448 iwl_enable_rfkill_int(trans);
1449
1450 /*
1451 * Check again since the RF kill state may have changed while
1452 * all the interrupts were disabled, in this case we couldn't
1453 * receive the RF kill interrupt and update the state in the
1454 * op_mode.
1455 */
1456 hw_rfkill = iwl_is_rfkill_set(trans);
1457 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1458 }
1459 }
1460
1461 static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1462 struct sk_buff_head *skbs)
1463 {
1464 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1465 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1466 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1467 int tfd_num = ssn & (txq->q.n_bd - 1);
1468 int freed = 0;
1469
1470 spin_lock(&txq->lock);
1471
1472 if (txq->q.read_ptr != tfd_num) {
1473 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1474 txq_id, txq->q.read_ptr, tfd_num, ssn);
1475 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1476 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1477 iwl_wake_queue(trans, txq);
1478 }
1479
1480 spin_unlock(&txq->lock);
1481 }
1482
1483 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1484 {
1485 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1486 }
1487
1488 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1489 {
1490 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1491 }
1492
1493 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1494 {
1495 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1496 }
1497
1498 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1499 const struct iwl_trans_config *trans_cfg)
1500 {
1501 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1502
1503 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1504 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1505 trans_pcie->n_no_reclaim_cmds = 0;
1506 else
1507 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1508 if (trans_pcie->n_no_reclaim_cmds)
1509 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1510 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1511
1512 trans_pcie->n_q_to_fifo = trans_cfg->n_queue_to_fifo;
1513
1514 if (WARN_ON(trans_pcie->n_q_to_fifo > IWL_MAX_HW_QUEUES))
1515 trans_pcie->n_q_to_fifo = IWL_MAX_HW_QUEUES;
1516
1517 /* at least the command queue must be mapped */
1518 WARN_ON(!trans_pcie->n_q_to_fifo);
1519
1520 memcpy(trans_pcie->setup_q_to_fifo, trans_cfg->queue_to_fifo,
1521 trans_pcie->n_q_to_fifo * sizeof(u8));
1522
1523 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1524 if (trans_pcie->rx_buf_size_8k)
1525 trans_pcie->rx_page_order = get_order(8 * 1024);
1526 else
1527 trans_pcie->rx_page_order = get_order(4 * 1024);
1528
1529 trans_pcie->wd_timeout =
1530 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1531
1532 trans_pcie->command_names = trans_cfg->command_names;
1533 }
1534
1535 void iwl_trans_pcie_free(struct iwl_trans *trans)
1536 {
1537 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1538
1539 iwl_trans_pcie_tx_free(trans);
1540 #ifndef CONFIG_IWLWIFI_IDI
1541 iwl_trans_pcie_rx_free(trans);
1542 #endif
1543 if (trans_pcie->irq_requested == true) {
1544 free_irq(trans_pcie->irq, trans);
1545 iwl_free_isr_ict(trans);
1546 }
1547
1548 pci_disable_msi(trans_pcie->pci_dev);
1549 iounmap(trans_pcie->hw_base);
1550 pci_release_regions(trans_pcie->pci_dev);
1551 pci_disable_device(trans_pcie->pci_dev);
1552
1553 kfree(trans);
1554 }
1555
1556 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1557 {
1558 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1559
1560 if (state)
1561 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1562 else
1563 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1564 }
1565
1566 #ifdef CONFIG_PM_SLEEP
1567 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1568 {
1569 return 0;
1570 }
1571
1572 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1573 {
1574 bool hw_rfkill;
1575
1576 iwl_enable_rfkill_int(trans);
1577
1578 hw_rfkill = iwl_is_rfkill_set(trans);
1579 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1580
1581 if (!hw_rfkill)
1582 iwl_enable_interrupts(trans);
1583
1584 return 0;
1585 }
1586 #endif /* CONFIG_PM_SLEEP */
1587
1588 #define IWL_FLUSH_WAIT_MS 2000
1589
1590 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1591 {
1592 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1593 struct iwl_tx_queue *txq;
1594 struct iwl_queue *q;
1595 int cnt;
1596 unsigned long now = jiffies;
1597 int ret = 0;
1598
1599 /* waiting for all the tx frames complete might take a while */
1600 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1601 if (cnt == trans_pcie->cmd_queue)
1602 continue;
1603 txq = &trans_pcie->txq[cnt];
1604 q = &txq->q;
1605 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1606 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1607 msleep(1);
1608
1609 if (q->read_ptr != q->write_ptr) {
1610 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1611 ret = -ETIMEDOUT;
1612 break;
1613 }
1614 }
1615 return ret;
1616 }
1617
1618 static const char *get_fh_string(int cmd)
1619 {
1620 #define IWL_CMD(x) case x: return #x
1621 switch (cmd) {
1622 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1623 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1624 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1625 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1626 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1627 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1628 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1629 IWL_CMD(FH_TSSR_TX_STATUS_REG);
1630 IWL_CMD(FH_TSSR_TX_ERROR_REG);
1631 default:
1632 return "UNKNOWN";
1633 }
1634 #undef IWL_CMD
1635 }
1636
1637 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1638 {
1639 int i;
1640 #ifdef CONFIG_IWLWIFI_DEBUG
1641 int pos = 0;
1642 size_t bufsz = 0;
1643 #endif
1644 static const u32 fh_tbl[] = {
1645 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1646 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1647 FH_RSCSR_CHNL0_WPTR,
1648 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1649 FH_MEM_RSSR_SHARED_CTRL_REG,
1650 FH_MEM_RSSR_RX_STATUS_REG,
1651 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1652 FH_TSSR_TX_STATUS_REG,
1653 FH_TSSR_TX_ERROR_REG
1654 };
1655 #ifdef CONFIG_IWLWIFI_DEBUG
1656 if (display) {
1657 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1658 *buf = kmalloc(bufsz, GFP_KERNEL);
1659 if (!*buf)
1660 return -ENOMEM;
1661 pos += scnprintf(*buf + pos, bufsz - pos,
1662 "FH register values:\n");
1663 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1664 pos += scnprintf(*buf + pos, bufsz - pos,
1665 " %34s: 0X%08x\n",
1666 get_fh_string(fh_tbl[i]),
1667 iwl_read_direct32(trans, fh_tbl[i]));
1668 }
1669 return pos;
1670 }
1671 #endif
1672 IWL_ERR(trans, "FH register values:\n");
1673 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1674 IWL_ERR(trans, " %34s: 0X%08x\n",
1675 get_fh_string(fh_tbl[i]),
1676 iwl_read_direct32(trans, fh_tbl[i]));
1677 }
1678 return 0;
1679 }
1680
1681 static const char *get_csr_string(int cmd)
1682 {
1683 #define IWL_CMD(x) case x: return #x
1684 switch (cmd) {
1685 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1686 IWL_CMD(CSR_INT_COALESCING);
1687 IWL_CMD(CSR_INT);
1688 IWL_CMD(CSR_INT_MASK);
1689 IWL_CMD(CSR_FH_INT_STATUS);
1690 IWL_CMD(CSR_GPIO_IN);
1691 IWL_CMD(CSR_RESET);
1692 IWL_CMD(CSR_GP_CNTRL);
1693 IWL_CMD(CSR_HW_REV);
1694 IWL_CMD(CSR_EEPROM_REG);
1695 IWL_CMD(CSR_EEPROM_GP);
1696 IWL_CMD(CSR_OTP_GP_REG);
1697 IWL_CMD(CSR_GIO_REG);
1698 IWL_CMD(CSR_GP_UCODE_REG);
1699 IWL_CMD(CSR_GP_DRIVER_REG);
1700 IWL_CMD(CSR_UCODE_DRV_GP1);
1701 IWL_CMD(CSR_UCODE_DRV_GP2);
1702 IWL_CMD(CSR_LED_REG);
1703 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1704 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1705 IWL_CMD(CSR_ANA_PLL_CFG);
1706 IWL_CMD(CSR_HW_REV_WA_REG);
1707 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1708 default:
1709 return "UNKNOWN";
1710 }
1711 #undef IWL_CMD
1712 }
1713
1714 void iwl_dump_csr(struct iwl_trans *trans)
1715 {
1716 int i;
1717 static const u32 csr_tbl[] = {
1718 CSR_HW_IF_CONFIG_REG,
1719 CSR_INT_COALESCING,
1720 CSR_INT,
1721 CSR_INT_MASK,
1722 CSR_FH_INT_STATUS,
1723 CSR_GPIO_IN,
1724 CSR_RESET,
1725 CSR_GP_CNTRL,
1726 CSR_HW_REV,
1727 CSR_EEPROM_REG,
1728 CSR_EEPROM_GP,
1729 CSR_OTP_GP_REG,
1730 CSR_GIO_REG,
1731 CSR_GP_UCODE_REG,
1732 CSR_GP_DRIVER_REG,
1733 CSR_UCODE_DRV_GP1,
1734 CSR_UCODE_DRV_GP2,
1735 CSR_LED_REG,
1736 CSR_DRAM_INT_TBL_REG,
1737 CSR_GIO_CHICKEN_BITS,
1738 CSR_ANA_PLL_CFG,
1739 CSR_HW_REV_WA_REG,
1740 CSR_DBG_HPET_MEM_REG
1741 };
1742 IWL_ERR(trans, "CSR values:\n");
1743 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1744 "CSR_INT_PERIODIC_REG)\n");
1745 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1746 IWL_ERR(trans, " %25s: 0X%08x\n",
1747 get_csr_string(csr_tbl[i]),
1748 iwl_read32(trans, csr_tbl[i]));
1749 }
1750 }
1751
1752 #ifdef CONFIG_IWLWIFI_DEBUGFS
1753 /* create and remove of files */
1754 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1755 if (!debugfs_create_file(#name, mode, parent, trans, \
1756 &iwl_dbgfs_##name##_ops)) \
1757 return -ENOMEM; \
1758 } while (0)
1759
1760 /* file operation */
1761 #define DEBUGFS_READ_FUNC(name) \
1762 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1763 char __user *user_buf, \
1764 size_t count, loff_t *ppos);
1765
1766 #define DEBUGFS_WRITE_FUNC(name) \
1767 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1768 const char __user *user_buf, \
1769 size_t count, loff_t *ppos);
1770
1771
1772 #define DEBUGFS_READ_FILE_OPS(name) \
1773 DEBUGFS_READ_FUNC(name); \
1774 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1775 .read = iwl_dbgfs_##name##_read, \
1776 .open = simple_open, \
1777 .llseek = generic_file_llseek, \
1778 };
1779
1780 #define DEBUGFS_WRITE_FILE_OPS(name) \
1781 DEBUGFS_WRITE_FUNC(name); \
1782 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1783 .write = iwl_dbgfs_##name##_write, \
1784 .open = simple_open, \
1785 .llseek = generic_file_llseek, \
1786 };
1787
1788 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1789 DEBUGFS_READ_FUNC(name); \
1790 DEBUGFS_WRITE_FUNC(name); \
1791 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1792 .write = iwl_dbgfs_##name##_write, \
1793 .read = iwl_dbgfs_##name##_read, \
1794 .open = simple_open, \
1795 .llseek = generic_file_llseek, \
1796 };
1797
1798 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1799 char __user *user_buf,
1800 size_t count, loff_t *ppos)
1801 {
1802 struct iwl_trans *trans = file->private_data;
1803 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1804 struct iwl_tx_queue *txq;
1805 struct iwl_queue *q;
1806 char *buf;
1807 int pos = 0;
1808 int cnt;
1809 int ret;
1810 size_t bufsz;
1811
1812 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1813
1814 if (!trans_pcie->txq)
1815 return -EAGAIN;
1816
1817 buf = kzalloc(bufsz, GFP_KERNEL);
1818 if (!buf)
1819 return -ENOMEM;
1820
1821 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1822 txq = &trans_pcie->txq[cnt];
1823 q = &txq->q;
1824 pos += scnprintf(buf + pos, bufsz - pos,
1825 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1826 cnt, q->read_ptr, q->write_ptr,
1827 !!test_bit(cnt, trans_pcie->queue_used),
1828 !!test_bit(cnt, trans_pcie->queue_stopped));
1829 }
1830 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1831 kfree(buf);
1832 return ret;
1833 }
1834
1835 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1836 char __user *user_buf,
1837 size_t count, loff_t *ppos)
1838 {
1839 struct iwl_trans *trans = file->private_data;
1840 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1841 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1842 char buf[256];
1843 int pos = 0;
1844 const size_t bufsz = sizeof(buf);
1845
1846 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1847 rxq->read);
1848 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1849 rxq->write);
1850 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1851 rxq->free_count);
1852 if (rxq->rb_stts) {
1853 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1854 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1855 } else {
1856 pos += scnprintf(buf + pos, bufsz - pos,
1857 "closed_rb_num: Not Allocated\n");
1858 }
1859 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1860 }
1861
1862 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1863 char __user *user_buf,
1864 size_t count, loff_t *ppos)
1865 {
1866 struct iwl_trans *trans = file->private_data;
1867 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1868 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1869
1870 int pos = 0;
1871 char *buf;
1872 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1873 ssize_t ret;
1874
1875 buf = kzalloc(bufsz, GFP_KERNEL);
1876 if (!buf)
1877 return -ENOMEM;
1878
1879 pos += scnprintf(buf + pos, bufsz - pos,
1880 "Interrupt Statistics Report:\n");
1881
1882 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1883 isr_stats->hw);
1884 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1885 isr_stats->sw);
1886 if (isr_stats->sw || isr_stats->hw) {
1887 pos += scnprintf(buf + pos, bufsz - pos,
1888 "\tLast Restarting Code: 0x%X\n",
1889 isr_stats->err_code);
1890 }
1891 #ifdef CONFIG_IWLWIFI_DEBUG
1892 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1893 isr_stats->sch);
1894 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1895 isr_stats->alive);
1896 #endif
1897 pos += scnprintf(buf + pos, bufsz - pos,
1898 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1899
1900 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1901 isr_stats->ctkill);
1902
1903 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1904 isr_stats->wakeup);
1905
1906 pos += scnprintf(buf + pos, bufsz - pos,
1907 "Rx command responses:\t\t %u\n", isr_stats->rx);
1908
1909 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1910 isr_stats->tx);
1911
1912 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1913 isr_stats->unhandled);
1914
1915 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1916 kfree(buf);
1917 return ret;
1918 }
1919
1920 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1921 const char __user *user_buf,
1922 size_t count, loff_t *ppos)
1923 {
1924 struct iwl_trans *trans = file->private_data;
1925 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1926 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1927
1928 char buf[8];
1929 int buf_size;
1930 u32 reset_flag;
1931
1932 memset(buf, 0, sizeof(buf));
1933 buf_size = min(count, sizeof(buf) - 1);
1934 if (copy_from_user(buf, user_buf, buf_size))
1935 return -EFAULT;
1936 if (sscanf(buf, "%x", &reset_flag) != 1)
1937 return -EFAULT;
1938 if (reset_flag == 0)
1939 memset(isr_stats, 0, sizeof(*isr_stats));
1940
1941 return count;
1942 }
1943
1944 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1945 const char __user *user_buf,
1946 size_t count, loff_t *ppos)
1947 {
1948 struct iwl_trans *trans = file->private_data;
1949 char buf[8];
1950 int buf_size;
1951 int csr;
1952
1953 memset(buf, 0, sizeof(buf));
1954 buf_size = min(count, sizeof(buf) - 1);
1955 if (copy_from_user(buf, user_buf, buf_size))
1956 return -EFAULT;
1957 if (sscanf(buf, "%d", &csr) != 1)
1958 return -EFAULT;
1959
1960 iwl_dump_csr(trans);
1961
1962 return count;
1963 }
1964
1965 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1966 char __user *user_buf,
1967 size_t count, loff_t *ppos)
1968 {
1969 struct iwl_trans *trans = file->private_data;
1970 char *buf;
1971 int pos = 0;
1972 ssize_t ret = -EFAULT;
1973
1974 ret = pos = iwl_dump_fh(trans, &buf, true);
1975 if (buf) {
1976 ret = simple_read_from_buffer(user_buf,
1977 count, ppos, buf, pos);
1978 kfree(buf);
1979 }
1980
1981 return ret;
1982 }
1983
1984 static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
1985 const char __user *user_buf,
1986 size_t count, loff_t *ppos)
1987 {
1988 struct iwl_trans *trans = file->private_data;
1989
1990 if (!trans->op_mode)
1991 return -EAGAIN;
1992
1993 iwl_op_mode_nic_error(trans->op_mode);
1994
1995 return count;
1996 }
1997
1998 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1999 DEBUGFS_READ_FILE_OPS(fh_reg);
2000 DEBUGFS_READ_FILE_OPS(rx_queue);
2001 DEBUGFS_READ_FILE_OPS(tx_queue);
2002 DEBUGFS_WRITE_FILE_OPS(csr);
2003 DEBUGFS_WRITE_FILE_OPS(fw_restart);
2004
2005 /*
2006 * Create the debugfs files and directories
2007 *
2008 */
2009 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2010 struct dentry *dir)
2011 {
2012 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2013 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2014 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2015 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2016 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2017 DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR);
2018 return 0;
2019 }
2020 #else
2021 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2022 struct dentry *dir)
2023 {
2024 return 0;
2025 }
2026 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2027
2028 static const struct iwl_trans_ops trans_ops_pcie = {
2029 .start_hw = iwl_trans_pcie_start_hw,
2030 .stop_hw = iwl_trans_pcie_stop_hw,
2031 .fw_alive = iwl_trans_pcie_fw_alive,
2032 .start_fw = iwl_trans_pcie_start_fw,
2033 .stop_device = iwl_trans_pcie_stop_device,
2034
2035 .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2036
2037 .send_cmd = iwl_trans_pcie_send_cmd,
2038
2039 .tx = iwl_trans_pcie_tx,
2040 .reclaim = iwl_trans_pcie_reclaim,
2041
2042 .txq_disable = iwl_trans_pcie_txq_disable,
2043 .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
2044
2045 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2046
2047 .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2048
2049 #ifdef CONFIG_PM_SLEEP
2050 .suspend = iwl_trans_pcie_suspend,
2051 .resume = iwl_trans_pcie_resume,
2052 #endif
2053 .write8 = iwl_trans_pcie_write8,
2054 .write32 = iwl_trans_pcie_write32,
2055 .read32 = iwl_trans_pcie_read32,
2056 .configure = iwl_trans_pcie_configure,
2057 .set_pmi = iwl_trans_pcie_set_pmi,
2058 };
2059
2060 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2061 const struct pci_device_id *ent,
2062 const struct iwl_cfg *cfg)
2063 {
2064 struct iwl_trans_pcie *trans_pcie;
2065 struct iwl_trans *trans;
2066 u16 pci_cmd;
2067 int err;
2068
2069 trans = kzalloc(sizeof(struct iwl_trans) +
2070 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2071
2072 if (WARN_ON(!trans))
2073 return NULL;
2074
2075 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2076
2077 trans->ops = &trans_ops_pcie;
2078 trans->cfg = cfg;
2079 trans_pcie->trans = trans;
2080 spin_lock_init(&trans_pcie->irq_lock);
2081 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2082
2083 /* W/A - seems to solve weird behavior. We need to remove this if we
2084 * don't want to stay in L1 all the time. This wastes a lot of power */
2085 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2086 PCIE_LINK_STATE_CLKPM);
2087
2088 if (pci_enable_device(pdev)) {
2089 err = -ENODEV;
2090 goto out_no_pci;
2091 }
2092
2093 pci_set_master(pdev);
2094
2095 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2096 if (!err)
2097 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2098 if (err) {
2099 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2100 if (!err)
2101 err = pci_set_consistent_dma_mask(pdev,
2102 DMA_BIT_MASK(32));
2103 /* both attempts failed: */
2104 if (err) {
2105 dev_printk(KERN_ERR, &pdev->dev,
2106 "No suitable DMA available.\n");
2107 goto out_pci_disable_device;
2108 }
2109 }
2110
2111 err = pci_request_regions(pdev, DRV_NAME);
2112 if (err) {
2113 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2114 goto out_pci_disable_device;
2115 }
2116
2117 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2118 if (!trans_pcie->hw_base) {
2119 dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed");
2120 err = -ENODEV;
2121 goto out_pci_release_regions;
2122 }
2123
2124 dev_printk(KERN_INFO, &pdev->dev,
2125 "pci_resource_len = 0x%08llx\n",
2126 (unsigned long long) pci_resource_len(pdev, 0));
2127 dev_printk(KERN_INFO, &pdev->dev,
2128 "pci_resource_base = %p\n", trans_pcie->hw_base);
2129
2130 dev_printk(KERN_INFO, &pdev->dev,
2131 "HW Revision ID = 0x%X\n", pdev->revision);
2132
2133 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2134 * PCI Tx retries from interfering with C3 CPU state */
2135 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2136
2137 err = pci_enable_msi(pdev);
2138 if (err)
2139 dev_printk(KERN_ERR, &pdev->dev,
2140 "pci_enable_msi failed(0X%x)", err);
2141
2142 trans->dev = &pdev->dev;
2143 trans_pcie->irq = pdev->irq;
2144 trans_pcie->pci_dev = pdev;
2145 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2146 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2147 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2148 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2149
2150 /* TODO: Move this away, not needed if not MSI */
2151 /* enable rfkill interrupt: hw bug w/a */
2152 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2153 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2154 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2155 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2156 }
2157
2158 /* Initialize the wait queue for commands */
2159 init_waitqueue_head(&trans->wait_command_queue);
2160 spin_lock_init(&trans->reg_lock);
2161
2162 return trans;
2163
2164 out_pci_release_regions:
2165 pci_release_regions(pdev);
2166 out_pci_disable_device:
2167 pci_disable_device(pdev);
2168 out_no_pci:
2169 kfree(trans);
2170 return NULL;
2171 }
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