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Merge tag 'media/v3.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab...
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / iwlwifi / pcie / trans.c
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
26 * in the file called COPYING.
27 *
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
34 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
35 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 *****************************************************************************/
65 #include <linux/pci.h>
66 #include <linux/pci-aspm.h>
67 #include <linux/interrupt.h>
68 #include <linux/debugfs.h>
69 #include <linux/sched.h>
70 #include <linux/bitops.h>
71 #include <linux/gfp.h>
72 #include <linux/vmalloc.h>
73
74 #include "iwl-drv.h"
75 #include "iwl-trans.h"
76 #include "iwl-csr.h"
77 #include "iwl-prph.h"
78 #include "iwl-scd.h"
79 #include "iwl-agn-hw.h"
80 #include "iwl-fw-error-dump.h"
81 #include "internal.h"
82 #include "iwl-fh.h"
83
84 /* extended range in FW SRAM */
85 #define IWL_FW_MEM_EXTENDED_START 0x40000
86 #define IWL_FW_MEM_EXTENDED_END 0x57FFF
87
88 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
89 {
90 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
91
92 if (!trans_pcie->fw_mon_page)
93 return;
94
95 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
96 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
97 __free_pages(trans_pcie->fw_mon_page,
98 get_order(trans_pcie->fw_mon_size));
99 trans_pcie->fw_mon_page = NULL;
100 trans_pcie->fw_mon_phys = 0;
101 trans_pcie->fw_mon_size = 0;
102 }
103
104 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans)
105 {
106 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
107 struct page *page;
108 dma_addr_t phys;
109 u32 size;
110 u8 power;
111
112 if (trans_pcie->fw_mon_page) {
113 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
114 trans_pcie->fw_mon_size,
115 DMA_FROM_DEVICE);
116 return;
117 }
118
119 phys = 0;
120 for (power = 26; power >= 11; power--) {
121 int order;
122
123 size = BIT(power);
124 order = get_order(size);
125 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
126 order);
127 if (!page)
128 continue;
129
130 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
131 DMA_FROM_DEVICE);
132 if (dma_mapping_error(trans->dev, phys)) {
133 __free_pages(page, order);
134 continue;
135 }
136 IWL_INFO(trans,
137 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
138 size, order);
139 break;
140 }
141
142 if (WARN_ON_ONCE(!page))
143 return;
144
145 trans_pcie->fw_mon_page = page;
146 trans_pcie->fw_mon_phys = phys;
147 trans_pcie->fw_mon_size = size;
148 }
149
150 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
151 {
152 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
153 ((reg & 0x0000ffff) | (2 << 28)));
154 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
155 }
156
157 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
158 {
159 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
160 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
161 ((reg & 0x0000ffff) | (3 << 28)));
162 }
163
164 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
165 {
166 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
167 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
168 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
169 ~APMG_PS_CTRL_MSK_PWR_SRC);
170 else
171 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
172 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
173 ~APMG_PS_CTRL_MSK_PWR_SRC);
174 }
175
176 /* PCI registers */
177 #define PCI_CFG_RETRY_TIMEOUT 0x041
178
179 static void iwl_pcie_apm_config(struct iwl_trans *trans)
180 {
181 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
182 u16 lctl;
183 u16 cap;
184
185 /*
186 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
187 * Check if BIOS (or OS) enabled L1-ASPM on this device.
188 * If so (likely), disable L0S, so device moves directly L0->L1;
189 * costs negligible amount of power savings.
190 * If not (unlikely), enable L0S, so there is at least some
191 * power savings, even without L1.
192 */
193 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
194 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
195 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
196 else
197 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
198 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
199
200 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
201 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
202 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
203 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
204 trans->ltr_enabled ? "En" : "Dis");
205 }
206
207 /*
208 * Start up NIC's basic functionality after it has been reset
209 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
210 * NOTE: This does not load uCode nor start the embedded processor
211 */
212 static int iwl_pcie_apm_init(struct iwl_trans *trans)
213 {
214 int ret = 0;
215 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
216
217 /*
218 * Use "set_bit" below rather than "write", to preserve any hardware
219 * bits already set by default after reset.
220 */
221
222 /* Disable L0S exit timer (platform NMI Work/Around) */
223 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
224 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
225 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
226
227 /*
228 * Disable L0s without affecting L1;
229 * don't wait for ICH L0s (ICH bug W/A)
230 */
231 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
232 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
233
234 /* Set FH wait threshold to maximum (HW error during stress W/A) */
235 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
236
237 /*
238 * Enable HAP INTA (interrupt from management bus) to
239 * wake device's PCI Express link L1a -> L0s
240 */
241 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
242 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
243
244 iwl_pcie_apm_config(trans);
245
246 /* Configure analog phase-lock-loop before activating to D0A */
247 if (trans->cfg->base_params->pll_cfg_val)
248 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
249 trans->cfg->base_params->pll_cfg_val);
250
251 /*
252 * Set "initialization complete" bit to move adapter from
253 * D0U* --> D0A* (powered-up active) state.
254 */
255 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
256
257 /*
258 * Wait for clock stabilization; once stabilized, access to
259 * device-internal resources is supported, e.g. iwl_write_prph()
260 * and accesses to uCode SRAM.
261 */
262 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
263 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
264 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
265 if (ret < 0) {
266 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
267 goto out;
268 }
269
270 if (trans->cfg->host_interrupt_operation_mode) {
271 /*
272 * This is a bit of an abuse - This is needed for 7260 / 3160
273 * only check host_interrupt_operation_mode even if this is
274 * not related to host_interrupt_operation_mode.
275 *
276 * Enable the oscillator to count wake up time for L1 exit. This
277 * consumes slightly more power (100uA) - but allows to be sure
278 * that we wake up from L1 on time.
279 *
280 * This looks weird: read twice the same register, discard the
281 * value, set a bit, and yet again, read that same register
282 * just to discard the value. But that's the way the hardware
283 * seems to like it.
284 */
285 iwl_read_prph(trans, OSC_CLK);
286 iwl_read_prph(trans, OSC_CLK);
287 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
288 iwl_read_prph(trans, OSC_CLK);
289 iwl_read_prph(trans, OSC_CLK);
290 }
291
292 /*
293 * Enable DMA clock and wait for it to stabilize.
294 *
295 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
296 * bits do not disable clocks. This preserves any hardware
297 * bits already set by default in "CLK_CTRL_REG" after reset.
298 */
299 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
300 iwl_write_prph(trans, APMG_CLK_EN_REG,
301 APMG_CLK_VAL_DMA_CLK_RQT);
302 udelay(20);
303
304 /* Disable L1-Active */
305 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
306 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
307
308 /* Clear the interrupt in APMG if the NIC is in RFKILL */
309 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
310 APMG_RTC_INT_STT_RFKILL);
311 }
312
313 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
314
315 out:
316 return ret;
317 }
318
319 /*
320 * Enable LP XTAL to avoid HW bug where device may consume much power if
321 * FW is not loaded after device reset. LP XTAL is disabled by default
322 * after device HW reset. Do it only if XTAL is fed by internal source.
323 * Configure device's "persistence" mode to avoid resetting XTAL again when
324 * SHRD_HW_RST occurs in S3.
325 */
326 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
327 {
328 int ret;
329 u32 apmg_gp1_reg;
330 u32 apmg_xtal_cfg_reg;
331 u32 dl_cfg_reg;
332
333 /* Force XTAL ON */
334 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
335 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
336
337 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
338 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
339
340 udelay(10);
341
342 /*
343 * Set "initialization complete" bit to move adapter from
344 * D0U* --> D0A* (powered-up active) state.
345 */
346 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
347
348 /*
349 * Wait for clock stabilization; once stabilized, access to
350 * device-internal resources is possible.
351 */
352 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
353 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
354 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
355 25000);
356 if (WARN_ON(ret < 0)) {
357 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
358 /* Release XTAL ON request */
359 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
360 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
361 return;
362 }
363
364 /*
365 * Clear "disable persistence" to avoid LP XTAL resetting when
366 * SHRD_HW_RST is applied in S3.
367 */
368 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
369 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
370
371 /*
372 * Force APMG XTAL to be active to prevent its disabling by HW
373 * caused by APMG idle state.
374 */
375 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
376 SHR_APMG_XTAL_CFG_REG);
377 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
378 apmg_xtal_cfg_reg |
379 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
380
381 /*
382 * Reset entire device again - do controller reset (results in
383 * SHRD_HW_RST). Turn MAC off before proceeding.
384 */
385 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
386
387 udelay(10);
388
389 /* Enable LP XTAL by indirect access through CSR */
390 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
391 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
392 SHR_APMG_GP1_WF_XTAL_LP_EN |
393 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
394
395 /* Clear delay line clock power up */
396 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
397 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
398 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
399
400 /*
401 * Enable persistence mode to avoid LP XTAL resetting when
402 * SHRD_HW_RST is applied in S3.
403 */
404 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
405 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
406
407 /*
408 * Clear "initialization complete" bit to move adapter from
409 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
410 */
411 iwl_clear_bit(trans, CSR_GP_CNTRL,
412 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
413
414 /* Activates XTAL resources monitor */
415 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
416 CSR_MONITOR_XTAL_RESOURCES);
417
418 /* Release XTAL ON request */
419 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
420 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
421 udelay(10);
422
423 /* Release APMG XTAL */
424 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
425 apmg_xtal_cfg_reg &
426 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
427 }
428
429 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
430 {
431 int ret = 0;
432
433 /* stop device's busmaster DMA activity */
434 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
435
436 ret = iwl_poll_bit(trans, CSR_RESET,
437 CSR_RESET_REG_FLAG_MASTER_DISABLED,
438 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
439 if (ret < 0)
440 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
441
442 IWL_DEBUG_INFO(trans, "stop master\n");
443
444 return ret;
445 }
446
447 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
448 {
449 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
450
451 if (op_mode_leave) {
452 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
453 iwl_pcie_apm_init(trans);
454
455 /* inform ME that we are leaving */
456 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
457 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
458 APMG_PCIDEV_STT_VAL_WAKE_ME);
459 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
460 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
461 CSR_HW_IF_CONFIG_REG_PREPARE |
462 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
463 mdelay(5);
464 }
465
466 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
467
468 /* Stop device's DMA activity */
469 iwl_pcie_apm_stop_master(trans);
470
471 if (trans->cfg->lp_xtal_workaround) {
472 iwl_pcie_apm_lp_xtal_enable(trans);
473 return;
474 }
475
476 /* Reset the entire device */
477 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
478
479 udelay(10);
480
481 /*
482 * Clear "initialization complete" bit to move adapter from
483 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
484 */
485 iwl_clear_bit(trans, CSR_GP_CNTRL,
486 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
487 }
488
489 static int iwl_pcie_nic_init(struct iwl_trans *trans)
490 {
491 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
492
493 /* nic_init */
494 spin_lock(&trans_pcie->irq_lock);
495 iwl_pcie_apm_init(trans);
496
497 spin_unlock(&trans_pcie->irq_lock);
498
499 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
500 iwl_pcie_set_pwr(trans, false);
501
502 iwl_op_mode_nic_config(trans->op_mode);
503
504 /* Allocate the RX queue, or reset if it is already allocated */
505 iwl_pcie_rx_init(trans);
506
507 /* Allocate or reset and init all Tx and Command queues */
508 if (iwl_pcie_tx_init(trans))
509 return -ENOMEM;
510
511 if (trans->cfg->base_params->shadow_reg_enable) {
512 /* enable shadow regs in HW */
513 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
514 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
515 }
516
517 return 0;
518 }
519
520 #define HW_READY_TIMEOUT (50)
521
522 /* Note: returns poll_bit return value, which is >= 0 if success */
523 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
524 {
525 int ret;
526
527 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
528 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
529
530 /* See if we got it */
531 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
532 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
533 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
534 HW_READY_TIMEOUT);
535
536 if (ret >= 0)
537 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
538
539 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
540 return ret;
541 }
542
543 /* Note: returns standard 0/-ERROR code */
544 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
545 {
546 int ret;
547 int t = 0;
548 int iter;
549
550 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
551
552 ret = iwl_pcie_set_hw_ready(trans);
553 /* If the card is ready, exit 0 */
554 if (ret >= 0)
555 return 0;
556
557 for (iter = 0; iter < 10; iter++) {
558 /* If HW is not ready, prepare the conditions to check again */
559 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
560 CSR_HW_IF_CONFIG_REG_PREPARE);
561
562 do {
563 ret = iwl_pcie_set_hw_ready(trans);
564 if (ret >= 0)
565 return 0;
566
567 usleep_range(200, 1000);
568 t += 200;
569 } while (t < 150000);
570 msleep(25);
571 }
572
573 IWL_ERR(trans, "Couldn't prepare the card\n");
574
575 return ret;
576 }
577
578 /*
579 * ucode
580 */
581 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
582 dma_addr_t phy_addr, u32 byte_cnt)
583 {
584 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
585 int ret;
586
587 trans_pcie->ucode_write_complete = false;
588
589 iwl_write_direct32(trans,
590 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
591 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
592
593 iwl_write_direct32(trans,
594 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
595 dst_addr);
596
597 iwl_write_direct32(trans,
598 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
599 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
600
601 iwl_write_direct32(trans,
602 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
603 (iwl_get_dma_hi_addr(phy_addr)
604 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
605
606 iwl_write_direct32(trans,
607 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
608 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
609 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
610 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
611
612 iwl_write_direct32(trans,
613 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
614 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
615 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
616 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
617
618 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
619 trans_pcie->ucode_write_complete, 5 * HZ);
620 if (!ret) {
621 IWL_ERR(trans, "Failed to load firmware chunk!\n");
622 return -ETIMEDOUT;
623 }
624
625 return 0;
626 }
627
628 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
629 const struct fw_desc *section)
630 {
631 u8 *v_addr;
632 dma_addr_t p_addr;
633 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
634 int ret = 0;
635
636 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
637 section_num);
638
639 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
640 GFP_KERNEL | __GFP_NOWARN);
641 if (!v_addr) {
642 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
643 chunk_sz = PAGE_SIZE;
644 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
645 &p_addr, GFP_KERNEL);
646 if (!v_addr)
647 return -ENOMEM;
648 }
649
650 for (offset = 0; offset < section->len; offset += chunk_sz) {
651 u32 copy_size, dst_addr;
652 bool extended_addr = false;
653
654 copy_size = min_t(u32, chunk_sz, section->len - offset);
655 dst_addr = section->offset + offset;
656
657 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
658 dst_addr <= IWL_FW_MEM_EXTENDED_END)
659 extended_addr = true;
660
661 if (extended_addr)
662 iwl_set_bits_prph(trans, LMPM_CHICK,
663 LMPM_CHICK_EXTENDED_ADDR_SPACE);
664
665 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
666 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
667 copy_size);
668
669 if (extended_addr)
670 iwl_clear_bits_prph(trans, LMPM_CHICK,
671 LMPM_CHICK_EXTENDED_ADDR_SPACE);
672
673 if (ret) {
674 IWL_ERR(trans,
675 "Could not load the [%d] uCode section\n",
676 section_num);
677 break;
678 }
679 }
680
681 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
682 return ret;
683 }
684
685 static int iwl_pcie_load_cpu_sections_8000b(struct iwl_trans *trans,
686 const struct fw_img *image,
687 int cpu,
688 int *first_ucode_section)
689 {
690 int shift_param;
691 int i, ret = 0, sec_num = 0x1;
692 u32 val, last_read_idx = 0;
693
694 if (cpu == 1) {
695 shift_param = 0;
696 *first_ucode_section = 0;
697 } else {
698 shift_param = 16;
699 (*first_ucode_section)++;
700 }
701
702 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
703 last_read_idx = i;
704
705 if (!image->sec[i].data ||
706 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
707 IWL_DEBUG_FW(trans,
708 "Break since Data not valid or Empty section, sec = %d\n",
709 i);
710 break;
711 }
712
713 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
714 if (ret)
715 return ret;
716
717 /* Notify the ucode of the loaded section number and status */
718 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
719 val = val | (sec_num << shift_param);
720 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
721 sec_num = (sec_num << 1) | 0x1;
722 }
723
724 *first_ucode_section = last_read_idx;
725
726 if (cpu == 1)
727 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
728 else
729 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
730
731 return 0;
732 }
733
734 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
735 const struct fw_img *image,
736 int cpu,
737 int *first_ucode_section)
738 {
739 int shift_param;
740 int i, ret = 0;
741 u32 last_read_idx = 0;
742
743 if (cpu == 1) {
744 shift_param = 0;
745 *first_ucode_section = 0;
746 } else {
747 shift_param = 16;
748 (*first_ucode_section)++;
749 }
750
751 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
752 last_read_idx = i;
753
754 if (!image->sec[i].data ||
755 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
756 IWL_DEBUG_FW(trans,
757 "Break since Data not valid or Empty section, sec = %d\n",
758 i);
759 break;
760 }
761
762 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
763 if (ret)
764 return ret;
765 }
766
767 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
768 iwl_set_bits_prph(trans,
769 CSR_UCODE_LOAD_STATUS_ADDR,
770 (LMPM_CPU_UCODE_LOADING_COMPLETED |
771 LMPM_CPU_HDRS_LOADING_COMPLETED |
772 LMPM_CPU_UCODE_LOADING_STARTED) <<
773 shift_param);
774
775 *first_ucode_section = last_read_idx;
776
777 return 0;
778 }
779
780 static void iwl_pcie_apply_destination(struct iwl_trans *trans)
781 {
782 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
783 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
784 int i;
785
786 if (dest->version)
787 IWL_ERR(trans,
788 "DBG DEST version is %d - expect issues\n",
789 dest->version);
790
791 IWL_INFO(trans, "Applying debug destination %s\n",
792 get_fw_dbg_mode_string(dest->monitor_mode));
793
794 if (dest->monitor_mode == EXTERNAL_MODE)
795 iwl_pcie_alloc_fw_monitor(trans);
796 else
797 IWL_WARN(trans, "PCI should have external buffer debug\n");
798
799 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
800 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
801 u32 val = le32_to_cpu(dest->reg_ops[i].val);
802
803 switch (dest->reg_ops[i].op) {
804 case CSR_ASSIGN:
805 iwl_write32(trans, addr, val);
806 break;
807 case CSR_SETBIT:
808 iwl_set_bit(trans, addr, BIT(val));
809 break;
810 case CSR_CLEARBIT:
811 iwl_clear_bit(trans, addr, BIT(val));
812 break;
813 case PRPH_ASSIGN:
814 iwl_write_prph(trans, addr, val);
815 break;
816 case PRPH_SETBIT:
817 iwl_set_bits_prph(trans, addr, BIT(val));
818 break;
819 case PRPH_CLEARBIT:
820 iwl_clear_bits_prph(trans, addr, BIT(val));
821 break;
822 default:
823 IWL_ERR(trans, "FW debug - unknown OP %d\n",
824 dest->reg_ops[i].op);
825 break;
826 }
827 }
828
829 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
830 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
831 trans_pcie->fw_mon_phys >> dest->base_shift);
832 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
833 (trans_pcie->fw_mon_phys +
834 trans_pcie->fw_mon_size) >> dest->end_shift);
835 }
836 }
837
838 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
839 const struct fw_img *image)
840 {
841 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
842 int ret = 0;
843 int first_ucode_section;
844
845 IWL_DEBUG_FW(trans, "working with %s CPU\n",
846 image->is_dual_cpus ? "Dual" : "Single");
847
848 /* load to FW the binary non secured sections of CPU1 */
849 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
850 if (ret)
851 return ret;
852
853 if (image->is_dual_cpus) {
854 /* set CPU2 header address */
855 iwl_write_prph(trans,
856 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
857 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
858
859 /* load to FW the binary sections of CPU2 */
860 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
861 &first_ucode_section);
862 if (ret)
863 return ret;
864 }
865
866 /* supported for 7000 only for the moment */
867 if (iwlwifi_mod_params.fw_monitor &&
868 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
869 iwl_pcie_alloc_fw_monitor(trans);
870
871 if (trans_pcie->fw_mon_size) {
872 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
873 trans_pcie->fw_mon_phys >> 4);
874 iwl_write_prph(trans, MON_BUFF_END_ADDR,
875 (trans_pcie->fw_mon_phys +
876 trans_pcie->fw_mon_size) >> 4);
877 }
878 } else if (trans->dbg_dest_tlv) {
879 iwl_pcie_apply_destination(trans);
880 }
881
882 /* release CPU reset */
883 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
884 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
885 else
886 iwl_write32(trans, CSR_RESET, 0);
887
888 return 0;
889 }
890
891 static int iwl_pcie_load_given_ucode_8000b(struct iwl_trans *trans,
892 const struct fw_img *image)
893 {
894 int ret = 0;
895 int first_ucode_section;
896 u32 reg;
897
898 IWL_DEBUG_FW(trans, "working with %s CPU\n",
899 image->is_dual_cpus ? "Dual" : "Single");
900
901 /* configure the ucode to be ready to get the secured image */
902 /* release CPU reset */
903 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
904
905 /* load to FW the binary Secured sections of CPU1 */
906 ret = iwl_pcie_load_cpu_sections_8000b(trans, image, 1,
907 &first_ucode_section);
908 if (ret)
909 return ret;
910
911 /* load to FW the binary sections of CPU2 */
912 ret = iwl_pcie_load_cpu_sections_8000b(trans, image, 2,
913 &first_ucode_section);
914 if (ret)
915 return ret;
916
917 if (trans->dbg_dest_tlv)
918 iwl_pcie_apply_destination(trans);
919
920 /* wait for image verification to complete */
921 ret = iwl_poll_prph_bit(trans, LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0,
922 LMPM_SECURE_BOOT_STATUS_SUCCESS,
923 LMPM_SECURE_BOOT_STATUS_SUCCESS,
924 LMPM_SECURE_TIME_OUT);
925 if (ret < 0) {
926 reg = iwl_read_prph(trans,
927 LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0);
928
929 IWL_ERR(trans, "Timeout on secure boot process, reg = %x\n",
930 reg);
931 return ret;
932 }
933
934 return 0;
935 }
936
937 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
938 const struct fw_img *fw, bool run_in_rfkill)
939 {
940 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
941 int ret;
942 bool hw_rfkill;
943
944 /* This may fail if AMT took ownership of the device */
945 if (iwl_pcie_prepare_card_hw(trans)) {
946 IWL_WARN(trans, "Exit HW not ready\n");
947 return -EIO;
948 }
949
950 iwl_enable_rfkill_int(trans);
951
952 /* If platform's RF_KILL switch is NOT set to KILL */
953 hw_rfkill = iwl_is_rfkill_set(trans);
954 if (hw_rfkill)
955 set_bit(STATUS_RFKILL, &trans->status);
956 else
957 clear_bit(STATUS_RFKILL, &trans->status);
958 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
959 if (hw_rfkill && !run_in_rfkill)
960 return -ERFKILL;
961
962 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
963
964 ret = iwl_pcie_nic_init(trans);
965 if (ret) {
966 IWL_ERR(trans, "Unable to init nic\n");
967 return ret;
968 }
969
970 /* init ref_count to 1 (should be cleared when ucode is loaded) */
971 trans_pcie->ref_count = 1;
972
973 /* make sure rfkill handshake bits are cleared */
974 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
975 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
976 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
977
978 /* clear (again), then enable host interrupts */
979 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
980 iwl_enable_interrupts(trans);
981
982 /* really make sure rfkill handshake bits are cleared */
983 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
984 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
985
986 /* Load the given image to the HW */
987 if ((trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) &&
988 (CSR_HW_REV_STEP(trans->hw_rev) != SILICON_A_STEP))
989 return iwl_pcie_load_given_ucode_8000b(trans, fw);
990 else
991 return iwl_pcie_load_given_ucode(trans, fw);
992 }
993
994 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
995 {
996 iwl_pcie_reset_ict(trans);
997 iwl_pcie_tx_start(trans, scd_addr);
998 }
999
1000 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1001 {
1002 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1003 bool hw_rfkill, was_hw_rfkill;
1004
1005 was_hw_rfkill = iwl_is_rfkill_set(trans);
1006
1007 /* tell the device to stop sending interrupts */
1008 spin_lock(&trans_pcie->irq_lock);
1009 iwl_disable_interrupts(trans);
1010 spin_unlock(&trans_pcie->irq_lock);
1011
1012 /* device going down, Stop using ICT table */
1013 iwl_pcie_disable_ict(trans);
1014
1015 /*
1016 * If a HW restart happens during firmware loading,
1017 * then the firmware loading might call this function
1018 * and later it might be called again due to the
1019 * restart. So don't process again if the device is
1020 * already dead.
1021 */
1022 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1023 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
1024 iwl_pcie_tx_stop(trans);
1025 iwl_pcie_rx_stop(trans);
1026
1027 /* Power-down device's busmaster DMA clocks */
1028 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1029 APMG_CLK_VAL_DMA_CLK_RQT);
1030 udelay(5);
1031 }
1032
1033 /* Make sure (redundant) we've released our request to stay awake */
1034 iwl_clear_bit(trans, CSR_GP_CNTRL,
1035 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1036
1037 /* Stop the device, and put it in low power state */
1038 iwl_pcie_apm_stop(trans, false);
1039
1040 /* stop and reset the on-board processor */
1041 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1042 udelay(20);
1043
1044 /*
1045 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1046 * This is a bug in certain verions of the hardware.
1047 * Certain devices also keep sending HW RF kill interrupt all
1048 * the time, unless the interrupt is ACKed even if the interrupt
1049 * should be masked. Re-ACK all the interrupts here.
1050 */
1051 spin_lock(&trans_pcie->irq_lock);
1052 iwl_disable_interrupts(trans);
1053 spin_unlock(&trans_pcie->irq_lock);
1054
1055
1056 /* clear all status bits */
1057 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1058 clear_bit(STATUS_INT_ENABLED, &trans->status);
1059 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1060 clear_bit(STATUS_RFKILL, &trans->status);
1061
1062 /*
1063 * Even if we stop the HW, we still want the RF kill
1064 * interrupt
1065 */
1066 iwl_enable_rfkill_int(trans);
1067
1068 /*
1069 * Check again since the RF kill state may have changed while
1070 * all the interrupts were disabled, in this case we couldn't
1071 * receive the RF kill interrupt and update the state in the
1072 * op_mode.
1073 * Don't call the op_mode if the rkfill state hasn't changed.
1074 * This allows the op_mode to call stop_device from the rfkill
1075 * notification without endless recursion. Under very rare
1076 * circumstances, we might have a small recursion if the rfkill
1077 * state changed exactly now while we were called from stop_device.
1078 * This is very unlikely but can happen and is supported.
1079 */
1080 hw_rfkill = iwl_is_rfkill_set(trans);
1081 if (hw_rfkill)
1082 set_bit(STATUS_RFKILL, &trans->status);
1083 else
1084 clear_bit(STATUS_RFKILL, &trans->status);
1085 if (hw_rfkill != was_hw_rfkill)
1086 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1087
1088 /* re-take ownership to prevent other users from stealing the deivce */
1089 iwl_pcie_prepare_card_hw(trans);
1090 }
1091
1092 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1093 {
1094 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1095 iwl_trans_pcie_stop_device(trans);
1096 }
1097
1098 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
1099 {
1100 iwl_disable_interrupts(trans);
1101
1102 /*
1103 * in testing mode, the host stays awake and the
1104 * hardware won't be reset (not even partially)
1105 */
1106 if (test)
1107 return;
1108
1109 iwl_pcie_disable_ict(trans);
1110
1111 iwl_clear_bit(trans, CSR_GP_CNTRL,
1112 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1113 iwl_clear_bit(trans, CSR_GP_CNTRL,
1114 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1115
1116 /*
1117 * reset TX queues -- some of their registers reset during S3
1118 * so if we don't reset everything here the D3 image would try
1119 * to execute some invalid memory upon resume
1120 */
1121 iwl_trans_pcie_tx_reset(trans);
1122
1123 iwl_pcie_set_pwr(trans, true);
1124 }
1125
1126 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1127 enum iwl_d3_status *status,
1128 bool test)
1129 {
1130 u32 val;
1131 int ret;
1132
1133 if (test) {
1134 iwl_enable_interrupts(trans);
1135 *status = IWL_D3_STATUS_ALIVE;
1136 return 0;
1137 }
1138
1139 /*
1140 * Also enables interrupts - none will happen as the device doesn't
1141 * know we're waking it up, only when the opmode actually tells it
1142 * after this call.
1143 */
1144 iwl_pcie_reset_ict(trans);
1145
1146 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1147 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1148
1149 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1150 udelay(2);
1151
1152 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1153 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1154 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1155 25000);
1156 if (ret < 0) {
1157 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1158 return ret;
1159 }
1160
1161 iwl_pcie_set_pwr(trans, false);
1162
1163 iwl_trans_pcie_tx_reset(trans);
1164
1165 ret = iwl_pcie_rx_init(trans);
1166 if (ret) {
1167 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1168 return ret;
1169 }
1170
1171 val = iwl_read32(trans, CSR_RESET);
1172 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1173 *status = IWL_D3_STATUS_RESET;
1174 else
1175 *status = IWL_D3_STATUS_ALIVE;
1176
1177 return 0;
1178 }
1179
1180 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1181 {
1182 bool hw_rfkill;
1183 int err;
1184
1185 err = iwl_pcie_prepare_card_hw(trans);
1186 if (err) {
1187 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1188 return err;
1189 }
1190
1191 /* Reset the entire device */
1192 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1193
1194 usleep_range(10, 15);
1195
1196 iwl_pcie_apm_init(trans);
1197
1198 /* From now on, the op_mode will be kept updated about RF kill state */
1199 iwl_enable_rfkill_int(trans);
1200
1201 hw_rfkill = iwl_is_rfkill_set(trans);
1202 if (hw_rfkill)
1203 set_bit(STATUS_RFKILL, &trans->status);
1204 else
1205 clear_bit(STATUS_RFKILL, &trans->status);
1206 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1207
1208 return 0;
1209 }
1210
1211 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1212 {
1213 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1214
1215 /* disable interrupts - don't enable HW RF kill interrupt */
1216 spin_lock(&trans_pcie->irq_lock);
1217 iwl_disable_interrupts(trans);
1218 spin_unlock(&trans_pcie->irq_lock);
1219
1220 iwl_pcie_apm_stop(trans, true);
1221
1222 spin_lock(&trans_pcie->irq_lock);
1223 iwl_disable_interrupts(trans);
1224 spin_unlock(&trans_pcie->irq_lock);
1225
1226 iwl_pcie_disable_ict(trans);
1227 }
1228
1229 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1230 {
1231 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1232 }
1233
1234 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1235 {
1236 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1237 }
1238
1239 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1240 {
1241 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1242 }
1243
1244 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1245 {
1246 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1247 ((reg & 0x000FFFFF) | (3 << 24)));
1248 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1249 }
1250
1251 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1252 u32 val)
1253 {
1254 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1255 ((addr & 0x000FFFFF) | (3 << 24)));
1256 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1257 }
1258
1259 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1260 {
1261 WARN_ON(1);
1262 return 0;
1263 }
1264
1265 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1266 const struct iwl_trans_config *trans_cfg)
1267 {
1268 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1269
1270 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1271 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1272 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1273 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1274 trans_pcie->n_no_reclaim_cmds = 0;
1275 else
1276 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1277 if (trans_pcie->n_no_reclaim_cmds)
1278 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1279 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1280
1281 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1282 if (trans_pcie->rx_buf_size_8k)
1283 trans_pcie->rx_page_order = get_order(8 * 1024);
1284 else
1285 trans_pcie->rx_page_order = get_order(4 * 1024);
1286
1287 trans_pcie->command_names = trans_cfg->command_names;
1288 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1289 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1290
1291 /* Initialize NAPI here - it should be before registering to mac80211
1292 * in the opmode but after the HW struct is allocated.
1293 * As this function may be called again in some corner cases don't
1294 * do anything if NAPI was already initialized.
1295 */
1296 if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1297 init_dummy_netdev(&trans_pcie->napi_dev);
1298 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1299 &trans_pcie->napi_dev,
1300 iwl_pcie_dummy_napi_poll, 64);
1301 }
1302 }
1303
1304 void iwl_trans_pcie_free(struct iwl_trans *trans)
1305 {
1306 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1307
1308 synchronize_irq(trans_pcie->pci_dev->irq);
1309
1310 iwl_pcie_tx_free(trans);
1311 iwl_pcie_rx_free(trans);
1312
1313 free_irq(trans_pcie->pci_dev->irq, trans);
1314 iwl_pcie_free_ict(trans);
1315
1316 pci_disable_msi(trans_pcie->pci_dev);
1317 iounmap(trans_pcie->hw_base);
1318 pci_release_regions(trans_pcie->pci_dev);
1319 pci_disable_device(trans_pcie->pci_dev);
1320 kmem_cache_destroy(trans->dev_cmd_pool);
1321
1322 if (trans_pcie->napi.poll)
1323 netif_napi_del(&trans_pcie->napi);
1324
1325 iwl_pcie_free_fw_monitor(trans);
1326
1327 kfree(trans);
1328 }
1329
1330 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1331 {
1332 if (state)
1333 set_bit(STATUS_TPOWER_PMI, &trans->status);
1334 else
1335 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1336 }
1337
1338 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1339 unsigned long *flags)
1340 {
1341 int ret;
1342 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1343
1344 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1345
1346 if (trans_pcie->cmd_in_flight)
1347 goto out;
1348
1349 /* this bit wakes up the NIC */
1350 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1351 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1352 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1353 udelay(2);
1354
1355 /*
1356 * These bits say the device is running, and should keep running for
1357 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1358 * but they do not indicate that embedded SRAM is restored yet;
1359 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1360 * to/from host DRAM when sleeping/waking for power-saving.
1361 * Each direction takes approximately 1/4 millisecond; with this
1362 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1363 * series of register accesses are expected (e.g. reading Event Log),
1364 * to keep device from sleeping.
1365 *
1366 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1367 * SRAM is okay/restored. We don't check that here because this call
1368 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1369 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1370 *
1371 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1372 * and do not save/restore SRAM when power cycling.
1373 */
1374 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1375 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1376 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1377 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1378 if (unlikely(ret < 0)) {
1379 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1380 if (!silent) {
1381 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1382 WARN_ONCE(1,
1383 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1384 val);
1385 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1386 return false;
1387 }
1388 }
1389
1390 out:
1391 /*
1392 * Fool sparse by faking we release the lock - sparse will
1393 * track nic_access anyway.
1394 */
1395 __release(&trans_pcie->reg_lock);
1396 return true;
1397 }
1398
1399 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1400 unsigned long *flags)
1401 {
1402 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1403
1404 lockdep_assert_held(&trans_pcie->reg_lock);
1405
1406 /*
1407 * Fool sparse by faking we acquiring the lock - sparse will
1408 * track nic_access anyway.
1409 */
1410 __acquire(&trans_pcie->reg_lock);
1411
1412 if (trans_pcie->cmd_in_flight)
1413 goto out;
1414
1415 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1416 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1417 /*
1418 * Above we read the CSR_GP_CNTRL register, which will flush
1419 * any previous writes, but we need the write that clears the
1420 * MAC_ACCESS_REQ bit to be performed before any other writes
1421 * scheduled on different CPUs (after we drop reg_lock).
1422 */
1423 mmiowb();
1424 out:
1425 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1426 }
1427
1428 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1429 void *buf, int dwords)
1430 {
1431 unsigned long flags;
1432 int offs, ret = 0;
1433 u32 *vals = buf;
1434
1435 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1436 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1437 for (offs = 0; offs < dwords; offs++)
1438 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1439 iwl_trans_release_nic_access(trans, &flags);
1440 } else {
1441 ret = -EBUSY;
1442 }
1443 return ret;
1444 }
1445
1446 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1447 const void *buf, int dwords)
1448 {
1449 unsigned long flags;
1450 int offs, ret = 0;
1451 const u32 *vals = buf;
1452
1453 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1454 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1455 for (offs = 0; offs < dwords; offs++)
1456 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1457 vals ? vals[offs] : 0);
1458 iwl_trans_release_nic_access(trans, &flags);
1459 } else {
1460 ret = -EBUSY;
1461 }
1462 return ret;
1463 }
1464
1465 #define IWL_FLUSH_WAIT_MS 2000
1466
1467 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1468 {
1469 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1470 struct iwl_txq *txq;
1471 struct iwl_queue *q;
1472 int cnt;
1473 unsigned long now = jiffies;
1474 u32 scd_sram_addr;
1475 u8 buf[16];
1476 int ret = 0;
1477
1478 /* waiting for all the tx frames complete might take a while */
1479 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1480 u8 wr_ptr;
1481
1482 if (cnt == trans_pcie->cmd_queue)
1483 continue;
1484 if (!test_bit(cnt, trans_pcie->queue_used))
1485 continue;
1486 if (!(BIT(cnt) & txq_bm))
1487 continue;
1488
1489 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1490 txq = &trans_pcie->txq[cnt];
1491 q = &txq->q;
1492 wr_ptr = ACCESS_ONCE(q->write_ptr);
1493
1494 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1495 !time_after(jiffies,
1496 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1497 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1498
1499 if (WARN_ONCE(wr_ptr != write_ptr,
1500 "WR pointer moved while flushing %d -> %d\n",
1501 wr_ptr, write_ptr))
1502 return -ETIMEDOUT;
1503 msleep(1);
1504 }
1505
1506 if (q->read_ptr != q->write_ptr) {
1507 IWL_ERR(trans,
1508 "fail to flush all tx fifo queues Q %d\n", cnt);
1509 ret = -ETIMEDOUT;
1510 break;
1511 }
1512 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1513 }
1514
1515 if (!ret)
1516 return 0;
1517
1518 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1519 txq->q.read_ptr, txq->q.write_ptr);
1520
1521 scd_sram_addr = trans_pcie->scd_base_addr +
1522 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1523 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1524
1525 iwl_print_hex_error(trans, buf, sizeof(buf));
1526
1527 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1528 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1529 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1530
1531 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1532 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1533 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1534 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1535 u32 tbl_dw =
1536 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1537 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1538
1539 if (cnt & 0x1)
1540 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1541 else
1542 tbl_dw = tbl_dw & 0x0000FFFF;
1543
1544 IWL_ERR(trans,
1545 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1546 cnt, active ? "" : "in", fifo, tbl_dw,
1547 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1548 (TFD_QUEUE_SIZE_MAX - 1),
1549 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1550 }
1551
1552 return ret;
1553 }
1554
1555 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1556 u32 mask, u32 value)
1557 {
1558 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1559 unsigned long flags;
1560
1561 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1562 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1563 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1564 }
1565
1566 void iwl_trans_pcie_ref(struct iwl_trans *trans)
1567 {
1568 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1569 unsigned long flags;
1570
1571 if (iwlwifi_mod_params.d0i3_disable)
1572 return;
1573
1574 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1575 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1576 trans_pcie->ref_count++;
1577 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1578 }
1579
1580 void iwl_trans_pcie_unref(struct iwl_trans *trans)
1581 {
1582 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1583 unsigned long flags;
1584
1585 if (iwlwifi_mod_params.d0i3_disable)
1586 return;
1587
1588 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1589 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1590 if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1591 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1592 return;
1593 }
1594 trans_pcie->ref_count--;
1595 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1596 }
1597
1598 static const char *get_csr_string(int cmd)
1599 {
1600 #define IWL_CMD(x) case x: return #x
1601 switch (cmd) {
1602 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1603 IWL_CMD(CSR_INT_COALESCING);
1604 IWL_CMD(CSR_INT);
1605 IWL_CMD(CSR_INT_MASK);
1606 IWL_CMD(CSR_FH_INT_STATUS);
1607 IWL_CMD(CSR_GPIO_IN);
1608 IWL_CMD(CSR_RESET);
1609 IWL_CMD(CSR_GP_CNTRL);
1610 IWL_CMD(CSR_HW_REV);
1611 IWL_CMD(CSR_EEPROM_REG);
1612 IWL_CMD(CSR_EEPROM_GP);
1613 IWL_CMD(CSR_OTP_GP_REG);
1614 IWL_CMD(CSR_GIO_REG);
1615 IWL_CMD(CSR_GP_UCODE_REG);
1616 IWL_CMD(CSR_GP_DRIVER_REG);
1617 IWL_CMD(CSR_UCODE_DRV_GP1);
1618 IWL_CMD(CSR_UCODE_DRV_GP2);
1619 IWL_CMD(CSR_LED_REG);
1620 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1621 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1622 IWL_CMD(CSR_ANA_PLL_CFG);
1623 IWL_CMD(CSR_HW_REV_WA_REG);
1624 IWL_CMD(CSR_MONITOR_STATUS_REG);
1625 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1626 default:
1627 return "UNKNOWN";
1628 }
1629 #undef IWL_CMD
1630 }
1631
1632 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1633 {
1634 int i;
1635 static const u32 csr_tbl[] = {
1636 CSR_HW_IF_CONFIG_REG,
1637 CSR_INT_COALESCING,
1638 CSR_INT,
1639 CSR_INT_MASK,
1640 CSR_FH_INT_STATUS,
1641 CSR_GPIO_IN,
1642 CSR_RESET,
1643 CSR_GP_CNTRL,
1644 CSR_HW_REV,
1645 CSR_EEPROM_REG,
1646 CSR_EEPROM_GP,
1647 CSR_OTP_GP_REG,
1648 CSR_GIO_REG,
1649 CSR_GP_UCODE_REG,
1650 CSR_GP_DRIVER_REG,
1651 CSR_UCODE_DRV_GP1,
1652 CSR_UCODE_DRV_GP2,
1653 CSR_LED_REG,
1654 CSR_DRAM_INT_TBL_REG,
1655 CSR_GIO_CHICKEN_BITS,
1656 CSR_ANA_PLL_CFG,
1657 CSR_MONITOR_STATUS_REG,
1658 CSR_HW_REV_WA_REG,
1659 CSR_DBG_HPET_MEM_REG
1660 };
1661 IWL_ERR(trans, "CSR values:\n");
1662 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1663 "CSR_INT_PERIODIC_REG)\n");
1664 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1665 IWL_ERR(trans, " %25s: 0X%08x\n",
1666 get_csr_string(csr_tbl[i]),
1667 iwl_read32(trans, csr_tbl[i]));
1668 }
1669 }
1670
1671 #ifdef CONFIG_IWLWIFI_DEBUGFS
1672 /* create and remove of files */
1673 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1674 if (!debugfs_create_file(#name, mode, parent, trans, \
1675 &iwl_dbgfs_##name##_ops)) \
1676 goto err; \
1677 } while (0)
1678
1679 /* file operation */
1680 #define DEBUGFS_READ_FILE_OPS(name) \
1681 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1682 .read = iwl_dbgfs_##name##_read, \
1683 .open = simple_open, \
1684 .llseek = generic_file_llseek, \
1685 };
1686
1687 #define DEBUGFS_WRITE_FILE_OPS(name) \
1688 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1689 .write = iwl_dbgfs_##name##_write, \
1690 .open = simple_open, \
1691 .llseek = generic_file_llseek, \
1692 };
1693
1694 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1695 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1696 .write = iwl_dbgfs_##name##_write, \
1697 .read = iwl_dbgfs_##name##_read, \
1698 .open = simple_open, \
1699 .llseek = generic_file_llseek, \
1700 };
1701
1702 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1703 char __user *user_buf,
1704 size_t count, loff_t *ppos)
1705 {
1706 struct iwl_trans *trans = file->private_data;
1707 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1708 struct iwl_txq *txq;
1709 struct iwl_queue *q;
1710 char *buf;
1711 int pos = 0;
1712 int cnt;
1713 int ret;
1714 size_t bufsz;
1715
1716 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1717
1718 if (!trans_pcie->txq)
1719 return -EAGAIN;
1720
1721 buf = kzalloc(bufsz, GFP_KERNEL);
1722 if (!buf)
1723 return -ENOMEM;
1724
1725 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1726 txq = &trans_pcie->txq[cnt];
1727 q = &txq->q;
1728 pos += scnprintf(buf + pos, bufsz - pos,
1729 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d%s\n",
1730 cnt, q->read_ptr, q->write_ptr,
1731 !!test_bit(cnt, trans_pcie->queue_used),
1732 !!test_bit(cnt, trans_pcie->queue_stopped),
1733 txq->need_update,
1734 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
1735 }
1736 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1737 kfree(buf);
1738 return ret;
1739 }
1740
1741 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1742 char __user *user_buf,
1743 size_t count, loff_t *ppos)
1744 {
1745 struct iwl_trans *trans = file->private_data;
1746 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1747 struct iwl_rxq *rxq = &trans_pcie->rxq;
1748 char buf[256];
1749 int pos = 0;
1750 const size_t bufsz = sizeof(buf);
1751
1752 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1753 rxq->read);
1754 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1755 rxq->write);
1756 pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1757 rxq->write_actual);
1758 pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1759 rxq->need_update);
1760 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1761 rxq->free_count);
1762 if (rxq->rb_stts) {
1763 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1764 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1765 } else {
1766 pos += scnprintf(buf + pos, bufsz - pos,
1767 "closed_rb_num: Not Allocated\n");
1768 }
1769 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1770 }
1771
1772 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1773 char __user *user_buf,
1774 size_t count, loff_t *ppos)
1775 {
1776 struct iwl_trans *trans = file->private_data;
1777 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1778 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1779
1780 int pos = 0;
1781 char *buf;
1782 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1783 ssize_t ret;
1784
1785 buf = kzalloc(bufsz, GFP_KERNEL);
1786 if (!buf)
1787 return -ENOMEM;
1788
1789 pos += scnprintf(buf + pos, bufsz - pos,
1790 "Interrupt Statistics Report:\n");
1791
1792 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1793 isr_stats->hw);
1794 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1795 isr_stats->sw);
1796 if (isr_stats->sw || isr_stats->hw) {
1797 pos += scnprintf(buf + pos, bufsz - pos,
1798 "\tLast Restarting Code: 0x%X\n",
1799 isr_stats->err_code);
1800 }
1801 #ifdef CONFIG_IWLWIFI_DEBUG
1802 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1803 isr_stats->sch);
1804 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1805 isr_stats->alive);
1806 #endif
1807 pos += scnprintf(buf + pos, bufsz - pos,
1808 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1809
1810 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1811 isr_stats->ctkill);
1812
1813 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1814 isr_stats->wakeup);
1815
1816 pos += scnprintf(buf + pos, bufsz - pos,
1817 "Rx command responses:\t\t %u\n", isr_stats->rx);
1818
1819 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1820 isr_stats->tx);
1821
1822 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1823 isr_stats->unhandled);
1824
1825 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1826 kfree(buf);
1827 return ret;
1828 }
1829
1830 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1831 const char __user *user_buf,
1832 size_t count, loff_t *ppos)
1833 {
1834 struct iwl_trans *trans = file->private_data;
1835 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1836 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1837
1838 char buf[8];
1839 int buf_size;
1840 u32 reset_flag;
1841
1842 memset(buf, 0, sizeof(buf));
1843 buf_size = min(count, sizeof(buf) - 1);
1844 if (copy_from_user(buf, user_buf, buf_size))
1845 return -EFAULT;
1846 if (sscanf(buf, "%x", &reset_flag) != 1)
1847 return -EFAULT;
1848 if (reset_flag == 0)
1849 memset(isr_stats, 0, sizeof(*isr_stats));
1850
1851 return count;
1852 }
1853
1854 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1855 const char __user *user_buf,
1856 size_t count, loff_t *ppos)
1857 {
1858 struct iwl_trans *trans = file->private_data;
1859 char buf[8];
1860 int buf_size;
1861 int csr;
1862
1863 memset(buf, 0, sizeof(buf));
1864 buf_size = min(count, sizeof(buf) - 1);
1865 if (copy_from_user(buf, user_buf, buf_size))
1866 return -EFAULT;
1867 if (sscanf(buf, "%d", &csr) != 1)
1868 return -EFAULT;
1869
1870 iwl_pcie_dump_csr(trans);
1871
1872 return count;
1873 }
1874
1875 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1876 char __user *user_buf,
1877 size_t count, loff_t *ppos)
1878 {
1879 struct iwl_trans *trans = file->private_data;
1880 char *buf = NULL;
1881 ssize_t ret;
1882
1883 ret = iwl_dump_fh(trans, &buf);
1884 if (ret < 0)
1885 return ret;
1886 if (!buf)
1887 return -EINVAL;
1888 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1889 kfree(buf);
1890 return ret;
1891 }
1892
1893 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1894 DEBUGFS_READ_FILE_OPS(fh_reg);
1895 DEBUGFS_READ_FILE_OPS(rx_queue);
1896 DEBUGFS_READ_FILE_OPS(tx_queue);
1897 DEBUGFS_WRITE_FILE_OPS(csr);
1898
1899 /*
1900 * Create the debugfs files and directories
1901 *
1902 */
1903 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1904 struct dentry *dir)
1905 {
1906 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1907 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1908 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1909 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1910 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1911 return 0;
1912
1913 err:
1914 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1915 return -ENOMEM;
1916 }
1917 #else
1918 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1919 struct dentry *dir)
1920 {
1921 return 0;
1922 }
1923 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1924
1925 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
1926 {
1927 u32 cmdlen = 0;
1928 int i;
1929
1930 for (i = 0; i < IWL_NUM_OF_TBS; i++)
1931 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
1932
1933 return cmdlen;
1934 }
1935
1936 static const struct {
1937 u32 start, end;
1938 } iwl_prph_dump_addr[] = {
1939 { .start = 0x00a00000, .end = 0x00a00000 },
1940 { .start = 0x00a0000c, .end = 0x00a00024 },
1941 { .start = 0x00a0002c, .end = 0x00a0003c },
1942 { .start = 0x00a00410, .end = 0x00a00418 },
1943 { .start = 0x00a00420, .end = 0x00a00420 },
1944 { .start = 0x00a00428, .end = 0x00a00428 },
1945 { .start = 0x00a00430, .end = 0x00a0043c },
1946 { .start = 0x00a00444, .end = 0x00a00444 },
1947 { .start = 0x00a004c0, .end = 0x00a004cc },
1948 { .start = 0x00a004d8, .end = 0x00a004d8 },
1949 { .start = 0x00a004e0, .end = 0x00a004f0 },
1950 { .start = 0x00a00840, .end = 0x00a00840 },
1951 { .start = 0x00a00850, .end = 0x00a00858 },
1952 { .start = 0x00a01004, .end = 0x00a01008 },
1953 { .start = 0x00a01010, .end = 0x00a01010 },
1954 { .start = 0x00a01018, .end = 0x00a01018 },
1955 { .start = 0x00a01024, .end = 0x00a01024 },
1956 { .start = 0x00a0102c, .end = 0x00a01034 },
1957 { .start = 0x00a0103c, .end = 0x00a01040 },
1958 { .start = 0x00a01048, .end = 0x00a01094 },
1959 { .start = 0x00a01c00, .end = 0x00a01c20 },
1960 { .start = 0x00a01c58, .end = 0x00a01c58 },
1961 { .start = 0x00a01c7c, .end = 0x00a01c7c },
1962 { .start = 0x00a01c28, .end = 0x00a01c54 },
1963 { .start = 0x00a01c5c, .end = 0x00a01c5c },
1964 { .start = 0x00a01c84, .end = 0x00a01c84 },
1965 { .start = 0x00a01ce0, .end = 0x00a01d0c },
1966 { .start = 0x00a01d18, .end = 0x00a01d20 },
1967 { .start = 0x00a01d2c, .end = 0x00a01d30 },
1968 { .start = 0x00a01d40, .end = 0x00a01d5c },
1969 { .start = 0x00a01d80, .end = 0x00a01d80 },
1970 { .start = 0x00a01d98, .end = 0x00a01d98 },
1971 { .start = 0x00a01dc0, .end = 0x00a01dfc },
1972 { .start = 0x00a01e00, .end = 0x00a01e2c },
1973 { .start = 0x00a01e40, .end = 0x00a01e60 },
1974 { .start = 0x00a01e84, .end = 0x00a01e90 },
1975 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
1976 { .start = 0x00a01ed0, .end = 0x00a01ed0 },
1977 { .start = 0x00a01f00, .end = 0x00a01f14 },
1978 { .start = 0x00a01f44, .end = 0x00a01f58 },
1979 { .start = 0x00a01f80, .end = 0x00a01fa8 },
1980 { .start = 0x00a01fb0, .end = 0x00a01fbc },
1981 { .start = 0x00a01ff8, .end = 0x00a01ffc },
1982 { .start = 0x00a02000, .end = 0x00a02048 },
1983 { .start = 0x00a02068, .end = 0x00a020f0 },
1984 { .start = 0x00a02100, .end = 0x00a02118 },
1985 { .start = 0x00a02140, .end = 0x00a0214c },
1986 { .start = 0x00a02168, .end = 0x00a0218c },
1987 { .start = 0x00a021c0, .end = 0x00a021c0 },
1988 { .start = 0x00a02400, .end = 0x00a02410 },
1989 { .start = 0x00a02418, .end = 0x00a02420 },
1990 { .start = 0x00a02428, .end = 0x00a0242c },
1991 { .start = 0x00a02434, .end = 0x00a02434 },
1992 { .start = 0x00a02440, .end = 0x00a02460 },
1993 { .start = 0x00a02468, .end = 0x00a024b0 },
1994 { .start = 0x00a024c8, .end = 0x00a024cc },
1995 { .start = 0x00a02500, .end = 0x00a02504 },
1996 { .start = 0x00a0250c, .end = 0x00a02510 },
1997 { .start = 0x00a02540, .end = 0x00a02554 },
1998 { .start = 0x00a02580, .end = 0x00a025f4 },
1999 { .start = 0x00a02600, .end = 0x00a0260c },
2000 { .start = 0x00a02648, .end = 0x00a02650 },
2001 { .start = 0x00a02680, .end = 0x00a02680 },
2002 { .start = 0x00a026c0, .end = 0x00a026d0 },
2003 { .start = 0x00a02700, .end = 0x00a0270c },
2004 { .start = 0x00a02804, .end = 0x00a02804 },
2005 { .start = 0x00a02818, .end = 0x00a0281c },
2006 { .start = 0x00a02c00, .end = 0x00a02db4 },
2007 { .start = 0x00a02df4, .end = 0x00a02fb0 },
2008 { .start = 0x00a03000, .end = 0x00a03014 },
2009 { .start = 0x00a0301c, .end = 0x00a0302c },
2010 { .start = 0x00a03034, .end = 0x00a03038 },
2011 { .start = 0x00a03040, .end = 0x00a03048 },
2012 { .start = 0x00a03060, .end = 0x00a03068 },
2013 { .start = 0x00a03070, .end = 0x00a03074 },
2014 { .start = 0x00a0307c, .end = 0x00a0307c },
2015 { .start = 0x00a03080, .end = 0x00a03084 },
2016 { .start = 0x00a0308c, .end = 0x00a03090 },
2017 { .start = 0x00a03098, .end = 0x00a03098 },
2018 { .start = 0x00a030a0, .end = 0x00a030a0 },
2019 { .start = 0x00a030a8, .end = 0x00a030b4 },
2020 { .start = 0x00a030bc, .end = 0x00a030bc },
2021 { .start = 0x00a030c0, .end = 0x00a0312c },
2022 { .start = 0x00a03c00, .end = 0x00a03c5c },
2023 { .start = 0x00a04400, .end = 0x00a04454 },
2024 { .start = 0x00a04460, .end = 0x00a04474 },
2025 { .start = 0x00a044c0, .end = 0x00a044ec },
2026 { .start = 0x00a04500, .end = 0x00a04504 },
2027 { .start = 0x00a04510, .end = 0x00a04538 },
2028 { .start = 0x00a04540, .end = 0x00a04548 },
2029 { .start = 0x00a04560, .end = 0x00a0457c },
2030 { .start = 0x00a04590, .end = 0x00a04598 },
2031 { .start = 0x00a045c0, .end = 0x00a045f4 },
2032 };
2033
2034 static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
2035 struct iwl_fw_error_dump_data **data)
2036 {
2037 struct iwl_fw_error_dump_prph *prph;
2038 unsigned long flags;
2039 u32 prph_len = 0, i;
2040
2041 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2042 return 0;
2043
2044 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2045 /* The range includes both boundaries */
2046 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2047 iwl_prph_dump_addr[i].start + 4;
2048 int reg;
2049 __le32 *val;
2050
2051 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
2052
2053 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
2054 (*data)->len = cpu_to_le32(sizeof(*prph) +
2055 num_bytes_in_chunk);
2056 prph = (void *)(*data)->data;
2057 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
2058 val = (void *)prph->data;
2059
2060 for (reg = iwl_prph_dump_addr[i].start;
2061 reg <= iwl_prph_dump_addr[i].end;
2062 reg += 4)
2063 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2064 reg));
2065 *data = iwl_fw_error_next_data(*data);
2066 }
2067
2068 iwl_trans_release_nic_access(trans, &flags);
2069
2070 return prph_len;
2071 }
2072
2073 #define IWL_CSR_TO_DUMP (0x250)
2074
2075 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2076 struct iwl_fw_error_dump_data **data)
2077 {
2078 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2079 __le32 *val;
2080 int i;
2081
2082 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2083 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2084 val = (void *)(*data)->data;
2085
2086 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2087 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2088
2089 *data = iwl_fw_error_next_data(*data);
2090
2091 return csr_len;
2092 }
2093
2094 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2095 struct iwl_fw_error_dump_data **data)
2096 {
2097 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2098 unsigned long flags;
2099 __le32 *val;
2100 int i;
2101
2102 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2103 return 0;
2104
2105 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2106 (*data)->len = cpu_to_le32(fh_regs_len);
2107 val = (void *)(*data)->data;
2108
2109 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2110 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2111
2112 iwl_trans_release_nic_access(trans, &flags);
2113
2114 *data = iwl_fw_error_next_data(*data);
2115
2116 return sizeof(**data) + fh_regs_len;
2117 }
2118
2119 static
2120 struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
2121 {
2122 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2123 struct iwl_fw_error_dump_data *data;
2124 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2125 struct iwl_fw_error_dump_txcmd *txcmd;
2126 struct iwl_trans_dump_data *dump_data;
2127 u32 len;
2128 u32 monitor_len;
2129 int i, ptr;
2130
2131 /* transport dump header */
2132 len = sizeof(*dump_data);
2133
2134 /* host commands */
2135 len += sizeof(*data) +
2136 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2137
2138 /* CSR registers */
2139 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2140
2141 /* PRPH registers */
2142 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2143 /* The range includes both boundaries */
2144 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2145 iwl_prph_dump_addr[i].start + 4;
2146
2147 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
2148 num_bytes_in_chunk;
2149 }
2150
2151 /* FH registers */
2152 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2153
2154 /* FW monitor */
2155 if (trans_pcie->fw_mon_page) {
2156 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2157 trans_pcie->fw_mon_size;
2158 monitor_len = trans_pcie->fw_mon_size;
2159 } else if (trans->dbg_dest_tlv) {
2160 u32 base, end;
2161
2162 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2163 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2164
2165 base = iwl_read_prph(trans, base) <<
2166 trans->dbg_dest_tlv->base_shift;
2167 end = iwl_read_prph(trans, end) <<
2168 trans->dbg_dest_tlv->end_shift;
2169
2170 /* Make "end" point to the actual end */
2171 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2172 end += (1 << trans->dbg_dest_tlv->end_shift);
2173 monitor_len = end - base;
2174 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2175 monitor_len;
2176 } else {
2177 monitor_len = 0;
2178 }
2179
2180 dump_data = vzalloc(len);
2181 if (!dump_data)
2182 return NULL;
2183
2184 len = 0;
2185 data = (void *)dump_data->data;
2186 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2187 txcmd = (void *)data->data;
2188 spin_lock_bh(&cmdq->lock);
2189 ptr = cmdq->q.write_ptr;
2190 for (i = 0; i < cmdq->q.n_window; i++) {
2191 u8 idx = get_cmd_index(&cmdq->q, ptr);
2192 u32 caplen, cmdlen;
2193
2194 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2195 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2196
2197 if (cmdlen) {
2198 len += sizeof(*txcmd) + caplen;
2199 txcmd->cmdlen = cpu_to_le32(cmdlen);
2200 txcmd->caplen = cpu_to_le32(caplen);
2201 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2202 txcmd = (void *)((u8 *)txcmd->data + caplen);
2203 }
2204
2205 ptr = iwl_queue_dec_wrap(ptr);
2206 }
2207 spin_unlock_bh(&cmdq->lock);
2208
2209 data->len = cpu_to_le32(len);
2210 len += sizeof(*data);
2211 data = iwl_fw_error_next_data(data);
2212
2213 len += iwl_trans_pcie_dump_prph(trans, &data);
2214 len += iwl_trans_pcie_dump_csr(trans, &data);
2215 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2216 /* data is already pointing to the next section */
2217
2218 if ((trans_pcie->fw_mon_page &&
2219 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2220 trans->dbg_dest_tlv) {
2221 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2222 u32 base, write_ptr, wrap_cnt;
2223
2224 /* If there was a dest TLV - use the values from there */
2225 if (trans->dbg_dest_tlv) {
2226 write_ptr =
2227 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2228 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2229 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2230 } else {
2231 base = MON_BUFF_BASE_ADDR;
2232 write_ptr = MON_BUFF_WRPTR;
2233 wrap_cnt = MON_BUFF_CYCLE_CNT;
2234 }
2235
2236 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2237 fw_mon_data = (void *)data->data;
2238 fw_mon_data->fw_mon_wr_ptr =
2239 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2240 fw_mon_data->fw_mon_cycle_cnt =
2241 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2242 fw_mon_data->fw_mon_base_ptr =
2243 cpu_to_le32(iwl_read_prph(trans, base));
2244
2245 len += sizeof(*data) + sizeof(*fw_mon_data);
2246 if (trans_pcie->fw_mon_page) {
2247 data->len = cpu_to_le32(trans_pcie->fw_mon_size +
2248 sizeof(*fw_mon_data));
2249
2250 /*
2251 * The firmware is now asserted, it won't write anything
2252 * to the buffer. CPU can take ownership to fetch the
2253 * data. The buffer will be handed back to the device
2254 * before the firmware will be restarted.
2255 */
2256 dma_sync_single_for_cpu(trans->dev,
2257 trans_pcie->fw_mon_phys,
2258 trans_pcie->fw_mon_size,
2259 DMA_FROM_DEVICE);
2260 memcpy(fw_mon_data->data,
2261 page_address(trans_pcie->fw_mon_page),
2262 trans_pcie->fw_mon_size);
2263
2264 len += trans_pcie->fw_mon_size;
2265 } else {
2266 /* If we are here then the buffer is internal */
2267
2268 /*
2269 * Update pointers to reflect actual values after
2270 * shifting
2271 */
2272 base = iwl_read_prph(trans, base) <<
2273 trans->dbg_dest_tlv->base_shift;
2274 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2275 monitor_len / sizeof(u32));
2276 data->len = cpu_to_le32(sizeof(*fw_mon_data) +
2277 monitor_len);
2278 len += monitor_len;
2279 }
2280 }
2281
2282 dump_data->len = len;
2283
2284 return dump_data;
2285 }
2286
2287 static const struct iwl_trans_ops trans_ops_pcie = {
2288 .start_hw = iwl_trans_pcie_start_hw,
2289 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2290 .fw_alive = iwl_trans_pcie_fw_alive,
2291 .start_fw = iwl_trans_pcie_start_fw,
2292 .stop_device = iwl_trans_pcie_stop_device,
2293
2294 .d3_suspend = iwl_trans_pcie_d3_suspend,
2295 .d3_resume = iwl_trans_pcie_d3_resume,
2296
2297 .send_cmd = iwl_trans_pcie_send_hcmd,
2298
2299 .tx = iwl_trans_pcie_tx,
2300 .reclaim = iwl_trans_pcie_reclaim,
2301
2302 .txq_disable = iwl_trans_pcie_txq_disable,
2303 .txq_enable = iwl_trans_pcie_txq_enable,
2304
2305 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2306
2307 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2308
2309 .write8 = iwl_trans_pcie_write8,
2310 .write32 = iwl_trans_pcie_write32,
2311 .read32 = iwl_trans_pcie_read32,
2312 .read_prph = iwl_trans_pcie_read_prph,
2313 .write_prph = iwl_trans_pcie_write_prph,
2314 .read_mem = iwl_trans_pcie_read_mem,
2315 .write_mem = iwl_trans_pcie_write_mem,
2316 .configure = iwl_trans_pcie_configure,
2317 .set_pmi = iwl_trans_pcie_set_pmi,
2318 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2319 .release_nic_access = iwl_trans_pcie_release_nic_access,
2320 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2321
2322 .ref = iwl_trans_pcie_ref,
2323 .unref = iwl_trans_pcie_unref,
2324
2325 .dump_data = iwl_trans_pcie_dump_data,
2326 };
2327
2328 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2329 const struct pci_device_id *ent,
2330 const struct iwl_cfg *cfg)
2331 {
2332 struct iwl_trans_pcie *trans_pcie;
2333 struct iwl_trans *trans;
2334 u16 pci_cmd;
2335 int err;
2336
2337 trans = kzalloc(sizeof(struct iwl_trans) +
2338 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2339 if (!trans) {
2340 err = -ENOMEM;
2341 goto out;
2342 }
2343
2344 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2345
2346 trans->ops = &trans_ops_pcie;
2347 trans->cfg = cfg;
2348 trans_lockdep_init(trans);
2349 trans_pcie->trans = trans;
2350 spin_lock_init(&trans_pcie->irq_lock);
2351 spin_lock_init(&trans_pcie->reg_lock);
2352 spin_lock_init(&trans_pcie->ref_lock);
2353 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2354
2355 err = pci_enable_device(pdev);
2356 if (err)
2357 goto out_no_pci;
2358
2359 if (!cfg->base_params->pcie_l1_allowed) {
2360 /*
2361 * W/A - seems to solve weird behavior. We need to remove this
2362 * if we don't want to stay in L1 all the time. This wastes a
2363 * lot of power.
2364 */
2365 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2366 PCIE_LINK_STATE_L1 |
2367 PCIE_LINK_STATE_CLKPM);
2368 }
2369
2370 pci_set_master(pdev);
2371
2372 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2373 if (!err)
2374 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2375 if (err) {
2376 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2377 if (!err)
2378 err = pci_set_consistent_dma_mask(pdev,
2379 DMA_BIT_MASK(32));
2380 /* both attempts failed: */
2381 if (err) {
2382 dev_err(&pdev->dev, "No suitable DMA available\n");
2383 goto out_pci_disable_device;
2384 }
2385 }
2386
2387 err = pci_request_regions(pdev, DRV_NAME);
2388 if (err) {
2389 dev_err(&pdev->dev, "pci_request_regions failed\n");
2390 goto out_pci_disable_device;
2391 }
2392
2393 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2394 if (!trans_pcie->hw_base) {
2395 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2396 err = -ENODEV;
2397 goto out_pci_release_regions;
2398 }
2399
2400 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2401 * PCI Tx retries from interfering with C3 CPU state */
2402 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2403
2404 trans->dev = &pdev->dev;
2405 trans_pcie->pci_dev = pdev;
2406 iwl_disable_interrupts(trans);
2407
2408 err = pci_enable_msi(pdev);
2409 if (err) {
2410 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
2411 /* enable rfkill interrupt: hw bug w/a */
2412 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2413 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2414 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2415 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2416 }
2417 }
2418
2419 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2420 /*
2421 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2422 * changed, and now the revision step also includes bit 0-1 (no more
2423 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2424 * in the old format.
2425 */
2426 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2427 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2428 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2429
2430 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2431 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2432 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2433
2434 /* Initialize the wait queue for commands */
2435 init_waitqueue_head(&trans_pcie->wait_command_queue);
2436
2437 snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2438 "iwl_cmd_pool:%s", dev_name(trans->dev));
2439
2440 trans->dev_cmd_headroom = 0;
2441 trans->dev_cmd_pool =
2442 kmem_cache_create(trans->dev_cmd_pool_name,
2443 sizeof(struct iwl_device_cmd)
2444 + trans->dev_cmd_headroom,
2445 sizeof(void *),
2446 SLAB_HWCACHE_ALIGN,
2447 NULL);
2448
2449 if (!trans->dev_cmd_pool) {
2450 err = -ENOMEM;
2451 goto out_pci_disable_msi;
2452 }
2453
2454 if (iwl_pcie_alloc_ict(trans))
2455 goto out_free_cmd_pool;
2456
2457 err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2458 iwl_pcie_irq_handler,
2459 IRQF_SHARED, DRV_NAME, trans);
2460 if (err) {
2461 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2462 goto out_free_ict;
2463 }
2464
2465 trans_pcie->inta_mask = CSR_INI_SET_MASK;
2466 trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND;
2467
2468 return trans;
2469
2470 out_free_ict:
2471 iwl_pcie_free_ict(trans);
2472 out_free_cmd_pool:
2473 kmem_cache_destroy(trans->dev_cmd_pool);
2474 out_pci_disable_msi:
2475 pci_disable_msi(pdev);
2476 out_pci_release_regions:
2477 pci_release_regions(pdev);
2478 out_pci_disable_device:
2479 pci_disable_device(pdev);
2480 out_no_pci:
2481 kfree(trans);
2482 out:
2483 return ERR_PTR(err);
2484 }
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