1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called COPYING.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
34 * All rights reserved.
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37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
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43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
72 #include "iwl-trans.h"
75 #include "iwl-agn-hw.h"
78 static void __iwl_trans_pcie_set_bits_mask(struct iwl_trans
*trans
,
79 u32 reg
, u32 mask
, u32 value
)
83 #ifdef CONFIG_IWLWIFI_DEBUG
84 WARN_ON_ONCE(value
& ~mask
);
87 v
= iwl_read32(trans
, reg
);
90 iwl_write32(trans
, reg
, v
);
93 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans
*trans
,
96 __iwl_trans_pcie_set_bits_mask(trans
, reg
, mask
, 0);
99 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans
*trans
,
102 __iwl_trans_pcie_set_bits_mask(trans
, reg
, mask
, mask
);
105 static void iwl_pcie_set_pwr(struct iwl_trans
*trans
, bool vaux
)
107 if (vaux
&& pci_pme_capable(to_pci_dev(trans
->dev
), PCI_D3cold
))
108 iwl_set_bits_mask_prph(trans
, APMG_PS_CTRL_REG
,
109 APMG_PS_CTRL_VAL_PWR_SRC_VAUX
,
110 ~APMG_PS_CTRL_MSK_PWR_SRC
);
112 iwl_set_bits_mask_prph(trans
, APMG_PS_CTRL_REG
,
113 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
,
114 ~APMG_PS_CTRL_MSK_PWR_SRC
);
118 #define PCI_CFG_RETRY_TIMEOUT 0x041
120 static void iwl_pcie_apm_config(struct iwl_trans
*trans
)
122 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
126 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
127 * Check if BIOS (or OS) enabled L1-ASPM on this device.
128 * If so (likely), disable L0S, so device moves directly L0->L1;
129 * costs negligible amount of power savings.
130 * If not (unlikely), enable L0S, so there is at least some
131 * power savings, even without L1.
133 pcie_capability_read_word(trans_pcie
->pci_dev
, PCI_EXP_LNKCTL
, &lctl
);
134 if (lctl
& PCI_EXP_LNKCTL_ASPM_L1
) {
135 /* L1-ASPM enabled; disable(!) L0S */
136 iwl_set_bit(trans
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
137 dev_info(trans
->dev
, "L1 Enabled; Disabling L0S\n");
139 /* L1-ASPM disabled; enable(!) L0S */
140 iwl_clear_bit(trans
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
141 dev_info(trans
->dev
, "L1 Disabled; Enabling L0S\n");
143 trans
->pm_support
= !(lctl
& PCI_EXP_LNKCTL_ASPM_L0S
);
147 * Start up NIC's basic functionality after it has been reset
148 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
149 * NOTE: This does not load uCode nor start the embedded processor
151 static int iwl_pcie_apm_init(struct iwl_trans
*trans
)
153 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
155 IWL_DEBUG_INFO(trans
, "Init card's basic functions\n");
158 * Use "set_bit" below rather than "write", to preserve any hardware
159 * bits already set by default after reset.
162 /* Disable L0S exit timer (platform NMI Work/Around) */
163 iwl_set_bit(trans
, CSR_GIO_CHICKEN_BITS
,
164 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER
);
167 * Disable L0s without affecting L1;
168 * don't wait for ICH L0s (ICH bug W/A)
170 iwl_set_bit(trans
, CSR_GIO_CHICKEN_BITS
,
171 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX
);
173 /* Set FH wait threshold to maximum (HW error during stress W/A) */
174 iwl_set_bit(trans
, CSR_DBG_HPET_MEM_REG
, CSR_DBG_HPET_MEM_REG_VAL
);
177 * Enable HAP INTA (interrupt from management bus) to
178 * wake device's PCI Express link L1a -> L0s
180 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
181 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A
);
183 iwl_pcie_apm_config(trans
);
185 /* Configure analog phase-lock-loop before activating to D0A */
186 if (trans
->cfg
->base_params
->pll_cfg_val
)
187 iwl_set_bit(trans
, CSR_ANA_PLL_CFG
,
188 trans
->cfg
->base_params
->pll_cfg_val
);
191 * Set "initialization complete" bit to move adapter from
192 * D0U* --> D0A* (powered-up active) state.
194 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
197 * Wait for clock stabilization; once stabilized, access to
198 * device-internal resources is supported, e.g. iwl_write_prph()
199 * and accesses to uCode SRAM.
201 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
202 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
203 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
, 25000);
205 IWL_DEBUG_INFO(trans
, "Failed to init the card\n");
210 * Enable DMA clock and wait for it to stabilize.
212 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
213 * do not disable clocks. This preserves any hardware bits already
214 * set by default in "CLK_CTRL_REG" after reset.
216 iwl_write_prph(trans
, APMG_CLK_EN_REG
, APMG_CLK_VAL_DMA_CLK_RQT
);
219 /* Disable L1-Active */
220 iwl_set_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
221 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
223 set_bit(STATUS_DEVICE_ENABLED
, &trans_pcie
->status
);
229 static int iwl_pcie_apm_stop_master(struct iwl_trans
*trans
)
233 /* stop device's busmaster DMA activity */
234 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_STOP_MASTER
);
236 ret
= iwl_poll_bit(trans
, CSR_RESET
,
237 CSR_RESET_REG_FLAG_MASTER_DISABLED
,
238 CSR_RESET_REG_FLAG_MASTER_DISABLED
, 100);
240 IWL_WARN(trans
, "Master Disable Timed Out, 100 usec\n");
242 IWL_DEBUG_INFO(trans
, "stop master\n");
247 static void iwl_pcie_apm_stop(struct iwl_trans
*trans
)
249 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
250 IWL_DEBUG_INFO(trans
, "Stop card, put in low power state\n");
252 clear_bit(STATUS_DEVICE_ENABLED
, &trans_pcie
->status
);
254 /* Stop device's DMA activity */
255 iwl_pcie_apm_stop_master(trans
);
257 /* Reset the entire device */
258 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
263 * Clear "initialization complete" bit to move adapter from
264 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
266 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
267 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
270 static int iwl_pcie_nic_init(struct iwl_trans
*trans
)
272 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
276 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
277 iwl_pcie_apm_init(trans
);
279 /* Set interrupt coalescing calibration timer to default (512 usecs) */
280 iwl_write8(trans
, CSR_INT_COALESCING
, IWL_HOST_INT_CALIB_TIMEOUT_DEF
);
282 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
284 iwl_pcie_set_pwr(trans
, false);
286 iwl_op_mode_nic_config(trans
->op_mode
);
288 /* Allocate the RX queue, or reset if it is already allocated */
289 iwl_pcie_rx_init(trans
);
291 /* Allocate or reset and init all Tx and Command queues */
292 if (iwl_pcie_tx_init(trans
))
295 if (trans
->cfg
->base_params
->shadow_reg_enable
) {
296 /* enable shadow regs in HW */
297 iwl_set_bit(trans
, CSR_MAC_SHADOW_REG_CTRL
, 0x800FFFFF);
298 IWL_DEBUG_INFO(trans
, "Enabling shadow registers in device\n");
304 #define HW_READY_TIMEOUT (50)
306 /* Note: returns poll_bit return value, which is >= 0 if success */
307 static int iwl_pcie_set_hw_ready(struct iwl_trans
*trans
)
311 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
312 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
);
314 /* See if we got it */
315 ret
= iwl_poll_bit(trans
, CSR_HW_IF_CONFIG_REG
,
316 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
317 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
320 IWL_DEBUG_INFO(trans
, "hardware%s ready\n", ret
< 0 ? " not" : "");
324 /* Note: returns standard 0/-ERROR code */
325 static int iwl_pcie_prepare_card_hw(struct iwl_trans
*trans
)
330 IWL_DEBUG_INFO(trans
, "iwl_trans_prepare_card_hw enter\n");
332 ret
= iwl_pcie_set_hw_ready(trans
);
333 /* If the card is ready, exit 0 */
337 /* If HW is not ready, prepare the conditions to check again */
338 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
339 CSR_HW_IF_CONFIG_REG_PREPARE
);
342 ret
= iwl_pcie_set_hw_ready(trans
);
346 usleep_range(200, 1000);
348 } while (t
< 150000);
356 static int iwl_pcie_load_firmware_chunk(struct iwl_trans
*trans
, u32 dst_addr
,
357 dma_addr_t phy_addr
, u32 byte_cnt
)
359 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
362 trans_pcie
->ucode_write_complete
= false;
364 iwl_write_direct32(trans
,
365 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
366 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE
);
368 iwl_write_direct32(trans
,
369 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL
),
372 iwl_write_direct32(trans
,
373 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL
),
374 phy_addr
& FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK
);
376 iwl_write_direct32(trans
,
377 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL
),
378 (iwl_get_dma_hi_addr(phy_addr
)
379 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT
) | byte_cnt
);
381 iwl_write_direct32(trans
,
382 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL
),
383 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM
|
384 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX
|
385 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID
);
387 iwl_write_direct32(trans
,
388 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
389 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
390 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE
|
391 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD
);
393 ret
= wait_event_timeout(trans_pcie
->ucode_write_waitq
,
394 trans_pcie
->ucode_write_complete
, 5 * HZ
);
396 IWL_ERR(trans
, "Failed to load firmware chunk!\n");
403 static int iwl_pcie_load_section(struct iwl_trans
*trans
, u8 section_num
,
404 const struct fw_desc
*section
)
408 u32 offset
, chunk_sz
= section
->len
;
411 IWL_DEBUG_FW(trans
, "[%d] uCode section being loaded...\n",
414 v_addr
= dma_alloc_coherent(trans
->dev
, chunk_sz
, &p_addr
,
415 GFP_KERNEL
| __GFP_NOWARN
);
417 IWL_DEBUG_INFO(trans
, "Falling back to small chunks of DMA\n");
418 chunk_sz
= PAGE_SIZE
;
419 v_addr
= dma_alloc_coherent(trans
->dev
, chunk_sz
,
420 &p_addr
, GFP_KERNEL
);
425 for (offset
= 0; offset
< section
->len
; offset
+= chunk_sz
) {
428 copy_size
= min_t(u32
, chunk_sz
, section
->len
- offset
);
430 memcpy(v_addr
, (u8
*)section
->data
+ offset
, copy_size
);
431 ret
= iwl_pcie_load_firmware_chunk(trans
,
432 section
->offset
+ offset
,
436 "Could not load the [%d] uCode section\n",
442 dma_free_coherent(trans
->dev
, chunk_sz
, v_addr
, p_addr
);
446 static int iwl_pcie_load_given_ucode(struct iwl_trans
*trans
,
447 const struct fw_img
*image
)
451 for (i
= 0; i
< IWL_UCODE_SECTION_MAX
; i
++) {
452 if (!image
->sec
[i
].data
)
455 ret
= iwl_pcie_load_section(trans
, i
, &image
->sec
[i
]);
460 /* Remove all resets to allow NIC to operate */
461 iwl_write32(trans
, CSR_RESET
, 0);
466 static int iwl_trans_pcie_start_fw(struct iwl_trans
*trans
,
467 const struct fw_img
*fw
, bool run_in_rfkill
)
469 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
473 /* This may fail if AMT took ownership of the device */
474 if (iwl_pcie_prepare_card_hw(trans
)) {
475 IWL_WARN(trans
, "Exit HW not ready\n");
479 clear_bit(STATUS_FW_ERROR
, &trans_pcie
->status
);
481 iwl_enable_rfkill_int(trans
);
483 /* If platform's RF_KILL switch is NOT set to KILL */
484 hw_rfkill
= iwl_is_rfkill_set(trans
);
486 set_bit(STATUS_RFKILL
, &trans_pcie
->status
);
488 clear_bit(STATUS_RFKILL
, &trans_pcie
->status
);
489 iwl_op_mode_hw_rf_kill(trans
->op_mode
, hw_rfkill
);
490 if (hw_rfkill
&& !run_in_rfkill
)
493 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
495 ret
= iwl_pcie_nic_init(trans
);
497 IWL_ERR(trans
, "Unable to init nic\n");
501 /* make sure rfkill handshake bits are cleared */
502 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
503 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
,
504 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED
);
506 /* clear (again), then enable host interrupts */
507 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
508 iwl_enable_interrupts(trans
);
510 /* really make sure rfkill handshake bits are cleared */
511 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
512 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
514 /* Load the given image to the HW */
515 return iwl_pcie_load_given_ucode(trans
, fw
);
518 static void iwl_trans_pcie_fw_alive(struct iwl_trans
*trans
, u32 scd_addr
)
520 iwl_pcie_reset_ict(trans
);
521 iwl_pcie_tx_start(trans
, scd_addr
);
524 static void iwl_trans_pcie_stop_device(struct iwl_trans
*trans
)
526 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
529 /* tell the device to stop sending interrupts */
530 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
531 iwl_disable_interrupts(trans
);
532 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
534 /* device going down, Stop using ICT table */
535 iwl_pcie_disable_ict(trans
);
538 * If a HW restart happens during firmware loading,
539 * then the firmware loading might call this function
540 * and later it might be called again due to the
541 * restart. So don't process again if the device is
544 if (test_bit(STATUS_DEVICE_ENABLED
, &trans_pcie
->status
)) {
545 iwl_pcie_tx_stop(trans
);
546 iwl_pcie_rx_stop(trans
);
548 /* Power-down device's busmaster DMA clocks */
549 iwl_write_prph(trans
, APMG_CLK_DIS_REG
,
550 APMG_CLK_VAL_DMA_CLK_RQT
);
554 /* Make sure (redundant) we've released our request to stay awake */
555 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
556 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
558 /* Stop the device, and put it in low power state */
559 iwl_pcie_apm_stop(trans
);
561 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
562 * Clean again the interrupt here
564 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
565 iwl_disable_interrupts(trans
);
566 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
568 iwl_enable_rfkill_int(trans
);
570 /* stop and reset the on-board processor */
571 iwl_write32(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_NEVO_RESET
);
573 /* clear all status bits */
574 clear_bit(STATUS_HCMD_ACTIVE
, &trans_pcie
->status
);
575 clear_bit(STATUS_INT_ENABLED
, &trans_pcie
->status
);
576 clear_bit(STATUS_DEVICE_ENABLED
, &trans_pcie
->status
);
577 clear_bit(STATUS_TPOWER_PMI
, &trans_pcie
->status
);
578 clear_bit(STATUS_RFKILL
, &trans_pcie
->status
);
581 static void iwl_trans_pcie_d3_suspend(struct iwl_trans
*trans
)
583 iwl_disable_interrupts(trans
);
584 iwl_pcie_disable_ict(trans
);
586 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
587 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
588 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
589 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
592 * reset TX queues -- some of their registers reset during S3
593 * so if we don't reset everything here the D3 image would try
594 * to execute some invalid memory upon resume
596 iwl_trans_pcie_tx_reset(trans
);
598 iwl_pcie_set_pwr(trans
, true);
601 static int iwl_trans_pcie_d3_resume(struct iwl_trans
*trans
,
602 enum iwl_d3_status
*status
)
607 iwl_pcie_set_pwr(trans
, false);
609 val
= iwl_read32(trans
, CSR_RESET
);
610 if (val
& CSR_RESET_REG_FLAG_NEVO_RESET
) {
611 *status
= IWL_D3_STATUS_RESET
;
616 * Also enables interrupts - none will happen as the device doesn't
617 * know we're waking it up, only when the opmode actually tells it
620 iwl_pcie_reset_ict(trans
);
622 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
623 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
625 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
626 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
627 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
630 IWL_ERR(trans
, "Failed to resume the device (mac ready)\n");
634 iwl_trans_pcie_tx_reset(trans
);
636 ret
= iwl_pcie_rx_init(trans
);
638 IWL_ERR(trans
, "Failed to resume the device (RX reset)\n");
642 *status
= IWL_D3_STATUS_ALIVE
;
646 static int iwl_trans_pcie_start_hw(struct iwl_trans
*trans
)
648 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
652 err
= iwl_pcie_prepare_card_hw(trans
);
654 IWL_ERR(trans
, "Error while preparing HW: %d\n", err
);
658 iwl_pcie_apm_init(trans
);
660 /* From now on, the op_mode will be kept updated about RF kill state */
661 iwl_enable_rfkill_int(trans
);
663 hw_rfkill
= iwl_is_rfkill_set(trans
);
665 set_bit(STATUS_RFKILL
, &trans_pcie
->status
);
667 clear_bit(STATUS_RFKILL
, &trans_pcie
->status
);
668 iwl_op_mode_hw_rf_kill(trans
->op_mode
, hw_rfkill
);
673 static void iwl_trans_pcie_stop_hw(struct iwl_trans
*trans
,
674 bool op_mode_leaving
)
676 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
680 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
681 iwl_disable_interrupts(trans
);
682 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
684 iwl_pcie_apm_stop(trans
);
686 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
687 iwl_disable_interrupts(trans
);
688 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
690 iwl_pcie_disable_ict(trans
);
692 if (!op_mode_leaving
) {
694 * Even if we stop the HW, we still want the RF kill
697 iwl_enable_rfkill_int(trans
);
700 * Check again since the RF kill state may have changed while
701 * all the interrupts were disabled, in this case we couldn't
702 * receive the RF kill interrupt and update the state in the
705 hw_rfkill
= iwl_is_rfkill_set(trans
);
707 set_bit(STATUS_RFKILL
, &trans_pcie
->status
);
709 clear_bit(STATUS_RFKILL
, &trans_pcie
->status
);
710 iwl_op_mode_hw_rf_kill(trans
->op_mode
, hw_rfkill
);
714 static void iwl_trans_pcie_write8(struct iwl_trans
*trans
, u32 ofs
, u8 val
)
716 writeb(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
719 static void iwl_trans_pcie_write32(struct iwl_trans
*trans
, u32 ofs
, u32 val
)
721 writel(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
724 static u32
iwl_trans_pcie_read32(struct iwl_trans
*trans
, u32 ofs
)
726 return readl(IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
729 static u32
iwl_trans_pcie_read_prph(struct iwl_trans
*trans
, u32 reg
)
731 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_RADDR
,
732 ((reg
& 0x000FFFFF) | (3 << 24)));
733 return iwl_trans_pcie_read32(trans
, HBUS_TARG_PRPH_RDAT
);
736 static void iwl_trans_pcie_write_prph(struct iwl_trans
*trans
, u32 addr
,
739 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_WADDR
,
740 ((addr
& 0x000FFFFF) | (3 << 24)));
741 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_WDAT
, val
);
744 static void iwl_trans_pcie_configure(struct iwl_trans
*trans
,
745 const struct iwl_trans_config
*trans_cfg
)
747 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
749 trans_pcie
->cmd_queue
= trans_cfg
->cmd_queue
;
750 trans_pcie
->cmd_fifo
= trans_cfg
->cmd_fifo
;
751 if (WARN_ON(trans_cfg
->n_no_reclaim_cmds
> MAX_NO_RECLAIM_CMDS
))
752 trans_pcie
->n_no_reclaim_cmds
= 0;
754 trans_pcie
->n_no_reclaim_cmds
= trans_cfg
->n_no_reclaim_cmds
;
755 if (trans_pcie
->n_no_reclaim_cmds
)
756 memcpy(trans_pcie
->no_reclaim_cmds
, trans_cfg
->no_reclaim_cmds
,
757 trans_pcie
->n_no_reclaim_cmds
* sizeof(u8
));
759 trans_pcie
->rx_buf_size_8k
= trans_cfg
->rx_buf_size_8k
;
760 if (trans_pcie
->rx_buf_size_8k
)
761 trans_pcie
->rx_page_order
= get_order(8 * 1024);
763 trans_pcie
->rx_page_order
= get_order(4 * 1024);
765 trans_pcie
->wd_timeout
=
766 msecs_to_jiffies(trans_cfg
->queue_watchdog_timeout
);
768 trans_pcie
->command_names
= trans_cfg
->command_names
;
769 trans_pcie
->bc_table_dword
= trans_cfg
->bc_table_dword
;
772 void iwl_trans_pcie_free(struct iwl_trans
*trans
)
774 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
776 synchronize_irq(trans_pcie
->pci_dev
->irq
);
778 iwl_pcie_tx_free(trans
);
779 iwl_pcie_rx_free(trans
);
781 free_irq(trans_pcie
->pci_dev
->irq
, trans
);
782 iwl_pcie_free_ict(trans
);
784 pci_disable_msi(trans_pcie
->pci_dev
);
785 iounmap(trans_pcie
->hw_base
);
786 pci_release_regions(trans_pcie
->pci_dev
);
787 pci_disable_device(trans_pcie
->pci_dev
);
788 kmem_cache_destroy(trans
->dev_cmd_pool
);
793 static void iwl_trans_pcie_set_pmi(struct iwl_trans
*trans
, bool state
)
795 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
798 set_bit(STATUS_TPOWER_PMI
, &trans_pcie
->status
);
800 clear_bit(STATUS_TPOWER_PMI
, &trans_pcie
->status
);
803 #ifdef CONFIG_PM_SLEEP
804 static int iwl_trans_pcie_suspend(struct iwl_trans
*trans
)
809 static int iwl_trans_pcie_resume(struct iwl_trans
*trans
)
813 iwl_enable_rfkill_int(trans
);
815 hw_rfkill
= iwl_is_rfkill_set(trans
);
816 iwl_op_mode_hw_rf_kill(trans
->op_mode
, hw_rfkill
);
820 #endif /* CONFIG_PM_SLEEP */
822 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans
*trans
, bool silent
,
823 unsigned long *flags
)
826 struct iwl_trans_pcie
*pcie_trans
= IWL_TRANS_GET_PCIE_TRANS(trans
);
827 spin_lock_irqsave(&pcie_trans
->reg_lock
, *flags
);
829 /* this bit wakes up the NIC */
830 __iwl_trans_pcie_set_bit(trans
, CSR_GP_CNTRL
,
831 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
834 * These bits say the device is running, and should keep running for
835 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
836 * but they do not indicate that embedded SRAM is restored yet;
837 * 3945 and 4965 have volatile SRAM, and must save/restore contents
838 * to/from host DRAM when sleeping/waking for power-saving.
839 * Each direction takes approximately 1/4 millisecond; with this
840 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
841 * series of register accesses are expected (e.g. reading Event Log),
842 * to keep device from sleeping.
844 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
845 * SRAM is okay/restored. We don't check that here because this call
846 * is just for hardware register access; but GP1 MAC_SLEEP check is a
847 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
849 * 5000 series and later (including 1000 series) have non-volatile SRAM,
850 * and do not save/restore SRAM when power cycling.
852 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
853 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN
,
854 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
|
855 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP
), 15000);
856 if (unlikely(ret
< 0)) {
857 iwl_write32(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_FORCE_NMI
);
859 u32 val
= iwl_read32(trans
, CSR_GP_CNTRL
);
861 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
863 spin_unlock_irqrestore(&pcie_trans
->reg_lock
, *flags
);
869 * Fool sparse by faking we release the lock - sparse will
870 * track nic_access anyway.
872 __release(&pcie_trans
->reg_lock
);
876 static void iwl_trans_pcie_release_nic_access(struct iwl_trans
*trans
,
877 unsigned long *flags
)
879 struct iwl_trans_pcie
*pcie_trans
= IWL_TRANS_GET_PCIE_TRANS(trans
);
881 lockdep_assert_held(&pcie_trans
->reg_lock
);
884 * Fool sparse by faking we acquiring the lock - sparse will
885 * track nic_access anyway.
887 __acquire(&pcie_trans
->reg_lock
);
889 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
890 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
892 * Above we read the CSR_GP_CNTRL register, which will flush
893 * any previous writes, but we need the write that clears the
894 * MAC_ACCESS_REQ bit to be performed before any other writes
895 * scheduled on different CPUs (after we drop reg_lock).
898 spin_unlock_irqrestore(&pcie_trans
->reg_lock
, *flags
);
901 static int iwl_trans_pcie_read_mem(struct iwl_trans
*trans
, u32 addr
,
902 void *buf
, int dwords
)
908 if (iwl_trans_grab_nic_access(trans
, false, &flags
)) {
909 iwl_write32(trans
, HBUS_TARG_MEM_RADDR
, addr
);
910 for (offs
= 0; offs
< dwords
; offs
++)
911 vals
[offs
] = iwl_read32(trans
, HBUS_TARG_MEM_RDAT
);
912 iwl_trans_release_nic_access(trans
, &flags
);
919 static int iwl_trans_pcie_write_mem(struct iwl_trans
*trans
, u32 addr
,
920 const void *buf
, int dwords
)
924 const u32
*vals
= buf
;
926 if (iwl_trans_grab_nic_access(trans
, false, &flags
)) {
927 iwl_write32(trans
, HBUS_TARG_MEM_WADDR
, addr
);
928 for (offs
= 0; offs
< dwords
; offs
++)
929 iwl_write32(trans
, HBUS_TARG_MEM_WDAT
,
930 vals
? vals
[offs
] : 0);
931 iwl_trans_release_nic_access(trans
, &flags
);
938 #define IWL_FLUSH_WAIT_MS 2000
940 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans
*trans
)
942 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
946 unsigned long now
= jiffies
;
951 /* waiting for all the tx frames complete might take a while */
952 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
953 if (cnt
== trans_pcie
->cmd_queue
)
955 txq
= &trans_pcie
->txq
[cnt
];
957 while (q
->read_ptr
!= q
->write_ptr
&& !time_after(jiffies
,
958 now
+ msecs_to_jiffies(IWL_FLUSH_WAIT_MS
)))
961 if (q
->read_ptr
!= q
->write_ptr
) {
963 "fail to flush all tx fifo queues Q %d\n", cnt
);
972 IWL_ERR(trans
, "Current SW read_ptr %d write_ptr %d\n",
973 txq
->q
.read_ptr
, txq
->q
.write_ptr
);
975 scd_sram_addr
= trans_pcie
->scd_base_addr
+
976 SCD_TX_STTS_QUEUE_OFFSET(txq
->q
.id
);
977 iwl_trans_read_mem_bytes(trans
, scd_sram_addr
, buf
, sizeof(buf
));
979 iwl_print_hex_error(trans
, buf
, sizeof(buf
));
981 for (cnt
= 0; cnt
< FH_TCSR_CHNL_NUM
; cnt
++)
982 IWL_ERR(trans
, "FH TRBs(%d) = 0x%08x\n", cnt
,
983 iwl_read_direct32(trans
, FH_TX_TRB_REG(cnt
)));
985 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
986 u32 status
= iwl_read_prph(trans
, SCD_QUEUE_STATUS_BITS(cnt
));
987 u8 fifo
= (status
>> SCD_QUEUE_STTS_REG_POS_TXF
) & 0x7;
988 bool active
= !!(status
& BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE
));
990 iwl_trans_read_mem32(trans
, trans_pcie
->scd_base_addr
+
991 SCD_TRANS_TBL_OFFSET_QUEUE(cnt
));
994 tbl_dw
= (tbl_dw
& 0xFFFF0000) >> 16;
996 tbl_dw
= tbl_dw
& 0x0000FFFF;
999 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1000 cnt
, active
? "" : "in", fifo
, tbl_dw
,
1001 iwl_read_prph(trans
,
1002 SCD_QUEUE_RDPTR(cnt
)) & (txq
->q
.n_bd
- 1),
1003 iwl_read_prph(trans
, SCD_QUEUE_WRPTR(cnt
)));
1009 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans
*trans
, u32 reg
,
1010 u32 mask
, u32 value
)
1012 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1013 unsigned long flags
;
1015 spin_lock_irqsave(&trans_pcie
->reg_lock
, flags
);
1016 __iwl_trans_pcie_set_bits_mask(trans
, reg
, mask
, value
);
1017 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
1020 static const char *get_fh_string(int cmd
)
1022 #define IWL_CMD(x) case x: return #x
1024 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG
);
1025 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG
);
1026 IWL_CMD(FH_RSCSR_CHNL0_WPTR
);
1027 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG
);
1028 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG
);
1029 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG
);
1030 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
);
1031 IWL_CMD(FH_TSSR_TX_STATUS_REG
);
1032 IWL_CMD(FH_TSSR_TX_ERROR_REG
);
1039 int iwl_pcie_dump_fh(struct iwl_trans
*trans
, char **buf
)
1042 static const u32 fh_tbl
[] = {
1043 FH_RSCSR_CHNL0_STTS_WPTR_REG
,
1044 FH_RSCSR_CHNL0_RBDCB_BASE_REG
,
1045 FH_RSCSR_CHNL0_WPTR
,
1046 FH_MEM_RCSR_CHNL0_CONFIG_REG
,
1047 FH_MEM_RSSR_SHARED_CTRL_REG
,
1048 FH_MEM_RSSR_RX_STATUS_REG
,
1049 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
,
1050 FH_TSSR_TX_STATUS_REG
,
1051 FH_TSSR_TX_ERROR_REG
1054 #ifdef CONFIG_IWLWIFI_DEBUGFS
1057 size_t bufsz
= ARRAY_SIZE(fh_tbl
) * 48 + 40;
1059 *buf
= kmalloc(bufsz
, GFP_KERNEL
);
1063 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
1064 "FH register values:\n");
1066 for (i
= 0; i
< ARRAY_SIZE(fh_tbl
); i
++)
1067 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
1069 get_fh_string(fh_tbl
[i
]),
1070 iwl_read_direct32(trans
, fh_tbl
[i
]));
1076 IWL_ERR(trans
, "FH register values:\n");
1077 for (i
= 0; i
< ARRAY_SIZE(fh_tbl
); i
++)
1078 IWL_ERR(trans
, " %34s: 0X%08x\n",
1079 get_fh_string(fh_tbl
[i
]),
1080 iwl_read_direct32(trans
, fh_tbl
[i
]));
1085 static const char *get_csr_string(int cmd
)
1087 #define IWL_CMD(x) case x: return #x
1089 IWL_CMD(CSR_HW_IF_CONFIG_REG
);
1090 IWL_CMD(CSR_INT_COALESCING
);
1092 IWL_CMD(CSR_INT_MASK
);
1093 IWL_CMD(CSR_FH_INT_STATUS
);
1094 IWL_CMD(CSR_GPIO_IN
);
1096 IWL_CMD(CSR_GP_CNTRL
);
1097 IWL_CMD(CSR_HW_REV
);
1098 IWL_CMD(CSR_EEPROM_REG
);
1099 IWL_CMD(CSR_EEPROM_GP
);
1100 IWL_CMD(CSR_OTP_GP_REG
);
1101 IWL_CMD(CSR_GIO_REG
);
1102 IWL_CMD(CSR_GP_UCODE_REG
);
1103 IWL_CMD(CSR_GP_DRIVER_REG
);
1104 IWL_CMD(CSR_UCODE_DRV_GP1
);
1105 IWL_CMD(CSR_UCODE_DRV_GP2
);
1106 IWL_CMD(CSR_LED_REG
);
1107 IWL_CMD(CSR_DRAM_INT_TBL_REG
);
1108 IWL_CMD(CSR_GIO_CHICKEN_BITS
);
1109 IWL_CMD(CSR_ANA_PLL_CFG
);
1110 IWL_CMD(CSR_HW_REV_WA_REG
);
1111 IWL_CMD(CSR_DBG_HPET_MEM_REG
);
1118 void iwl_pcie_dump_csr(struct iwl_trans
*trans
)
1121 static const u32 csr_tbl
[] = {
1122 CSR_HW_IF_CONFIG_REG
,
1140 CSR_DRAM_INT_TBL_REG
,
1141 CSR_GIO_CHICKEN_BITS
,
1144 CSR_DBG_HPET_MEM_REG
1146 IWL_ERR(trans
, "CSR values:\n");
1147 IWL_ERR(trans
, "(2nd byte of CSR_INT_COALESCING is "
1148 "CSR_INT_PERIODIC_REG)\n");
1149 for (i
= 0; i
< ARRAY_SIZE(csr_tbl
); i
++) {
1150 IWL_ERR(trans
, " %25s: 0X%08x\n",
1151 get_csr_string(csr_tbl
[i
]),
1152 iwl_read32(trans
, csr_tbl
[i
]));
1156 #ifdef CONFIG_IWLWIFI_DEBUGFS
1157 /* create and remove of files */
1158 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1159 if (!debugfs_create_file(#name, mode, parent, trans, \
1160 &iwl_dbgfs_##name##_ops)) \
1164 /* file operation */
1165 #define DEBUGFS_READ_FUNC(name) \
1166 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1167 char __user *user_buf, \
1168 size_t count, loff_t *ppos);
1170 #define DEBUGFS_WRITE_FUNC(name) \
1171 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1172 const char __user *user_buf, \
1173 size_t count, loff_t *ppos);
1175 #define DEBUGFS_READ_FILE_OPS(name) \
1176 DEBUGFS_READ_FUNC(name); \
1177 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1178 .read = iwl_dbgfs_##name##_read, \
1179 .open = simple_open, \
1180 .llseek = generic_file_llseek, \
1183 #define DEBUGFS_WRITE_FILE_OPS(name) \
1184 DEBUGFS_WRITE_FUNC(name); \
1185 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1186 .write = iwl_dbgfs_##name##_write, \
1187 .open = simple_open, \
1188 .llseek = generic_file_llseek, \
1191 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1192 DEBUGFS_READ_FUNC(name); \
1193 DEBUGFS_WRITE_FUNC(name); \
1194 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1195 .write = iwl_dbgfs_##name##_write, \
1196 .read = iwl_dbgfs_##name##_read, \
1197 .open = simple_open, \
1198 .llseek = generic_file_llseek, \
1201 static ssize_t
iwl_dbgfs_tx_queue_read(struct file
*file
,
1202 char __user
*user_buf
,
1203 size_t count
, loff_t
*ppos
)
1205 struct iwl_trans
*trans
= file
->private_data
;
1206 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1207 struct iwl_txq
*txq
;
1208 struct iwl_queue
*q
;
1215 bufsz
= sizeof(char) * 64 * trans
->cfg
->base_params
->num_of_queues
;
1217 if (!trans_pcie
->txq
)
1220 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1224 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
1225 txq
= &trans_pcie
->txq
[cnt
];
1227 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1228 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1229 cnt
, q
->read_ptr
, q
->write_ptr
,
1230 !!test_bit(cnt
, trans_pcie
->queue_used
),
1231 !!test_bit(cnt
, trans_pcie
->queue_stopped
));
1233 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1238 static ssize_t
iwl_dbgfs_rx_queue_read(struct file
*file
,
1239 char __user
*user_buf
,
1240 size_t count
, loff_t
*ppos
)
1242 struct iwl_trans
*trans
= file
->private_data
;
1243 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1244 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
;
1247 const size_t bufsz
= sizeof(buf
);
1249 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "read: %u\n",
1251 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "write: %u\n",
1253 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "free_count: %u\n",
1256 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "closed_rb_num: %u\n",
1257 le16_to_cpu(rxq
->rb_stts
->closed_rb_num
) & 0x0FFF);
1259 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1260 "closed_rb_num: Not Allocated\n");
1262 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1265 static ssize_t
iwl_dbgfs_interrupt_read(struct file
*file
,
1266 char __user
*user_buf
,
1267 size_t count
, loff_t
*ppos
)
1269 struct iwl_trans
*trans
= file
->private_data
;
1270 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1271 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
1275 int bufsz
= 24 * 64; /* 24 items * 64 char per item */
1278 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1282 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1283 "Interrupt Statistics Report:\n");
1285 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "HW Error:\t\t\t %u\n",
1287 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "SW Error:\t\t\t %u\n",
1289 if (isr_stats
->sw
|| isr_stats
->hw
) {
1290 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1291 "\tLast Restarting Code: 0x%X\n",
1292 isr_stats
->err_code
);
1294 #ifdef CONFIG_IWLWIFI_DEBUG
1295 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Frame transmitted:\t\t %u\n",
1297 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Alive interrupt:\t\t %u\n",
1300 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1301 "HW RF KILL switch toggled:\t %u\n", isr_stats
->rfkill
);
1303 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "CT KILL:\t\t\t %u\n",
1306 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Wakeup Interrupt:\t\t %u\n",
1309 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1310 "Rx command responses:\t\t %u\n", isr_stats
->rx
);
1312 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Tx/FH interrupt:\t\t %u\n",
1315 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Unexpected INTA:\t\t %u\n",
1316 isr_stats
->unhandled
);
1318 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1323 static ssize_t
iwl_dbgfs_interrupt_write(struct file
*file
,
1324 const char __user
*user_buf
,
1325 size_t count
, loff_t
*ppos
)
1327 struct iwl_trans
*trans
= file
->private_data
;
1328 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1329 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
1335 memset(buf
, 0, sizeof(buf
));
1336 buf_size
= min(count
, sizeof(buf
) - 1);
1337 if (copy_from_user(buf
, user_buf
, buf_size
))
1339 if (sscanf(buf
, "%x", &reset_flag
) != 1)
1341 if (reset_flag
== 0)
1342 memset(isr_stats
, 0, sizeof(*isr_stats
));
1347 static ssize_t
iwl_dbgfs_csr_write(struct file
*file
,
1348 const char __user
*user_buf
,
1349 size_t count
, loff_t
*ppos
)
1351 struct iwl_trans
*trans
= file
->private_data
;
1356 memset(buf
, 0, sizeof(buf
));
1357 buf_size
= min(count
, sizeof(buf
) - 1);
1358 if (copy_from_user(buf
, user_buf
, buf_size
))
1360 if (sscanf(buf
, "%d", &csr
) != 1)
1363 iwl_pcie_dump_csr(trans
);
1368 static ssize_t
iwl_dbgfs_fh_reg_read(struct file
*file
,
1369 char __user
*user_buf
,
1370 size_t count
, loff_t
*ppos
)
1372 struct iwl_trans
*trans
= file
->private_data
;
1375 ssize_t ret
= -EFAULT
;
1377 ret
= pos
= iwl_pcie_dump_fh(trans
, &buf
);
1379 ret
= simple_read_from_buffer(user_buf
,
1380 count
, ppos
, buf
, pos
);
1387 DEBUGFS_READ_WRITE_FILE_OPS(interrupt
);
1388 DEBUGFS_READ_FILE_OPS(fh_reg
);
1389 DEBUGFS_READ_FILE_OPS(rx_queue
);
1390 DEBUGFS_READ_FILE_OPS(tx_queue
);
1391 DEBUGFS_WRITE_FILE_OPS(csr
);
1394 * Create the debugfs files and directories
1397 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
,
1400 DEBUGFS_ADD_FILE(rx_queue
, dir
, S_IRUSR
);
1401 DEBUGFS_ADD_FILE(tx_queue
, dir
, S_IRUSR
);
1402 DEBUGFS_ADD_FILE(interrupt
, dir
, S_IWUSR
| S_IRUSR
);
1403 DEBUGFS_ADD_FILE(csr
, dir
, S_IWUSR
);
1404 DEBUGFS_ADD_FILE(fh_reg
, dir
, S_IRUSR
);
1408 IWL_ERR(trans
, "failed to create the trans debugfs entry\n");
1412 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
,
1417 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1419 static const struct iwl_trans_ops trans_ops_pcie
= {
1420 .start_hw
= iwl_trans_pcie_start_hw
,
1421 .stop_hw
= iwl_trans_pcie_stop_hw
,
1422 .fw_alive
= iwl_trans_pcie_fw_alive
,
1423 .start_fw
= iwl_trans_pcie_start_fw
,
1424 .stop_device
= iwl_trans_pcie_stop_device
,
1426 .d3_suspend
= iwl_trans_pcie_d3_suspend
,
1427 .d3_resume
= iwl_trans_pcie_d3_resume
,
1429 .send_cmd
= iwl_trans_pcie_send_hcmd
,
1431 .tx
= iwl_trans_pcie_tx
,
1432 .reclaim
= iwl_trans_pcie_reclaim
,
1434 .txq_disable
= iwl_trans_pcie_txq_disable
,
1435 .txq_enable
= iwl_trans_pcie_txq_enable
,
1437 .dbgfs_register
= iwl_trans_pcie_dbgfs_register
,
1439 .wait_tx_queue_empty
= iwl_trans_pcie_wait_txq_empty
,
1441 #ifdef CONFIG_PM_SLEEP
1442 .suspend
= iwl_trans_pcie_suspend
,
1443 .resume
= iwl_trans_pcie_resume
,
1445 .write8
= iwl_trans_pcie_write8
,
1446 .write32
= iwl_trans_pcie_write32
,
1447 .read32
= iwl_trans_pcie_read32
,
1448 .read_prph
= iwl_trans_pcie_read_prph
,
1449 .write_prph
= iwl_trans_pcie_write_prph
,
1450 .read_mem
= iwl_trans_pcie_read_mem
,
1451 .write_mem
= iwl_trans_pcie_write_mem
,
1452 .configure
= iwl_trans_pcie_configure
,
1453 .set_pmi
= iwl_trans_pcie_set_pmi
,
1454 .grab_nic_access
= iwl_trans_pcie_grab_nic_access
,
1455 .release_nic_access
= iwl_trans_pcie_release_nic_access
,
1456 .set_bits_mask
= iwl_trans_pcie_set_bits_mask
,
1459 struct iwl_trans
*iwl_trans_pcie_alloc(struct pci_dev
*pdev
,
1460 const struct pci_device_id
*ent
,
1461 const struct iwl_cfg
*cfg
)
1463 struct iwl_trans_pcie
*trans_pcie
;
1464 struct iwl_trans
*trans
;
1468 trans
= kzalloc(sizeof(struct iwl_trans
) +
1469 sizeof(struct iwl_trans_pcie
), GFP_KERNEL
);
1474 trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1476 trans
->ops
= &trans_ops_pcie
;
1478 trans_lockdep_init(trans
);
1479 trans_pcie
->trans
= trans
;
1480 spin_lock_init(&trans_pcie
->irq_lock
);
1481 spin_lock_init(&trans_pcie
->reg_lock
);
1482 init_waitqueue_head(&trans_pcie
->ucode_write_waitq
);
1484 /* W/A - seems to solve weird behavior. We need to remove this if we
1485 * don't want to stay in L1 all the time. This wastes a lot of power */
1486 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
1487 PCIE_LINK_STATE_CLKPM
);
1489 if (pci_enable_device(pdev
)) {
1494 pci_set_master(pdev
);
1496 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(36));
1498 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(36));
1500 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
1502 err
= pci_set_consistent_dma_mask(pdev
,
1504 /* both attempts failed: */
1506 dev_err(&pdev
->dev
, "No suitable DMA available\n");
1507 goto out_pci_disable_device
;
1511 err
= pci_request_regions(pdev
, DRV_NAME
);
1513 dev_err(&pdev
->dev
, "pci_request_regions failed\n");
1514 goto out_pci_disable_device
;
1517 trans_pcie
->hw_base
= pci_ioremap_bar(pdev
, 0);
1518 if (!trans_pcie
->hw_base
) {
1519 dev_err(&pdev
->dev
, "pci_ioremap_bar failed\n");
1521 goto out_pci_release_regions
;
1524 /* We disable the RETRY_TIMEOUT register (0x41) to keep
1525 * PCI Tx retries from interfering with C3 CPU state */
1526 pci_write_config_byte(pdev
, PCI_CFG_RETRY_TIMEOUT
, 0x00);
1528 err
= pci_enable_msi(pdev
);
1530 dev_err(&pdev
->dev
, "pci_enable_msi failed(0X%x)\n", err
);
1531 /* enable rfkill interrupt: hw bug w/a */
1532 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
1533 if (pci_cmd
& PCI_COMMAND_INTX_DISABLE
) {
1534 pci_cmd
&= ~PCI_COMMAND_INTX_DISABLE
;
1535 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
1539 trans
->dev
= &pdev
->dev
;
1540 trans_pcie
->pci_dev
= pdev
;
1541 trans
->hw_rev
= iwl_read32(trans
, CSR_HW_REV
);
1542 trans
->hw_id
= (pdev
->device
<< 16) + pdev
->subsystem_device
;
1543 snprintf(trans
->hw_id_str
, sizeof(trans
->hw_id_str
),
1544 "PCI ID: 0x%04X:0x%04X", pdev
->device
, pdev
->subsystem_device
);
1546 /* Initialize the wait queue for commands */
1547 init_waitqueue_head(&trans_pcie
->wait_command_queue
);
1549 snprintf(trans
->dev_cmd_pool_name
, sizeof(trans
->dev_cmd_pool_name
),
1550 "iwl_cmd_pool:%s", dev_name(trans
->dev
));
1552 trans
->dev_cmd_headroom
= 0;
1553 trans
->dev_cmd_pool
=
1554 kmem_cache_create(trans
->dev_cmd_pool_name
,
1555 sizeof(struct iwl_device_cmd
)
1556 + trans
->dev_cmd_headroom
,
1561 if (!trans
->dev_cmd_pool
)
1562 goto out_pci_disable_msi
;
1564 trans_pcie
->inta_mask
= CSR_INI_SET_MASK
;
1566 if (iwl_pcie_alloc_ict(trans
))
1567 goto out_free_cmd_pool
;
1569 if (request_threaded_irq(pdev
->irq
, iwl_pcie_isr_ict
,
1570 iwl_pcie_irq_handler
,
1571 IRQF_SHARED
, DRV_NAME
, trans
)) {
1572 IWL_ERR(trans
, "Error allocating IRQ %d\n", pdev
->irq
);
1579 iwl_pcie_free_ict(trans
);
1581 kmem_cache_destroy(trans
->dev_cmd_pool
);
1582 out_pci_disable_msi
:
1583 pci_disable_msi(pdev
);
1584 out_pci_release_regions
:
1585 pci_release_regions(pdev
);
1586 out_pci_disable_device
:
1587 pci_disable_device(pdev
);