1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
25 * The full GNU General Public License is included in this distribution
26 * in the file called COPYING.
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
34 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
35 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
36 * All rights reserved.
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
64 *****************************************************************************/
65 #include <linux/pci.h>
66 #include <linux/pci-aspm.h>
67 #include <linux/interrupt.h>
68 #include <linux/debugfs.h>
69 #include <linux/sched.h>
70 #include <linux/bitops.h>
71 #include <linux/gfp.h>
72 #include <linux/vmalloc.h>
75 #include "iwl-trans.h"
78 #include "iwl-agn-hw.h"
79 #include "iwl-fw-error-dump.h"
83 /* extended range in FW SRAM */
84 #define IWL_FW_MEM_EXTENDED_START 0x40000
85 #define IWL_FW_MEM_EXTENDED_END 0x57FFF
87 static void iwl_pcie_free_fw_monitor(struct iwl_trans
*trans
)
89 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
91 if (!trans_pcie
->fw_mon_page
)
94 dma_unmap_page(trans
->dev
, trans_pcie
->fw_mon_phys
,
95 trans_pcie
->fw_mon_size
, DMA_FROM_DEVICE
);
96 __free_pages(trans_pcie
->fw_mon_page
,
97 get_order(trans_pcie
->fw_mon_size
));
98 trans_pcie
->fw_mon_page
= NULL
;
99 trans_pcie
->fw_mon_phys
= 0;
100 trans_pcie
->fw_mon_size
= 0;
103 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans
*trans
)
105 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
111 if (trans_pcie
->fw_mon_page
) {
112 dma_sync_single_for_device(trans
->dev
, trans_pcie
->fw_mon_phys
,
113 trans_pcie
->fw_mon_size
,
119 for (power
= 26; power
>= 11; power
--) {
123 order
= get_order(size
);
124 page
= alloc_pages(__GFP_COMP
| __GFP_NOWARN
| __GFP_ZERO
,
129 phys
= dma_map_page(trans
->dev
, page
, 0, PAGE_SIZE
<< order
,
131 if (dma_mapping_error(trans
->dev
, phys
)) {
132 __free_pages(page
, order
);
136 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
141 if (WARN_ON_ONCE(!page
))
144 trans_pcie
->fw_mon_page
= page
;
145 trans_pcie
->fw_mon_phys
= phys
;
146 trans_pcie
->fw_mon_size
= size
;
149 static u32
iwl_trans_pcie_read_shr(struct iwl_trans
*trans
, u32 reg
)
151 iwl_write32(trans
, HEEP_CTRL_WRD_PCIEX_CTRL_REG
,
152 ((reg
& 0x0000ffff) | (2 << 28)));
153 return iwl_read32(trans
, HEEP_CTRL_WRD_PCIEX_DATA_REG
);
156 static void iwl_trans_pcie_write_shr(struct iwl_trans
*trans
, u32 reg
, u32 val
)
158 iwl_write32(trans
, HEEP_CTRL_WRD_PCIEX_DATA_REG
, val
);
159 iwl_write32(trans
, HEEP_CTRL_WRD_PCIEX_CTRL_REG
,
160 ((reg
& 0x0000ffff) | (3 << 28)));
163 static void iwl_pcie_set_pwr(struct iwl_trans
*trans
, bool vaux
)
165 if (vaux
&& pci_pme_capable(to_pci_dev(trans
->dev
), PCI_D3cold
))
166 iwl_set_bits_mask_prph(trans
, APMG_PS_CTRL_REG
,
167 APMG_PS_CTRL_VAL_PWR_SRC_VAUX
,
168 ~APMG_PS_CTRL_MSK_PWR_SRC
);
170 iwl_set_bits_mask_prph(trans
, APMG_PS_CTRL_REG
,
171 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
,
172 ~APMG_PS_CTRL_MSK_PWR_SRC
);
176 #define PCI_CFG_RETRY_TIMEOUT 0x041
178 static void iwl_pcie_apm_config(struct iwl_trans
*trans
)
180 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
185 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
186 * Check if BIOS (or OS) enabled L1-ASPM on this device.
187 * If so (likely), disable L0S, so device moves directly L0->L1;
188 * costs negligible amount of power savings.
189 * If not (unlikely), enable L0S, so there is at least some
190 * power savings, even without L1.
192 pcie_capability_read_word(trans_pcie
->pci_dev
, PCI_EXP_LNKCTL
, &lctl
);
193 if (lctl
& PCI_EXP_LNKCTL_ASPM_L1
)
194 iwl_set_bit(trans
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
196 iwl_clear_bit(trans
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
197 trans
->pm_support
= !(lctl
& PCI_EXP_LNKCTL_ASPM_L0S
);
199 pcie_capability_read_word(trans_pcie
->pci_dev
, PCI_EXP_DEVCTL2
, &cap
);
200 trans
->ltr_enabled
= cap
& PCI_EXP_DEVCTL2_LTR_EN
;
201 dev_info(trans
->dev
, "L1 %sabled - LTR %sabled\n",
202 (lctl
& PCI_EXP_LNKCTL_ASPM_L1
) ? "En" : "Dis",
203 trans
->ltr_enabled
? "En" : "Dis");
207 * Start up NIC's basic functionality after it has been reset
208 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
209 * NOTE: This does not load uCode nor start the embedded processor
211 static int iwl_pcie_apm_init(struct iwl_trans
*trans
)
214 IWL_DEBUG_INFO(trans
, "Init card's basic functions\n");
217 * Use "set_bit" below rather than "write", to preserve any hardware
218 * bits already set by default after reset.
221 /* Disable L0S exit timer (platform NMI Work/Around) */
222 if (trans
->cfg
->device_family
!= IWL_DEVICE_FAMILY_8000
)
223 iwl_set_bit(trans
, CSR_GIO_CHICKEN_BITS
,
224 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER
);
227 * Disable L0s without affecting L1;
228 * don't wait for ICH L0s (ICH bug W/A)
230 iwl_set_bit(trans
, CSR_GIO_CHICKEN_BITS
,
231 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX
);
233 /* Set FH wait threshold to maximum (HW error during stress W/A) */
234 iwl_set_bit(trans
, CSR_DBG_HPET_MEM_REG
, CSR_DBG_HPET_MEM_REG_VAL
);
237 * Enable HAP INTA (interrupt from management bus) to
238 * wake device's PCI Express link L1a -> L0s
240 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
241 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A
);
243 iwl_pcie_apm_config(trans
);
245 /* Configure analog phase-lock-loop before activating to D0A */
246 if (trans
->cfg
->base_params
->pll_cfg_val
)
247 iwl_set_bit(trans
, CSR_ANA_PLL_CFG
,
248 trans
->cfg
->base_params
->pll_cfg_val
);
251 * Set "initialization complete" bit to move adapter from
252 * D0U* --> D0A* (powered-up active) state.
254 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
257 * Wait for clock stabilization; once stabilized, access to
258 * device-internal resources is supported, e.g. iwl_write_prph()
259 * and accesses to uCode SRAM.
261 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
262 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
263 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
, 25000);
265 IWL_DEBUG_INFO(trans
, "Failed to init the card\n");
269 if (trans
->cfg
->host_interrupt_operation_mode
) {
271 * This is a bit of an abuse - This is needed for 7260 / 3160
272 * only check host_interrupt_operation_mode even if this is
273 * not related to host_interrupt_operation_mode.
275 * Enable the oscillator to count wake up time for L1 exit. This
276 * consumes slightly more power (100uA) - but allows to be sure
277 * that we wake up from L1 on time.
279 * This looks weird: read twice the same register, discard the
280 * value, set a bit, and yet again, read that same register
281 * just to discard the value. But that's the way the hardware
284 iwl_read_prph(trans
, OSC_CLK
);
285 iwl_read_prph(trans
, OSC_CLK
);
286 iwl_set_bits_prph(trans
, OSC_CLK
, OSC_CLK_FORCE_CONTROL
);
287 iwl_read_prph(trans
, OSC_CLK
);
288 iwl_read_prph(trans
, OSC_CLK
);
292 * Enable DMA clock and wait for it to stabilize.
294 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
295 * bits do not disable clocks. This preserves any hardware
296 * bits already set by default in "CLK_CTRL_REG" after reset.
298 if (trans
->cfg
->device_family
!= IWL_DEVICE_FAMILY_8000
) {
299 iwl_write_prph(trans
, APMG_CLK_EN_REG
,
300 APMG_CLK_VAL_DMA_CLK_RQT
);
303 /* Disable L1-Active */
304 iwl_set_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
305 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
307 /* Clear the interrupt in APMG if the NIC is in RFKILL */
308 iwl_write_prph(trans
, APMG_RTC_INT_STT_REG
,
309 APMG_RTC_INT_STT_RFKILL
);
312 set_bit(STATUS_DEVICE_ENABLED
, &trans
->status
);
319 * Enable LP XTAL to avoid HW bug where device may consume much power if
320 * FW is not loaded after device reset. LP XTAL is disabled by default
321 * after device HW reset. Do it only if XTAL is fed by internal source.
322 * Configure device's "persistence" mode to avoid resetting XTAL again when
323 * SHRD_HW_RST occurs in S3.
325 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans
*trans
)
329 u32 apmg_xtal_cfg_reg
;
333 __iwl_trans_pcie_set_bit(trans
, CSR_GP_CNTRL
,
334 CSR_GP_CNTRL_REG_FLAG_XTAL_ON
);
336 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
337 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
342 * Set "initialization complete" bit to move adapter from
343 * D0U* --> D0A* (powered-up active) state.
345 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
348 * Wait for clock stabilization; once stabilized, access to
349 * device-internal resources is possible.
351 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
352 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
353 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
355 if (WARN_ON(ret
< 0)) {
356 IWL_ERR(trans
, "Access time out - failed to enable LP XTAL\n");
357 /* Release XTAL ON request */
358 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON
);
364 * Clear "disable persistence" to avoid LP XTAL resetting when
365 * SHRD_HW_RST is applied in S3.
367 iwl_clear_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
368 APMG_PCIDEV_STT_VAL_PERSIST_DIS
);
371 * Force APMG XTAL to be active to prevent its disabling by HW
372 * caused by APMG idle state.
374 apmg_xtal_cfg_reg
= iwl_trans_pcie_read_shr(trans
,
375 SHR_APMG_XTAL_CFG_REG
);
376 iwl_trans_pcie_write_shr(trans
, SHR_APMG_XTAL_CFG_REG
,
378 SHR_APMG_XTAL_CFG_XTAL_ON_REQ
);
381 * Reset entire device again - do controller reset (results in
382 * SHRD_HW_RST). Turn MAC off before proceeding.
384 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
388 /* Enable LP XTAL by indirect access through CSR */
389 apmg_gp1_reg
= iwl_trans_pcie_read_shr(trans
, SHR_APMG_GP1_REG
);
390 iwl_trans_pcie_write_shr(trans
, SHR_APMG_GP1_REG
, apmg_gp1_reg
|
391 SHR_APMG_GP1_WF_XTAL_LP_EN
|
392 SHR_APMG_GP1_CHICKEN_BIT_SELECT
);
394 /* Clear delay line clock power up */
395 dl_cfg_reg
= iwl_trans_pcie_read_shr(trans
, SHR_APMG_DL_CFG_REG
);
396 iwl_trans_pcie_write_shr(trans
, SHR_APMG_DL_CFG_REG
, dl_cfg_reg
&
397 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP
);
400 * Enable persistence mode to avoid LP XTAL resetting when
401 * SHRD_HW_RST is applied in S3.
403 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
404 CSR_HW_IF_CONFIG_REG_PERSIST_MODE
);
407 * Clear "initialization complete" bit to move adapter from
408 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
410 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
411 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
413 /* Activates XTAL resources monitor */
414 __iwl_trans_pcie_set_bit(trans
, CSR_MONITOR_CFG_REG
,
415 CSR_MONITOR_XTAL_RESOURCES
);
417 /* Release XTAL ON request */
418 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
419 CSR_GP_CNTRL_REG_FLAG_XTAL_ON
);
422 /* Release APMG XTAL */
423 iwl_trans_pcie_write_shr(trans
, SHR_APMG_XTAL_CFG_REG
,
425 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ
);
428 static int iwl_pcie_apm_stop_master(struct iwl_trans
*trans
)
432 /* stop device's busmaster DMA activity */
433 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_STOP_MASTER
);
435 ret
= iwl_poll_bit(trans
, CSR_RESET
,
436 CSR_RESET_REG_FLAG_MASTER_DISABLED
,
437 CSR_RESET_REG_FLAG_MASTER_DISABLED
, 100);
439 IWL_WARN(trans
, "Master Disable Timed Out, 100 usec\n");
441 IWL_DEBUG_INFO(trans
, "stop master\n");
446 static void iwl_pcie_apm_stop(struct iwl_trans
*trans
)
448 IWL_DEBUG_INFO(trans
, "Stop card, put in low power state\n");
450 clear_bit(STATUS_DEVICE_ENABLED
, &trans
->status
);
452 /* Stop device's DMA activity */
453 iwl_pcie_apm_stop_master(trans
);
455 if (trans
->cfg
->lp_xtal_workaround
) {
456 iwl_pcie_apm_lp_xtal_enable(trans
);
460 /* Reset the entire device */
461 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
466 * Clear "initialization complete" bit to move adapter from
467 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
469 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
470 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
473 static int iwl_pcie_nic_init(struct iwl_trans
*trans
)
475 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
478 spin_lock(&trans_pcie
->irq_lock
);
479 iwl_pcie_apm_init(trans
);
481 spin_unlock(&trans_pcie
->irq_lock
);
483 if (trans
->cfg
->device_family
!= IWL_DEVICE_FAMILY_8000
)
484 iwl_pcie_set_pwr(trans
, false);
486 iwl_op_mode_nic_config(trans
->op_mode
);
488 /* Allocate the RX queue, or reset if it is already allocated */
489 iwl_pcie_rx_init(trans
);
491 /* Allocate or reset and init all Tx and Command queues */
492 if (iwl_pcie_tx_init(trans
))
495 if (trans
->cfg
->base_params
->shadow_reg_enable
) {
496 /* enable shadow regs in HW */
497 iwl_set_bit(trans
, CSR_MAC_SHADOW_REG_CTRL
, 0x800FFFFF);
498 IWL_DEBUG_INFO(trans
, "Enabling shadow registers in device\n");
504 #define HW_READY_TIMEOUT (50)
506 /* Note: returns poll_bit return value, which is >= 0 if success */
507 static int iwl_pcie_set_hw_ready(struct iwl_trans
*trans
)
511 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
512 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
);
514 /* See if we got it */
515 ret
= iwl_poll_bit(trans
, CSR_HW_IF_CONFIG_REG
,
516 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
517 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
521 iwl_set_bit(trans
, CSR_MBOX_SET_REG
, CSR_MBOX_SET_REG_OS_ALIVE
);
523 IWL_DEBUG_INFO(trans
, "hardware%s ready\n", ret
< 0 ? " not" : "");
527 /* Note: returns standard 0/-ERROR code */
528 static int iwl_pcie_prepare_card_hw(struct iwl_trans
*trans
)
534 IWL_DEBUG_INFO(trans
, "iwl_trans_prepare_card_hw enter\n");
536 ret
= iwl_pcie_set_hw_ready(trans
);
537 /* If the card is ready, exit 0 */
541 for (iter
= 0; iter
< 10; iter
++) {
542 /* If HW is not ready, prepare the conditions to check again */
543 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
544 CSR_HW_IF_CONFIG_REG_PREPARE
);
547 ret
= iwl_pcie_set_hw_ready(trans
);
551 usleep_range(200, 1000);
553 } while (t
< 150000);
557 IWL_ERR(trans
, "Couldn't prepare the card\n");
565 static int iwl_pcie_load_firmware_chunk(struct iwl_trans
*trans
, u32 dst_addr
,
566 dma_addr_t phy_addr
, u32 byte_cnt
)
568 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
571 trans_pcie
->ucode_write_complete
= false;
573 iwl_write_direct32(trans
,
574 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
575 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE
);
577 iwl_write_direct32(trans
,
578 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL
),
581 iwl_write_direct32(trans
,
582 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL
),
583 phy_addr
& FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK
);
585 iwl_write_direct32(trans
,
586 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL
),
587 (iwl_get_dma_hi_addr(phy_addr
)
588 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT
) | byte_cnt
);
590 iwl_write_direct32(trans
,
591 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL
),
592 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM
|
593 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX
|
594 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID
);
596 iwl_write_direct32(trans
,
597 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
598 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
599 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE
|
600 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD
);
602 ret
= wait_event_timeout(trans_pcie
->ucode_write_waitq
,
603 trans_pcie
->ucode_write_complete
, 5 * HZ
);
605 IWL_ERR(trans
, "Failed to load firmware chunk!\n");
612 static int iwl_pcie_load_section(struct iwl_trans
*trans
, u8 section_num
,
613 const struct fw_desc
*section
)
617 u32 offset
, chunk_sz
= min_t(u32
, FH_MEM_TB_MAX_LENGTH
, section
->len
);
620 IWL_DEBUG_FW(trans
, "[%d] uCode section being loaded...\n",
623 v_addr
= dma_alloc_coherent(trans
->dev
, chunk_sz
, &p_addr
,
624 GFP_KERNEL
| __GFP_NOWARN
);
626 IWL_DEBUG_INFO(trans
, "Falling back to small chunks of DMA\n");
627 chunk_sz
= PAGE_SIZE
;
628 v_addr
= dma_alloc_coherent(trans
->dev
, chunk_sz
,
629 &p_addr
, GFP_KERNEL
);
634 for (offset
= 0; offset
< section
->len
; offset
+= chunk_sz
) {
635 u32 copy_size
, dst_addr
;
636 bool extended_addr
= false;
638 copy_size
= min_t(u32
, chunk_sz
, section
->len
- offset
);
639 dst_addr
= section
->offset
+ offset
;
641 if (dst_addr
>= IWL_FW_MEM_EXTENDED_START
&&
642 dst_addr
<= IWL_FW_MEM_EXTENDED_END
)
643 extended_addr
= true;
646 iwl_set_bits_prph(trans
, LMPM_CHICK
,
647 LMPM_CHICK_EXTENDED_ADDR_SPACE
);
649 memcpy(v_addr
, (u8
*)section
->data
+ offset
, copy_size
);
650 ret
= iwl_pcie_load_firmware_chunk(trans
, dst_addr
, p_addr
,
654 iwl_clear_bits_prph(trans
, LMPM_CHICK
,
655 LMPM_CHICK_EXTENDED_ADDR_SPACE
);
659 "Could not load the [%d] uCode section\n",
665 dma_free_coherent(trans
->dev
, chunk_sz
, v_addr
, p_addr
);
669 static int iwl_pcie_load_cpu_sections_8000b(struct iwl_trans
*trans
,
670 const struct fw_img
*image
,
672 int *first_ucode_section
)
675 int i
, ret
= 0, sec_num
= 0x1;
676 u32 val
, last_read_idx
= 0;
680 *first_ucode_section
= 0;
683 (*first_ucode_section
)++;
686 for (i
= *first_ucode_section
; i
< IWL_UCODE_SECTION_MAX
; i
++) {
689 if (!image
->sec
[i
].data
||
690 image
->sec
[i
].offset
== CPU1_CPU2_SEPARATOR_SECTION
) {
692 "Break since Data not valid or Empty section, sec = %d\n",
697 ret
= iwl_pcie_load_section(trans
, i
, &image
->sec
[i
]);
701 /* Notify the ucode of the loaded section number and status */
702 val
= iwl_read_direct32(trans
, FH_UCODE_LOAD_STATUS
);
703 val
= val
| (sec_num
<< shift_param
);
704 iwl_write_direct32(trans
, FH_UCODE_LOAD_STATUS
, val
);
705 sec_num
= (sec_num
<< 1) | 0x1;
708 *first_ucode_section
= last_read_idx
;
713 static int iwl_pcie_load_cpu_sections(struct iwl_trans
*trans
,
714 const struct fw_img
*image
,
716 int *first_ucode_section
)
720 u32 last_read_idx
= 0;
724 *first_ucode_section
= 0;
727 (*first_ucode_section
)++;
730 for (i
= *first_ucode_section
; i
< IWL_UCODE_SECTION_MAX
; i
++) {
733 if (!image
->sec
[i
].data
||
734 image
->sec
[i
].offset
== CPU1_CPU2_SEPARATOR_SECTION
) {
736 "Break since Data not valid or Empty section, sec = %d\n",
741 ret
= iwl_pcie_load_section(trans
, i
, &image
->sec
[i
]);
746 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
)
747 iwl_set_bits_prph(trans
,
748 CSR_UCODE_LOAD_STATUS_ADDR
,
749 (LMPM_CPU_UCODE_LOADING_COMPLETED
|
750 LMPM_CPU_HDRS_LOADING_COMPLETED
|
751 LMPM_CPU_UCODE_LOADING_STARTED
) <<
754 *first_ucode_section
= last_read_idx
;
759 static void iwl_pcie_apply_destination(struct iwl_trans
*trans
)
761 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
762 const struct iwl_fw_dbg_dest_tlv
*dest
= trans
->dbg_dest_tlv
;
767 "DBG DEST version is %d - expect issues\n",
770 IWL_INFO(trans
, "Applying debug destination %s\n",
771 get_fw_dbg_mode_string(dest
->monitor_mode
));
773 if (dest
->monitor_mode
== EXTERNAL_MODE
)
774 iwl_pcie_alloc_fw_monitor(trans
);
776 IWL_WARN(trans
, "PCI should have external buffer debug\n");
778 for (i
= 0; i
< trans
->dbg_dest_reg_num
; i
++) {
779 u32 addr
= le32_to_cpu(dest
->reg_ops
[i
].addr
);
780 u32 val
= le32_to_cpu(dest
->reg_ops
[i
].val
);
782 switch (dest
->reg_ops
[i
].op
) {
784 iwl_write32(trans
, addr
, val
);
787 iwl_set_bit(trans
, addr
, BIT(val
));
790 iwl_clear_bit(trans
, addr
, BIT(val
));
793 iwl_write_prph(trans
, addr
, val
);
796 iwl_set_bits_prph(trans
, addr
, BIT(val
));
799 iwl_clear_bits_prph(trans
, addr
, BIT(val
));
802 IWL_ERR(trans
, "FW debug - unknown OP %d\n",
803 dest
->reg_ops
[i
].op
);
808 if (dest
->monitor_mode
== EXTERNAL_MODE
&& trans_pcie
->fw_mon_size
) {
809 iwl_write_prph(trans
, le32_to_cpu(dest
->base_reg
),
810 trans_pcie
->fw_mon_phys
>> dest
->base_shift
);
811 iwl_write_prph(trans
, le32_to_cpu(dest
->end_reg
),
812 (trans_pcie
->fw_mon_phys
+
813 trans_pcie
->fw_mon_size
) >> dest
->end_shift
);
817 static int iwl_pcie_load_given_ucode(struct iwl_trans
*trans
,
818 const struct fw_img
*image
)
820 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
822 int first_ucode_section
;
824 IWL_DEBUG_FW(trans
, "working with %s CPU\n",
825 image
->is_dual_cpus
? "Dual" : "Single");
827 /* load to FW the binary non secured sections of CPU1 */
828 ret
= iwl_pcie_load_cpu_sections(trans
, image
, 1, &first_ucode_section
);
832 if (image
->is_dual_cpus
) {
833 /* set CPU2 header address */
834 iwl_write_prph(trans
,
835 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR
,
836 LMPM_SECURE_CPU2_HDR_MEM_SPACE
);
838 /* load to FW the binary sections of CPU2 */
839 ret
= iwl_pcie_load_cpu_sections(trans
, image
, 2,
840 &first_ucode_section
);
845 /* supported for 7000 only for the moment */
846 if (iwlwifi_mod_params
.fw_monitor
&&
847 trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_7000
) {
848 iwl_pcie_alloc_fw_monitor(trans
);
850 if (trans_pcie
->fw_mon_size
) {
851 iwl_write_prph(trans
, MON_BUFF_BASE_ADDR
,
852 trans_pcie
->fw_mon_phys
>> 4);
853 iwl_write_prph(trans
, MON_BUFF_END_ADDR
,
854 (trans_pcie
->fw_mon_phys
+
855 trans_pcie
->fw_mon_size
) >> 4);
857 } else if (trans
->dbg_dest_tlv
) {
858 iwl_pcie_apply_destination(trans
);
861 /* release CPU reset */
862 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
)
863 iwl_write_prph(trans
, RELEASE_CPU_RESET
, RELEASE_CPU_RESET_BIT
);
865 iwl_write32(trans
, CSR_RESET
, 0);
870 static int iwl_pcie_load_given_ucode_8000b(struct iwl_trans
*trans
,
871 const struct fw_img
*image
)
874 int first_ucode_section
;
877 IWL_DEBUG_FW(trans
, "working with %s CPU\n",
878 image
->is_dual_cpus
? "Dual" : "Single");
880 /* configure the ucode to be ready to get the secured image */
881 /* release CPU reset */
882 iwl_write_prph(trans
, RELEASE_CPU_RESET
, RELEASE_CPU_RESET_BIT
);
884 /* load to FW the binary Secured sections of CPU1 */
885 ret
= iwl_pcie_load_cpu_sections_8000b(trans
, image
, 1,
886 &first_ucode_section
);
890 /* load to FW the binary sections of CPU2 */
891 ret
= iwl_pcie_load_cpu_sections_8000b(trans
, image
, 2,
892 &first_ucode_section
);
896 /* Notify FW loading is done */
897 iwl_write_direct32(trans
, FH_UCODE_LOAD_STATUS
, 0xFFFFFFFF);
899 /* wait for image verification to complete */
900 ret
= iwl_poll_prph_bit(trans
, LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0
,
901 LMPM_SECURE_BOOT_STATUS_SUCCESS
,
902 LMPM_SECURE_BOOT_STATUS_SUCCESS
,
903 LMPM_SECURE_TIME_OUT
);
905 reg
= iwl_read_prph(trans
,
906 LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0
);
908 IWL_ERR(trans
, "Timeout on secure boot process, reg = %x\n",
916 static int iwl_trans_pcie_start_fw(struct iwl_trans
*trans
,
917 const struct fw_img
*fw
, bool run_in_rfkill
)
922 /* This may fail if AMT took ownership of the device */
923 if (iwl_pcie_prepare_card_hw(trans
)) {
924 IWL_WARN(trans
, "Exit HW not ready\n");
928 iwl_enable_rfkill_int(trans
);
930 /* If platform's RF_KILL switch is NOT set to KILL */
931 hw_rfkill
= iwl_is_rfkill_set(trans
);
933 set_bit(STATUS_RFKILL
, &trans
->status
);
935 clear_bit(STATUS_RFKILL
, &trans
->status
);
936 iwl_trans_pcie_rf_kill(trans
, hw_rfkill
);
937 if (hw_rfkill
&& !run_in_rfkill
)
940 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
942 ret
= iwl_pcie_nic_init(trans
);
944 IWL_ERR(trans
, "Unable to init nic\n");
948 /* make sure rfkill handshake bits are cleared */
949 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
950 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
,
951 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED
);
953 /* clear (again), then enable host interrupts */
954 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
955 iwl_enable_interrupts(trans
);
957 /* really make sure rfkill handshake bits are cleared */
958 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
959 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
961 /* Load the given image to the HW */
962 if ((trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
) &&
963 (CSR_HW_REV_STEP(trans
->hw_rev
) == SILICON_B_STEP
))
964 return iwl_pcie_load_given_ucode_8000b(trans
, fw
);
966 return iwl_pcie_load_given_ucode(trans
, fw
);
969 static void iwl_trans_pcie_fw_alive(struct iwl_trans
*trans
, u32 scd_addr
)
971 iwl_pcie_reset_ict(trans
);
972 iwl_pcie_tx_start(trans
, scd_addr
);
975 static void iwl_trans_pcie_stop_device(struct iwl_trans
*trans
)
977 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
978 bool hw_rfkill
, was_hw_rfkill
;
980 was_hw_rfkill
= iwl_is_rfkill_set(trans
);
982 /* tell the device to stop sending interrupts */
983 spin_lock(&trans_pcie
->irq_lock
);
984 iwl_disable_interrupts(trans
);
985 spin_unlock(&trans_pcie
->irq_lock
);
987 /* device going down, Stop using ICT table */
988 iwl_pcie_disable_ict(trans
);
991 * If a HW restart happens during firmware loading,
992 * then the firmware loading might call this function
993 * and later it might be called again due to the
994 * restart. So don't process again if the device is
997 if (test_and_clear_bit(STATUS_DEVICE_ENABLED
, &trans
->status
)) {
998 IWL_DEBUG_INFO(trans
, "DEVICE_ENABLED bit was set and is now cleared\n");
999 iwl_pcie_tx_stop(trans
);
1000 iwl_pcie_rx_stop(trans
);
1002 /* Power-down device's busmaster DMA clocks */
1003 iwl_write_prph(trans
, APMG_CLK_DIS_REG
,
1004 APMG_CLK_VAL_DMA_CLK_RQT
);
1008 /* Make sure (redundant) we've released our request to stay awake */
1009 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1010 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1012 /* Stop the device, and put it in low power state */
1013 iwl_pcie_apm_stop(trans
);
1015 /* stop and reset the on-board processor */
1016 iwl_write32(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
1020 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1021 * This is a bug in certain verions of the hardware.
1022 * Certain devices also keep sending HW RF kill interrupt all
1023 * the time, unless the interrupt is ACKed even if the interrupt
1024 * should be masked. Re-ACK all the interrupts here.
1026 spin_lock(&trans_pcie
->irq_lock
);
1027 iwl_disable_interrupts(trans
);
1028 spin_unlock(&trans_pcie
->irq_lock
);
1031 /* clear all status bits */
1032 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1033 clear_bit(STATUS_INT_ENABLED
, &trans
->status
);
1034 clear_bit(STATUS_TPOWER_PMI
, &trans
->status
);
1035 clear_bit(STATUS_RFKILL
, &trans
->status
);
1038 * Even if we stop the HW, we still want the RF kill
1041 iwl_enable_rfkill_int(trans
);
1044 * Check again since the RF kill state may have changed while
1045 * all the interrupts were disabled, in this case we couldn't
1046 * receive the RF kill interrupt and update the state in the
1048 * Don't call the op_mode if the rkfill state hasn't changed.
1049 * This allows the op_mode to call stop_device from the rfkill
1050 * notification without endless recursion. Under very rare
1051 * circumstances, we might have a small recursion if the rfkill
1052 * state changed exactly now while we were called from stop_device.
1053 * This is very unlikely but can happen and is supported.
1055 hw_rfkill
= iwl_is_rfkill_set(trans
);
1057 set_bit(STATUS_RFKILL
, &trans
->status
);
1059 clear_bit(STATUS_RFKILL
, &trans
->status
);
1060 if (hw_rfkill
!= was_hw_rfkill
)
1061 iwl_trans_pcie_rf_kill(trans
, hw_rfkill
);
1063 /* re-take ownership to prevent other users from stealing the deivce */
1064 iwl_pcie_prepare_card_hw(trans
);
1067 void iwl_trans_pcie_rf_kill(struct iwl_trans
*trans
, bool state
)
1069 if (iwl_op_mode_hw_rf_kill(trans
->op_mode
, state
))
1070 iwl_trans_pcie_stop_device(trans
);
1073 static void iwl_trans_pcie_d3_suspend(struct iwl_trans
*trans
, bool test
)
1075 iwl_disable_interrupts(trans
);
1078 * in testing mode, the host stays awake and the
1079 * hardware won't be reset (not even partially)
1084 iwl_pcie_disable_ict(trans
);
1086 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1087 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1088 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1089 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
1092 * reset TX queues -- some of their registers reset during S3
1093 * so if we don't reset everything here the D3 image would try
1094 * to execute some invalid memory upon resume
1096 iwl_trans_pcie_tx_reset(trans
);
1098 iwl_pcie_set_pwr(trans
, true);
1101 static int iwl_trans_pcie_d3_resume(struct iwl_trans
*trans
,
1102 enum iwl_d3_status
*status
,
1109 iwl_enable_interrupts(trans
);
1110 *status
= IWL_D3_STATUS_ALIVE
;
1115 * Also enables interrupts - none will happen as the device doesn't
1116 * know we're waking it up, only when the opmode actually tells it
1119 iwl_pcie_reset_ict(trans
);
1121 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1122 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
1124 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
)
1127 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
1128 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
1129 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
1132 IWL_ERR(trans
, "Failed to resume the device (mac ready)\n");
1136 iwl_pcie_set_pwr(trans
, false);
1138 iwl_trans_pcie_tx_reset(trans
);
1140 ret
= iwl_pcie_rx_init(trans
);
1142 IWL_ERR(trans
, "Failed to resume the device (RX reset)\n");
1146 val
= iwl_read32(trans
, CSR_RESET
);
1147 if (val
& CSR_RESET_REG_FLAG_NEVO_RESET
)
1148 *status
= IWL_D3_STATUS_RESET
;
1150 *status
= IWL_D3_STATUS_ALIVE
;
1155 static int iwl_trans_pcie_start_hw(struct iwl_trans
*trans
)
1160 err
= iwl_pcie_prepare_card_hw(trans
);
1162 IWL_ERR(trans
, "Error while preparing HW: %d\n", err
);
1166 /* Reset the entire device */
1167 iwl_write32(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
1169 usleep_range(10, 15);
1171 iwl_pcie_apm_init(trans
);
1173 /* From now on, the op_mode will be kept updated about RF kill state */
1174 iwl_enable_rfkill_int(trans
);
1176 hw_rfkill
= iwl_is_rfkill_set(trans
);
1178 set_bit(STATUS_RFKILL
, &trans
->status
);
1180 clear_bit(STATUS_RFKILL
, &trans
->status
);
1181 iwl_trans_pcie_rf_kill(trans
, hw_rfkill
);
1186 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans
*trans
)
1188 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1190 /* disable interrupts - don't enable HW RF kill interrupt */
1191 spin_lock(&trans_pcie
->irq_lock
);
1192 iwl_disable_interrupts(trans
);
1193 spin_unlock(&trans_pcie
->irq_lock
);
1195 iwl_pcie_apm_stop(trans
);
1197 spin_lock(&trans_pcie
->irq_lock
);
1198 iwl_disable_interrupts(trans
);
1199 spin_unlock(&trans_pcie
->irq_lock
);
1201 iwl_pcie_disable_ict(trans
);
1204 static void iwl_trans_pcie_write8(struct iwl_trans
*trans
, u32 ofs
, u8 val
)
1206 writeb(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1209 static void iwl_trans_pcie_write32(struct iwl_trans
*trans
, u32 ofs
, u32 val
)
1211 writel(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1214 static u32
iwl_trans_pcie_read32(struct iwl_trans
*trans
, u32 ofs
)
1216 return readl(IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1219 static u32
iwl_trans_pcie_read_prph(struct iwl_trans
*trans
, u32 reg
)
1221 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_RADDR
,
1222 ((reg
& 0x000FFFFF) | (3 << 24)));
1223 return iwl_trans_pcie_read32(trans
, HBUS_TARG_PRPH_RDAT
);
1226 static void iwl_trans_pcie_write_prph(struct iwl_trans
*trans
, u32 addr
,
1229 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_WADDR
,
1230 ((addr
& 0x000FFFFF) | (3 << 24)));
1231 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_WDAT
, val
);
1234 static int iwl_pcie_dummy_napi_poll(struct napi_struct
*napi
, int budget
)
1240 static void iwl_trans_pcie_configure(struct iwl_trans
*trans
,
1241 const struct iwl_trans_config
*trans_cfg
)
1243 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1245 trans_pcie
->cmd_queue
= trans_cfg
->cmd_queue
;
1246 trans_pcie
->cmd_fifo
= trans_cfg
->cmd_fifo
;
1247 if (WARN_ON(trans_cfg
->n_no_reclaim_cmds
> MAX_NO_RECLAIM_CMDS
))
1248 trans_pcie
->n_no_reclaim_cmds
= 0;
1250 trans_pcie
->n_no_reclaim_cmds
= trans_cfg
->n_no_reclaim_cmds
;
1251 if (trans_pcie
->n_no_reclaim_cmds
)
1252 memcpy(trans_pcie
->no_reclaim_cmds
, trans_cfg
->no_reclaim_cmds
,
1253 trans_pcie
->n_no_reclaim_cmds
* sizeof(u8
));
1255 trans_pcie
->rx_buf_size_8k
= trans_cfg
->rx_buf_size_8k
;
1256 if (trans_pcie
->rx_buf_size_8k
)
1257 trans_pcie
->rx_page_order
= get_order(8 * 1024);
1259 trans_pcie
->rx_page_order
= get_order(4 * 1024);
1261 trans_pcie
->wd_timeout
=
1262 msecs_to_jiffies(trans_cfg
->queue_watchdog_timeout
);
1264 trans_pcie
->command_names
= trans_cfg
->command_names
;
1265 trans_pcie
->bc_table_dword
= trans_cfg
->bc_table_dword
;
1266 trans_pcie
->scd_set_active
= trans_cfg
->scd_set_active
;
1268 /* Initialize NAPI here - it should be before registering to mac80211
1269 * in the opmode but after the HW struct is allocated.
1270 * As this function may be called again in some corner cases don't
1271 * do anything if NAPI was already initialized.
1273 if (!trans_pcie
->napi
.poll
&& trans
->op_mode
->ops
->napi_add
) {
1274 init_dummy_netdev(&trans_pcie
->napi_dev
);
1275 iwl_op_mode_napi_add(trans
->op_mode
, &trans_pcie
->napi
,
1276 &trans_pcie
->napi_dev
,
1277 iwl_pcie_dummy_napi_poll
, 64);
1281 void iwl_trans_pcie_free(struct iwl_trans
*trans
)
1283 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1285 synchronize_irq(trans_pcie
->pci_dev
->irq
);
1287 iwl_pcie_tx_free(trans
);
1288 iwl_pcie_rx_free(trans
);
1290 free_irq(trans_pcie
->pci_dev
->irq
, trans
);
1291 iwl_pcie_free_ict(trans
);
1293 pci_disable_msi(trans_pcie
->pci_dev
);
1294 iounmap(trans_pcie
->hw_base
);
1295 pci_release_regions(trans_pcie
->pci_dev
);
1296 pci_disable_device(trans_pcie
->pci_dev
);
1297 kmem_cache_destroy(trans
->dev_cmd_pool
);
1299 if (trans_pcie
->napi
.poll
)
1300 netif_napi_del(&trans_pcie
->napi
);
1302 iwl_pcie_free_fw_monitor(trans
);
1307 static void iwl_trans_pcie_set_pmi(struct iwl_trans
*trans
, bool state
)
1310 set_bit(STATUS_TPOWER_PMI
, &trans
->status
);
1312 clear_bit(STATUS_TPOWER_PMI
, &trans
->status
);
1315 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans
*trans
, bool silent
,
1316 unsigned long *flags
)
1319 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1321 spin_lock_irqsave(&trans_pcie
->reg_lock
, *flags
);
1323 if (trans_pcie
->cmd_in_flight
)
1326 /* this bit wakes up the NIC */
1327 __iwl_trans_pcie_set_bit(trans
, CSR_GP_CNTRL
,
1328 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1329 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
)
1333 * These bits say the device is running, and should keep running for
1334 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1335 * but they do not indicate that embedded SRAM is restored yet;
1336 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1337 * to/from host DRAM when sleeping/waking for power-saving.
1338 * Each direction takes approximately 1/4 millisecond; with this
1339 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1340 * series of register accesses are expected (e.g. reading Event Log),
1341 * to keep device from sleeping.
1343 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1344 * SRAM is okay/restored. We don't check that here because this call
1345 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1346 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1348 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1349 * and do not save/restore SRAM when power cycling.
1351 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
1352 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN
,
1353 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
|
1354 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP
), 15000);
1355 if (unlikely(ret
< 0)) {
1356 iwl_write32(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_FORCE_NMI
);
1358 u32 val
= iwl_read32(trans
, CSR_GP_CNTRL
);
1360 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1362 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, *flags
);
1369 * Fool sparse by faking we release the lock - sparse will
1370 * track nic_access anyway.
1372 __release(&trans_pcie
->reg_lock
);
1376 static void iwl_trans_pcie_release_nic_access(struct iwl_trans
*trans
,
1377 unsigned long *flags
)
1379 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1381 lockdep_assert_held(&trans_pcie
->reg_lock
);
1384 * Fool sparse by faking we acquiring the lock - sparse will
1385 * track nic_access anyway.
1387 __acquire(&trans_pcie
->reg_lock
);
1389 if (trans_pcie
->cmd_in_flight
)
1392 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
1393 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1395 * Above we read the CSR_GP_CNTRL register, which will flush
1396 * any previous writes, but we need the write that clears the
1397 * MAC_ACCESS_REQ bit to be performed before any other writes
1398 * scheduled on different CPUs (after we drop reg_lock).
1402 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, *flags
);
1405 static int iwl_trans_pcie_read_mem(struct iwl_trans
*trans
, u32 addr
,
1406 void *buf
, int dwords
)
1408 unsigned long flags
;
1412 if (iwl_trans_grab_nic_access(trans
, false, &flags
)) {
1413 iwl_write32(trans
, HBUS_TARG_MEM_RADDR
, addr
);
1414 for (offs
= 0; offs
< dwords
; offs
++)
1415 vals
[offs
] = iwl_read32(trans
, HBUS_TARG_MEM_RDAT
);
1416 iwl_trans_release_nic_access(trans
, &flags
);
1423 static int iwl_trans_pcie_write_mem(struct iwl_trans
*trans
, u32 addr
,
1424 const void *buf
, int dwords
)
1426 unsigned long flags
;
1428 const u32
*vals
= buf
;
1430 if (iwl_trans_grab_nic_access(trans
, false, &flags
)) {
1431 iwl_write32(trans
, HBUS_TARG_MEM_WADDR
, addr
);
1432 for (offs
= 0; offs
< dwords
; offs
++)
1433 iwl_write32(trans
, HBUS_TARG_MEM_WDAT
,
1434 vals
? vals
[offs
] : 0);
1435 iwl_trans_release_nic_access(trans
, &flags
);
1442 #define IWL_FLUSH_WAIT_MS 2000
1444 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans
*trans
, u32 txq_bm
)
1446 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1447 struct iwl_txq
*txq
;
1448 struct iwl_queue
*q
;
1450 unsigned long now
= jiffies
;
1455 /* waiting for all the tx frames complete might take a while */
1456 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
1459 if (cnt
== trans_pcie
->cmd_queue
)
1461 if (!test_bit(cnt
, trans_pcie
->queue_used
))
1463 if (!(BIT(cnt
) & txq_bm
))
1466 IWL_DEBUG_TX_QUEUES(trans
, "Emptying queue %d...\n", cnt
);
1467 txq
= &trans_pcie
->txq
[cnt
];
1469 wr_ptr
= ACCESS_ONCE(q
->write_ptr
);
1471 while (q
->read_ptr
!= ACCESS_ONCE(q
->write_ptr
) &&
1472 !time_after(jiffies
,
1473 now
+ msecs_to_jiffies(IWL_FLUSH_WAIT_MS
))) {
1474 u8 write_ptr
= ACCESS_ONCE(q
->write_ptr
);
1476 if (WARN_ONCE(wr_ptr
!= write_ptr
,
1477 "WR pointer moved while flushing %d -> %d\n",
1483 if (q
->read_ptr
!= q
->write_ptr
) {
1485 "fail to flush all tx fifo queues Q %d\n", cnt
);
1489 IWL_DEBUG_TX_QUEUES(trans
, "Queue %d is now empty.\n", cnt
);
1495 IWL_ERR(trans
, "Current SW read_ptr %d write_ptr %d\n",
1496 txq
->q
.read_ptr
, txq
->q
.write_ptr
);
1498 scd_sram_addr
= trans_pcie
->scd_base_addr
+
1499 SCD_TX_STTS_QUEUE_OFFSET(txq
->q
.id
);
1500 iwl_trans_read_mem_bytes(trans
, scd_sram_addr
, buf
, sizeof(buf
));
1502 iwl_print_hex_error(trans
, buf
, sizeof(buf
));
1504 for (cnt
= 0; cnt
< FH_TCSR_CHNL_NUM
; cnt
++)
1505 IWL_ERR(trans
, "FH TRBs(%d) = 0x%08x\n", cnt
,
1506 iwl_read_direct32(trans
, FH_TX_TRB_REG(cnt
)));
1508 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
1509 u32 status
= iwl_read_prph(trans
, SCD_QUEUE_STATUS_BITS(cnt
));
1510 u8 fifo
= (status
>> SCD_QUEUE_STTS_REG_POS_TXF
) & 0x7;
1511 bool active
= !!(status
& BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE
));
1513 iwl_trans_read_mem32(trans
, trans_pcie
->scd_base_addr
+
1514 SCD_TRANS_TBL_OFFSET_QUEUE(cnt
));
1517 tbl_dw
= (tbl_dw
& 0xFFFF0000) >> 16;
1519 tbl_dw
= tbl_dw
& 0x0000FFFF;
1522 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1523 cnt
, active
? "" : "in", fifo
, tbl_dw
,
1524 iwl_read_prph(trans
, SCD_QUEUE_RDPTR(cnt
)) &
1525 (TFD_QUEUE_SIZE_MAX
- 1),
1526 iwl_read_prph(trans
, SCD_QUEUE_WRPTR(cnt
)));
1532 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans
*trans
, u32 reg
,
1533 u32 mask
, u32 value
)
1535 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1536 unsigned long flags
;
1538 spin_lock_irqsave(&trans_pcie
->reg_lock
, flags
);
1539 __iwl_trans_pcie_set_bits_mask(trans
, reg
, mask
, value
);
1540 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
1543 static const char *get_csr_string(int cmd
)
1545 #define IWL_CMD(x) case x: return #x
1547 IWL_CMD(CSR_HW_IF_CONFIG_REG
);
1548 IWL_CMD(CSR_INT_COALESCING
);
1550 IWL_CMD(CSR_INT_MASK
);
1551 IWL_CMD(CSR_FH_INT_STATUS
);
1552 IWL_CMD(CSR_GPIO_IN
);
1554 IWL_CMD(CSR_GP_CNTRL
);
1555 IWL_CMD(CSR_HW_REV
);
1556 IWL_CMD(CSR_EEPROM_REG
);
1557 IWL_CMD(CSR_EEPROM_GP
);
1558 IWL_CMD(CSR_OTP_GP_REG
);
1559 IWL_CMD(CSR_GIO_REG
);
1560 IWL_CMD(CSR_GP_UCODE_REG
);
1561 IWL_CMD(CSR_GP_DRIVER_REG
);
1562 IWL_CMD(CSR_UCODE_DRV_GP1
);
1563 IWL_CMD(CSR_UCODE_DRV_GP2
);
1564 IWL_CMD(CSR_LED_REG
);
1565 IWL_CMD(CSR_DRAM_INT_TBL_REG
);
1566 IWL_CMD(CSR_GIO_CHICKEN_BITS
);
1567 IWL_CMD(CSR_ANA_PLL_CFG
);
1568 IWL_CMD(CSR_HW_REV_WA_REG
);
1569 IWL_CMD(CSR_MONITOR_STATUS_REG
);
1570 IWL_CMD(CSR_DBG_HPET_MEM_REG
);
1577 void iwl_pcie_dump_csr(struct iwl_trans
*trans
)
1580 static const u32 csr_tbl
[] = {
1581 CSR_HW_IF_CONFIG_REG
,
1599 CSR_DRAM_INT_TBL_REG
,
1600 CSR_GIO_CHICKEN_BITS
,
1602 CSR_MONITOR_STATUS_REG
,
1604 CSR_DBG_HPET_MEM_REG
1606 IWL_ERR(trans
, "CSR values:\n");
1607 IWL_ERR(trans
, "(2nd byte of CSR_INT_COALESCING is "
1608 "CSR_INT_PERIODIC_REG)\n");
1609 for (i
= 0; i
< ARRAY_SIZE(csr_tbl
); i
++) {
1610 IWL_ERR(trans
, " %25s: 0X%08x\n",
1611 get_csr_string(csr_tbl
[i
]),
1612 iwl_read32(trans
, csr_tbl
[i
]));
1616 #ifdef CONFIG_IWLWIFI_DEBUGFS
1617 /* create and remove of files */
1618 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1619 if (!debugfs_create_file(#name, mode, parent, trans, \
1620 &iwl_dbgfs_##name##_ops)) \
1624 /* file operation */
1625 #define DEBUGFS_READ_FILE_OPS(name) \
1626 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1627 .read = iwl_dbgfs_##name##_read, \
1628 .open = simple_open, \
1629 .llseek = generic_file_llseek, \
1632 #define DEBUGFS_WRITE_FILE_OPS(name) \
1633 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1634 .write = iwl_dbgfs_##name##_write, \
1635 .open = simple_open, \
1636 .llseek = generic_file_llseek, \
1639 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1640 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1641 .write = iwl_dbgfs_##name##_write, \
1642 .read = iwl_dbgfs_##name##_read, \
1643 .open = simple_open, \
1644 .llseek = generic_file_llseek, \
1647 static ssize_t
iwl_dbgfs_tx_queue_read(struct file
*file
,
1648 char __user
*user_buf
,
1649 size_t count
, loff_t
*ppos
)
1651 struct iwl_trans
*trans
= file
->private_data
;
1652 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1653 struct iwl_txq
*txq
;
1654 struct iwl_queue
*q
;
1661 bufsz
= sizeof(char) * 64 * trans
->cfg
->base_params
->num_of_queues
;
1663 if (!trans_pcie
->txq
)
1666 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1670 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
1671 txq
= &trans_pcie
->txq
[cnt
];
1673 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1674 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d%s\n",
1675 cnt
, q
->read_ptr
, q
->write_ptr
,
1676 !!test_bit(cnt
, trans_pcie
->queue_used
),
1677 !!test_bit(cnt
, trans_pcie
->queue_stopped
),
1679 (cnt
== trans_pcie
->cmd_queue
? " HCMD" : ""));
1681 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1686 static ssize_t
iwl_dbgfs_rx_queue_read(struct file
*file
,
1687 char __user
*user_buf
,
1688 size_t count
, loff_t
*ppos
)
1690 struct iwl_trans
*trans
= file
->private_data
;
1691 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1692 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
;
1695 const size_t bufsz
= sizeof(buf
);
1697 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "read: %u\n",
1699 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "write: %u\n",
1701 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "write_actual: %u\n",
1703 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "need_update: %d\n",
1705 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "free_count: %u\n",
1708 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "closed_rb_num: %u\n",
1709 le16_to_cpu(rxq
->rb_stts
->closed_rb_num
) & 0x0FFF);
1711 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1712 "closed_rb_num: Not Allocated\n");
1714 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1717 static ssize_t
iwl_dbgfs_interrupt_read(struct file
*file
,
1718 char __user
*user_buf
,
1719 size_t count
, loff_t
*ppos
)
1721 struct iwl_trans
*trans
= file
->private_data
;
1722 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1723 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
1727 int bufsz
= 24 * 64; /* 24 items * 64 char per item */
1730 buf
= kzalloc(bufsz
, GFP_KERNEL
);
1734 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1735 "Interrupt Statistics Report:\n");
1737 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "HW Error:\t\t\t %u\n",
1739 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "SW Error:\t\t\t %u\n",
1741 if (isr_stats
->sw
|| isr_stats
->hw
) {
1742 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1743 "\tLast Restarting Code: 0x%X\n",
1744 isr_stats
->err_code
);
1746 #ifdef CONFIG_IWLWIFI_DEBUG
1747 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Frame transmitted:\t\t %u\n",
1749 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Alive interrupt:\t\t %u\n",
1752 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1753 "HW RF KILL switch toggled:\t %u\n", isr_stats
->rfkill
);
1755 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "CT KILL:\t\t\t %u\n",
1758 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Wakeup Interrupt:\t\t %u\n",
1761 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
1762 "Rx command responses:\t\t %u\n", isr_stats
->rx
);
1764 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Tx/FH interrupt:\t\t %u\n",
1767 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Unexpected INTA:\t\t %u\n",
1768 isr_stats
->unhandled
);
1770 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
1775 static ssize_t
iwl_dbgfs_interrupt_write(struct file
*file
,
1776 const char __user
*user_buf
,
1777 size_t count
, loff_t
*ppos
)
1779 struct iwl_trans
*trans
= file
->private_data
;
1780 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1781 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
1787 memset(buf
, 0, sizeof(buf
));
1788 buf_size
= min(count
, sizeof(buf
) - 1);
1789 if (copy_from_user(buf
, user_buf
, buf_size
))
1791 if (sscanf(buf
, "%x", &reset_flag
) != 1)
1793 if (reset_flag
== 0)
1794 memset(isr_stats
, 0, sizeof(*isr_stats
));
1799 static ssize_t
iwl_dbgfs_csr_write(struct file
*file
,
1800 const char __user
*user_buf
,
1801 size_t count
, loff_t
*ppos
)
1803 struct iwl_trans
*trans
= file
->private_data
;
1808 memset(buf
, 0, sizeof(buf
));
1809 buf_size
= min(count
, sizeof(buf
) - 1);
1810 if (copy_from_user(buf
, user_buf
, buf_size
))
1812 if (sscanf(buf
, "%d", &csr
) != 1)
1815 iwl_pcie_dump_csr(trans
);
1820 static ssize_t
iwl_dbgfs_fh_reg_read(struct file
*file
,
1821 char __user
*user_buf
,
1822 size_t count
, loff_t
*ppos
)
1824 struct iwl_trans
*trans
= file
->private_data
;
1828 ret
= iwl_dump_fh(trans
, &buf
);
1833 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, ret
);
1838 DEBUGFS_READ_WRITE_FILE_OPS(interrupt
);
1839 DEBUGFS_READ_FILE_OPS(fh_reg
);
1840 DEBUGFS_READ_FILE_OPS(rx_queue
);
1841 DEBUGFS_READ_FILE_OPS(tx_queue
);
1842 DEBUGFS_WRITE_FILE_OPS(csr
);
1845 * Create the debugfs files and directories
1848 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
,
1851 DEBUGFS_ADD_FILE(rx_queue
, dir
, S_IRUSR
);
1852 DEBUGFS_ADD_FILE(tx_queue
, dir
, S_IRUSR
);
1853 DEBUGFS_ADD_FILE(interrupt
, dir
, S_IWUSR
| S_IRUSR
);
1854 DEBUGFS_ADD_FILE(csr
, dir
, S_IWUSR
);
1855 DEBUGFS_ADD_FILE(fh_reg
, dir
, S_IRUSR
);
1859 IWL_ERR(trans
, "failed to create the trans debugfs entry\n");
1863 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
,
1868 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1870 static u32
iwl_trans_pcie_get_cmdlen(struct iwl_tfd
*tfd
)
1875 for (i
= 0; i
< IWL_NUM_OF_TBS
; i
++)
1876 cmdlen
+= iwl_pcie_tfd_tb_get_len(tfd
, i
);
1881 static const struct {
1883 } iwl_prph_dump_addr
[] = {
1884 { .start
= 0x00a00000, .end
= 0x00a00000 },
1885 { .start
= 0x00a0000c, .end
= 0x00a00024 },
1886 { .start
= 0x00a0002c, .end
= 0x00a0003c },
1887 { .start
= 0x00a00410, .end
= 0x00a00418 },
1888 { .start
= 0x00a00420, .end
= 0x00a00420 },
1889 { .start
= 0x00a00428, .end
= 0x00a00428 },
1890 { .start
= 0x00a00430, .end
= 0x00a0043c },
1891 { .start
= 0x00a00444, .end
= 0x00a00444 },
1892 { .start
= 0x00a004c0, .end
= 0x00a004cc },
1893 { .start
= 0x00a004d8, .end
= 0x00a004d8 },
1894 { .start
= 0x00a004e0, .end
= 0x00a004f0 },
1895 { .start
= 0x00a00840, .end
= 0x00a00840 },
1896 { .start
= 0x00a00850, .end
= 0x00a00858 },
1897 { .start
= 0x00a01004, .end
= 0x00a01008 },
1898 { .start
= 0x00a01010, .end
= 0x00a01010 },
1899 { .start
= 0x00a01018, .end
= 0x00a01018 },
1900 { .start
= 0x00a01024, .end
= 0x00a01024 },
1901 { .start
= 0x00a0102c, .end
= 0x00a01034 },
1902 { .start
= 0x00a0103c, .end
= 0x00a01040 },
1903 { .start
= 0x00a01048, .end
= 0x00a01094 },
1904 { .start
= 0x00a01c00, .end
= 0x00a01c20 },
1905 { .start
= 0x00a01c58, .end
= 0x00a01c58 },
1906 { .start
= 0x00a01c7c, .end
= 0x00a01c7c },
1907 { .start
= 0x00a01c28, .end
= 0x00a01c54 },
1908 { .start
= 0x00a01c5c, .end
= 0x00a01c5c },
1909 { .start
= 0x00a01c84, .end
= 0x00a01c84 },
1910 { .start
= 0x00a01ce0, .end
= 0x00a01d0c },
1911 { .start
= 0x00a01d18, .end
= 0x00a01d20 },
1912 { .start
= 0x00a01d2c, .end
= 0x00a01d30 },
1913 { .start
= 0x00a01d40, .end
= 0x00a01d5c },
1914 { .start
= 0x00a01d80, .end
= 0x00a01d80 },
1915 { .start
= 0x00a01d98, .end
= 0x00a01d98 },
1916 { .start
= 0x00a01dc0, .end
= 0x00a01dfc },
1917 { .start
= 0x00a01e00, .end
= 0x00a01e2c },
1918 { .start
= 0x00a01e40, .end
= 0x00a01e60 },
1919 { .start
= 0x00a01e84, .end
= 0x00a01e90 },
1920 { .start
= 0x00a01e9c, .end
= 0x00a01ec4 },
1921 { .start
= 0x00a01ed0, .end
= 0x00a01ed0 },
1922 { .start
= 0x00a01f00, .end
= 0x00a01f14 },
1923 { .start
= 0x00a01f44, .end
= 0x00a01f58 },
1924 { .start
= 0x00a01f80, .end
= 0x00a01fa8 },
1925 { .start
= 0x00a01fb0, .end
= 0x00a01fbc },
1926 { .start
= 0x00a01ff8, .end
= 0x00a01ffc },
1927 { .start
= 0x00a02000, .end
= 0x00a02048 },
1928 { .start
= 0x00a02068, .end
= 0x00a020f0 },
1929 { .start
= 0x00a02100, .end
= 0x00a02118 },
1930 { .start
= 0x00a02140, .end
= 0x00a0214c },
1931 { .start
= 0x00a02168, .end
= 0x00a0218c },
1932 { .start
= 0x00a021c0, .end
= 0x00a021c0 },
1933 { .start
= 0x00a02400, .end
= 0x00a02410 },
1934 { .start
= 0x00a02418, .end
= 0x00a02420 },
1935 { .start
= 0x00a02428, .end
= 0x00a0242c },
1936 { .start
= 0x00a02434, .end
= 0x00a02434 },
1937 { .start
= 0x00a02440, .end
= 0x00a02460 },
1938 { .start
= 0x00a02468, .end
= 0x00a024b0 },
1939 { .start
= 0x00a024c8, .end
= 0x00a024cc },
1940 { .start
= 0x00a02500, .end
= 0x00a02504 },
1941 { .start
= 0x00a0250c, .end
= 0x00a02510 },
1942 { .start
= 0x00a02540, .end
= 0x00a02554 },
1943 { .start
= 0x00a02580, .end
= 0x00a025f4 },
1944 { .start
= 0x00a02600, .end
= 0x00a0260c },
1945 { .start
= 0x00a02648, .end
= 0x00a02650 },
1946 { .start
= 0x00a02680, .end
= 0x00a02680 },
1947 { .start
= 0x00a026c0, .end
= 0x00a026d0 },
1948 { .start
= 0x00a02700, .end
= 0x00a0270c },
1949 { .start
= 0x00a02804, .end
= 0x00a02804 },
1950 { .start
= 0x00a02818, .end
= 0x00a0281c },
1951 { .start
= 0x00a02c00, .end
= 0x00a02db4 },
1952 { .start
= 0x00a02df4, .end
= 0x00a02fb0 },
1953 { .start
= 0x00a03000, .end
= 0x00a03014 },
1954 { .start
= 0x00a0301c, .end
= 0x00a0302c },
1955 { .start
= 0x00a03034, .end
= 0x00a03038 },
1956 { .start
= 0x00a03040, .end
= 0x00a03048 },
1957 { .start
= 0x00a03060, .end
= 0x00a03068 },
1958 { .start
= 0x00a03070, .end
= 0x00a03074 },
1959 { .start
= 0x00a0307c, .end
= 0x00a0307c },
1960 { .start
= 0x00a03080, .end
= 0x00a03084 },
1961 { .start
= 0x00a0308c, .end
= 0x00a03090 },
1962 { .start
= 0x00a03098, .end
= 0x00a03098 },
1963 { .start
= 0x00a030a0, .end
= 0x00a030a0 },
1964 { .start
= 0x00a030a8, .end
= 0x00a030b4 },
1965 { .start
= 0x00a030bc, .end
= 0x00a030bc },
1966 { .start
= 0x00a030c0, .end
= 0x00a0312c },
1967 { .start
= 0x00a03c00, .end
= 0x00a03c5c },
1968 { .start
= 0x00a04400, .end
= 0x00a04454 },
1969 { .start
= 0x00a04460, .end
= 0x00a04474 },
1970 { .start
= 0x00a044c0, .end
= 0x00a044ec },
1971 { .start
= 0x00a04500, .end
= 0x00a04504 },
1972 { .start
= 0x00a04510, .end
= 0x00a04538 },
1973 { .start
= 0x00a04540, .end
= 0x00a04548 },
1974 { .start
= 0x00a04560, .end
= 0x00a0457c },
1975 { .start
= 0x00a04590, .end
= 0x00a04598 },
1976 { .start
= 0x00a045c0, .end
= 0x00a045f4 },
1979 static u32
iwl_trans_pcie_dump_prph(struct iwl_trans
*trans
,
1980 struct iwl_fw_error_dump_data
**data
)
1982 struct iwl_fw_error_dump_prph
*prph
;
1983 unsigned long flags
;
1984 u32 prph_len
= 0, i
;
1986 if (!iwl_trans_grab_nic_access(trans
, false, &flags
))
1989 for (i
= 0; i
< ARRAY_SIZE(iwl_prph_dump_addr
); i
++) {
1990 /* The range includes both boundaries */
1991 int num_bytes_in_chunk
= iwl_prph_dump_addr
[i
].end
-
1992 iwl_prph_dump_addr
[i
].start
+ 4;
1996 prph_len
+= sizeof(**data
) + sizeof(*prph
) + num_bytes_in_chunk
;
1998 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH
);
1999 (*data
)->len
= cpu_to_le32(sizeof(*prph
) +
2000 num_bytes_in_chunk
);
2001 prph
= (void *)(*data
)->data
;
2002 prph
->prph_start
= cpu_to_le32(iwl_prph_dump_addr
[i
].start
);
2003 val
= (void *)prph
->data
;
2005 for (reg
= iwl_prph_dump_addr
[i
].start
;
2006 reg
<= iwl_prph_dump_addr
[i
].end
;
2008 *val
++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans
,
2010 *data
= iwl_fw_error_next_data(*data
);
2013 iwl_trans_release_nic_access(trans
, &flags
);
2018 #define IWL_CSR_TO_DUMP (0x250)
2020 static u32
iwl_trans_pcie_dump_csr(struct iwl_trans
*trans
,
2021 struct iwl_fw_error_dump_data
**data
)
2023 u32 csr_len
= sizeof(**data
) + IWL_CSR_TO_DUMP
;
2027 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_CSR
);
2028 (*data
)->len
= cpu_to_le32(IWL_CSR_TO_DUMP
);
2029 val
= (void *)(*data
)->data
;
2031 for (i
= 0; i
< IWL_CSR_TO_DUMP
; i
+= 4)
2032 *val
++ = cpu_to_le32(iwl_trans_pcie_read32(trans
, i
));
2034 *data
= iwl_fw_error_next_data(*data
);
2039 static u32
iwl_trans_pcie_fh_regs_dump(struct iwl_trans
*trans
,
2040 struct iwl_fw_error_dump_data
**data
)
2042 u32 fh_regs_len
= FH_MEM_UPPER_BOUND
- FH_MEM_LOWER_BOUND
;
2043 unsigned long flags
;
2047 if (!iwl_trans_grab_nic_access(trans
, false, &flags
))
2050 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS
);
2051 (*data
)->len
= cpu_to_le32(fh_regs_len
);
2052 val
= (void *)(*data
)->data
;
2054 for (i
= FH_MEM_LOWER_BOUND
; i
< FH_MEM_UPPER_BOUND
; i
+= sizeof(u32
))
2055 *val
++ = cpu_to_le32(iwl_trans_pcie_read32(trans
, i
));
2057 iwl_trans_release_nic_access(trans
, &flags
);
2059 *data
= iwl_fw_error_next_data(*data
);
2061 return sizeof(**data
) + fh_regs_len
;
2065 struct iwl_trans_dump_data
*iwl_trans_pcie_dump_data(struct iwl_trans
*trans
)
2067 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2068 struct iwl_fw_error_dump_data
*data
;
2069 struct iwl_txq
*cmdq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
2070 struct iwl_fw_error_dump_txcmd
*txcmd
;
2071 struct iwl_trans_dump_data
*dump_data
;
2076 /* transport dump header */
2077 len
= sizeof(*dump_data
);
2080 len
+= sizeof(*data
) +
2081 cmdq
->q
.n_window
* (sizeof(*txcmd
) + TFD_MAX_PAYLOAD_SIZE
);
2084 len
+= sizeof(*data
) + IWL_CSR_TO_DUMP
;
2086 /* PRPH registers */
2087 for (i
= 0; i
< ARRAY_SIZE(iwl_prph_dump_addr
); i
++) {
2088 /* The range includes both boundaries */
2089 int num_bytes_in_chunk
= iwl_prph_dump_addr
[i
].end
-
2090 iwl_prph_dump_addr
[i
].start
+ 4;
2092 len
+= sizeof(*data
) + sizeof(struct iwl_fw_error_dump_prph
) +
2097 len
+= sizeof(*data
) + (FH_MEM_UPPER_BOUND
- FH_MEM_LOWER_BOUND
);
2100 if (trans_pcie
->fw_mon_page
) {
2101 len
+= sizeof(*data
) + sizeof(struct iwl_fw_error_dump_fw_mon
) +
2102 trans_pcie
->fw_mon_size
;
2103 monitor_len
= trans_pcie
->fw_mon_size
;
2104 } else if (trans
->dbg_dest_tlv
) {
2107 base
= le32_to_cpu(trans
->dbg_dest_tlv
->base_reg
);
2108 end
= le32_to_cpu(trans
->dbg_dest_tlv
->end_reg
);
2110 base
= iwl_read_prph(trans
, base
) <<
2111 trans
->dbg_dest_tlv
->base_shift
;
2112 end
= iwl_read_prph(trans
, end
) <<
2113 trans
->dbg_dest_tlv
->end_shift
;
2115 /* Make "end" point to the actual end */
2116 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
)
2117 end
+= (1 << trans
->dbg_dest_tlv
->end_shift
);
2118 monitor_len
= end
- base
;
2119 len
+= sizeof(*data
) + sizeof(struct iwl_fw_error_dump_fw_mon
) +
2125 dump_data
= vzalloc(len
);
2130 data
= (void *)dump_data
->data
;
2131 data
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD
);
2132 txcmd
= (void *)data
->data
;
2133 spin_lock_bh(&cmdq
->lock
);
2134 ptr
= cmdq
->q
.write_ptr
;
2135 for (i
= 0; i
< cmdq
->q
.n_window
; i
++) {
2136 u8 idx
= get_cmd_index(&cmdq
->q
, ptr
);
2139 cmdlen
= iwl_trans_pcie_get_cmdlen(&cmdq
->tfds
[ptr
]);
2140 caplen
= min_t(u32
, TFD_MAX_PAYLOAD_SIZE
, cmdlen
);
2143 len
+= sizeof(*txcmd
) + caplen
;
2144 txcmd
->cmdlen
= cpu_to_le32(cmdlen
);
2145 txcmd
->caplen
= cpu_to_le32(caplen
);
2146 memcpy(txcmd
->data
, cmdq
->entries
[idx
].cmd
, caplen
);
2147 txcmd
= (void *)((u8
*)txcmd
->data
+ caplen
);
2150 ptr
= iwl_queue_dec_wrap(ptr
);
2152 spin_unlock_bh(&cmdq
->lock
);
2154 data
->len
= cpu_to_le32(len
);
2155 len
+= sizeof(*data
);
2156 data
= iwl_fw_error_next_data(data
);
2158 len
+= iwl_trans_pcie_dump_prph(trans
, &data
);
2159 len
+= iwl_trans_pcie_dump_csr(trans
, &data
);
2160 len
+= iwl_trans_pcie_fh_regs_dump(trans
, &data
);
2161 /* data is already pointing to the next section */
2163 if ((trans_pcie
->fw_mon_page
&&
2164 trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_7000
) ||
2165 trans
->dbg_dest_tlv
) {
2166 struct iwl_fw_error_dump_fw_mon
*fw_mon_data
;
2167 u32 base
, write_ptr
, wrap_cnt
;
2169 /* If there was a dest TLV - use the values from there */
2170 if (trans
->dbg_dest_tlv
) {
2172 le32_to_cpu(trans
->dbg_dest_tlv
->write_ptr_reg
);
2173 wrap_cnt
= le32_to_cpu(trans
->dbg_dest_tlv
->wrap_count
);
2174 base
= le32_to_cpu(trans
->dbg_dest_tlv
->base_reg
);
2176 base
= MON_BUFF_BASE_ADDR
;
2177 write_ptr
= MON_BUFF_WRPTR
;
2178 wrap_cnt
= MON_BUFF_CYCLE_CNT
;
2181 data
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR
);
2182 fw_mon_data
= (void *)data
->data
;
2183 fw_mon_data
->fw_mon_wr_ptr
=
2184 cpu_to_le32(iwl_read_prph(trans
, write_ptr
));
2185 fw_mon_data
->fw_mon_cycle_cnt
=
2186 cpu_to_le32(iwl_read_prph(trans
, wrap_cnt
));
2187 fw_mon_data
->fw_mon_base_ptr
=
2188 cpu_to_le32(iwl_read_prph(trans
, base
));
2190 len
+= sizeof(*data
) + sizeof(*fw_mon_data
);
2191 if (trans_pcie
->fw_mon_page
) {
2192 data
->len
= cpu_to_le32(trans_pcie
->fw_mon_size
+
2193 sizeof(*fw_mon_data
));
2196 * The firmware is now asserted, it won't write anything
2197 * to the buffer. CPU can take ownership to fetch the
2198 * data. The buffer will be handed back to the device
2199 * before the firmware will be restarted.
2201 dma_sync_single_for_cpu(trans
->dev
,
2202 trans_pcie
->fw_mon_phys
,
2203 trans_pcie
->fw_mon_size
,
2205 memcpy(fw_mon_data
->data
,
2206 page_address(trans_pcie
->fw_mon_page
),
2207 trans_pcie
->fw_mon_size
);
2209 len
+= trans_pcie
->fw_mon_size
;
2211 /* If we are here then the buffer is internal */
2214 * Update pointers to reflect actual values after
2217 base
= iwl_read_prph(trans
, base
) <<
2218 trans
->dbg_dest_tlv
->base_shift
;
2219 iwl_trans_read_mem(trans
, base
, fw_mon_data
->data
,
2220 monitor_len
/ sizeof(u32
));
2221 data
->len
= cpu_to_le32(sizeof(*fw_mon_data
) +
2227 dump_data
->len
= len
;
2232 static const struct iwl_trans_ops trans_ops_pcie
= {
2233 .start_hw
= iwl_trans_pcie_start_hw
,
2234 .op_mode_leave
= iwl_trans_pcie_op_mode_leave
,
2235 .fw_alive
= iwl_trans_pcie_fw_alive
,
2236 .start_fw
= iwl_trans_pcie_start_fw
,
2237 .stop_device
= iwl_trans_pcie_stop_device
,
2239 .d3_suspend
= iwl_trans_pcie_d3_suspend
,
2240 .d3_resume
= iwl_trans_pcie_d3_resume
,
2242 .send_cmd
= iwl_trans_pcie_send_hcmd
,
2244 .tx
= iwl_trans_pcie_tx
,
2245 .reclaim
= iwl_trans_pcie_reclaim
,
2247 .txq_disable
= iwl_trans_pcie_txq_disable
,
2248 .txq_enable
= iwl_trans_pcie_txq_enable
,
2250 .dbgfs_register
= iwl_trans_pcie_dbgfs_register
,
2252 .wait_tx_queue_empty
= iwl_trans_pcie_wait_txq_empty
,
2254 .write8
= iwl_trans_pcie_write8
,
2255 .write32
= iwl_trans_pcie_write32
,
2256 .read32
= iwl_trans_pcie_read32
,
2257 .read_prph
= iwl_trans_pcie_read_prph
,
2258 .write_prph
= iwl_trans_pcie_write_prph
,
2259 .read_mem
= iwl_trans_pcie_read_mem
,
2260 .write_mem
= iwl_trans_pcie_write_mem
,
2261 .configure
= iwl_trans_pcie_configure
,
2262 .set_pmi
= iwl_trans_pcie_set_pmi
,
2263 .grab_nic_access
= iwl_trans_pcie_grab_nic_access
,
2264 .release_nic_access
= iwl_trans_pcie_release_nic_access
,
2265 .set_bits_mask
= iwl_trans_pcie_set_bits_mask
,
2267 .dump_data
= iwl_trans_pcie_dump_data
,
2270 struct iwl_trans
*iwl_trans_pcie_alloc(struct pci_dev
*pdev
,
2271 const struct pci_device_id
*ent
,
2272 const struct iwl_cfg
*cfg
)
2274 struct iwl_trans_pcie
*trans_pcie
;
2275 struct iwl_trans
*trans
;
2279 trans
= kzalloc(sizeof(struct iwl_trans
) +
2280 sizeof(struct iwl_trans_pcie
), GFP_KERNEL
);
2286 trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2288 trans
->ops
= &trans_ops_pcie
;
2290 trans_lockdep_init(trans
);
2291 trans_pcie
->trans
= trans
;
2292 spin_lock_init(&trans_pcie
->irq_lock
);
2293 spin_lock_init(&trans_pcie
->reg_lock
);
2294 init_waitqueue_head(&trans_pcie
->ucode_write_waitq
);
2296 err
= pci_enable_device(pdev
);
2300 if (!cfg
->base_params
->pcie_l1_allowed
) {
2302 * W/A - seems to solve weird behavior. We need to remove this
2303 * if we don't want to stay in L1 all the time. This wastes a
2306 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
|
2307 PCIE_LINK_STATE_L1
|
2308 PCIE_LINK_STATE_CLKPM
);
2311 pci_set_master(pdev
);
2313 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(36));
2315 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(36));
2317 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2319 err
= pci_set_consistent_dma_mask(pdev
,
2321 /* both attempts failed: */
2323 dev_err(&pdev
->dev
, "No suitable DMA available\n");
2324 goto out_pci_disable_device
;
2328 err
= pci_request_regions(pdev
, DRV_NAME
);
2330 dev_err(&pdev
->dev
, "pci_request_regions failed\n");
2331 goto out_pci_disable_device
;
2334 trans_pcie
->hw_base
= pci_ioremap_bar(pdev
, 0);
2335 if (!trans_pcie
->hw_base
) {
2336 dev_err(&pdev
->dev
, "pci_ioremap_bar failed\n");
2338 goto out_pci_release_regions
;
2341 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2342 * PCI Tx retries from interfering with C3 CPU state */
2343 pci_write_config_byte(pdev
, PCI_CFG_RETRY_TIMEOUT
, 0x00);
2345 trans
->dev
= &pdev
->dev
;
2346 trans_pcie
->pci_dev
= pdev
;
2347 iwl_disable_interrupts(trans
);
2349 err
= pci_enable_msi(pdev
);
2351 dev_err(&pdev
->dev
, "pci_enable_msi failed(0X%x)\n", err
);
2352 /* enable rfkill interrupt: hw bug w/a */
2353 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
2354 if (pci_cmd
& PCI_COMMAND_INTX_DISABLE
) {
2355 pci_cmd
&= ~PCI_COMMAND_INTX_DISABLE
;
2356 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
2360 trans
->hw_rev
= iwl_read32(trans
, CSR_HW_REV
);
2362 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2363 * changed, and now the revision step also includes bit 0-1 (no more
2364 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2365 * in the old format.
2367 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_8000
)
2368 trans
->hw_rev
= (trans
->hw_rev
& 0xfff0) |
2369 (CSR_HW_REV_STEP(trans
->hw_rev
<< 2) << 2);
2371 trans
->hw_id
= (pdev
->device
<< 16) + pdev
->subsystem_device
;
2372 snprintf(trans
->hw_id_str
, sizeof(trans
->hw_id_str
),
2373 "PCI ID: 0x%04X:0x%04X", pdev
->device
, pdev
->subsystem_device
);
2375 /* Initialize the wait queue for commands */
2376 init_waitqueue_head(&trans_pcie
->wait_command_queue
);
2378 snprintf(trans
->dev_cmd_pool_name
, sizeof(trans
->dev_cmd_pool_name
),
2379 "iwl_cmd_pool:%s", dev_name(trans
->dev
));
2381 trans
->dev_cmd_headroom
= 0;
2382 trans
->dev_cmd_pool
=
2383 kmem_cache_create(trans
->dev_cmd_pool_name
,
2384 sizeof(struct iwl_device_cmd
)
2385 + trans
->dev_cmd_headroom
,
2390 if (!trans
->dev_cmd_pool
) {
2392 goto out_pci_disable_msi
;
2395 if (iwl_pcie_alloc_ict(trans
))
2396 goto out_free_cmd_pool
;
2398 err
= request_threaded_irq(pdev
->irq
, iwl_pcie_isr
,
2399 iwl_pcie_irq_handler
,
2400 IRQF_SHARED
, DRV_NAME
, trans
);
2402 IWL_ERR(trans
, "Error allocating IRQ %d\n", pdev
->irq
);
2406 trans_pcie
->inta_mask
= CSR_INI_SET_MASK
;
2411 iwl_pcie_free_ict(trans
);
2413 kmem_cache_destroy(trans
->dev_cmd_pool
);
2414 out_pci_disable_msi
:
2415 pci_disable_msi(pdev
);
2416 out_pci_release_regions
:
2417 pci_release_regions(pdev
);
2418 out_pci_disable_device
:
2419 pci_disable_device(pdev
);
2423 return ERR_PTR(err
);