1 /******************************************************************************
3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/slab.h>
31 #include <linux/sched.h>
33 #include "iwl-debug.h"
37 #include "iwl-op-mode.h"
39 /* FIXME: need to abstract out TX command (once we know what it looks like) */
40 #include "dvm/commands.h"
42 #define IWL_TX_CRC_SIZE 4
43 #define IWL_TX_DELIMITER_SIZE 4
45 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
50 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
51 * of buffer descriptors, each of which points to one or more data buffers for
52 * the device to read from or fill. Driver and device exchange status of each
53 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
54 * entries in each circular buffer, to protect against confusing empty and full
57 * The device reads or writes the data in the queues via the device's several
58 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
60 * For Tx queue, there are low mark and high mark limits. If, after queuing
61 * the packet for Tx, free space become < low mark, Tx queue stopped. When
62 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
65 ***************************************************/
66 static int iwl_queue_space(const struct iwl_queue
*q
)
72 * To avoid ambiguity between empty and completely full queues, there
73 * should always be less than q->n_bd elements in the queue.
74 * If q->n_window is smaller than q->n_bd, there is no need to reserve
75 * any queue entries for this purpose.
77 if (q
->n_window
< q
->n_bd
)
83 * q->n_bd is a power of 2, so the following is equivalent to modulo by
84 * q->n_bd and is well defined for negative dividends.
86 used
= (q
->write_ptr
- q
->read_ptr
) & (q
->n_bd
- 1);
88 if (WARN_ON(used
> max
))
95 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
97 static int iwl_queue_init(struct iwl_queue
*q
, int count
, int slots_num
, u32 id
)
100 q
->n_window
= slots_num
;
103 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
104 * and iwl_queue_dec_wrap are broken. */
105 if (WARN_ON(!is_power_of_2(count
)))
108 /* slots_num must be power-of-two size, otherwise
109 * get_cmd_index is broken. */
110 if (WARN_ON(!is_power_of_2(slots_num
)))
113 q
->low_mark
= q
->n_window
/ 4;
117 q
->high_mark
= q
->n_window
/ 8;
118 if (q
->high_mark
< 2)
127 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans
*trans
,
128 struct iwl_dma_ptr
*ptr
, size_t size
)
130 if (WARN_ON(ptr
->addr
))
133 ptr
->addr
= dma_alloc_coherent(trans
->dev
, size
,
134 &ptr
->dma
, GFP_KERNEL
);
141 static void iwl_pcie_free_dma_ptr(struct iwl_trans
*trans
,
142 struct iwl_dma_ptr
*ptr
)
144 if (unlikely(!ptr
->addr
))
147 dma_free_coherent(trans
->dev
, ptr
->size
, ptr
->addr
, ptr
->dma
);
148 memset(ptr
, 0, sizeof(*ptr
));
151 static void iwl_pcie_txq_stuck_timer(unsigned long data
)
153 struct iwl_txq
*txq
= (void *)data
;
154 struct iwl_queue
*q
= &txq
->q
;
155 struct iwl_trans_pcie
*trans_pcie
= txq
->trans_pcie
;
156 struct iwl_trans
*trans
= iwl_trans_pcie_get_trans(trans_pcie
);
157 u32 scd_sram_addr
= trans_pcie
->scd_base_addr
+
158 SCD_TX_STTS_QUEUE_OFFSET(txq
->q
.id
);
162 spin_lock(&txq
->lock
);
163 /* check if triggered erroneously */
164 if (txq
->q
.read_ptr
== txq
->q
.write_ptr
) {
165 spin_unlock(&txq
->lock
);
168 spin_unlock(&txq
->lock
);
170 IWL_ERR(trans
, "Queue %d stuck for %u ms.\n", txq
->q
.id
,
171 jiffies_to_msecs(trans_pcie
->wd_timeout
));
172 IWL_ERR(trans
, "Current SW read_ptr %d write_ptr %d\n",
173 txq
->q
.read_ptr
, txq
->q
.write_ptr
);
175 iwl_trans_read_mem_bytes(trans
, scd_sram_addr
, buf
, sizeof(buf
));
177 iwl_print_hex_error(trans
, buf
, sizeof(buf
));
179 for (i
= 0; i
< FH_TCSR_CHNL_NUM
; i
++)
180 IWL_ERR(trans
, "FH TRBs(%d) = 0x%08x\n", i
,
181 iwl_read_direct32(trans
, FH_TX_TRB_REG(i
)));
183 for (i
= 0; i
< trans
->cfg
->base_params
->num_of_queues
; i
++) {
184 u32 status
= iwl_read_prph(trans
, SCD_QUEUE_STATUS_BITS(i
));
185 u8 fifo
= (status
>> SCD_QUEUE_STTS_REG_POS_TXF
) & 0x7;
186 bool active
= !!(status
& BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE
));
188 iwl_trans_read_mem32(trans
,
189 trans_pcie
->scd_base_addr
+
190 SCD_TRANS_TBL_OFFSET_QUEUE(i
));
193 tbl_dw
= (tbl_dw
& 0xFFFF0000) >> 16;
195 tbl_dw
= tbl_dw
& 0x0000FFFF;
198 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
199 i
, active
? "" : "in", fifo
, tbl_dw
,
201 SCD_QUEUE_RDPTR(i
)) & (txq
->q
.n_bd
- 1),
202 iwl_read_prph(trans
, SCD_QUEUE_WRPTR(i
)));
205 for (i
= q
->read_ptr
; i
!= q
->write_ptr
;
206 i
= iwl_queue_inc_wrap(i
, q
->n_bd
))
207 IWL_ERR(trans
, "scratch %d = 0x%08x\n", i
,
208 le32_to_cpu(txq
->scratchbufs
[i
].scratch
));
210 iwl_write_prph(trans
, DEVICE_SET_NMI_REG
, 1);
214 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
216 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans
*trans
,
217 struct iwl_txq
*txq
, u16 byte_cnt
)
219 struct iwlagn_scd_bc_tbl
*scd_bc_tbl
;
220 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
221 int write_ptr
= txq
->q
.write_ptr
;
222 int txq_id
= txq
->q
.id
;
225 u16 len
= byte_cnt
+ IWL_TX_CRC_SIZE
+ IWL_TX_DELIMITER_SIZE
;
227 struct iwl_tx_cmd
*tx_cmd
=
228 (void *) txq
->entries
[txq
->q
.write_ptr
].cmd
->payload
;
230 scd_bc_tbl
= trans_pcie
->scd_bc_tbls
.addr
;
232 WARN_ON(len
> 0xFFF || write_ptr
>= TFD_QUEUE_SIZE_MAX
);
234 sta_id
= tx_cmd
->sta_id
;
235 sec_ctl
= tx_cmd
->sec_ctl
;
237 switch (sec_ctl
& TX_CMD_SEC_MSK
) {
239 len
+= IEEE80211_CCMP_MIC_LEN
;
241 case TX_CMD_SEC_TKIP
:
242 len
+= IEEE80211_TKIP_ICV_LEN
;
245 len
+= IEEE80211_WEP_IV_LEN
+ IEEE80211_WEP_ICV_LEN
;
249 if (trans_pcie
->bc_table_dword
)
250 len
= DIV_ROUND_UP(len
, 4);
252 bc_ent
= cpu_to_le16(len
| (sta_id
<< 12));
254 scd_bc_tbl
[txq_id
].tfd_offset
[write_ptr
] = bc_ent
;
256 if (write_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
258 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ write_ptr
] = bc_ent
;
261 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans
*trans
,
264 struct iwl_trans_pcie
*trans_pcie
=
265 IWL_TRANS_GET_PCIE_TRANS(trans
);
266 struct iwlagn_scd_bc_tbl
*scd_bc_tbl
= trans_pcie
->scd_bc_tbls
.addr
;
267 int txq_id
= txq
->q
.id
;
268 int read_ptr
= txq
->q
.read_ptr
;
271 struct iwl_tx_cmd
*tx_cmd
=
272 (void *)txq
->entries
[txq
->q
.read_ptr
].cmd
->payload
;
274 WARN_ON(read_ptr
>= TFD_QUEUE_SIZE_MAX
);
276 if (txq_id
!= trans_pcie
->cmd_queue
)
277 sta_id
= tx_cmd
->sta_id
;
279 bc_ent
= cpu_to_le16(1 | (sta_id
<< 12));
280 scd_bc_tbl
[txq_id
].tfd_offset
[read_ptr
] = bc_ent
;
282 if (read_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
284 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ read_ptr
] = bc_ent
;
288 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
290 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans
*trans
,
293 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
295 int txq_id
= txq
->q
.id
;
297 lockdep_assert_held(&txq
->lock
);
300 * explicitly wake up the NIC if:
301 * 1. shadow registers aren't enabled
302 * 2. NIC is woken up for CMD regardless of shadow outside this function
303 * 3. there is a chance that the NIC is asleep
305 if (!trans
->cfg
->base_params
->shadow_reg_enable
&&
306 txq_id
!= trans_pcie
->cmd_queue
&&
307 test_bit(STATUS_TPOWER_PMI
, &trans
->status
)) {
309 * wake up nic if it's powered down ...
310 * uCode will wake up, and interrupt us again, so next
311 * time we'll skip this part.
313 reg
= iwl_read32(trans
, CSR_UCODE_DRV_GP1
);
315 if (reg
& CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP
) {
316 IWL_DEBUG_INFO(trans
, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
318 iwl_set_bit(trans
, CSR_GP_CNTRL
,
319 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
320 txq
->need_update
= true;
326 * if not in power-save mode, uCode will never sleep when we're
327 * trying to tx (during RFKILL, we're not trying to tx).
329 IWL_DEBUG_TX(trans
, "Q:%d WR: 0x%x\n", txq_id
, txq
->q
.write_ptr
);
330 iwl_write32(trans
, HBUS_TARG_WRPTR
, txq
->q
.write_ptr
| (txq_id
<< 8));
333 void iwl_pcie_txq_check_wrptrs(struct iwl_trans
*trans
)
335 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
338 for (i
= 0; i
< trans
->cfg
->base_params
->num_of_queues
; i
++) {
339 struct iwl_txq
*txq
= &trans_pcie
->txq
[i
];
341 spin_lock(&txq
->lock
);
342 if (trans_pcie
->txq
[i
].need_update
) {
343 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
344 trans_pcie
->txq
[i
].need_update
= false;
346 spin_unlock(&txq
->lock
);
350 static inline dma_addr_t
iwl_pcie_tfd_tb_get_addr(struct iwl_tfd
*tfd
, u8 idx
)
352 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
354 dma_addr_t addr
= get_unaligned_le32(&tb
->lo
);
355 if (sizeof(dma_addr_t
) > sizeof(u32
))
357 ((dma_addr_t
)(le16_to_cpu(tb
->hi_n_len
) & 0xF) << 16) << 16;
362 static inline u16
iwl_pcie_tfd_tb_get_len(struct iwl_tfd
*tfd
, u8 idx
)
364 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
366 return le16_to_cpu(tb
->hi_n_len
) >> 4;
369 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd
*tfd
, u8 idx
,
370 dma_addr_t addr
, u16 len
)
372 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
373 u16 hi_n_len
= len
<< 4;
375 put_unaligned_le32(addr
, &tb
->lo
);
376 if (sizeof(dma_addr_t
) > sizeof(u32
))
377 hi_n_len
|= ((addr
>> 16) >> 16) & 0xF;
379 tb
->hi_n_len
= cpu_to_le16(hi_n_len
);
381 tfd
->num_tbs
= idx
+ 1;
384 static inline u8
iwl_pcie_tfd_get_num_tbs(struct iwl_tfd
*tfd
)
386 return tfd
->num_tbs
& 0x1f;
389 static void iwl_pcie_tfd_unmap(struct iwl_trans
*trans
,
390 struct iwl_cmd_meta
*meta
,
396 /* Sanity check on number of chunks */
397 num_tbs
= iwl_pcie_tfd_get_num_tbs(tfd
);
399 if (num_tbs
>= IWL_NUM_OF_TBS
) {
400 IWL_ERR(trans
, "Too many chunks: %i\n", num_tbs
);
401 /* @todo issue fatal error, it is quite serious situation */
405 /* first TB is never freed - it's the scratchbuf data */
407 for (i
= 1; i
< num_tbs
; i
++)
408 dma_unmap_single(trans
->dev
, iwl_pcie_tfd_tb_get_addr(tfd
, i
),
409 iwl_pcie_tfd_tb_get_len(tfd
, i
),
416 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
417 * @trans - transport private data
419 * @dma_dir - the direction of the DMA mapping
421 * Does NOT advance any TFD circular buffer read/write indexes
422 * Does NOT free the TFD itself (which is within circular buffer)
424 static void iwl_pcie_txq_free_tfd(struct iwl_trans
*trans
, struct iwl_txq
*txq
)
426 struct iwl_tfd
*tfd_tmp
= txq
->tfds
;
428 /* rd_ptr is bounded by n_bd and idx is bounded by n_window */
429 int rd_ptr
= txq
->q
.read_ptr
;
430 int idx
= get_cmd_index(&txq
->q
, rd_ptr
);
432 lockdep_assert_held(&txq
->lock
);
434 /* We have only q->n_window txq->entries, but we use q->n_bd tfds */
435 iwl_pcie_tfd_unmap(trans
, &txq
->entries
[idx
].meta
, &tfd_tmp
[rd_ptr
]);
441 skb
= txq
->entries
[idx
].skb
;
443 /* Can be called from irqs-disabled context
444 * If skb is not NULL, it means that the whole queue is being
445 * freed and that the queue is not empty - free the skb
448 iwl_op_mode_free_skb(trans
->op_mode
, skb
);
449 txq
->entries
[idx
].skb
= NULL
;
454 static int iwl_pcie_txq_build_tfd(struct iwl_trans
*trans
, struct iwl_txq
*txq
,
455 dma_addr_t addr
, u16 len
, bool reset
)
458 struct iwl_tfd
*tfd
, *tfd_tmp
;
463 tfd
= &tfd_tmp
[q
->write_ptr
];
466 memset(tfd
, 0, sizeof(*tfd
));
468 num_tbs
= iwl_pcie_tfd_get_num_tbs(tfd
);
470 /* Each TFD can point to a maximum 20 Tx buffers */
471 if (num_tbs
>= IWL_NUM_OF_TBS
) {
472 IWL_ERR(trans
, "Error can not send more than %d chunks\n",
477 if (WARN(addr
& ~IWL_TX_DMA_MASK
,
478 "Unaligned address = %llx\n", (unsigned long long)addr
))
481 iwl_pcie_tfd_set_tb(tfd
, num_tbs
, addr
, len
);
486 static int iwl_pcie_txq_alloc(struct iwl_trans
*trans
,
487 struct iwl_txq
*txq
, int slots_num
,
490 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
491 size_t tfd_sz
= sizeof(struct iwl_tfd
) * TFD_QUEUE_SIZE_MAX
;
492 size_t scratchbuf_sz
;
495 if (WARN_ON(txq
->entries
|| txq
->tfds
))
498 setup_timer(&txq
->stuck_timer
, iwl_pcie_txq_stuck_timer
,
500 txq
->trans_pcie
= trans_pcie
;
502 txq
->q
.n_window
= slots_num
;
504 txq
->entries
= kcalloc(slots_num
,
505 sizeof(struct iwl_pcie_txq_entry
),
511 if (txq_id
== trans_pcie
->cmd_queue
)
512 for (i
= 0; i
< slots_num
; i
++) {
513 txq
->entries
[i
].cmd
=
514 kmalloc(sizeof(struct iwl_device_cmd
),
516 if (!txq
->entries
[i
].cmd
)
520 /* Circular buffer of transmit frame descriptors (TFDs),
521 * shared with device */
522 txq
->tfds
= dma_alloc_coherent(trans
->dev
, tfd_sz
,
523 &txq
->q
.dma_addr
, GFP_KERNEL
);
527 BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE
!= sizeof(*txq
->scratchbufs
));
528 BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf
, scratch
) !=
529 sizeof(struct iwl_cmd_header
) +
530 offsetof(struct iwl_tx_cmd
, scratch
));
532 scratchbuf_sz
= sizeof(*txq
->scratchbufs
) * slots_num
;
534 txq
->scratchbufs
= dma_alloc_coherent(trans
->dev
, scratchbuf_sz
,
535 &txq
->scratchbufs_dma
,
537 if (!txq
->scratchbufs
)
544 dma_free_coherent(trans
->dev
, tfd_sz
, txq
->tfds
, txq
->q
.dma_addr
);
546 if (txq
->entries
&& txq_id
== trans_pcie
->cmd_queue
)
547 for (i
= 0; i
< slots_num
; i
++)
548 kfree(txq
->entries
[i
].cmd
);
556 static int iwl_pcie_txq_init(struct iwl_trans
*trans
, struct iwl_txq
*txq
,
557 int slots_num
, u32 txq_id
)
561 txq
->need_update
= false;
563 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
564 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
565 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
567 /* Initialize queue's high/low-water marks, and head/tail indexes */
568 ret
= iwl_queue_init(&txq
->q
, TFD_QUEUE_SIZE_MAX
, slots_num
,
573 spin_lock_init(&txq
->lock
);
576 * Tell nic where to find circular buffer of Tx Frame Descriptors for
577 * given Tx queue, and enable the DMA channel used for that queue.
578 * Circular buffer (TFD queue in DRAM) physical base address */
579 iwl_write_direct32(trans
, FH_MEM_CBBC_QUEUE(txq_id
),
580 txq
->q
.dma_addr
>> 8);
586 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
588 static void iwl_pcie_txq_unmap(struct iwl_trans
*trans
, int txq_id
)
590 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
591 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
592 struct iwl_queue
*q
= &txq
->q
;
597 spin_lock_bh(&txq
->lock
);
598 while (q
->write_ptr
!= q
->read_ptr
) {
599 IWL_DEBUG_TX_REPLY(trans
, "Q %d Free %d\n",
600 txq_id
, q
->read_ptr
);
601 iwl_pcie_txq_free_tfd(trans
, txq
);
602 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
);
605 spin_unlock_bh(&txq
->lock
);
607 /* just in case - this queue may have been stopped */
608 iwl_wake_queue(trans
, txq
);
612 * iwl_pcie_txq_free - Deallocate DMA queue.
613 * @txq: Transmit queue to deallocate.
615 * Empty queue by removing and destroying all BD's.
617 * 0-fill, but do not free "txq" descriptor structure.
619 static void iwl_pcie_txq_free(struct iwl_trans
*trans
, int txq_id
)
621 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
622 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
623 struct device
*dev
= trans
->dev
;
629 iwl_pcie_txq_unmap(trans
, txq_id
);
631 /* De-alloc array of command/tx buffers */
632 if (txq_id
== trans_pcie
->cmd_queue
)
633 for (i
= 0; i
< txq
->q
.n_window
; i
++) {
634 kfree(txq
->entries
[i
].cmd
);
635 kfree(txq
->entries
[i
].free_buf
);
638 /* De-alloc circular buffer of TFDs */
640 dma_free_coherent(dev
, sizeof(struct iwl_tfd
) *
641 txq
->q
.n_bd
, txq
->tfds
, txq
->q
.dma_addr
);
644 dma_free_coherent(dev
,
645 sizeof(*txq
->scratchbufs
) * txq
->q
.n_window
,
646 txq
->scratchbufs
, txq
->scratchbufs_dma
);
652 del_timer_sync(&txq
->stuck_timer
);
654 /* 0-fill queue descriptor structure */
655 memset(txq
, 0, sizeof(*txq
));
659 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
661 static void iwl_pcie_txq_set_sched(struct iwl_trans
*trans
, u32 mask
)
663 struct iwl_trans_pcie __maybe_unused
*trans_pcie
=
664 IWL_TRANS_GET_PCIE_TRANS(trans
);
666 iwl_write_prph(trans
, SCD_TXFACT
, mask
);
669 void iwl_pcie_tx_start(struct iwl_trans
*trans
, u32 scd_base_addr
)
671 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
672 int nq
= trans
->cfg
->base_params
->num_of_queues
;
675 int clear_dwords
= (SCD_TRANS_TBL_OFFSET_QUEUE(nq
) -
676 SCD_CONTEXT_MEM_LOWER_BOUND
) / sizeof(u32
);
678 /* make sure all queue are not stopped/used */
679 memset(trans_pcie
->queue_stopped
, 0, sizeof(trans_pcie
->queue_stopped
));
680 memset(trans_pcie
->queue_used
, 0, sizeof(trans_pcie
->queue_used
));
682 trans_pcie
->scd_base_addr
=
683 iwl_read_prph(trans
, SCD_SRAM_BASE_ADDR
);
685 WARN_ON(scd_base_addr
!= 0 &&
686 scd_base_addr
!= trans_pcie
->scd_base_addr
);
688 /* reset context data, TX status and translation data */
689 iwl_trans_write_mem(trans
, trans_pcie
->scd_base_addr
+
690 SCD_CONTEXT_MEM_LOWER_BOUND
,
693 iwl_write_prph(trans
, SCD_DRAM_BASE_ADDR
,
694 trans_pcie
->scd_bc_tbls
.dma
>> 10);
696 /* The chain extension of the SCD doesn't work well. This feature is
697 * enabled by default by the HW, so we need to disable it manually.
699 if (trans
->cfg
->base_params
->scd_chain_ext_wa
)
700 iwl_write_prph(trans
, SCD_CHAINEXT_EN
, 0);
702 iwl_trans_ac_txq_enable(trans
, trans_pcie
->cmd_queue
,
703 trans_pcie
->cmd_fifo
);
705 /* Activate all Tx DMA/FIFO channels */
706 iwl_pcie_txq_set_sched(trans
, IWL_MASK(0, 7));
708 /* Enable DMA channel */
709 for (chan
= 0; chan
< FH_TCSR_CHNL_NUM
; chan
++)
710 iwl_write_direct32(trans
, FH_TCSR_CHNL_TX_CONFIG_REG(chan
),
711 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
712 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
);
714 /* Update FH chicken bits */
715 reg_val
= iwl_read_direct32(trans
, FH_TX_CHICKEN_BITS_REG
);
716 iwl_write_direct32(trans
, FH_TX_CHICKEN_BITS_REG
,
717 reg_val
| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
);
719 /* Enable L1-Active */
720 if (trans
->cfg
->device_family
!= IWL_DEVICE_FAMILY_8000
)
721 iwl_clear_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
722 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
725 void iwl_trans_pcie_tx_reset(struct iwl_trans
*trans
)
727 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
730 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
732 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
734 iwl_write_direct32(trans
, FH_MEM_CBBC_QUEUE(txq_id
),
735 txq
->q
.dma_addr
>> 8);
736 iwl_pcie_txq_unmap(trans
, txq_id
);
738 txq
->q
.write_ptr
= 0;
741 /* Tell NIC where to find the "keep warm" buffer */
742 iwl_write_direct32(trans
, FH_KW_MEM_ADDR_REG
,
743 trans_pcie
->kw
.dma
>> 4);
745 iwl_pcie_tx_start(trans
, trans_pcie
->scd_base_addr
);
749 * iwl_pcie_tx_stop - Stop all Tx DMA channels
751 int iwl_pcie_tx_stop(struct iwl_trans
*trans
)
753 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
756 /* Turn off all Tx DMA fifos */
757 spin_lock(&trans_pcie
->irq_lock
);
759 iwl_pcie_txq_set_sched(trans
, 0);
761 /* Stop each Tx DMA channel, and wait for it to be idle */
762 for (ch
= 0; ch
< FH_TCSR_CHNL_NUM
; ch
++) {
763 iwl_write_direct32(trans
,
764 FH_TCSR_CHNL_TX_CONFIG_REG(ch
), 0x0);
765 ret
= iwl_poll_direct_bit(trans
, FH_TSSR_TX_STATUS_REG
,
766 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch
), 1000);
769 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
771 iwl_read_direct32(trans
,
772 FH_TSSR_TX_STATUS_REG
));
774 spin_unlock(&trans_pcie
->irq_lock
);
777 * This function can be called before the op_mode disabled the
778 * queues. This happens when we have an rfkill interrupt.
779 * Since we stop Tx altogether - mark the queues as stopped.
781 memset(trans_pcie
->queue_stopped
, 0, sizeof(trans_pcie
->queue_stopped
));
782 memset(trans_pcie
->queue_used
, 0, sizeof(trans_pcie
->queue_used
));
784 /* This can happen: start_hw, stop_device */
785 if (!trans_pcie
->txq
)
788 /* Unmap DMA from host system and free skb's */
789 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
791 iwl_pcie_txq_unmap(trans
, txq_id
);
797 * iwl_trans_tx_free - Free TXQ Context
799 * Destroy all TX DMA queues and structures
801 void iwl_pcie_tx_free(struct iwl_trans
*trans
)
804 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
807 if (trans_pcie
->txq
) {
809 txq_id
< trans
->cfg
->base_params
->num_of_queues
; txq_id
++)
810 iwl_pcie_txq_free(trans
, txq_id
);
813 kfree(trans_pcie
->txq
);
814 trans_pcie
->txq
= NULL
;
816 iwl_pcie_free_dma_ptr(trans
, &trans_pcie
->kw
);
818 iwl_pcie_free_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
);
822 * iwl_pcie_tx_alloc - allocate TX context
823 * Allocate all Tx DMA structures and initialize them
825 static int iwl_pcie_tx_alloc(struct iwl_trans
*trans
)
828 int txq_id
, slots_num
;
829 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
831 u16 scd_bc_tbls_size
= trans
->cfg
->base_params
->num_of_queues
*
832 sizeof(struct iwlagn_scd_bc_tbl
);
834 /*It is not allowed to alloc twice, so warn when this happens.
835 * We cannot rely on the previous allocation, so free and fail */
836 if (WARN_ON(trans_pcie
->txq
)) {
841 ret
= iwl_pcie_alloc_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
,
844 IWL_ERR(trans
, "Scheduler BC Table allocation failed\n");
848 /* Alloc keep-warm buffer */
849 ret
= iwl_pcie_alloc_dma_ptr(trans
, &trans_pcie
->kw
, IWL_KW_SIZE
);
851 IWL_ERR(trans
, "Keep Warm allocation failed\n");
855 trans_pcie
->txq
= kcalloc(trans
->cfg
->base_params
->num_of_queues
,
856 sizeof(struct iwl_txq
), GFP_KERNEL
);
857 if (!trans_pcie
->txq
) {
858 IWL_ERR(trans
, "Not enough memory for txq\n");
863 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
864 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
866 slots_num
= (txq_id
== trans_pcie
->cmd_queue
) ?
867 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
868 ret
= iwl_pcie_txq_alloc(trans
, &trans_pcie
->txq
[txq_id
],
871 IWL_ERR(trans
, "Tx %d queue alloc failed\n", txq_id
);
879 iwl_pcie_tx_free(trans
);
883 int iwl_pcie_tx_init(struct iwl_trans
*trans
)
885 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
887 int txq_id
, slots_num
;
890 if (!trans_pcie
->txq
) {
891 ret
= iwl_pcie_tx_alloc(trans
);
897 spin_lock(&trans_pcie
->irq_lock
);
899 /* Turn off all Tx DMA fifos */
900 iwl_write_prph(trans
, SCD_TXFACT
, 0);
902 /* Tell NIC where to find the "keep warm" buffer */
903 iwl_write_direct32(trans
, FH_KW_MEM_ADDR_REG
,
904 trans_pcie
->kw
.dma
>> 4);
906 spin_unlock(&trans_pcie
->irq_lock
);
908 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
909 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
911 slots_num
= (txq_id
== trans_pcie
->cmd_queue
) ?
912 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
913 ret
= iwl_pcie_txq_init(trans
, &trans_pcie
->txq
[txq_id
],
916 IWL_ERR(trans
, "Tx %d queue init failed\n", txq_id
);
923 /*Upon error, free only if we allocated something */
925 iwl_pcie_tx_free(trans
);
929 static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie
*trans_pcie
,
932 if (!trans_pcie
->wd_timeout
)
936 * if empty delete timer, otherwise move timer forward
937 * since we're making progress on this queue
939 if (txq
->q
.read_ptr
== txq
->q
.write_ptr
)
940 del_timer(&txq
->stuck_timer
);
942 mod_timer(&txq
->stuck_timer
, jiffies
+ trans_pcie
->wd_timeout
);
945 /* Frees buffers until index _not_ inclusive */
946 void iwl_trans_pcie_reclaim(struct iwl_trans
*trans
, int txq_id
, int ssn
,
947 struct sk_buff_head
*skbs
)
949 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
950 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
951 /* n_bd is usually 256 => n_bd - 1 = 0xff */
952 int tfd_num
= ssn
& (txq
->q
.n_bd
- 1);
953 struct iwl_queue
*q
= &txq
->q
;
956 /* This function is not meant to release cmd queue*/
957 if (WARN_ON(txq_id
== trans_pcie
->cmd_queue
))
960 spin_lock_bh(&txq
->lock
);
963 IWL_DEBUG_TX_QUEUES(trans
, "Q %d inactive - ignoring idx %d\n",
968 if (txq
->q
.read_ptr
== tfd_num
)
971 IWL_DEBUG_TX_REPLY(trans
, "[Q %d] %d -> %d (%d)\n",
972 txq_id
, txq
->q
.read_ptr
, tfd_num
, ssn
);
974 /*Since we free until index _not_ inclusive, the one before index is
975 * the last we will free. This one must be used */
976 last_to_free
= iwl_queue_dec_wrap(tfd_num
, q
->n_bd
);
978 if (!iwl_queue_used(q
, last_to_free
)) {
980 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
981 __func__
, txq_id
, last_to_free
, q
->n_bd
,
982 q
->write_ptr
, q
->read_ptr
);
986 if (WARN_ON(!skb_queue_empty(skbs
)))
990 q
->read_ptr
!= tfd_num
;
991 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
993 if (WARN_ON_ONCE(txq
->entries
[txq
->q
.read_ptr
].skb
== NULL
))
996 __skb_queue_tail(skbs
, txq
->entries
[txq
->q
.read_ptr
].skb
);
998 txq
->entries
[txq
->q
.read_ptr
].skb
= NULL
;
1000 iwl_pcie_txq_inval_byte_cnt_tbl(trans
, txq
);
1002 iwl_pcie_txq_free_tfd(trans
, txq
);
1005 iwl_pcie_txq_progress(trans_pcie
, txq
);
1007 if (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
)
1008 iwl_wake_queue(trans
, txq
);
1010 spin_unlock_bh(&txq
->lock
);
1014 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1016 * When FW advances 'R' index, all entries between old and new 'R' index
1017 * need to be reclaimed. As result, some free space forms. If there is
1018 * enough free space (> low mark), wake the stack that feeds us.
1020 static void iwl_pcie_cmdq_reclaim(struct iwl_trans
*trans
, int txq_id
, int idx
)
1022 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1023 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
1024 struct iwl_queue
*q
= &txq
->q
;
1025 unsigned long flags
;
1028 lockdep_assert_held(&txq
->lock
);
1030 if ((idx
>= q
->n_bd
) || (!iwl_queue_used(q
, idx
))) {
1032 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1033 __func__
, txq_id
, idx
, q
->n_bd
,
1034 q
->write_ptr
, q
->read_ptr
);
1038 for (idx
= iwl_queue_inc_wrap(idx
, q
->n_bd
); q
->read_ptr
!= idx
;
1039 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
1042 IWL_ERR(trans
, "HCMD skipped: index (%d) %d %d\n",
1043 idx
, q
->write_ptr
, q
->read_ptr
);
1044 iwl_write_prph(trans
, DEVICE_SET_NMI_REG
, 1);
1048 if (trans
->cfg
->base_params
->apmg_wake_up_wa
&&
1049 q
->read_ptr
== q
->write_ptr
) {
1050 spin_lock_irqsave(&trans_pcie
->reg_lock
, flags
);
1051 WARN_ON(!trans_pcie
->cmd_in_flight
);
1052 trans_pcie
->cmd_in_flight
= false;
1053 __iwl_trans_pcie_clear_bit(trans
,
1055 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1056 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
1059 iwl_pcie_txq_progress(trans_pcie
, txq
);
1062 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans
*trans
, u16 ra_tid
,
1065 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1070 scd_q2ratid
= ra_tid
& SCD_QUEUE_RA_TID_MAP_RATID_MSK
;
1072 tbl_dw_addr
= trans_pcie
->scd_base_addr
+
1073 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id
);
1075 tbl_dw
= iwl_trans_read_mem32(trans
, tbl_dw_addr
);
1078 tbl_dw
= (scd_q2ratid
<< 16) | (tbl_dw
& 0x0000FFFF);
1080 tbl_dw
= scd_q2ratid
| (tbl_dw
& 0xFFFF0000);
1082 iwl_trans_write_mem32(trans
, tbl_dw_addr
, tbl_dw
);
1087 static inline void iwl_pcie_txq_set_inactive(struct iwl_trans
*trans
,
1090 /* Simply stop the queue, but don't change any configuration;
1091 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1092 iwl_write_prph(trans
,
1093 SCD_QUEUE_STATUS_BITS(txq_id
),
1094 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE
)|
1095 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN
));
1098 /* Receiver address (actually, Rx station's index into station table),
1099 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1100 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1102 void iwl_trans_pcie_txq_enable(struct iwl_trans
*trans
, int txq_id
, int fifo
,
1103 int sta_id
, int tid
, int frame_limit
, u16 ssn
)
1105 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1107 if (test_and_set_bit(txq_id
, trans_pcie
->queue_used
))
1108 WARN_ONCE(1, "queue %d already used - expect issues", txq_id
);
1110 /* Stop this Tx queue before configuring it */
1111 iwl_pcie_txq_set_inactive(trans
, txq_id
);
1113 /* Set this queue as a chain-building queue unless it is CMD queue */
1114 if (txq_id
!= trans_pcie
->cmd_queue
)
1115 iwl_set_bits_prph(trans
, SCD_QUEUECHAIN_SEL
, BIT(txq_id
));
1117 /* If this queue is mapped to a certain station: it is an AGG queue */
1119 u16 ra_tid
= BUILD_RAxTID(sta_id
, tid
);
1121 /* Map receiver-address / traffic-ID to this queue */
1122 iwl_pcie_txq_set_ratid_map(trans
, ra_tid
, txq_id
);
1124 /* enable aggregations for the queue */
1125 iwl_set_bits_prph(trans
, SCD_AGGR_SEL
, BIT(txq_id
));
1126 trans_pcie
->txq
[txq_id
].ampdu
= true;
1129 * disable aggregations for the queue, this will also make the
1130 * ra_tid mapping configuration irrelevant since it is now a
1133 iwl_clear_bits_prph(trans
, SCD_AGGR_SEL
, BIT(txq_id
));
1135 ssn
= trans_pcie
->txq
[txq_id
].q
.read_ptr
;
1138 /* Place first TFD at index corresponding to start sequence number.
1139 * Assumes that ssn_idx is valid (!= 0xFFF) */
1140 trans_pcie
->txq
[txq_id
].q
.read_ptr
= (ssn
& 0xff);
1141 trans_pcie
->txq
[txq_id
].q
.write_ptr
= (ssn
& 0xff);
1143 iwl_write_direct32(trans
, HBUS_TARG_WRPTR
,
1144 (ssn
& 0xff) | (txq_id
<< 8));
1145 iwl_write_prph(trans
, SCD_QUEUE_RDPTR(txq_id
), ssn
);
1147 /* Set up Tx window size and frame limit for this queue */
1148 iwl_trans_write_mem32(trans
, trans_pcie
->scd_base_addr
+
1149 SCD_CONTEXT_QUEUE_OFFSET(txq_id
), 0);
1150 iwl_trans_write_mem32(trans
, trans_pcie
->scd_base_addr
+
1151 SCD_CONTEXT_QUEUE_OFFSET(txq_id
) + sizeof(u32
),
1152 ((frame_limit
<< SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
1153 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
1154 ((frame_limit
<< SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
1155 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
1157 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1158 iwl_write_prph(trans
, SCD_QUEUE_STATUS_BITS(txq_id
),
1159 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE
) |
1160 (fifo
<< SCD_QUEUE_STTS_REG_POS_TXF
) |
1161 (1 << SCD_QUEUE_STTS_REG_POS_WSL
) |
1162 SCD_QUEUE_STTS_REG_MSK
);
1163 trans_pcie
->txq
[txq_id
].active
= true;
1164 IWL_DEBUG_TX_QUEUES(trans
, "Activate queue %d on FIFO %d WrPtr: %d\n",
1165 txq_id
, fifo
, ssn
& 0xff);
1168 void iwl_trans_pcie_txq_disable(struct iwl_trans
*trans
, int txq_id
)
1170 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1171 u32 stts_addr
= trans_pcie
->scd_base_addr
+
1172 SCD_TX_STTS_QUEUE_OFFSET(txq_id
);
1173 static const u32 zero_val
[4] = {};
1176 * Upon HW Rfkill - we stop the device, and then stop the queues
1177 * in the op_mode. Just for the sake of the simplicity of the op_mode,
1178 * allow the op_mode to call txq_disable after it already called
1181 if (!test_and_clear_bit(txq_id
, trans_pcie
->queue_used
)) {
1182 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED
, &trans
->status
),
1183 "queue %d not used", txq_id
);
1187 iwl_pcie_txq_set_inactive(trans
, txq_id
);
1189 iwl_trans_write_mem(trans
, stts_addr
, (void *)zero_val
,
1190 ARRAY_SIZE(zero_val
));
1192 iwl_pcie_txq_unmap(trans
, txq_id
);
1193 trans_pcie
->txq
[txq_id
].ampdu
= false;
1195 IWL_DEBUG_TX_QUEUES(trans
, "Deactivate queue %d\n", txq_id
);
1198 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1201 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1202 * @priv: device private data point
1203 * @cmd: a pointer to the ucode command structure
1205 * The function returns < 0 values to indicate the operation
1206 * failed. On success, it returns the index (>= 0) of command in the
1209 static int iwl_pcie_enqueue_hcmd(struct iwl_trans
*trans
,
1210 struct iwl_host_cmd
*cmd
)
1212 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1213 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1214 struct iwl_queue
*q
= &txq
->q
;
1215 struct iwl_device_cmd
*out_cmd
;
1216 struct iwl_cmd_meta
*out_meta
;
1217 unsigned long flags
;
1218 void *dup_buf
= NULL
;
1219 dma_addr_t phys_addr
;
1221 u16 copy_size
, cmd_size
, scratch_size
;
1222 bool had_nocopy
= false;
1225 const u8
*cmddata
[IWL_MAX_CMD_TBS_PER_TFD
];
1226 u16 cmdlen
[IWL_MAX_CMD_TBS_PER_TFD
];
1228 copy_size
= sizeof(out_cmd
->hdr
);
1229 cmd_size
= sizeof(out_cmd
->hdr
);
1231 /* need one for the header if the first is NOCOPY */
1232 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD
> IWL_NUM_OF_TBS
- 1);
1234 for (i
= 0; i
< IWL_MAX_CMD_TBS_PER_TFD
; i
++) {
1235 cmddata
[i
] = cmd
->data
[i
];
1236 cmdlen
[i
] = cmd
->len
[i
];
1241 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1242 if (copy_size
< IWL_HCMD_SCRATCHBUF_SIZE
) {
1243 int copy
= IWL_HCMD_SCRATCHBUF_SIZE
- copy_size
;
1245 if (copy
> cmdlen
[i
])
1252 if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_NOCOPY
) {
1254 if (WARN_ON(cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
)) {
1258 } else if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
) {
1260 * This is also a chunk that isn't copied
1261 * to the static buffer so set had_nocopy.
1265 /* only allowed once */
1266 if (WARN_ON(dup_buf
)) {
1271 dup_buf
= kmemdup(cmddata
[i
], cmdlen
[i
],
1276 /* NOCOPY must not be followed by normal! */
1277 if (WARN_ON(had_nocopy
)) {
1281 copy_size
+= cmdlen
[i
];
1283 cmd_size
+= cmd
->len
[i
];
1287 * If any of the command structures end up being larger than
1288 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1289 * allocated into separate TFDs, then we will need to
1290 * increase the size of the buffers.
1292 if (WARN(copy_size
> TFD_MAX_PAYLOAD_SIZE
,
1293 "Command %s (%#x) is too large (%d bytes)\n",
1294 get_cmd_string(trans_pcie
, cmd
->id
), cmd
->id
, copy_size
)) {
1299 spin_lock_bh(&txq
->lock
);
1301 if (iwl_queue_space(q
) < ((cmd
->flags
& CMD_ASYNC
) ? 2 : 1)) {
1302 spin_unlock_bh(&txq
->lock
);
1304 IWL_ERR(trans
, "No space in command queue\n");
1305 iwl_op_mode_cmd_queue_full(trans
->op_mode
);
1310 idx
= get_cmd_index(q
, q
->write_ptr
);
1311 out_cmd
= txq
->entries
[idx
].cmd
;
1312 out_meta
= &txq
->entries
[idx
].meta
;
1314 memset(out_meta
, 0, sizeof(*out_meta
)); /* re-initialize to NULL */
1315 if (cmd
->flags
& CMD_WANT_SKB
)
1316 out_meta
->source
= cmd
;
1318 /* set up the header */
1320 out_cmd
->hdr
.cmd
= cmd
->id
;
1321 out_cmd
->hdr
.flags
= 0;
1322 out_cmd
->hdr
.sequence
=
1323 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie
->cmd_queue
) |
1324 INDEX_TO_SEQ(q
->write_ptr
));
1326 /* and copy the data that needs to be copied */
1327 cmd_pos
= offsetof(struct iwl_device_cmd
, payload
);
1328 copy_size
= sizeof(out_cmd
->hdr
);
1329 for (i
= 0; i
< IWL_MAX_CMD_TBS_PER_TFD
; i
++) {
1335 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1336 if (copy_size
< IWL_HCMD_SCRATCHBUF_SIZE
) {
1337 copy
= IWL_HCMD_SCRATCHBUF_SIZE
- copy_size
;
1339 if (copy
> cmd
->len
[i
])
1343 /* copy everything if not nocopy/dup */
1344 if (!(cmd
->dataflags
[i
] & (IWL_HCMD_DFL_NOCOPY
|
1349 memcpy((u8
*)out_cmd
+ cmd_pos
, cmd
->data
[i
], copy
);
1356 "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1357 get_cmd_string(trans_pcie
, out_cmd
->hdr
.cmd
),
1358 out_cmd
->hdr
.cmd
, le16_to_cpu(out_cmd
->hdr
.sequence
),
1359 cmd_size
, q
->write_ptr
, idx
, trans_pcie
->cmd_queue
);
1361 /* start the TFD with the scratchbuf */
1362 scratch_size
= min_t(int, copy_size
, IWL_HCMD_SCRATCHBUF_SIZE
);
1363 memcpy(&txq
->scratchbufs
[q
->write_ptr
], &out_cmd
->hdr
, scratch_size
);
1364 iwl_pcie_txq_build_tfd(trans
, txq
,
1365 iwl_pcie_get_scratchbuf_dma(txq
, q
->write_ptr
),
1366 scratch_size
, true);
1368 /* map first command fragment, if any remains */
1369 if (copy_size
> scratch_size
) {
1370 phys_addr
= dma_map_single(trans
->dev
,
1371 ((u8
*)&out_cmd
->hdr
) + scratch_size
,
1372 copy_size
- scratch_size
,
1374 if (dma_mapping_error(trans
->dev
, phys_addr
)) {
1375 iwl_pcie_tfd_unmap(trans
, out_meta
,
1376 &txq
->tfds
[q
->write_ptr
]);
1381 iwl_pcie_txq_build_tfd(trans
, txq
, phys_addr
,
1382 copy_size
- scratch_size
, false);
1385 /* map the remaining (adjusted) nocopy/dup fragments */
1386 for (i
= 0; i
< IWL_MAX_CMD_TBS_PER_TFD
; i
++) {
1387 const void *data
= cmddata
[i
];
1391 if (!(cmd
->dataflags
[i
] & (IWL_HCMD_DFL_NOCOPY
|
1394 if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
)
1396 phys_addr
= dma_map_single(trans
->dev
, (void *)data
,
1397 cmdlen
[i
], DMA_TO_DEVICE
);
1398 if (dma_mapping_error(trans
->dev
, phys_addr
)) {
1399 iwl_pcie_tfd_unmap(trans
, out_meta
,
1400 &txq
->tfds
[q
->write_ptr
]);
1405 iwl_pcie_txq_build_tfd(trans
, txq
, phys_addr
, cmdlen
[i
], false);
1408 out_meta
->flags
= cmd
->flags
;
1409 if (WARN_ON_ONCE(txq
->entries
[idx
].free_buf
))
1410 kfree(txq
->entries
[idx
].free_buf
);
1411 txq
->entries
[idx
].free_buf
= dup_buf
;
1413 trace_iwlwifi_dev_hcmd(trans
->dev
, cmd
, cmd_size
, &out_cmd
->hdr
);
1415 /* start timer if queue currently empty */
1416 if (q
->read_ptr
== q
->write_ptr
&& trans_pcie
->wd_timeout
)
1417 mod_timer(&txq
->stuck_timer
, jiffies
+ trans_pcie
->wd_timeout
);
1419 spin_lock_irqsave(&trans_pcie
->reg_lock
, flags
);
1422 * wake up the NIC to make sure that the firmware will see the host
1423 * command - we will let the NIC sleep once all the host commands
1424 * returned. This needs to be done only on NICs that have
1425 * apmg_wake_up_wa set.
1427 if (trans
->cfg
->base_params
->apmg_wake_up_wa
&&
1428 !trans_pcie
->cmd_in_flight
) {
1429 trans_pcie
->cmd_in_flight
= true;
1430 __iwl_trans_pcie_set_bit(trans
, CSR_GP_CNTRL
,
1431 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1432 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
1433 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN
,
1434 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
|
1435 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP
),
1438 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
1439 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1440 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
1441 trans_pcie
->cmd_in_flight
= false;
1447 /* Increment and update queue's write index */
1448 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
1449 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
1451 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
1454 spin_unlock_bh(&txq
->lock
);
1462 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1463 * @rxb: Rx buffer to reclaim
1464 * @handler_status: return value of the handler of the command
1465 * (put in setup_rx_handlers)
1467 * If an Rx buffer has an async callback associated with it the callback
1468 * will be executed. The attached skb (if present) will only be freed
1469 * if the callback returns 1
1471 void iwl_pcie_hcmd_complete(struct iwl_trans
*trans
,
1472 struct iwl_rx_cmd_buffer
*rxb
, int handler_status
)
1474 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
1475 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
1476 int txq_id
= SEQ_TO_QUEUE(sequence
);
1477 int index
= SEQ_TO_INDEX(sequence
);
1479 struct iwl_device_cmd
*cmd
;
1480 struct iwl_cmd_meta
*meta
;
1481 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1482 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1484 /* If a Tx command is being handled and it isn't in the actual
1485 * command queue then there a command routing bug has been introduced
1486 * in the queue management code. */
1487 if (WARN(txq_id
!= trans_pcie
->cmd_queue
,
1488 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1489 txq_id
, trans_pcie
->cmd_queue
, sequence
,
1490 trans_pcie
->txq
[trans_pcie
->cmd_queue
].q
.read_ptr
,
1491 trans_pcie
->txq
[trans_pcie
->cmd_queue
].q
.write_ptr
)) {
1492 iwl_print_hex_error(trans
, pkt
, 32);
1496 spin_lock_bh(&txq
->lock
);
1498 cmd_index
= get_cmd_index(&txq
->q
, index
);
1499 cmd
= txq
->entries
[cmd_index
].cmd
;
1500 meta
= &txq
->entries
[cmd_index
].meta
;
1502 iwl_pcie_tfd_unmap(trans
, meta
, &txq
->tfds
[index
]);
1504 /* Input error checking is done when commands are added to queue. */
1505 if (meta
->flags
& CMD_WANT_SKB
) {
1506 struct page
*p
= rxb_steal_page(rxb
);
1508 meta
->source
->resp_pkt
= pkt
;
1509 meta
->source
->_rx_page_addr
= (unsigned long)page_address(p
);
1510 meta
->source
->_rx_page_order
= trans_pcie
->rx_page_order
;
1511 meta
->source
->handler_status
= handler_status
;
1514 iwl_pcie_cmdq_reclaim(trans
, txq_id
, index
);
1516 if (!(meta
->flags
& CMD_ASYNC
)) {
1517 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
)) {
1519 "HCMD_ACTIVE already clear for command %s\n",
1520 get_cmd_string(trans_pcie
, cmd
->hdr
.cmd
));
1522 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1523 IWL_DEBUG_INFO(trans
, "Clearing HCMD_ACTIVE for command %s\n",
1524 get_cmd_string(trans_pcie
, cmd
->hdr
.cmd
));
1525 wake_up(&trans_pcie
->wait_command_queue
);
1530 spin_unlock_bh(&txq
->lock
);
1533 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
1535 static int iwl_pcie_send_hcmd_async(struct iwl_trans
*trans
,
1536 struct iwl_host_cmd
*cmd
)
1538 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1541 /* An asynchronous command can not expect an SKB to be set. */
1542 if (WARN_ON(cmd
->flags
& CMD_WANT_SKB
))
1545 ret
= iwl_pcie_enqueue_hcmd(trans
, cmd
);
1548 "Error sending %s: enqueue_hcmd failed: %d\n",
1549 get_cmd_string(trans_pcie
, cmd
->id
), ret
);
1555 static int iwl_pcie_send_hcmd_sync(struct iwl_trans
*trans
,
1556 struct iwl_host_cmd
*cmd
)
1558 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1562 IWL_DEBUG_INFO(trans
, "Attempting to send sync command %s\n",
1563 get_cmd_string(trans_pcie
, cmd
->id
));
1565 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE
,
1567 "Command %s: a command is already active!\n",
1568 get_cmd_string(trans_pcie
, cmd
->id
)))
1571 IWL_DEBUG_INFO(trans
, "Setting HCMD_ACTIVE for command %s\n",
1572 get_cmd_string(trans_pcie
, cmd
->id
));
1574 cmd_idx
= iwl_pcie_enqueue_hcmd(trans
, cmd
);
1577 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1579 "Error sending %s: enqueue_hcmd failed: %d\n",
1580 get_cmd_string(trans_pcie
, cmd
->id
), ret
);
1584 ret
= wait_event_timeout(trans_pcie
->wait_command_queue
,
1585 !test_bit(STATUS_SYNC_HCMD_ACTIVE
,
1587 HOST_COMPLETE_TIMEOUT
);
1589 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1590 struct iwl_queue
*q
= &txq
->q
;
1592 IWL_ERR(trans
, "Error sending %s: time out after %dms.\n",
1593 get_cmd_string(trans_pcie
, cmd
->id
),
1594 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT
));
1596 IWL_ERR(trans
, "Current CMD queue read_ptr %d write_ptr %d\n",
1597 q
->read_ptr
, q
->write_ptr
);
1599 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1600 IWL_DEBUG_INFO(trans
, "Clearing HCMD_ACTIVE for command %s\n",
1601 get_cmd_string(trans_pcie
, cmd
->id
));
1604 iwl_write_prph(trans
, DEVICE_SET_NMI_REG
, 1);
1605 iwl_trans_fw_error(trans
);
1610 if (test_bit(STATUS_FW_ERROR
, &trans
->status
)) {
1611 IWL_ERR(trans
, "FW error in SYNC CMD %s\n",
1612 get_cmd_string(trans_pcie
, cmd
->id
));
1618 if (!(cmd
->flags
& CMD_SEND_IN_RFKILL
) &&
1619 test_bit(STATUS_RFKILL
, &trans
->status
)) {
1620 IWL_DEBUG_RF_KILL(trans
, "RFKILL in SYNC CMD... no rsp\n");
1625 if ((cmd
->flags
& CMD_WANT_SKB
) && !cmd
->resp_pkt
) {
1626 IWL_ERR(trans
, "Error: Response NULL in '%s'\n",
1627 get_cmd_string(trans_pcie
, cmd
->id
));
1635 if (cmd
->flags
& CMD_WANT_SKB
) {
1637 * Cancel the CMD_WANT_SKB flag for the cmd in the
1638 * TX cmd queue. Otherwise in case the cmd comes
1639 * in later, it will possibly set an invalid
1640 * address (cmd->meta.source).
1642 trans_pcie
->txq
[trans_pcie
->cmd_queue
].
1643 entries
[cmd_idx
].meta
.flags
&= ~CMD_WANT_SKB
;
1646 if (cmd
->resp_pkt
) {
1648 cmd
->resp_pkt
= NULL
;
1654 int iwl_trans_pcie_send_hcmd(struct iwl_trans
*trans
, struct iwl_host_cmd
*cmd
)
1656 if (!(cmd
->flags
& CMD_SEND_IN_RFKILL
) &&
1657 test_bit(STATUS_RFKILL
, &trans
->status
)) {
1658 IWL_DEBUG_RF_KILL(trans
, "Dropping CMD 0x%x: RF KILL\n",
1663 if (cmd
->flags
& CMD_ASYNC
)
1664 return iwl_pcie_send_hcmd_async(trans
, cmd
);
1666 /* We still can fail on RFKILL that can be asserted while we wait */
1667 return iwl_pcie_send_hcmd_sync(trans
, cmd
);
1670 int iwl_trans_pcie_tx(struct iwl_trans
*trans
, struct sk_buff
*skb
,
1671 struct iwl_device_cmd
*dev_cmd
, int txq_id
)
1673 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1674 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1675 struct iwl_tx_cmd
*tx_cmd
= (struct iwl_tx_cmd
*)dev_cmd
->payload
;
1676 struct iwl_cmd_meta
*out_meta
;
1677 struct iwl_txq
*txq
;
1678 struct iwl_queue
*q
;
1679 dma_addr_t tb0_phys
, tb1_phys
, scratch_phys
;
1681 u16 len
, tb1_len
, tb2_len
;
1682 bool wait_write_ptr
;
1683 __le16 fc
= hdr
->frame_control
;
1684 u8 hdr_len
= ieee80211_hdrlen(fc
);
1687 txq
= &trans_pcie
->txq
[txq_id
];
1690 if (WARN_ONCE(!test_bit(txq_id
, trans_pcie
->queue_used
),
1691 "TX on unused queue %d\n", txq_id
))
1694 spin_lock(&txq
->lock
);
1696 /* In AGG mode, the index in the ring must correspond to the WiFi
1697 * sequence number. This is a HW requirements to help the SCD to parse
1699 * Check here that the packets are in the right place on the ring.
1701 wifi_seq
= IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr
->seq_ctrl
));
1702 WARN_ONCE(txq
->ampdu
&&
1703 (wifi_seq
& 0xff) != q
->write_ptr
,
1704 "Q: %d WiFi Seq %d tfdNum %d",
1705 txq_id
, wifi_seq
, q
->write_ptr
);
1707 /* Set up driver data for this TFD */
1708 txq
->entries
[q
->write_ptr
].skb
= skb
;
1709 txq
->entries
[q
->write_ptr
].cmd
= dev_cmd
;
1711 dev_cmd
->hdr
.sequence
=
1712 cpu_to_le16((u16
)(QUEUE_TO_SEQ(txq_id
) |
1713 INDEX_TO_SEQ(q
->write_ptr
)));
1715 tb0_phys
= iwl_pcie_get_scratchbuf_dma(txq
, q
->write_ptr
);
1716 scratch_phys
= tb0_phys
+ sizeof(struct iwl_cmd_header
) +
1717 offsetof(struct iwl_tx_cmd
, scratch
);
1719 tx_cmd
->dram_lsb_ptr
= cpu_to_le32(scratch_phys
);
1720 tx_cmd
->dram_msb_ptr
= iwl_get_dma_hi_addr(scratch_phys
);
1722 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1723 out_meta
= &txq
->entries
[q
->write_ptr
].meta
;
1726 * The second TB (tb1) points to the remainder of the TX command
1727 * and the 802.11 header - dword aligned size
1728 * (This calculation modifies the TX command, so do it before the
1729 * setup of the first TB)
1731 len
= sizeof(struct iwl_tx_cmd
) + sizeof(struct iwl_cmd_header
) +
1732 hdr_len
- IWL_HCMD_SCRATCHBUF_SIZE
;
1733 tb1_len
= ALIGN(len
, 4);
1735 /* Tell NIC about any 2-byte padding after MAC header */
1737 tx_cmd
->tx_flags
|= TX_CMD_FLG_MH_PAD_MSK
;
1739 /* The first TB points to the scratchbuf data - min_copy bytes */
1740 memcpy(&txq
->scratchbufs
[q
->write_ptr
], &dev_cmd
->hdr
,
1741 IWL_HCMD_SCRATCHBUF_SIZE
);
1742 iwl_pcie_txq_build_tfd(trans
, txq
, tb0_phys
,
1743 IWL_HCMD_SCRATCHBUF_SIZE
, true);
1745 /* there must be data left over for TB1 or this code must be changed */
1746 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd
) < IWL_HCMD_SCRATCHBUF_SIZE
);
1748 /* map the data for TB1 */
1749 tb1_addr
= ((u8
*)&dev_cmd
->hdr
) + IWL_HCMD_SCRATCHBUF_SIZE
;
1750 tb1_phys
= dma_map_single(trans
->dev
, tb1_addr
, tb1_len
, DMA_TO_DEVICE
);
1751 if (unlikely(dma_mapping_error(trans
->dev
, tb1_phys
)))
1753 iwl_pcie_txq_build_tfd(trans
, txq
, tb1_phys
, tb1_len
, false);
1756 * Set up TFD's third entry to point directly to remainder
1757 * of skb, if any (802.11 null frames have no payload).
1759 tb2_len
= skb
->len
- hdr_len
;
1761 dma_addr_t tb2_phys
= dma_map_single(trans
->dev
,
1762 skb
->data
+ hdr_len
,
1763 tb2_len
, DMA_TO_DEVICE
);
1764 if (unlikely(dma_mapping_error(trans
->dev
, tb2_phys
))) {
1765 iwl_pcie_tfd_unmap(trans
, out_meta
,
1766 &txq
->tfds
[q
->write_ptr
]);
1769 iwl_pcie_txq_build_tfd(trans
, txq
, tb2_phys
, tb2_len
, false);
1772 /* Set up entry for this TFD in Tx byte-count array */
1773 iwl_pcie_txq_update_byte_cnt_tbl(trans
, txq
, le16_to_cpu(tx_cmd
->len
));
1775 trace_iwlwifi_dev_tx(trans
->dev
, skb
,
1776 &txq
->tfds
[txq
->q
.write_ptr
],
1777 sizeof(struct iwl_tfd
),
1778 &dev_cmd
->hdr
, IWL_HCMD_SCRATCHBUF_SIZE
+ tb1_len
,
1779 skb
->data
+ hdr_len
, tb2_len
);
1780 trace_iwlwifi_dev_tx_data(trans
->dev
, skb
,
1781 skb
->data
+ hdr_len
, tb2_len
);
1783 wait_write_ptr
= ieee80211_has_morefrags(fc
);
1785 /* start timer if queue currently empty */
1786 if (txq
->need_update
&& q
->read_ptr
== q
->write_ptr
&&
1787 trans_pcie
->wd_timeout
)
1788 mod_timer(&txq
->stuck_timer
, jiffies
+ trans_pcie
->wd_timeout
);
1790 /* Tell device the write index *just past* this latest filled TFD */
1791 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
1792 if (!wait_write_ptr
)
1793 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
1796 * At this point the frame is "transmitted" successfully
1797 * and we will get a TX status notification eventually.
1799 if (iwl_queue_space(q
) < q
->high_mark
) {
1801 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
1803 iwl_stop_queue(trans
, txq
);
1805 spin_unlock(&txq
->lock
);
1808 spin_unlock(&txq
->lock
);