1 /******************************************************************************
3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
4 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
6 * Portions of this file are derived from the ipw3945 project, as well
7 * as portions of the ieee80211 subsystem header files.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
22 * The full GNU General Public License is included in this distribution in the
23 * file called LICENSE.
25 * Contact Information:
26 * Intel Linux Wireless <ilw@linux.intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
29 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <linux/slab.h>
32 #include <linux/sched.h>
34 #include "iwl-debug.h"
39 #include "iwl-op-mode.h"
41 /* FIXME: need to abstract out TX command (once we know what it looks like) */
42 #include "dvm/commands.h"
44 #define IWL_TX_CRC_SIZE 4
45 #define IWL_TX_DELIMITER_SIZE 4
47 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
52 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
53 * of buffer descriptors, each of which points to one or more data buffers for
54 * the device to read from or fill. Driver and device exchange status of each
55 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
56 * entries in each circular buffer, to protect against confusing empty and full
59 * The device reads or writes the data in the queues via the device's several
60 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
62 * For Tx queue, there are low mark and high mark limits. If, after queuing
63 * the packet for Tx, free space become < low mark, Tx queue stopped. When
64 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
67 ***************************************************/
68 static int iwl_queue_space(const struct iwl_queue
*q
)
74 * To avoid ambiguity between empty and completely full queues, there
75 * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue.
76 * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need
77 * to reserve any queue entries for this purpose.
79 if (q
->n_window
< TFD_QUEUE_SIZE_MAX
)
82 max
= TFD_QUEUE_SIZE_MAX
- 1;
85 * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to
86 * modulo by TFD_QUEUE_SIZE_MAX and is well defined.
88 used
= (q
->write_ptr
- q
->read_ptr
) & (TFD_QUEUE_SIZE_MAX
- 1);
90 if (WARN_ON(used
> max
))
97 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
99 static int iwl_queue_init(struct iwl_queue
*q
, int slots_num
, u32 id
)
101 q
->n_window
= slots_num
;
104 /* slots_num must be power-of-two size, otherwise
105 * get_cmd_index is broken. */
106 if (WARN_ON(!is_power_of_2(slots_num
)))
109 q
->low_mark
= q
->n_window
/ 4;
113 q
->high_mark
= q
->n_window
/ 8;
114 if (q
->high_mark
< 2)
123 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans
*trans
,
124 struct iwl_dma_ptr
*ptr
, size_t size
)
126 if (WARN_ON(ptr
->addr
))
129 ptr
->addr
= dma_alloc_coherent(trans
->dev
, size
,
130 &ptr
->dma
, GFP_KERNEL
);
137 static void iwl_pcie_free_dma_ptr(struct iwl_trans
*trans
,
138 struct iwl_dma_ptr
*ptr
)
140 if (unlikely(!ptr
->addr
))
143 dma_free_coherent(trans
->dev
, ptr
->size
, ptr
->addr
, ptr
->dma
);
144 memset(ptr
, 0, sizeof(*ptr
));
147 static void iwl_pcie_txq_stuck_timer(unsigned long data
)
149 struct iwl_txq
*txq
= (void *)data
;
150 struct iwl_trans_pcie
*trans_pcie
= txq
->trans_pcie
;
151 struct iwl_trans
*trans
= iwl_trans_pcie_get_trans(trans_pcie
);
152 u32 scd_sram_addr
= trans_pcie
->scd_base_addr
+
153 SCD_TX_STTS_QUEUE_OFFSET(txq
->q
.id
);
157 spin_lock(&txq
->lock
);
158 /* check if triggered erroneously */
159 if (txq
->q
.read_ptr
== txq
->q
.write_ptr
) {
160 spin_unlock(&txq
->lock
);
163 spin_unlock(&txq
->lock
);
165 IWL_ERR(trans
, "Queue %d stuck for %u ms.\n", txq
->q
.id
,
166 jiffies_to_msecs(txq
->wd_timeout
));
167 IWL_ERR(trans
, "Current SW read_ptr %d write_ptr %d\n",
168 txq
->q
.read_ptr
, txq
->q
.write_ptr
);
170 iwl_trans_read_mem_bytes(trans
, scd_sram_addr
, buf
, sizeof(buf
));
172 iwl_print_hex_error(trans
, buf
, sizeof(buf
));
174 for (i
= 0; i
< FH_TCSR_CHNL_NUM
; i
++)
175 IWL_ERR(trans
, "FH TRBs(%d) = 0x%08x\n", i
,
176 iwl_read_direct32(trans
, FH_TX_TRB_REG(i
)));
178 for (i
= 0; i
< trans
->cfg
->base_params
->num_of_queues
; i
++) {
179 u32 status
= iwl_read_prph(trans
, SCD_QUEUE_STATUS_BITS(i
));
180 u8 fifo
= (status
>> SCD_QUEUE_STTS_REG_POS_TXF
) & 0x7;
181 bool active
= !!(status
& BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE
));
183 iwl_trans_read_mem32(trans
,
184 trans_pcie
->scd_base_addr
+
185 SCD_TRANS_TBL_OFFSET_QUEUE(i
));
188 tbl_dw
= (tbl_dw
& 0xFFFF0000) >> 16;
190 tbl_dw
= tbl_dw
& 0x0000FFFF;
193 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
194 i
, active
? "" : "in", fifo
, tbl_dw
,
195 iwl_read_prph(trans
, SCD_QUEUE_RDPTR(i
)) &
196 (TFD_QUEUE_SIZE_MAX
- 1),
197 iwl_read_prph(trans
, SCD_QUEUE_WRPTR(i
)));
200 iwl_force_nmi(trans
);
204 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
206 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans
*trans
,
207 struct iwl_txq
*txq
, u16 byte_cnt
)
209 struct iwlagn_scd_bc_tbl
*scd_bc_tbl
;
210 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
211 int write_ptr
= txq
->q
.write_ptr
;
212 int txq_id
= txq
->q
.id
;
215 u16 len
= byte_cnt
+ IWL_TX_CRC_SIZE
+ IWL_TX_DELIMITER_SIZE
;
217 struct iwl_tx_cmd
*tx_cmd
=
218 (void *) txq
->entries
[txq
->q
.write_ptr
].cmd
->payload
;
220 scd_bc_tbl
= trans_pcie
->scd_bc_tbls
.addr
;
222 WARN_ON(len
> 0xFFF || write_ptr
>= TFD_QUEUE_SIZE_MAX
);
224 sta_id
= tx_cmd
->sta_id
;
225 sec_ctl
= tx_cmd
->sec_ctl
;
227 switch (sec_ctl
& TX_CMD_SEC_MSK
) {
229 len
+= IEEE80211_CCMP_MIC_LEN
;
231 case TX_CMD_SEC_TKIP
:
232 len
+= IEEE80211_TKIP_ICV_LEN
;
235 len
+= IEEE80211_WEP_IV_LEN
+ IEEE80211_WEP_ICV_LEN
;
239 if (trans_pcie
->bc_table_dword
)
240 len
= DIV_ROUND_UP(len
, 4);
242 bc_ent
= cpu_to_le16(len
| (sta_id
<< 12));
244 scd_bc_tbl
[txq_id
].tfd_offset
[write_ptr
] = bc_ent
;
246 if (write_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
248 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ write_ptr
] = bc_ent
;
251 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans
*trans
,
254 struct iwl_trans_pcie
*trans_pcie
=
255 IWL_TRANS_GET_PCIE_TRANS(trans
);
256 struct iwlagn_scd_bc_tbl
*scd_bc_tbl
= trans_pcie
->scd_bc_tbls
.addr
;
257 int txq_id
= txq
->q
.id
;
258 int read_ptr
= txq
->q
.read_ptr
;
261 struct iwl_tx_cmd
*tx_cmd
=
262 (void *)txq
->entries
[txq
->q
.read_ptr
].cmd
->payload
;
264 WARN_ON(read_ptr
>= TFD_QUEUE_SIZE_MAX
);
266 if (txq_id
!= trans_pcie
->cmd_queue
)
267 sta_id
= tx_cmd
->sta_id
;
269 bc_ent
= cpu_to_le16(1 | (sta_id
<< 12));
270 scd_bc_tbl
[txq_id
].tfd_offset
[read_ptr
] = bc_ent
;
272 if (read_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
274 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ read_ptr
] = bc_ent
;
278 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
280 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans
*trans
,
283 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
285 int txq_id
= txq
->q
.id
;
287 lockdep_assert_held(&txq
->lock
);
290 * explicitly wake up the NIC if:
291 * 1. shadow registers aren't enabled
292 * 2. NIC is woken up for CMD regardless of shadow outside this function
293 * 3. there is a chance that the NIC is asleep
295 if (!trans
->cfg
->base_params
->shadow_reg_enable
&&
296 txq_id
!= trans_pcie
->cmd_queue
&&
297 test_bit(STATUS_TPOWER_PMI
, &trans
->status
)) {
299 * wake up nic if it's powered down ...
300 * uCode will wake up, and interrupt us again, so next
301 * time we'll skip this part.
303 reg
= iwl_read32(trans
, CSR_UCODE_DRV_GP1
);
305 if (reg
& CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP
) {
306 IWL_DEBUG_INFO(trans
, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
308 iwl_set_bit(trans
, CSR_GP_CNTRL
,
309 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
310 txq
->need_update
= true;
316 * if not in power-save mode, uCode will never sleep when we're
317 * trying to tx (during RFKILL, we're not trying to tx).
319 IWL_DEBUG_TX(trans
, "Q:%d WR: 0x%x\n", txq_id
, txq
->q
.write_ptr
);
320 iwl_write32(trans
, HBUS_TARG_WRPTR
, txq
->q
.write_ptr
| (txq_id
<< 8));
323 void iwl_pcie_txq_check_wrptrs(struct iwl_trans
*trans
)
325 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
328 for (i
= 0; i
< trans
->cfg
->base_params
->num_of_queues
; i
++) {
329 struct iwl_txq
*txq
= &trans_pcie
->txq
[i
];
331 spin_lock_bh(&txq
->lock
);
332 if (trans_pcie
->txq
[i
].need_update
) {
333 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
334 trans_pcie
->txq
[i
].need_update
= false;
336 spin_unlock_bh(&txq
->lock
);
340 static inline dma_addr_t
iwl_pcie_tfd_tb_get_addr(struct iwl_tfd
*tfd
, u8 idx
)
342 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
344 dma_addr_t addr
= get_unaligned_le32(&tb
->lo
);
345 if (sizeof(dma_addr_t
) > sizeof(u32
))
347 ((dma_addr_t
)(le16_to_cpu(tb
->hi_n_len
) & 0xF) << 16) << 16;
352 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd
*tfd
, u8 idx
,
353 dma_addr_t addr
, u16 len
)
355 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
356 u16 hi_n_len
= len
<< 4;
358 put_unaligned_le32(addr
, &tb
->lo
);
359 if (sizeof(dma_addr_t
) > sizeof(u32
))
360 hi_n_len
|= ((addr
>> 16) >> 16) & 0xF;
362 tb
->hi_n_len
= cpu_to_le16(hi_n_len
);
364 tfd
->num_tbs
= idx
+ 1;
367 static inline u8
iwl_pcie_tfd_get_num_tbs(struct iwl_tfd
*tfd
)
369 return tfd
->num_tbs
& 0x1f;
372 static void iwl_pcie_tfd_unmap(struct iwl_trans
*trans
,
373 struct iwl_cmd_meta
*meta
,
379 /* Sanity check on number of chunks */
380 num_tbs
= iwl_pcie_tfd_get_num_tbs(tfd
);
382 if (num_tbs
>= IWL_NUM_OF_TBS
) {
383 IWL_ERR(trans
, "Too many chunks: %i\n", num_tbs
);
384 /* @todo issue fatal error, it is quite serious situation */
388 /* first TB is never freed - it's the scratchbuf data */
390 for (i
= 1; i
< num_tbs
; i
++)
391 dma_unmap_single(trans
->dev
, iwl_pcie_tfd_tb_get_addr(tfd
, i
),
392 iwl_pcie_tfd_tb_get_len(tfd
, i
),
399 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
400 * @trans - transport private data
402 * @dma_dir - the direction of the DMA mapping
404 * Does NOT advance any TFD circular buffer read/write indexes
405 * Does NOT free the TFD itself (which is within circular buffer)
407 static void iwl_pcie_txq_free_tfd(struct iwl_trans
*trans
, struct iwl_txq
*txq
)
409 struct iwl_tfd
*tfd_tmp
= txq
->tfds
;
411 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
412 * idx is bounded by n_window
414 int rd_ptr
= txq
->q
.read_ptr
;
415 int idx
= get_cmd_index(&txq
->q
, rd_ptr
);
417 lockdep_assert_held(&txq
->lock
);
419 /* We have only q->n_window txq->entries, but we use
420 * TFD_QUEUE_SIZE_MAX tfds
422 iwl_pcie_tfd_unmap(trans
, &txq
->entries
[idx
].meta
, &tfd_tmp
[rd_ptr
]);
428 skb
= txq
->entries
[idx
].skb
;
430 /* Can be called from irqs-disabled context
431 * If skb is not NULL, it means that the whole queue is being
432 * freed and that the queue is not empty - free the skb
435 iwl_op_mode_free_skb(trans
->op_mode
, skb
);
436 txq
->entries
[idx
].skb
= NULL
;
441 static int iwl_pcie_txq_build_tfd(struct iwl_trans
*trans
, struct iwl_txq
*txq
,
442 dma_addr_t addr
, u16 len
, bool reset
)
445 struct iwl_tfd
*tfd
, *tfd_tmp
;
450 tfd
= &tfd_tmp
[q
->write_ptr
];
453 memset(tfd
, 0, sizeof(*tfd
));
455 num_tbs
= iwl_pcie_tfd_get_num_tbs(tfd
);
457 /* Each TFD can point to a maximum 20 Tx buffers */
458 if (num_tbs
>= IWL_NUM_OF_TBS
) {
459 IWL_ERR(trans
, "Error can not send more than %d chunks\n",
464 if (WARN(addr
& ~IWL_TX_DMA_MASK
,
465 "Unaligned address = %llx\n", (unsigned long long)addr
))
468 iwl_pcie_tfd_set_tb(tfd
, num_tbs
, addr
, len
);
473 static int iwl_pcie_txq_alloc(struct iwl_trans
*trans
,
474 struct iwl_txq
*txq
, int slots_num
,
477 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
478 size_t tfd_sz
= sizeof(struct iwl_tfd
) * TFD_QUEUE_SIZE_MAX
;
479 size_t scratchbuf_sz
;
482 if (WARN_ON(txq
->entries
|| txq
->tfds
))
485 setup_timer(&txq
->stuck_timer
, iwl_pcie_txq_stuck_timer
,
487 txq
->trans_pcie
= trans_pcie
;
489 txq
->q
.n_window
= slots_num
;
491 txq
->entries
= kcalloc(slots_num
,
492 sizeof(struct iwl_pcie_txq_entry
),
498 if (txq_id
== trans_pcie
->cmd_queue
)
499 for (i
= 0; i
< slots_num
; i
++) {
500 txq
->entries
[i
].cmd
=
501 kmalloc(sizeof(struct iwl_device_cmd
),
503 if (!txq
->entries
[i
].cmd
)
507 /* Circular buffer of transmit frame descriptors (TFDs),
508 * shared with device */
509 txq
->tfds
= dma_alloc_coherent(trans
->dev
, tfd_sz
,
510 &txq
->q
.dma_addr
, GFP_KERNEL
);
514 BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE
!= sizeof(*txq
->scratchbufs
));
515 BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf
, scratch
) !=
516 sizeof(struct iwl_cmd_header
) +
517 offsetof(struct iwl_tx_cmd
, scratch
));
519 scratchbuf_sz
= sizeof(*txq
->scratchbufs
) * slots_num
;
521 txq
->scratchbufs
= dma_alloc_coherent(trans
->dev
, scratchbuf_sz
,
522 &txq
->scratchbufs_dma
,
524 if (!txq
->scratchbufs
)
531 dma_free_coherent(trans
->dev
, tfd_sz
, txq
->tfds
, txq
->q
.dma_addr
);
533 if (txq
->entries
&& txq_id
== trans_pcie
->cmd_queue
)
534 for (i
= 0; i
< slots_num
; i
++)
535 kfree(txq
->entries
[i
].cmd
);
543 static int iwl_pcie_txq_init(struct iwl_trans
*trans
, struct iwl_txq
*txq
,
544 int slots_num
, u32 txq_id
)
548 txq
->need_update
= false;
550 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
551 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
552 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
554 /* Initialize queue's high/low-water marks, and head/tail indexes */
555 ret
= iwl_queue_init(&txq
->q
, slots_num
, txq_id
);
559 spin_lock_init(&txq
->lock
);
562 * Tell nic where to find circular buffer of Tx Frame Descriptors for
563 * given Tx queue, and enable the DMA channel used for that queue.
564 * Circular buffer (TFD queue in DRAM) physical base address */
565 iwl_write_direct32(trans
, FH_MEM_CBBC_QUEUE(txq_id
),
566 txq
->q
.dma_addr
>> 8);
572 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
574 static void iwl_pcie_txq_unmap(struct iwl_trans
*trans
, int txq_id
)
576 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
577 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
578 struct iwl_queue
*q
= &txq
->q
;
580 spin_lock_bh(&txq
->lock
);
581 while (q
->write_ptr
!= q
->read_ptr
) {
582 IWL_DEBUG_TX_REPLY(trans
, "Q %d Free %d\n",
583 txq_id
, q
->read_ptr
);
584 iwl_pcie_txq_free_tfd(trans
, txq
);
585 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
);
588 spin_unlock_bh(&txq
->lock
);
590 /* just in case - this queue may have been stopped */
591 iwl_wake_queue(trans
, txq
);
595 * iwl_pcie_txq_free - Deallocate DMA queue.
596 * @txq: Transmit queue to deallocate.
598 * Empty queue by removing and destroying all BD's.
600 * 0-fill, but do not free "txq" descriptor structure.
602 static void iwl_pcie_txq_free(struct iwl_trans
*trans
, int txq_id
)
604 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
605 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
606 struct device
*dev
= trans
->dev
;
612 iwl_pcie_txq_unmap(trans
, txq_id
);
614 /* De-alloc array of command/tx buffers */
615 if (txq_id
== trans_pcie
->cmd_queue
)
616 for (i
= 0; i
< txq
->q
.n_window
; i
++) {
617 kzfree(txq
->entries
[i
].cmd
);
618 kzfree(txq
->entries
[i
].free_buf
);
621 /* De-alloc circular buffer of TFDs */
623 dma_free_coherent(dev
,
624 sizeof(struct iwl_tfd
) * TFD_QUEUE_SIZE_MAX
,
625 txq
->tfds
, txq
->q
.dma_addr
);
629 dma_free_coherent(dev
,
630 sizeof(*txq
->scratchbufs
) * txq
->q
.n_window
,
631 txq
->scratchbufs
, txq
->scratchbufs_dma
);
637 del_timer_sync(&txq
->stuck_timer
);
639 /* 0-fill queue descriptor structure */
640 memset(txq
, 0, sizeof(*txq
));
643 void iwl_pcie_tx_start(struct iwl_trans
*trans
, u32 scd_base_addr
)
645 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
646 int nq
= trans
->cfg
->base_params
->num_of_queues
;
649 int clear_dwords
= (SCD_TRANS_TBL_OFFSET_QUEUE(nq
) -
650 SCD_CONTEXT_MEM_LOWER_BOUND
) / sizeof(u32
);
652 /* make sure all queue are not stopped/used */
653 memset(trans_pcie
->queue_stopped
, 0, sizeof(trans_pcie
->queue_stopped
));
654 memset(trans_pcie
->queue_used
, 0, sizeof(trans_pcie
->queue_used
));
656 trans_pcie
->scd_base_addr
=
657 iwl_read_prph(trans
, SCD_SRAM_BASE_ADDR
);
659 WARN_ON(scd_base_addr
!= 0 &&
660 scd_base_addr
!= trans_pcie
->scd_base_addr
);
662 /* reset context data, TX status and translation data */
663 iwl_trans_write_mem(trans
, trans_pcie
->scd_base_addr
+
664 SCD_CONTEXT_MEM_LOWER_BOUND
,
667 iwl_write_prph(trans
, SCD_DRAM_BASE_ADDR
,
668 trans_pcie
->scd_bc_tbls
.dma
>> 10);
670 /* The chain extension of the SCD doesn't work well. This feature is
671 * enabled by default by the HW, so we need to disable it manually.
673 if (trans
->cfg
->base_params
->scd_chain_ext_wa
)
674 iwl_write_prph(trans
, SCD_CHAINEXT_EN
, 0);
676 iwl_trans_ac_txq_enable(trans
, trans_pcie
->cmd_queue
,
677 trans_pcie
->cmd_fifo
,
678 trans_pcie
->cmd_q_wdg_timeout
);
680 /* Activate all Tx DMA/FIFO channels */
681 iwl_scd_activate_fifos(trans
);
683 /* Enable DMA channel */
684 for (chan
= 0; chan
< FH_TCSR_CHNL_NUM
; chan
++)
685 iwl_write_direct32(trans
, FH_TCSR_CHNL_TX_CONFIG_REG(chan
),
686 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
687 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
);
689 /* Update FH chicken bits */
690 reg_val
= iwl_read_direct32(trans
, FH_TX_CHICKEN_BITS_REG
);
691 iwl_write_direct32(trans
, FH_TX_CHICKEN_BITS_REG
,
692 reg_val
| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
);
694 /* Enable L1-Active */
695 if (trans
->cfg
->device_family
!= IWL_DEVICE_FAMILY_8000
)
696 iwl_clear_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
697 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
700 void iwl_trans_pcie_tx_reset(struct iwl_trans
*trans
)
702 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
705 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
707 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
709 iwl_write_direct32(trans
, FH_MEM_CBBC_QUEUE(txq_id
),
710 txq
->q
.dma_addr
>> 8);
711 iwl_pcie_txq_unmap(trans
, txq_id
);
713 txq
->q
.write_ptr
= 0;
716 /* Tell NIC where to find the "keep warm" buffer */
717 iwl_write_direct32(trans
, FH_KW_MEM_ADDR_REG
,
718 trans_pcie
->kw
.dma
>> 4);
721 * Send 0 as the scd_base_addr since the device may have be reset
722 * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
725 iwl_pcie_tx_start(trans
, 0);
728 static void iwl_pcie_tx_stop_fh(struct iwl_trans
*trans
)
730 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
735 spin_lock(&trans_pcie
->irq_lock
);
737 if (!iwl_trans_grab_nic_access(trans
, false, &flags
))
740 /* Stop each Tx DMA channel */
741 for (ch
= 0; ch
< FH_TCSR_CHNL_NUM
; ch
++) {
742 iwl_write32(trans
, FH_TCSR_CHNL_TX_CONFIG_REG(ch
), 0x0);
743 mask
|= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch
);
746 /* Wait for DMA channels to be idle */
747 ret
= iwl_poll_bit(trans
, FH_TSSR_TX_STATUS_REG
, mask
, mask
, 5000);
750 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
751 ch
, iwl_read32(trans
, FH_TSSR_TX_STATUS_REG
));
753 iwl_trans_release_nic_access(trans
, &flags
);
756 spin_unlock(&trans_pcie
->irq_lock
);
760 * iwl_pcie_tx_stop - Stop all Tx DMA channels
762 int iwl_pcie_tx_stop(struct iwl_trans
*trans
)
764 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
767 /* Turn off all Tx DMA fifos */
768 iwl_scd_deactivate_fifos(trans
);
770 /* Turn off all Tx DMA channels */
771 iwl_pcie_tx_stop_fh(trans
);
774 * This function can be called before the op_mode disabled the
775 * queues. This happens when we have an rfkill interrupt.
776 * Since we stop Tx altogether - mark the queues as stopped.
778 memset(trans_pcie
->queue_stopped
, 0, sizeof(trans_pcie
->queue_stopped
));
779 memset(trans_pcie
->queue_used
, 0, sizeof(trans_pcie
->queue_used
));
781 /* This can happen: start_hw, stop_device */
782 if (!trans_pcie
->txq
)
785 /* Unmap DMA from host system and free skb's */
786 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
788 iwl_pcie_txq_unmap(trans
, txq_id
);
794 * iwl_trans_tx_free - Free TXQ Context
796 * Destroy all TX DMA queues and structures
798 void iwl_pcie_tx_free(struct iwl_trans
*trans
)
801 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
804 if (trans_pcie
->txq
) {
806 txq_id
< trans
->cfg
->base_params
->num_of_queues
; txq_id
++)
807 iwl_pcie_txq_free(trans
, txq_id
);
810 kfree(trans_pcie
->txq
);
811 trans_pcie
->txq
= NULL
;
813 iwl_pcie_free_dma_ptr(trans
, &trans_pcie
->kw
);
815 iwl_pcie_free_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
);
819 * iwl_pcie_tx_alloc - allocate TX context
820 * Allocate all Tx DMA structures and initialize them
822 static int iwl_pcie_tx_alloc(struct iwl_trans
*trans
)
825 int txq_id
, slots_num
;
826 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
828 u16 scd_bc_tbls_size
= trans
->cfg
->base_params
->num_of_queues
*
829 sizeof(struct iwlagn_scd_bc_tbl
);
831 /*It is not allowed to alloc twice, so warn when this happens.
832 * We cannot rely on the previous allocation, so free and fail */
833 if (WARN_ON(trans_pcie
->txq
)) {
838 ret
= iwl_pcie_alloc_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
,
841 IWL_ERR(trans
, "Scheduler BC Table allocation failed\n");
845 /* Alloc keep-warm buffer */
846 ret
= iwl_pcie_alloc_dma_ptr(trans
, &trans_pcie
->kw
, IWL_KW_SIZE
);
848 IWL_ERR(trans
, "Keep Warm allocation failed\n");
852 trans_pcie
->txq
= kcalloc(trans
->cfg
->base_params
->num_of_queues
,
853 sizeof(struct iwl_txq
), GFP_KERNEL
);
854 if (!trans_pcie
->txq
) {
855 IWL_ERR(trans
, "Not enough memory for txq\n");
860 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
861 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
863 slots_num
= (txq_id
== trans_pcie
->cmd_queue
) ?
864 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
865 ret
= iwl_pcie_txq_alloc(trans
, &trans_pcie
->txq
[txq_id
],
868 IWL_ERR(trans
, "Tx %d queue alloc failed\n", txq_id
);
876 iwl_pcie_tx_free(trans
);
880 int iwl_pcie_tx_init(struct iwl_trans
*trans
)
882 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
884 int txq_id
, slots_num
;
887 if (!trans_pcie
->txq
) {
888 ret
= iwl_pcie_tx_alloc(trans
);
894 spin_lock(&trans_pcie
->irq_lock
);
896 /* Turn off all Tx DMA fifos */
897 iwl_scd_deactivate_fifos(trans
);
899 /* Tell NIC where to find the "keep warm" buffer */
900 iwl_write_direct32(trans
, FH_KW_MEM_ADDR_REG
,
901 trans_pcie
->kw
.dma
>> 4);
903 spin_unlock(&trans_pcie
->irq_lock
);
905 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
906 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
908 slots_num
= (txq_id
== trans_pcie
->cmd_queue
) ?
909 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
910 ret
= iwl_pcie_txq_init(trans
, &trans_pcie
->txq
[txq_id
],
913 IWL_ERR(trans
, "Tx %d queue init failed\n", txq_id
);
918 if (trans
->cfg
->base_params
->num_of_queues
> 20)
919 iwl_set_bits_prph(trans
, SCD_GP_CTRL
,
920 SCD_GP_CTRL_ENABLE_31_QUEUES
);
924 /*Upon error, free only if we allocated something */
926 iwl_pcie_tx_free(trans
);
930 static inline void iwl_pcie_txq_progress(struct iwl_txq
*txq
)
932 lockdep_assert_held(&txq
->lock
);
934 if (!txq
->wd_timeout
)
938 * station is asleep and we send data - that must
939 * be uAPSD or PS-Poll. Don't rearm the timer.
945 * if empty delete timer, otherwise move timer forward
946 * since we're making progress on this queue
948 if (txq
->q
.read_ptr
== txq
->q
.write_ptr
)
949 del_timer(&txq
->stuck_timer
);
951 mod_timer(&txq
->stuck_timer
, jiffies
+ txq
->wd_timeout
);
954 /* Frees buffers until index _not_ inclusive */
955 void iwl_trans_pcie_reclaim(struct iwl_trans
*trans
, int txq_id
, int ssn
,
956 struct sk_buff_head
*skbs
)
958 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
959 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
960 int tfd_num
= ssn
& (TFD_QUEUE_SIZE_MAX
- 1);
961 struct iwl_queue
*q
= &txq
->q
;
964 /* This function is not meant to release cmd queue*/
965 if (WARN_ON(txq_id
== trans_pcie
->cmd_queue
))
968 spin_lock_bh(&txq
->lock
);
971 IWL_DEBUG_TX_QUEUES(trans
, "Q %d inactive - ignoring idx %d\n",
976 if (txq
->q
.read_ptr
== tfd_num
)
979 IWL_DEBUG_TX_REPLY(trans
, "[Q %d] %d -> %d (%d)\n",
980 txq_id
, txq
->q
.read_ptr
, tfd_num
, ssn
);
982 /*Since we free until index _not_ inclusive, the one before index is
983 * the last we will free. This one must be used */
984 last_to_free
= iwl_queue_dec_wrap(tfd_num
);
986 if (!iwl_queue_used(q
, last_to_free
)) {
988 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
989 __func__
, txq_id
, last_to_free
, TFD_QUEUE_SIZE_MAX
,
990 q
->write_ptr
, q
->read_ptr
);
994 if (WARN_ON(!skb_queue_empty(skbs
)))
998 q
->read_ptr
!= tfd_num
;
999 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
)) {
1001 if (WARN_ON_ONCE(txq
->entries
[txq
->q
.read_ptr
].skb
== NULL
))
1004 __skb_queue_tail(skbs
, txq
->entries
[txq
->q
.read_ptr
].skb
);
1006 txq
->entries
[txq
->q
.read_ptr
].skb
= NULL
;
1008 iwl_pcie_txq_inval_byte_cnt_tbl(trans
, txq
);
1010 iwl_pcie_txq_free_tfd(trans
, txq
);
1013 iwl_pcie_txq_progress(txq
);
1015 if (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
)
1016 iwl_wake_queue(trans
, txq
);
1018 if (q
->read_ptr
== q
->write_ptr
) {
1019 IWL_DEBUG_RPM(trans
, "Q %d - last tx reclaimed\n", q
->id
);
1020 iwl_trans_pcie_unref(trans
);
1024 spin_unlock_bh(&txq
->lock
);
1027 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans
*trans
,
1028 const struct iwl_host_cmd
*cmd
)
1030 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1033 lockdep_assert_held(&trans_pcie
->reg_lock
);
1035 if (!(cmd
->flags
& CMD_SEND_IN_IDLE
) &&
1036 !trans_pcie
->ref_cmd_in_flight
) {
1037 trans_pcie
->ref_cmd_in_flight
= true;
1038 IWL_DEBUG_RPM(trans
, "set ref_cmd_in_flight - ref\n");
1039 iwl_trans_pcie_ref(trans
);
1043 * wake up the NIC to make sure that the firmware will see the host
1044 * command - we will let the NIC sleep once all the host commands
1045 * returned. This needs to be done only on NICs that have
1046 * apmg_wake_up_wa set.
1048 if (trans
->cfg
->base_params
->apmg_wake_up_wa
&&
1049 !trans_pcie
->cmd_hold_nic_awake
) {
1050 __iwl_trans_pcie_set_bit(trans
, CSR_GP_CNTRL
,
1051 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1053 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
1054 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN
,
1055 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
|
1056 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP
),
1059 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
1060 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1061 IWL_ERR(trans
, "Failed to wake NIC for hcmd\n");
1064 trans_pcie
->cmd_hold_nic_awake
= true;
1070 static int iwl_pcie_clear_cmd_in_flight(struct iwl_trans
*trans
)
1072 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1074 lockdep_assert_held(&trans_pcie
->reg_lock
);
1076 if (trans_pcie
->ref_cmd_in_flight
) {
1077 trans_pcie
->ref_cmd_in_flight
= false;
1078 IWL_DEBUG_RPM(trans
, "clear ref_cmd_in_flight - unref\n");
1079 iwl_trans_pcie_unref(trans
);
1082 if (trans
->cfg
->base_params
->apmg_wake_up_wa
) {
1083 if (WARN_ON(!trans_pcie
->cmd_hold_nic_awake
))
1086 trans_pcie
->cmd_hold_nic_awake
= false;
1087 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
1088 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1094 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1096 * When FW advances 'R' index, all entries between old and new 'R' index
1097 * need to be reclaimed. As result, some free space forms. If there is
1098 * enough free space (> low mark), wake the stack that feeds us.
1100 static void iwl_pcie_cmdq_reclaim(struct iwl_trans
*trans
, int txq_id
, int idx
)
1102 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1103 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
1104 struct iwl_queue
*q
= &txq
->q
;
1105 unsigned long flags
;
1108 lockdep_assert_held(&txq
->lock
);
1110 if ((idx
>= TFD_QUEUE_SIZE_MAX
) || (!iwl_queue_used(q
, idx
))) {
1112 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1113 __func__
, txq_id
, idx
, TFD_QUEUE_SIZE_MAX
,
1114 q
->write_ptr
, q
->read_ptr
);
1118 for (idx
= iwl_queue_inc_wrap(idx
); q
->read_ptr
!= idx
;
1119 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
)) {
1122 IWL_ERR(trans
, "HCMD skipped: index (%d) %d %d\n",
1123 idx
, q
->write_ptr
, q
->read_ptr
);
1124 iwl_force_nmi(trans
);
1128 if (q
->read_ptr
== q
->write_ptr
) {
1129 spin_lock_irqsave(&trans_pcie
->reg_lock
, flags
);
1130 iwl_pcie_clear_cmd_in_flight(trans
);
1131 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
1134 iwl_pcie_txq_progress(txq
);
1137 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans
*trans
, u16 ra_tid
,
1140 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1145 scd_q2ratid
= ra_tid
& SCD_QUEUE_RA_TID_MAP_RATID_MSK
;
1147 tbl_dw_addr
= trans_pcie
->scd_base_addr
+
1148 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id
);
1150 tbl_dw
= iwl_trans_read_mem32(trans
, tbl_dw_addr
);
1153 tbl_dw
= (scd_q2ratid
<< 16) | (tbl_dw
& 0x0000FFFF);
1155 tbl_dw
= scd_q2ratid
| (tbl_dw
& 0xFFFF0000);
1157 iwl_trans_write_mem32(trans
, tbl_dw_addr
, tbl_dw
);
1162 /* Receiver address (actually, Rx station's index into station table),
1163 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1164 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1166 void iwl_trans_pcie_txq_enable(struct iwl_trans
*trans
, int txq_id
, u16 ssn
,
1167 const struct iwl_trans_txq_scd_cfg
*cfg
,
1168 unsigned int wdg_timeout
)
1170 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1171 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
1174 if (test_and_set_bit(txq_id
, trans_pcie
->queue_used
))
1175 WARN_ONCE(1, "queue %d already used - expect issues", txq_id
);
1177 txq
->wd_timeout
= msecs_to_jiffies(wdg_timeout
);
1182 /* Disable the scheduler prior configuring the cmd queue */
1183 if (txq_id
== trans_pcie
->cmd_queue
&&
1184 trans_pcie
->scd_set_active
)
1185 iwl_scd_enable_set_active(trans
, 0);
1187 /* Stop this Tx queue before configuring it */
1188 iwl_scd_txq_set_inactive(trans
, txq_id
);
1190 /* Set this queue as a chain-building queue unless it is CMD */
1191 if (txq_id
!= trans_pcie
->cmd_queue
)
1192 iwl_scd_txq_set_chain(trans
, txq_id
);
1194 if (cfg
->aggregate
) {
1195 u16 ra_tid
= BUILD_RAxTID(cfg
->sta_id
, cfg
->tid
);
1197 /* Map receiver-address / traffic-ID to this queue */
1198 iwl_pcie_txq_set_ratid_map(trans
, ra_tid
, txq_id
);
1200 /* enable aggregations for the queue */
1201 iwl_scd_txq_enable_agg(trans
, txq_id
);
1205 * disable aggregations for the queue, this will also
1206 * make the ra_tid mapping configuration irrelevant
1207 * since it is now a non-AGG queue.
1209 iwl_scd_txq_disable_agg(trans
, txq_id
);
1211 ssn
= txq
->q
.read_ptr
;
1215 /* Place first TFD at index corresponding to start sequence number.
1216 * Assumes that ssn_idx is valid (!= 0xFFF) */
1217 txq
->q
.read_ptr
= (ssn
& 0xff);
1218 txq
->q
.write_ptr
= (ssn
& 0xff);
1219 iwl_write_direct32(trans
, HBUS_TARG_WRPTR
,
1220 (ssn
& 0xff) | (txq_id
<< 8));
1223 u8 frame_limit
= cfg
->frame_limit
;
1225 iwl_write_prph(trans
, SCD_QUEUE_RDPTR(txq_id
), ssn
);
1227 /* Set up Tx window size and frame limit for this queue */
1228 iwl_trans_write_mem32(trans
, trans_pcie
->scd_base_addr
+
1229 SCD_CONTEXT_QUEUE_OFFSET(txq_id
), 0);
1230 iwl_trans_write_mem32(trans
,
1231 trans_pcie
->scd_base_addr
+
1232 SCD_CONTEXT_QUEUE_OFFSET(txq_id
) + sizeof(u32
),
1233 ((frame_limit
<< SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
1234 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
1235 ((frame_limit
<< SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
1236 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
1238 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1239 iwl_write_prph(trans
, SCD_QUEUE_STATUS_BITS(txq_id
),
1240 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE
) |
1241 (cfg
->fifo
<< SCD_QUEUE_STTS_REG_POS_TXF
) |
1242 (1 << SCD_QUEUE_STTS_REG_POS_WSL
) |
1243 SCD_QUEUE_STTS_REG_MSK
);
1245 /* enable the scheduler for this queue (only) */
1246 if (txq_id
== trans_pcie
->cmd_queue
&&
1247 trans_pcie
->scd_set_active
)
1248 iwl_scd_enable_set_active(trans
, BIT(txq_id
));
1250 IWL_DEBUG_TX_QUEUES(trans
,
1251 "Activate queue %d on FIFO %d WrPtr: %d\n",
1252 txq_id
, fifo
, ssn
& 0xff);
1254 IWL_DEBUG_TX_QUEUES(trans
,
1255 "Activate queue %d WrPtr: %d\n",
1256 txq_id
, ssn
& 0xff);
1262 void iwl_trans_pcie_txq_disable(struct iwl_trans
*trans
, int txq_id
,
1265 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1266 u32 stts_addr
= trans_pcie
->scd_base_addr
+
1267 SCD_TX_STTS_QUEUE_OFFSET(txq_id
);
1268 static const u32 zero_val
[4] = {};
1270 trans_pcie
->txq
[txq_id
].frozen_expiry_remainder
= 0;
1271 trans_pcie
->txq
[txq_id
].frozen
= false;
1274 * Upon HW Rfkill - we stop the device, and then stop the queues
1275 * in the op_mode. Just for the sake of the simplicity of the op_mode,
1276 * allow the op_mode to call txq_disable after it already called
1279 if (!test_and_clear_bit(txq_id
, trans_pcie
->queue_used
)) {
1280 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED
, &trans
->status
),
1281 "queue %d not used", txq_id
);
1285 if (configure_scd
) {
1286 iwl_scd_txq_set_inactive(trans
, txq_id
);
1288 iwl_trans_write_mem(trans
, stts_addr
, (void *)zero_val
,
1289 ARRAY_SIZE(zero_val
));
1292 iwl_pcie_txq_unmap(trans
, txq_id
);
1293 trans_pcie
->txq
[txq_id
].ampdu
= false;
1295 IWL_DEBUG_TX_QUEUES(trans
, "Deactivate queue %d\n", txq_id
);
1298 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1301 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1302 * @priv: device private data point
1303 * @cmd: a pointer to the ucode command structure
1305 * The function returns < 0 values to indicate the operation
1306 * failed. On success, it returns the index (>= 0) of command in the
1309 static int iwl_pcie_enqueue_hcmd(struct iwl_trans
*trans
,
1310 struct iwl_host_cmd
*cmd
)
1312 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1313 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1314 struct iwl_queue
*q
= &txq
->q
;
1315 struct iwl_device_cmd
*out_cmd
;
1316 struct iwl_cmd_meta
*out_meta
;
1317 unsigned long flags
;
1318 void *dup_buf
= NULL
;
1319 dma_addr_t phys_addr
;
1321 u16 copy_size
, cmd_size
, scratch_size
;
1322 bool had_nocopy
= false;
1325 const u8
*cmddata
[IWL_MAX_CMD_TBS_PER_TFD
];
1326 u16 cmdlen
[IWL_MAX_CMD_TBS_PER_TFD
];
1328 copy_size
= sizeof(out_cmd
->hdr
);
1329 cmd_size
= sizeof(out_cmd
->hdr
);
1331 /* need one for the header if the first is NOCOPY */
1332 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD
> IWL_NUM_OF_TBS
- 1);
1334 for (i
= 0; i
< IWL_MAX_CMD_TBS_PER_TFD
; i
++) {
1335 cmddata
[i
] = cmd
->data
[i
];
1336 cmdlen
[i
] = cmd
->len
[i
];
1341 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1342 if (copy_size
< IWL_HCMD_SCRATCHBUF_SIZE
) {
1343 int copy
= IWL_HCMD_SCRATCHBUF_SIZE
- copy_size
;
1345 if (copy
> cmdlen
[i
])
1352 if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_NOCOPY
) {
1354 if (WARN_ON(cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
)) {
1358 } else if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
) {
1360 * This is also a chunk that isn't copied
1361 * to the static buffer so set had_nocopy.
1365 /* only allowed once */
1366 if (WARN_ON(dup_buf
)) {
1371 dup_buf
= kmemdup(cmddata
[i
], cmdlen
[i
],
1376 /* NOCOPY must not be followed by normal! */
1377 if (WARN_ON(had_nocopy
)) {
1381 copy_size
+= cmdlen
[i
];
1383 cmd_size
+= cmd
->len
[i
];
1387 * If any of the command structures end up being larger than
1388 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1389 * allocated into separate TFDs, then we will need to
1390 * increase the size of the buffers.
1392 if (WARN(copy_size
> TFD_MAX_PAYLOAD_SIZE
,
1393 "Command %s (%#x) is too large (%d bytes)\n",
1394 get_cmd_string(trans_pcie
, cmd
->id
), cmd
->id
, copy_size
)) {
1399 spin_lock_bh(&txq
->lock
);
1401 if (iwl_queue_space(q
) < ((cmd
->flags
& CMD_ASYNC
) ? 2 : 1)) {
1402 spin_unlock_bh(&txq
->lock
);
1404 IWL_ERR(trans
, "No space in command queue\n");
1405 iwl_op_mode_cmd_queue_full(trans
->op_mode
);
1410 idx
= get_cmd_index(q
, q
->write_ptr
);
1411 out_cmd
= txq
->entries
[idx
].cmd
;
1412 out_meta
= &txq
->entries
[idx
].meta
;
1414 memset(out_meta
, 0, sizeof(*out_meta
)); /* re-initialize to NULL */
1415 if (cmd
->flags
& CMD_WANT_SKB
)
1416 out_meta
->source
= cmd
;
1418 /* set up the header */
1420 out_cmd
->hdr
.cmd
= cmd
->id
;
1421 out_cmd
->hdr
.flags
= 0;
1422 out_cmd
->hdr
.sequence
=
1423 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie
->cmd_queue
) |
1424 INDEX_TO_SEQ(q
->write_ptr
));
1426 /* and copy the data that needs to be copied */
1427 cmd_pos
= offsetof(struct iwl_device_cmd
, payload
);
1428 copy_size
= sizeof(out_cmd
->hdr
);
1429 for (i
= 0; i
< IWL_MAX_CMD_TBS_PER_TFD
; i
++) {
1435 /* copy everything if not nocopy/dup */
1436 if (!(cmd
->dataflags
[i
] & (IWL_HCMD_DFL_NOCOPY
|
1437 IWL_HCMD_DFL_DUP
))) {
1440 memcpy((u8
*)out_cmd
+ cmd_pos
, cmd
->data
[i
], copy
);
1447 * Otherwise we need at least IWL_HCMD_SCRATCHBUF_SIZE copied
1448 * in total (for the scratchbuf handling), but copy up to what
1449 * we can fit into the payload for debug dump purposes.
1451 copy
= min_t(int, TFD_MAX_PAYLOAD_SIZE
- cmd_pos
, cmd
->len
[i
]);
1453 memcpy((u8
*)out_cmd
+ cmd_pos
, cmd
->data
[i
], copy
);
1456 /* However, treat copy_size the proper way, we need it below */
1457 if (copy_size
< IWL_HCMD_SCRATCHBUF_SIZE
) {
1458 copy
= IWL_HCMD_SCRATCHBUF_SIZE
- copy_size
;
1460 if (copy
> cmd
->len
[i
])
1467 "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1468 get_cmd_string(trans_pcie
, out_cmd
->hdr
.cmd
),
1469 out_cmd
->hdr
.cmd
, le16_to_cpu(out_cmd
->hdr
.sequence
),
1470 cmd_size
, q
->write_ptr
, idx
, trans_pcie
->cmd_queue
);
1472 /* start the TFD with the scratchbuf */
1473 scratch_size
= min_t(int, copy_size
, IWL_HCMD_SCRATCHBUF_SIZE
);
1474 memcpy(&txq
->scratchbufs
[q
->write_ptr
], &out_cmd
->hdr
, scratch_size
);
1475 iwl_pcie_txq_build_tfd(trans
, txq
,
1476 iwl_pcie_get_scratchbuf_dma(txq
, q
->write_ptr
),
1477 scratch_size
, true);
1479 /* map first command fragment, if any remains */
1480 if (copy_size
> scratch_size
) {
1481 phys_addr
= dma_map_single(trans
->dev
,
1482 ((u8
*)&out_cmd
->hdr
) + scratch_size
,
1483 copy_size
- scratch_size
,
1485 if (dma_mapping_error(trans
->dev
, phys_addr
)) {
1486 iwl_pcie_tfd_unmap(trans
, out_meta
,
1487 &txq
->tfds
[q
->write_ptr
]);
1492 iwl_pcie_txq_build_tfd(trans
, txq
, phys_addr
,
1493 copy_size
- scratch_size
, false);
1496 /* map the remaining (adjusted) nocopy/dup fragments */
1497 for (i
= 0; i
< IWL_MAX_CMD_TBS_PER_TFD
; i
++) {
1498 const void *data
= cmddata
[i
];
1502 if (!(cmd
->dataflags
[i
] & (IWL_HCMD_DFL_NOCOPY
|
1505 if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
)
1507 phys_addr
= dma_map_single(trans
->dev
, (void *)data
,
1508 cmdlen
[i
], DMA_TO_DEVICE
);
1509 if (dma_mapping_error(trans
->dev
, phys_addr
)) {
1510 iwl_pcie_tfd_unmap(trans
, out_meta
,
1511 &txq
->tfds
[q
->write_ptr
]);
1516 iwl_pcie_txq_build_tfd(trans
, txq
, phys_addr
, cmdlen
[i
], false);
1519 out_meta
->flags
= cmd
->flags
;
1520 if (WARN_ON_ONCE(txq
->entries
[idx
].free_buf
))
1521 kzfree(txq
->entries
[idx
].free_buf
);
1522 txq
->entries
[idx
].free_buf
= dup_buf
;
1524 trace_iwlwifi_dev_hcmd(trans
->dev
, cmd
, cmd_size
, &out_cmd
->hdr
);
1526 /* start timer if queue currently empty */
1527 if (q
->read_ptr
== q
->write_ptr
&& txq
->wd_timeout
)
1528 mod_timer(&txq
->stuck_timer
, jiffies
+ txq
->wd_timeout
);
1530 spin_lock_irqsave(&trans_pcie
->reg_lock
, flags
);
1531 ret
= iwl_pcie_set_cmd_in_flight(trans
, cmd
);
1534 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
1538 /* Increment and update queue's write index */
1539 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
);
1540 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
1542 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
1545 spin_unlock_bh(&txq
->lock
);
1553 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1554 * @rxb: Rx buffer to reclaim
1555 * @handler_status: return value of the handler of the command
1556 * (put in setup_rx_handlers)
1558 * If an Rx buffer has an async callback associated with it the callback
1559 * will be executed. The attached skb (if present) will only be freed
1560 * if the callback returns 1
1562 void iwl_pcie_hcmd_complete(struct iwl_trans
*trans
,
1563 struct iwl_rx_cmd_buffer
*rxb
, int handler_status
)
1565 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
1566 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
1567 int txq_id
= SEQ_TO_QUEUE(sequence
);
1568 int index
= SEQ_TO_INDEX(sequence
);
1570 struct iwl_device_cmd
*cmd
;
1571 struct iwl_cmd_meta
*meta
;
1572 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1573 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1575 /* If a Tx command is being handled and it isn't in the actual
1576 * command queue then there a command routing bug has been introduced
1577 * in the queue management code. */
1578 if (WARN(txq_id
!= trans_pcie
->cmd_queue
,
1579 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1580 txq_id
, trans_pcie
->cmd_queue
, sequence
,
1581 trans_pcie
->txq
[trans_pcie
->cmd_queue
].q
.read_ptr
,
1582 trans_pcie
->txq
[trans_pcie
->cmd_queue
].q
.write_ptr
)) {
1583 iwl_print_hex_error(trans
, pkt
, 32);
1587 spin_lock_bh(&txq
->lock
);
1589 cmd_index
= get_cmd_index(&txq
->q
, index
);
1590 cmd
= txq
->entries
[cmd_index
].cmd
;
1591 meta
= &txq
->entries
[cmd_index
].meta
;
1593 iwl_pcie_tfd_unmap(trans
, meta
, &txq
->tfds
[index
]);
1595 /* Input error checking is done when commands are added to queue. */
1596 if (meta
->flags
& CMD_WANT_SKB
) {
1597 struct page
*p
= rxb_steal_page(rxb
);
1599 meta
->source
->resp_pkt
= pkt
;
1600 meta
->source
->_rx_page_addr
= (unsigned long)page_address(p
);
1601 meta
->source
->_rx_page_order
= trans_pcie
->rx_page_order
;
1602 meta
->source
->handler_status
= handler_status
;
1605 iwl_pcie_cmdq_reclaim(trans
, txq_id
, index
);
1607 if (!(meta
->flags
& CMD_ASYNC
)) {
1608 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
)) {
1610 "HCMD_ACTIVE already clear for command %s\n",
1611 get_cmd_string(trans_pcie
, cmd
->hdr
.cmd
));
1613 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1614 IWL_DEBUG_INFO(trans
, "Clearing HCMD_ACTIVE for command %s\n",
1615 get_cmd_string(trans_pcie
, cmd
->hdr
.cmd
));
1616 wake_up(&trans_pcie
->wait_command_queue
);
1621 spin_unlock_bh(&txq
->lock
);
1624 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
1626 static int iwl_pcie_send_hcmd_async(struct iwl_trans
*trans
,
1627 struct iwl_host_cmd
*cmd
)
1629 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1632 /* An asynchronous command can not expect an SKB to be set. */
1633 if (WARN_ON(cmd
->flags
& CMD_WANT_SKB
))
1636 ret
= iwl_pcie_enqueue_hcmd(trans
, cmd
);
1639 "Error sending %s: enqueue_hcmd failed: %d\n",
1640 get_cmd_string(trans_pcie
, cmd
->id
), ret
);
1646 static int iwl_pcie_send_hcmd_sync(struct iwl_trans
*trans
,
1647 struct iwl_host_cmd
*cmd
)
1649 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1653 IWL_DEBUG_INFO(trans
, "Attempting to send sync command %s\n",
1654 get_cmd_string(trans_pcie
, cmd
->id
));
1656 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE
,
1658 "Command %s: a command is already active!\n",
1659 get_cmd_string(trans_pcie
, cmd
->id
)))
1662 IWL_DEBUG_INFO(trans
, "Setting HCMD_ACTIVE for command %s\n",
1663 get_cmd_string(trans_pcie
, cmd
->id
));
1665 cmd_idx
= iwl_pcie_enqueue_hcmd(trans
, cmd
);
1668 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1670 "Error sending %s: enqueue_hcmd failed: %d\n",
1671 get_cmd_string(trans_pcie
, cmd
->id
), ret
);
1675 ret
= wait_event_timeout(trans_pcie
->wait_command_queue
,
1676 !test_bit(STATUS_SYNC_HCMD_ACTIVE
,
1678 HOST_COMPLETE_TIMEOUT
);
1680 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1681 struct iwl_queue
*q
= &txq
->q
;
1683 IWL_ERR(trans
, "Error sending %s: time out after %dms.\n",
1684 get_cmd_string(trans_pcie
, cmd
->id
),
1685 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT
));
1687 IWL_ERR(trans
, "Current CMD queue read_ptr %d write_ptr %d\n",
1688 q
->read_ptr
, q
->write_ptr
);
1690 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1691 IWL_DEBUG_INFO(trans
, "Clearing HCMD_ACTIVE for command %s\n",
1692 get_cmd_string(trans_pcie
, cmd
->id
));
1695 iwl_force_nmi(trans
);
1696 iwl_trans_fw_error(trans
);
1701 if (test_bit(STATUS_FW_ERROR
, &trans
->status
)) {
1702 IWL_ERR(trans
, "FW error in SYNC CMD %s\n",
1703 get_cmd_string(trans_pcie
, cmd
->id
));
1709 if (!(cmd
->flags
& CMD_SEND_IN_RFKILL
) &&
1710 test_bit(STATUS_RFKILL
, &trans
->status
)) {
1711 IWL_DEBUG_RF_KILL(trans
, "RFKILL in SYNC CMD... no rsp\n");
1716 if ((cmd
->flags
& CMD_WANT_SKB
) && !cmd
->resp_pkt
) {
1717 IWL_ERR(trans
, "Error: Response NULL in '%s'\n",
1718 get_cmd_string(trans_pcie
, cmd
->id
));
1726 if (cmd
->flags
& CMD_WANT_SKB
) {
1728 * Cancel the CMD_WANT_SKB flag for the cmd in the
1729 * TX cmd queue. Otherwise in case the cmd comes
1730 * in later, it will possibly set an invalid
1731 * address (cmd->meta.source).
1733 trans_pcie
->txq
[trans_pcie
->cmd_queue
].
1734 entries
[cmd_idx
].meta
.flags
&= ~CMD_WANT_SKB
;
1737 if (cmd
->resp_pkt
) {
1739 cmd
->resp_pkt
= NULL
;
1745 int iwl_trans_pcie_send_hcmd(struct iwl_trans
*trans
, struct iwl_host_cmd
*cmd
)
1747 if (!(cmd
->flags
& CMD_SEND_IN_RFKILL
) &&
1748 test_bit(STATUS_RFKILL
, &trans
->status
)) {
1749 IWL_DEBUG_RF_KILL(trans
, "Dropping CMD 0x%x: RF KILL\n",
1754 if (cmd
->flags
& CMD_ASYNC
)
1755 return iwl_pcie_send_hcmd_async(trans
, cmd
);
1757 /* We still can fail on RFKILL that can be asserted while we wait */
1758 return iwl_pcie_send_hcmd_sync(trans
, cmd
);
1761 int iwl_trans_pcie_tx(struct iwl_trans
*trans
, struct sk_buff
*skb
,
1762 struct iwl_device_cmd
*dev_cmd
, int txq_id
)
1764 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1765 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1766 struct iwl_tx_cmd
*tx_cmd
= (struct iwl_tx_cmd
*)dev_cmd
->payload
;
1767 struct iwl_cmd_meta
*out_meta
;
1768 struct iwl_txq
*txq
;
1769 struct iwl_queue
*q
;
1770 dma_addr_t tb0_phys
, tb1_phys
, scratch_phys
;
1772 u16 len
, tb1_len
, tb2_len
;
1773 bool wait_write_ptr
;
1774 __le16 fc
= hdr
->frame_control
;
1775 u8 hdr_len
= ieee80211_hdrlen(fc
);
1778 txq
= &trans_pcie
->txq
[txq_id
];
1781 if (WARN_ONCE(!test_bit(txq_id
, trans_pcie
->queue_used
),
1782 "TX on unused queue %d\n", txq_id
))
1785 spin_lock(&txq
->lock
);
1787 /* In AGG mode, the index in the ring must correspond to the WiFi
1788 * sequence number. This is a HW requirements to help the SCD to parse
1790 * Check here that the packets are in the right place on the ring.
1792 wifi_seq
= IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr
->seq_ctrl
));
1793 WARN_ONCE(txq
->ampdu
&&
1794 (wifi_seq
& 0xff) != q
->write_ptr
,
1795 "Q: %d WiFi Seq %d tfdNum %d",
1796 txq_id
, wifi_seq
, q
->write_ptr
);
1798 /* Set up driver data for this TFD */
1799 txq
->entries
[q
->write_ptr
].skb
= skb
;
1800 txq
->entries
[q
->write_ptr
].cmd
= dev_cmd
;
1802 dev_cmd
->hdr
.sequence
=
1803 cpu_to_le16((u16
)(QUEUE_TO_SEQ(txq_id
) |
1804 INDEX_TO_SEQ(q
->write_ptr
)));
1806 tb0_phys
= iwl_pcie_get_scratchbuf_dma(txq
, q
->write_ptr
);
1807 scratch_phys
= tb0_phys
+ sizeof(struct iwl_cmd_header
) +
1808 offsetof(struct iwl_tx_cmd
, scratch
);
1810 tx_cmd
->dram_lsb_ptr
= cpu_to_le32(scratch_phys
);
1811 tx_cmd
->dram_msb_ptr
= iwl_get_dma_hi_addr(scratch_phys
);
1813 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1814 out_meta
= &txq
->entries
[q
->write_ptr
].meta
;
1817 * The second TB (tb1) points to the remainder of the TX command
1818 * and the 802.11 header - dword aligned size
1819 * (This calculation modifies the TX command, so do it before the
1820 * setup of the first TB)
1822 len
= sizeof(struct iwl_tx_cmd
) + sizeof(struct iwl_cmd_header
) +
1823 hdr_len
- IWL_HCMD_SCRATCHBUF_SIZE
;
1824 tb1_len
= ALIGN(len
, 4);
1826 /* Tell NIC about any 2-byte padding after MAC header */
1828 tx_cmd
->tx_flags
|= TX_CMD_FLG_MH_PAD_MSK
;
1830 /* The first TB points to the scratchbuf data - min_copy bytes */
1831 memcpy(&txq
->scratchbufs
[q
->write_ptr
], &dev_cmd
->hdr
,
1832 IWL_HCMD_SCRATCHBUF_SIZE
);
1833 iwl_pcie_txq_build_tfd(trans
, txq
, tb0_phys
,
1834 IWL_HCMD_SCRATCHBUF_SIZE
, true);
1836 /* there must be data left over for TB1 or this code must be changed */
1837 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd
) < IWL_HCMD_SCRATCHBUF_SIZE
);
1839 /* map the data for TB1 */
1840 tb1_addr
= ((u8
*)&dev_cmd
->hdr
) + IWL_HCMD_SCRATCHBUF_SIZE
;
1841 tb1_phys
= dma_map_single(trans
->dev
, tb1_addr
, tb1_len
, DMA_TO_DEVICE
);
1842 if (unlikely(dma_mapping_error(trans
->dev
, tb1_phys
)))
1844 iwl_pcie_txq_build_tfd(trans
, txq
, tb1_phys
, tb1_len
, false);
1847 * Set up TFD's third entry to point directly to remainder
1848 * of skb, if any (802.11 null frames have no payload).
1850 tb2_len
= skb
->len
- hdr_len
;
1852 dma_addr_t tb2_phys
= dma_map_single(trans
->dev
,
1853 skb
->data
+ hdr_len
,
1854 tb2_len
, DMA_TO_DEVICE
);
1855 if (unlikely(dma_mapping_error(trans
->dev
, tb2_phys
))) {
1856 iwl_pcie_tfd_unmap(trans
, out_meta
,
1857 &txq
->tfds
[q
->write_ptr
]);
1860 iwl_pcie_txq_build_tfd(trans
, txq
, tb2_phys
, tb2_len
, false);
1863 /* Set up entry for this TFD in Tx byte-count array */
1864 iwl_pcie_txq_update_byte_cnt_tbl(trans
, txq
, le16_to_cpu(tx_cmd
->len
));
1866 trace_iwlwifi_dev_tx(trans
->dev
, skb
,
1867 &txq
->tfds
[txq
->q
.write_ptr
],
1868 sizeof(struct iwl_tfd
),
1869 &dev_cmd
->hdr
, IWL_HCMD_SCRATCHBUF_SIZE
+ tb1_len
,
1870 skb
->data
+ hdr_len
, tb2_len
);
1871 trace_iwlwifi_dev_tx_data(trans
->dev
, skb
,
1872 skb
->data
+ hdr_len
, tb2_len
);
1874 wait_write_ptr
= ieee80211_has_morefrags(fc
);
1876 /* start timer if queue currently empty */
1877 if (q
->read_ptr
== q
->write_ptr
) {
1878 if (txq
->wd_timeout
)
1879 mod_timer(&txq
->stuck_timer
, jiffies
+ txq
->wd_timeout
);
1880 IWL_DEBUG_RPM(trans
, "Q: %d first tx - take ref\n", q
->id
);
1881 iwl_trans_pcie_ref(trans
);
1884 /* Tell device the write index *just past* this latest filled TFD */
1885 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
);
1886 if (!wait_write_ptr
)
1887 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
1890 * At this point the frame is "transmitted" successfully
1891 * and we will get a TX status notification eventually.
1893 if (iwl_queue_space(q
) < q
->high_mark
) {
1895 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
1897 iwl_stop_queue(trans
, txq
);
1899 spin_unlock(&txq
->lock
);
1902 spin_unlock(&txq
->lock
);