1 /******************************************************************************
3 * Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/slab.h>
31 #include <linux/sched.h>
33 #include "iwl-debug.h"
37 #include "iwl-op-mode.h"
39 /* FIXME: need to abstract out TX command (once we know what it looks like) */
40 #include "dvm/commands.h"
42 #define IWL_TX_CRC_SIZE 4
43 #define IWL_TX_DELIMITER_SIZE 4
45 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
50 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
51 * of buffer descriptors, each of which points to one or more data buffers for
52 * the device to read from or fill. Driver and device exchange status of each
53 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
54 * entries in each circular buffer, to protect against confusing empty and full
57 * The device reads or writes the data in the queues via the device's several
58 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
60 * For Tx queue, there are low mark and high mark limits. If, after queuing
61 * the packet for Tx, free space become < low mark, Tx queue stopped. When
62 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
65 ***************************************************/
66 static int iwl_queue_space(const struct iwl_queue
*q
)
68 int s
= q
->read_ptr
- q
->write_ptr
;
70 if (q
->read_ptr
> q
->write_ptr
)
75 /* keep some reserve to not confuse empty and full situations */
83 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
85 static int iwl_queue_init(struct iwl_queue
*q
, int count
, int slots_num
, u32 id
)
88 q
->n_window
= slots_num
;
91 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
92 * and iwl_queue_dec_wrap are broken. */
93 if (WARN_ON(!is_power_of_2(count
)))
96 /* slots_num must be power-of-two size, otherwise
97 * get_cmd_index is broken. */
98 if (WARN_ON(!is_power_of_2(slots_num
)))
101 q
->low_mark
= q
->n_window
/ 4;
105 q
->high_mark
= q
->n_window
/ 8;
106 if (q
->high_mark
< 2)
115 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans
*trans
,
116 struct iwl_dma_ptr
*ptr
, size_t size
)
118 if (WARN_ON(ptr
->addr
))
121 ptr
->addr
= dma_alloc_coherent(trans
->dev
, size
,
122 &ptr
->dma
, GFP_KERNEL
);
129 static void iwl_pcie_free_dma_ptr(struct iwl_trans
*trans
,
130 struct iwl_dma_ptr
*ptr
)
132 if (unlikely(!ptr
->addr
))
135 dma_free_coherent(trans
->dev
, ptr
->size
, ptr
->addr
, ptr
->dma
);
136 memset(ptr
, 0, sizeof(*ptr
));
139 static void iwl_pcie_txq_stuck_timer(unsigned long data
)
141 struct iwl_txq
*txq
= (void *)data
;
142 struct iwl_queue
*q
= &txq
->q
;
143 struct iwl_trans_pcie
*trans_pcie
= txq
->trans_pcie
;
144 struct iwl_trans
*trans
= iwl_trans_pcie_get_trans(trans_pcie
);
145 u32 scd_sram_addr
= trans_pcie
->scd_base_addr
+
146 SCD_TX_STTS_QUEUE_OFFSET(txq
->q
.id
);
150 spin_lock(&txq
->lock
);
151 /* check if triggered erroneously */
152 if (txq
->q
.read_ptr
== txq
->q
.write_ptr
) {
153 spin_unlock(&txq
->lock
);
156 spin_unlock(&txq
->lock
);
158 IWL_ERR(trans
, "Queue %d stuck for %u ms.\n", txq
->q
.id
,
159 jiffies_to_msecs(trans_pcie
->wd_timeout
));
160 IWL_ERR(trans
, "Current SW read_ptr %d write_ptr %d\n",
161 txq
->q
.read_ptr
, txq
->q
.write_ptr
);
163 iwl_trans_read_mem_bytes(trans
, scd_sram_addr
, buf
, sizeof(buf
));
165 iwl_print_hex_error(trans
, buf
, sizeof(buf
));
167 for (i
= 0; i
< FH_TCSR_CHNL_NUM
; i
++)
168 IWL_ERR(trans
, "FH TRBs(%d) = 0x%08x\n", i
,
169 iwl_read_direct32(trans
, FH_TX_TRB_REG(i
)));
171 for (i
= 0; i
< trans
->cfg
->base_params
->num_of_queues
; i
++) {
172 u32 status
= iwl_read_prph(trans
, SCD_QUEUE_STATUS_BITS(i
));
173 u8 fifo
= (status
>> SCD_QUEUE_STTS_REG_POS_TXF
) & 0x7;
174 bool active
= !!(status
& BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE
));
176 iwl_trans_read_mem32(trans
,
177 trans_pcie
->scd_base_addr
+
178 SCD_TRANS_TBL_OFFSET_QUEUE(i
));
181 tbl_dw
= (tbl_dw
& 0xFFFF0000) >> 16;
183 tbl_dw
= tbl_dw
& 0x0000FFFF;
186 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
187 i
, active
? "" : "in", fifo
, tbl_dw
,
189 SCD_QUEUE_RDPTR(i
)) & (txq
->q
.n_bd
- 1),
190 iwl_read_prph(trans
, SCD_QUEUE_WRPTR(i
)));
193 for (i
= q
->read_ptr
; i
!= q
->write_ptr
;
194 i
= iwl_queue_inc_wrap(i
, q
->n_bd
))
195 IWL_ERR(trans
, "scratch %d = 0x%08x\n", i
,
196 le32_to_cpu(txq
->scratchbufs
[i
].scratch
));
198 iwl_op_mode_nic_error(trans
->op_mode
);
202 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
204 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans
*trans
,
205 struct iwl_txq
*txq
, u16 byte_cnt
)
207 struct iwlagn_scd_bc_tbl
*scd_bc_tbl
;
208 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
209 int write_ptr
= txq
->q
.write_ptr
;
210 int txq_id
= txq
->q
.id
;
213 u16 len
= byte_cnt
+ IWL_TX_CRC_SIZE
+ IWL_TX_DELIMITER_SIZE
;
215 struct iwl_tx_cmd
*tx_cmd
=
216 (void *) txq
->entries
[txq
->q
.write_ptr
].cmd
->payload
;
218 scd_bc_tbl
= trans_pcie
->scd_bc_tbls
.addr
;
220 WARN_ON(len
> 0xFFF || write_ptr
>= TFD_QUEUE_SIZE_MAX
);
222 sta_id
= tx_cmd
->sta_id
;
223 sec_ctl
= tx_cmd
->sec_ctl
;
225 switch (sec_ctl
& TX_CMD_SEC_MSK
) {
229 case TX_CMD_SEC_TKIP
:
233 len
+= WEP_IV_LEN
+ WEP_ICV_LEN
;
237 if (trans_pcie
->bc_table_dword
)
238 len
= DIV_ROUND_UP(len
, 4);
240 bc_ent
= cpu_to_le16(len
| (sta_id
<< 12));
242 scd_bc_tbl
[txq_id
].tfd_offset
[write_ptr
] = bc_ent
;
244 if (write_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
246 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ write_ptr
] = bc_ent
;
249 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans
*trans
,
252 struct iwl_trans_pcie
*trans_pcie
=
253 IWL_TRANS_GET_PCIE_TRANS(trans
);
254 struct iwlagn_scd_bc_tbl
*scd_bc_tbl
= trans_pcie
->scd_bc_tbls
.addr
;
255 int txq_id
= txq
->q
.id
;
256 int read_ptr
= txq
->q
.read_ptr
;
259 struct iwl_tx_cmd
*tx_cmd
=
260 (void *)txq
->entries
[txq
->q
.read_ptr
].cmd
->payload
;
262 WARN_ON(read_ptr
>= TFD_QUEUE_SIZE_MAX
);
264 if (txq_id
!= trans_pcie
->cmd_queue
)
265 sta_id
= tx_cmd
->sta_id
;
267 bc_ent
= cpu_to_le16(1 | (sta_id
<< 12));
268 scd_bc_tbl
[txq_id
].tfd_offset
[read_ptr
] = bc_ent
;
270 if (read_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
272 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ read_ptr
] = bc_ent
;
276 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
278 void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans
*trans
, struct iwl_txq
*txq
)
281 int txq_id
= txq
->q
.id
;
283 if (txq
->need_update
== 0)
286 if (trans
->cfg
->base_params
->shadow_reg_enable
) {
287 /* shadow register enabled */
288 iwl_write32(trans
, HBUS_TARG_WRPTR
,
289 txq
->q
.write_ptr
| (txq_id
<< 8));
291 struct iwl_trans_pcie
*trans_pcie
=
292 IWL_TRANS_GET_PCIE_TRANS(trans
);
293 /* if we're trying to save power */
294 if (test_bit(STATUS_TPOWER_PMI
, &trans_pcie
->status
)) {
295 /* wake up nic if it's powered down ...
296 * uCode will wake up, and interrupt us again, so next
297 * time we'll skip this part. */
298 reg
= iwl_read32(trans
, CSR_UCODE_DRV_GP1
);
300 if (reg
& CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP
) {
301 IWL_DEBUG_INFO(trans
,
302 "Tx queue %d requesting wakeup,"
303 " GP1 = 0x%x\n", txq_id
, reg
);
304 iwl_set_bit(trans
, CSR_GP_CNTRL
,
305 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
309 IWL_DEBUG_TX(trans
, "Q:%d WR: 0x%x\n", txq_id
,
312 iwl_write_direct32(trans
, HBUS_TARG_WRPTR
,
313 txq
->q
.write_ptr
| (txq_id
<< 8));
316 * else not in power-save mode,
317 * uCode will never sleep when we're
318 * trying to tx (during RFKILL, we're not trying to tx).
321 iwl_write32(trans
, HBUS_TARG_WRPTR
,
322 txq
->q
.write_ptr
| (txq_id
<< 8));
324 txq
->need_update
= 0;
327 static inline dma_addr_t
iwl_pcie_tfd_tb_get_addr(struct iwl_tfd
*tfd
, u8 idx
)
329 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
331 dma_addr_t addr
= get_unaligned_le32(&tb
->lo
);
332 if (sizeof(dma_addr_t
) > sizeof(u32
))
334 ((dma_addr_t
)(le16_to_cpu(tb
->hi_n_len
) & 0xF) << 16) << 16;
339 static inline u16
iwl_pcie_tfd_tb_get_len(struct iwl_tfd
*tfd
, u8 idx
)
341 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
343 return le16_to_cpu(tb
->hi_n_len
) >> 4;
346 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd
*tfd
, u8 idx
,
347 dma_addr_t addr
, u16 len
)
349 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
350 u16 hi_n_len
= len
<< 4;
352 put_unaligned_le32(addr
, &tb
->lo
);
353 if (sizeof(dma_addr_t
) > sizeof(u32
))
354 hi_n_len
|= ((addr
>> 16) >> 16) & 0xF;
356 tb
->hi_n_len
= cpu_to_le16(hi_n_len
);
358 tfd
->num_tbs
= idx
+ 1;
361 static inline u8
iwl_pcie_tfd_get_num_tbs(struct iwl_tfd
*tfd
)
363 return tfd
->num_tbs
& 0x1f;
366 static void iwl_pcie_tfd_unmap(struct iwl_trans
*trans
,
367 struct iwl_cmd_meta
*meta
,
373 /* Sanity check on number of chunks */
374 num_tbs
= iwl_pcie_tfd_get_num_tbs(tfd
);
376 if (num_tbs
>= IWL_NUM_OF_TBS
) {
377 IWL_ERR(trans
, "Too many chunks: %i\n", num_tbs
);
378 /* @todo issue fatal error, it is quite serious situation */
382 /* first TB is never freed - it's the scratchbuf data */
384 for (i
= 1; i
< num_tbs
; i
++)
385 dma_unmap_single(trans
->dev
, iwl_pcie_tfd_tb_get_addr(tfd
, i
),
386 iwl_pcie_tfd_tb_get_len(tfd
, i
),
393 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
394 * @trans - transport private data
396 * @dma_dir - the direction of the DMA mapping
398 * Does NOT advance any TFD circular buffer read/write indexes
399 * Does NOT free the TFD itself (which is within circular buffer)
401 static void iwl_pcie_txq_free_tfd(struct iwl_trans
*trans
, struct iwl_txq
*txq
)
403 struct iwl_tfd
*tfd_tmp
= txq
->tfds
;
405 /* rd_ptr is bounded by n_bd and idx is bounded by n_window */
406 int rd_ptr
= txq
->q
.read_ptr
;
407 int idx
= get_cmd_index(&txq
->q
, rd_ptr
);
409 lockdep_assert_held(&txq
->lock
);
411 /* We have only q->n_window txq->entries, but we use q->n_bd tfds */
412 iwl_pcie_tfd_unmap(trans
, &txq
->entries
[idx
].meta
, &tfd_tmp
[rd_ptr
]);
418 skb
= txq
->entries
[idx
].skb
;
420 /* Can be called from irqs-disabled context
421 * If skb is not NULL, it means that the whole queue is being
422 * freed and that the queue is not empty - free the skb
425 iwl_op_mode_free_skb(trans
->op_mode
, skb
);
426 txq
->entries
[idx
].skb
= NULL
;
431 static int iwl_pcie_txq_build_tfd(struct iwl_trans
*trans
, struct iwl_txq
*txq
,
432 dma_addr_t addr
, u16 len
, u8 reset
)
435 struct iwl_tfd
*tfd
, *tfd_tmp
;
440 tfd
= &tfd_tmp
[q
->write_ptr
];
443 memset(tfd
, 0, sizeof(*tfd
));
445 num_tbs
= iwl_pcie_tfd_get_num_tbs(tfd
);
447 /* Each TFD can point to a maximum 20 Tx buffers */
448 if (num_tbs
>= IWL_NUM_OF_TBS
) {
449 IWL_ERR(trans
, "Error can not send more than %d chunks\n",
454 if (WARN_ON(addr
& ~DMA_BIT_MASK(36)))
457 if (unlikely(addr
& ~IWL_TX_DMA_MASK
))
458 IWL_ERR(trans
, "Unaligned address = %llx\n",
459 (unsigned long long)addr
);
461 iwl_pcie_tfd_set_tb(tfd
, num_tbs
, addr
, len
);
466 static int iwl_pcie_txq_alloc(struct iwl_trans
*trans
,
467 struct iwl_txq
*txq
, int slots_num
,
470 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
471 size_t tfd_sz
= sizeof(struct iwl_tfd
) * TFD_QUEUE_SIZE_MAX
;
472 size_t scratchbuf_sz
;
475 if (WARN_ON(txq
->entries
|| txq
->tfds
))
478 setup_timer(&txq
->stuck_timer
, iwl_pcie_txq_stuck_timer
,
480 txq
->trans_pcie
= trans_pcie
;
482 txq
->q
.n_window
= slots_num
;
484 txq
->entries
= kcalloc(slots_num
,
485 sizeof(struct iwl_pcie_txq_entry
),
491 if (txq_id
== trans_pcie
->cmd_queue
)
492 for (i
= 0; i
< slots_num
; i
++) {
493 txq
->entries
[i
].cmd
=
494 kmalloc(sizeof(struct iwl_device_cmd
),
496 if (!txq
->entries
[i
].cmd
)
500 /* Circular buffer of transmit frame descriptors (TFDs),
501 * shared with device */
502 txq
->tfds
= dma_alloc_coherent(trans
->dev
, tfd_sz
,
503 &txq
->q
.dma_addr
, GFP_KERNEL
);
505 IWL_ERR(trans
, "dma_alloc_coherent(%zd) failed\n", tfd_sz
);
509 BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE
!= sizeof(*txq
->scratchbufs
));
510 BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf
, scratch
) !=
511 sizeof(struct iwl_cmd_header
) +
512 offsetof(struct iwl_tx_cmd
, scratch
));
514 scratchbuf_sz
= sizeof(*txq
->scratchbufs
) * slots_num
;
516 txq
->scratchbufs
= dma_alloc_coherent(trans
->dev
, scratchbuf_sz
,
517 &txq
->scratchbufs_dma
,
519 if (!txq
->scratchbufs
)
526 dma_free_coherent(trans
->dev
, tfd_sz
, txq
->tfds
, txq
->q
.dma_addr
);
528 if (txq
->entries
&& txq_id
== trans_pcie
->cmd_queue
)
529 for (i
= 0; i
< slots_num
; i
++)
530 kfree(txq
->entries
[i
].cmd
);
538 static int iwl_pcie_txq_init(struct iwl_trans
*trans
, struct iwl_txq
*txq
,
539 int slots_num
, u32 txq_id
)
543 txq
->need_update
= 0;
545 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
546 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
547 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
549 /* Initialize queue's high/low-water marks, and head/tail indexes */
550 ret
= iwl_queue_init(&txq
->q
, TFD_QUEUE_SIZE_MAX
, slots_num
,
555 spin_lock_init(&txq
->lock
);
558 * Tell nic where to find circular buffer of Tx Frame Descriptors for
559 * given Tx queue, and enable the DMA channel used for that queue.
560 * Circular buffer (TFD queue in DRAM) physical base address */
561 iwl_write_direct32(trans
, FH_MEM_CBBC_QUEUE(txq_id
),
562 txq
->q
.dma_addr
>> 8);
568 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
570 static void iwl_pcie_txq_unmap(struct iwl_trans
*trans
, int txq_id
)
572 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
573 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
574 struct iwl_queue
*q
= &txq
->q
;
579 spin_lock_bh(&txq
->lock
);
580 while (q
->write_ptr
!= q
->read_ptr
) {
581 iwl_pcie_txq_free_tfd(trans
, txq
);
582 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
);
584 spin_unlock_bh(&txq
->lock
);
588 * iwl_pcie_txq_free - Deallocate DMA queue.
589 * @txq: Transmit queue to deallocate.
591 * Empty queue by removing and destroying all BD's.
593 * 0-fill, but do not free "txq" descriptor structure.
595 static void iwl_pcie_txq_free(struct iwl_trans
*trans
, int txq_id
)
597 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
598 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
599 struct device
*dev
= trans
->dev
;
605 iwl_pcie_txq_unmap(trans
, txq_id
);
607 /* De-alloc array of command/tx buffers */
608 if (txq_id
== trans_pcie
->cmd_queue
)
609 for (i
= 0; i
< txq
->q
.n_window
; i
++) {
610 kfree(txq
->entries
[i
].cmd
);
611 kfree(txq
->entries
[i
].free_buf
);
614 /* De-alloc circular buffer of TFDs */
616 dma_free_coherent(dev
, sizeof(struct iwl_tfd
) *
617 txq
->q
.n_bd
, txq
->tfds
, txq
->q
.dma_addr
);
620 dma_free_coherent(dev
,
621 sizeof(*txq
->scratchbufs
) * txq
->q
.n_window
,
622 txq
->scratchbufs
, txq
->scratchbufs_dma
);
628 del_timer_sync(&txq
->stuck_timer
);
630 /* 0-fill queue descriptor structure */
631 memset(txq
, 0, sizeof(*txq
));
635 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
637 static void iwl_pcie_txq_set_sched(struct iwl_trans
*trans
, u32 mask
)
639 struct iwl_trans_pcie __maybe_unused
*trans_pcie
=
640 IWL_TRANS_GET_PCIE_TRANS(trans
);
642 iwl_write_prph(trans
, SCD_TXFACT
, mask
);
645 void iwl_pcie_tx_start(struct iwl_trans
*trans
, u32 scd_base_addr
)
647 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
648 int nq
= trans
->cfg
->base_params
->num_of_queues
;
651 int clear_dwords
= (SCD_TRANS_TBL_OFFSET_QUEUE(nq
) -
652 SCD_CONTEXT_MEM_LOWER_BOUND
) / sizeof(u32
);
654 /* make sure all queue are not stopped/used */
655 memset(trans_pcie
->queue_stopped
, 0, sizeof(trans_pcie
->queue_stopped
));
656 memset(trans_pcie
->queue_used
, 0, sizeof(trans_pcie
->queue_used
));
658 trans_pcie
->scd_base_addr
=
659 iwl_read_prph(trans
, SCD_SRAM_BASE_ADDR
);
661 WARN_ON(scd_base_addr
!= 0 &&
662 scd_base_addr
!= trans_pcie
->scd_base_addr
);
664 /* reset context data, TX status and translation data */
665 iwl_trans_write_mem(trans
, trans_pcie
->scd_base_addr
+
666 SCD_CONTEXT_MEM_LOWER_BOUND
,
669 iwl_write_prph(trans
, SCD_DRAM_BASE_ADDR
,
670 trans_pcie
->scd_bc_tbls
.dma
>> 10);
672 /* The chain extension of the SCD doesn't work well. This feature is
673 * enabled by default by the HW, so we need to disable it manually.
675 iwl_write_prph(trans
, SCD_CHAINEXT_EN
, 0);
677 iwl_trans_ac_txq_enable(trans
, trans_pcie
->cmd_queue
,
678 trans_pcie
->cmd_fifo
);
680 /* Activate all Tx DMA/FIFO channels */
681 iwl_pcie_txq_set_sched(trans
, IWL_MASK(0, 7));
683 /* Enable DMA channel */
684 for (chan
= 0; chan
< FH_TCSR_CHNL_NUM
; chan
++)
685 iwl_write_direct32(trans
, FH_TCSR_CHNL_TX_CONFIG_REG(chan
),
686 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
687 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
);
689 /* Update FH chicken bits */
690 reg_val
= iwl_read_direct32(trans
, FH_TX_CHICKEN_BITS_REG
);
691 iwl_write_direct32(trans
, FH_TX_CHICKEN_BITS_REG
,
692 reg_val
| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
);
694 /* Enable L1-Active */
695 iwl_clear_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
696 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
699 void iwl_trans_pcie_tx_reset(struct iwl_trans
*trans
)
701 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
704 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
706 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
708 iwl_write_direct32(trans
, FH_MEM_CBBC_QUEUE(txq_id
),
709 txq
->q
.dma_addr
>> 8);
710 iwl_pcie_txq_unmap(trans
, txq_id
);
712 txq
->q
.write_ptr
= 0;
715 /* Tell NIC where to find the "keep warm" buffer */
716 iwl_write_direct32(trans
, FH_KW_MEM_ADDR_REG
,
717 trans_pcie
->kw
.dma
>> 4);
719 iwl_pcie_tx_start(trans
, trans_pcie
->scd_base_addr
);
723 * iwl_pcie_tx_stop - Stop all Tx DMA channels
725 int iwl_pcie_tx_stop(struct iwl_trans
*trans
)
727 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
731 /* Turn off all Tx DMA fifos */
732 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
734 iwl_pcie_txq_set_sched(trans
, 0);
736 /* Stop each Tx DMA channel, and wait for it to be idle */
737 for (ch
= 0; ch
< FH_TCSR_CHNL_NUM
; ch
++) {
738 iwl_write_direct32(trans
,
739 FH_TCSR_CHNL_TX_CONFIG_REG(ch
), 0x0);
740 ret
= iwl_poll_direct_bit(trans
, FH_TSSR_TX_STATUS_REG
,
741 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch
), 1000);
744 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
746 iwl_read_direct32(trans
,
747 FH_TSSR_TX_STATUS_REG
));
749 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
751 if (!trans_pcie
->txq
) {
753 "Stopping tx queues that aren't allocated...\n");
757 /* Unmap DMA from host system and free skb's */
758 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
760 iwl_pcie_txq_unmap(trans
, txq_id
);
766 * iwl_trans_tx_free - Free TXQ Context
768 * Destroy all TX DMA queues and structures
770 void iwl_pcie_tx_free(struct iwl_trans
*trans
)
773 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
776 if (trans_pcie
->txq
) {
778 txq_id
< trans
->cfg
->base_params
->num_of_queues
; txq_id
++)
779 iwl_pcie_txq_free(trans
, txq_id
);
782 kfree(trans_pcie
->txq
);
783 trans_pcie
->txq
= NULL
;
785 iwl_pcie_free_dma_ptr(trans
, &trans_pcie
->kw
);
787 iwl_pcie_free_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
);
791 * iwl_pcie_tx_alloc - allocate TX context
792 * Allocate all Tx DMA structures and initialize them
794 static int iwl_pcie_tx_alloc(struct iwl_trans
*trans
)
797 int txq_id
, slots_num
;
798 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
800 u16 scd_bc_tbls_size
= trans
->cfg
->base_params
->num_of_queues
*
801 sizeof(struct iwlagn_scd_bc_tbl
);
803 /*It is not allowed to alloc twice, so warn when this happens.
804 * We cannot rely on the previous allocation, so free and fail */
805 if (WARN_ON(trans_pcie
->txq
)) {
810 ret
= iwl_pcie_alloc_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
,
813 IWL_ERR(trans
, "Scheduler BC Table allocation failed\n");
817 /* Alloc keep-warm buffer */
818 ret
= iwl_pcie_alloc_dma_ptr(trans
, &trans_pcie
->kw
, IWL_KW_SIZE
);
820 IWL_ERR(trans
, "Keep Warm allocation failed\n");
824 trans_pcie
->txq
= kcalloc(trans
->cfg
->base_params
->num_of_queues
,
825 sizeof(struct iwl_txq
), GFP_KERNEL
);
826 if (!trans_pcie
->txq
) {
827 IWL_ERR(trans
, "Not enough memory for txq\n");
832 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
833 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
835 slots_num
= (txq_id
== trans_pcie
->cmd_queue
) ?
836 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
837 ret
= iwl_pcie_txq_alloc(trans
, &trans_pcie
->txq
[txq_id
],
840 IWL_ERR(trans
, "Tx %d queue alloc failed\n", txq_id
);
848 iwl_pcie_tx_free(trans
);
852 int iwl_pcie_tx_init(struct iwl_trans
*trans
)
854 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
856 int txq_id
, slots_num
;
860 if (!trans_pcie
->txq
) {
861 ret
= iwl_pcie_tx_alloc(trans
);
867 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
869 /* Turn off all Tx DMA fifos */
870 iwl_write_prph(trans
, SCD_TXFACT
, 0);
872 /* Tell NIC where to find the "keep warm" buffer */
873 iwl_write_direct32(trans
, FH_KW_MEM_ADDR_REG
,
874 trans_pcie
->kw
.dma
>> 4);
876 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
878 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
879 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
881 slots_num
= (txq_id
== trans_pcie
->cmd_queue
) ?
882 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
883 ret
= iwl_pcie_txq_init(trans
, &trans_pcie
->txq
[txq_id
],
886 IWL_ERR(trans
, "Tx %d queue init failed\n", txq_id
);
893 /*Upon error, free only if we allocated something */
895 iwl_pcie_tx_free(trans
);
899 static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie
*trans_pcie
,
902 if (!trans_pcie
->wd_timeout
)
906 * if empty delete timer, otherwise move timer forward
907 * since we're making progress on this queue
909 if (txq
->q
.read_ptr
== txq
->q
.write_ptr
)
910 del_timer(&txq
->stuck_timer
);
912 mod_timer(&txq
->stuck_timer
, jiffies
+ trans_pcie
->wd_timeout
);
915 /* Frees buffers until index _not_ inclusive */
916 void iwl_trans_pcie_reclaim(struct iwl_trans
*trans
, int txq_id
, int ssn
,
917 struct sk_buff_head
*skbs
)
919 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
920 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
921 /* n_bd is usually 256 => n_bd - 1 = 0xff */
922 int tfd_num
= ssn
& (txq
->q
.n_bd
- 1);
923 struct iwl_queue
*q
= &txq
->q
;
926 /* This function is not meant to release cmd queue*/
927 if (WARN_ON(txq_id
== trans_pcie
->cmd_queue
))
930 spin_lock_bh(&txq
->lock
);
932 if (txq
->q
.read_ptr
== tfd_num
)
935 IWL_DEBUG_TX_REPLY(trans
, "[Q %d] %d -> %d (%d)\n",
936 txq_id
, txq
->q
.read_ptr
, tfd_num
, ssn
);
938 /*Since we free until index _not_ inclusive, the one before index is
939 * the last we will free. This one must be used */
940 last_to_free
= iwl_queue_dec_wrap(tfd_num
, q
->n_bd
);
942 if (!iwl_queue_used(q
, last_to_free
)) {
944 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
945 __func__
, txq_id
, last_to_free
, q
->n_bd
,
946 q
->write_ptr
, q
->read_ptr
);
950 if (WARN_ON(!skb_queue_empty(skbs
)))
954 q
->read_ptr
!= tfd_num
;
955 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
957 if (WARN_ON_ONCE(txq
->entries
[txq
->q
.read_ptr
].skb
== NULL
))
960 __skb_queue_tail(skbs
, txq
->entries
[txq
->q
.read_ptr
].skb
);
962 txq
->entries
[txq
->q
.read_ptr
].skb
= NULL
;
964 iwl_pcie_txq_inval_byte_cnt_tbl(trans
, txq
);
966 iwl_pcie_txq_free_tfd(trans
, txq
);
969 iwl_pcie_txq_progress(trans_pcie
, txq
);
971 if (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
)
972 iwl_wake_queue(trans
, txq
);
974 spin_unlock_bh(&txq
->lock
);
978 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
980 * When FW advances 'R' index, all entries between old and new 'R' index
981 * need to be reclaimed. As result, some free space forms. If there is
982 * enough free space (> low mark), wake the stack that feeds us.
984 static void iwl_pcie_cmdq_reclaim(struct iwl_trans
*trans
, int txq_id
, int idx
)
986 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
987 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
988 struct iwl_queue
*q
= &txq
->q
;
991 lockdep_assert_held(&txq
->lock
);
993 if ((idx
>= q
->n_bd
) || (!iwl_queue_used(q
, idx
))) {
995 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
996 __func__
, txq_id
, idx
, q
->n_bd
,
997 q
->write_ptr
, q
->read_ptr
);
1001 for (idx
= iwl_queue_inc_wrap(idx
, q
->n_bd
); q
->read_ptr
!= idx
;
1002 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
1005 IWL_ERR(trans
, "HCMD skipped: index (%d) %d %d\n",
1006 idx
, q
->write_ptr
, q
->read_ptr
);
1007 iwl_op_mode_nic_error(trans
->op_mode
);
1011 iwl_pcie_txq_progress(trans_pcie
, txq
);
1014 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans
*trans
, u16 ra_tid
,
1017 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1022 scd_q2ratid
= ra_tid
& SCD_QUEUE_RA_TID_MAP_RATID_MSK
;
1024 tbl_dw_addr
= trans_pcie
->scd_base_addr
+
1025 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id
);
1027 tbl_dw
= iwl_trans_read_mem32(trans
, tbl_dw_addr
);
1030 tbl_dw
= (scd_q2ratid
<< 16) | (tbl_dw
& 0x0000FFFF);
1032 tbl_dw
= scd_q2ratid
| (tbl_dw
& 0xFFFF0000);
1034 iwl_trans_write_mem32(trans
, tbl_dw_addr
, tbl_dw
);
1039 static inline void iwl_pcie_txq_set_inactive(struct iwl_trans
*trans
,
1042 /* Simply stop the queue, but don't change any configuration;
1043 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1044 iwl_write_prph(trans
,
1045 SCD_QUEUE_STATUS_BITS(txq_id
),
1046 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE
)|
1047 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN
));
1050 void iwl_trans_pcie_txq_enable(struct iwl_trans
*trans
, int txq_id
, int fifo
,
1051 int sta_id
, int tid
, int frame_limit
, u16 ssn
)
1053 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1055 if (test_and_set_bit(txq_id
, trans_pcie
->queue_used
))
1056 WARN_ONCE(1, "queue %d already used - expect issues", txq_id
);
1058 /* Stop this Tx queue before configuring it */
1059 iwl_pcie_txq_set_inactive(trans
, txq_id
);
1061 /* Set this queue as a chain-building queue unless it is CMD queue */
1062 if (txq_id
!= trans_pcie
->cmd_queue
)
1063 iwl_set_bits_prph(trans
, SCD_QUEUECHAIN_SEL
, BIT(txq_id
));
1065 /* If this queue is mapped to a certain station: it is an AGG queue */
1066 if (sta_id
!= IWL_INVALID_STATION
) {
1067 u16 ra_tid
= BUILD_RAxTID(sta_id
, tid
);
1069 /* Map receiver-address / traffic-ID to this queue */
1070 iwl_pcie_txq_set_ratid_map(trans
, ra_tid
, txq_id
);
1072 /* enable aggregations for the queue */
1073 iwl_set_bits_prph(trans
, SCD_AGGR_SEL
, BIT(txq_id
));
1076 * disable aggregations for the queue, this will also make the
1077 * ra_tid mapping configuration irrelevant since it is now a
1080 iwl_clear_bits_prph(trans
, SCD_AGGR_SEL
, BIT(txq_id
));
1083 /* Place first TFD at index corresponding to start sequence number.
1084 * Assumes that ssn_idx is valid (!= 0xFFF) */
1085 trans_pcie
->txq
[txq_id
].q
.read_ptr
= (ssn
& 0xff);
1086 trans_pcie
->txq
[txq_id
].q
.write_ptr
= (ssn
& 0xff);
1088 iwl_write_direct32(trans
, HBUS_TARG_WRPTR
,
1089 (ssn
& 0xff) | (txq_id
<< 8));
1090 iwl_write_prph(trans
, SCD_QUEUE_RDPTR(txq_id
), ssn
);
1092 /* Set up Tx window size and frame limit for this queue */
1093 iwl_trans_write_mem32(trans
, trans_pcie
->scd_base_addr
+
1094 SCD_CONTEXT_QUEUE_OFFSET(txq_id
), 0);
1095 iwl_trans_write_mem32(trans
, trans_pcie
->scd_base_addr
+
1096 SCD_CONTEXT_QUEUE_OFFSET(txq_id
) + sizeof(u32
),
1097 ((frame_limit
<< SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
1098 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
1099 ((frame_limit
<< SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
1100 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
1102 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1103 iwl_write_prph(trans
, SCD_QUEUE_STATUS_BITS(txq_id
),
1104 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE
) |
1105 (fifo
<< SCD_QUEUE_STTS_REG_POS_TXF
) |
1106 (1 << SCD_QUEUE_STTS_REG_POS_WSL
) |
1107 SCD_QUEUE_STTS_REG_MSK
);
1108 IWL_DEBUG_TX_QUEUES(trans
, "Activate queue %d on FIFO %d WrPtr: %d\n",
1109 txq_id
, fifo
, ssn
& 0xff);
1112 void iwl_trans_pcie_txq_disable(struct iwl_trans
*trans
, int txq_id
)
1114 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1115 u32 stts_addr
= trans_pcie
->scd_base_addr
+
1116 SCD_TX_STTS_QUEUE_OFFSET(txq_id
);
1117 static const u32 zero_val
[4] = {};
1119 if (!test_and_clear_bit(txq_id
, trans_pcie
->queue_used
)) {
1120 WARN_ONCE(1, "queue %d not used", txq_id
);
1124 iwl_pcie_txq_set_inactive(trans
, txq_id
);
1126 iwl_trans_write_mem(trans
, stts_addr
, (void *)zero_val
,
1127 ARRAY_SIZE(zero_val
));
1129 iwl_pcie_txq_unmap(trans
, txq_id
);
1131 IWL_DEBUG_TX_QUEUES(trans
, "Deactivate queue %d\n", txq_id
);
1134 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1137 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1138 * @priv: device private data point
1139 * @cmd: a point to the ucode command structure
1141 * The function returns < 0 values to indicate the operation is
1142 * failed. On success, it turns the index (> 0) of command in the
1145 static int iwl_pcie_enqueue_hcmd(struct iwl_trans
*trans
,
1146 struct iwl_host_cmd
*cmd
)
1148 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1149 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1150 struct iwl_queue
*q
= &txq
->q
;
1151 struct iwl_device_cmd
*out_cmd
;
1152 struct iwl_cmd_meta
*out_meta
;
1153 void *dup_buf
= NULL
;
1154 dma_addr_t phys_addr
;
1156 u16 copy_size
, cmd_size
, scratch_size
;
1157 bool had_nocopy
= false;
1160 const u8
*cmddata
[IWL_MAX_CMD_TBS_PER_TFD
];
1161 u16 cmdlen
[IWL_MAX_CMD_TBS_PER_TFD
];
1163 copy_size
= sizeof(out_cmd
->hdr
);
1164 cmd_size
= sizeof(out_cmd
->hdr
);
1166 /* need one for the header if the first is NOCOPY */
1167 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD
> IWL_NUM_OF_TBS
- 1);
1169 for (i
= 0; i
< IWL_MAX_CMD_TBS_PER_TFD
; i
++) {
1170 cmddata
[i
] = cmd
->data
[i
];
1171 cmdlen
[i
] = cmd
->len
[i
];
1176 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1177 if (copy_size
< IWL_HCMD_SCRATCHBUF_SIZE
) {
1178 int copy
= IWL_HCMD_SCRATCHBUF_SIZE
- copy_size
;
1180 if (copy
> cmdlen
[i
])
1187 if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_NOCOPY
) {
1189 if (WARN_ON(cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
)) {
1193 } else if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
) {
1195 * This is also a chunk that isn't copied
1196 * to the static buffer so set had_nocopy.
1200 /* only allowed once */
1201 if (WARN_ON(dup_buf
)) {
1206 dup_buf
= kmemdup(cmddata
[i
], cmdlen
[i
],
1211 /* NOCOPY must not be followed by normal! */
1212 if (WARN_ON(had_nocopy
)) {
1216 copy_size
+= cmdlen
[i
];
1218 cmd_size
+= cmd
->len
[i
];
1222 * If any of the command structures end up being larger than
1223 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1224 * allocated into separate TFDs, then we will need to
1225 * increase the size of the buffers.
1227 if (WARN(copy_size
> TFD_MAX_PAYLOAD_SIZE
,
1228 "Command %s (%#x) is too large (%d bytes)\n",
1229 get_cmd_string(trans_pcie
, cmd
->id
), cmd
->id
, copy_size
)) {
1234 spin_lock_bh(&txq
->lock
);
1236 if (iwl_queue_space(q
) < ((cmd
->flags
& CMD_ASYNC
) ? 2 : 1)) {
1237 spin_unlock_bh(&txq
->lock
);
1239 IWL_ERR(trans
, "No space in command queue\n");
1240 iwl_op_mode_cmd_queue_full(trans
->op_mode
);
1245 idx
= get_cmd_index(q
, q
->write_ptr
);
1246 out_cmd
= txq
->entries
[idx
].cmd
;
1247 out_meta
= &txq
->entries
[idx
].meta
;
1249 memset(out_meta
, 0, sizeof(*out_meta
)); /* re-initialize to NULL */
1250 if (cmd
->flags
& CMD_WANT_SKB
)
1251 out_meta
->source
= cmd
;
1253 /* set up the header */
1255 out_cmd
->hdr
.cmd
= cmd
->id
;
1256 out_cmd
->hdr
.flags
= 0;
1257 out_cmd
->hdr
.sequence
=
1258 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie
->cmd_queue
) |
1259 INDEX_TO_SEQ(q
->write_ptr
));
1261 /* and copy the data that needs to be copied */
1262 cmd_pos
= offsetof(struct iwl_device_cmd
, payload
);
1263 copy_size
= sizeof(out_cmd
->hdr
);
1264 for (i
= 0; i
< IWL_MAX_CMD_TBS_PER_TFD
; i
++) {
1270 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1271 if (copy_size
< IWL_HCMD_SCRATCHBUF_SIZE
) {
1272 copy
= IWL_HCMD_SCRATCHBUF_SIZE
- copy_size
;
1274 if (copy
> cmd
->len
[i
])
1278 /* copy everything if not nocopy/dup */
1279 if (!(cmd
->dataflags
[i
] & (IWL_HCMD_DFL_NOCOPY
|
1284 memcpy((u8
*)out_cmd
+ cmd_pos
, cmd
->data
[i
], copy
);
1291 "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1292 get_cmd_string(trans_pcie
, out_cmd
->hdr
.cmd
),
1293 out_cmd
->hdr
.cmd
, le16_to_cpu(out_cmd
->hdr
.sequence
),
1294 cmd_size
, q
->write_ptr
, idx
, trans_pcie
->cmd_queue
);
1296 /* start the TFD with the scratchbuf */
1297 scratch_size
= min_t(int, copy_size
, IWL_HCMD_SCRATCHBUF_SIZE
);
1298 memcpy(&txq
->scratchbufs
[q
->write_ptr
], &out_cmd
->hdr
, scratch_size
);
1299 iwl_pcie_txq_build_tfd(trans
, txq
,
1300 iwl_pcie_get_scratchbuf_dma(txq
, q
->write_ptr
),
1303 /* map first command fragment, if any remains */
1304 if (copy_size
> scratch_size
) {
1305 phys_addr
= dma_map_single(trans
->dev
,
1306 ((u8
*)&out_cmd
->hdr
) + scratch_size
,
1307 copy_size
- scratch_size
,
1309 if (dma_mapping_error(trans
->dev
, phys_addr
)) {
1310 iwl_pcie_tfd_unmap(trans
, out_meta
,
1311 &txq
->tfds
[q
->write_ptr
]);
1316 iwl_pcie_txq_build_tfd(trans
, txq
, phys_addr
,
1317 copy_size
- scratch_size
, 0);
1320 /* map the remaining (adjusted) nocopy/dup fragments */
1321 for (i
= 0; i
< IWL_MAX_CMD_TBS_PER_TFD
; i
++) {
1322 const void *data
= cmddata
[i
];
1326 if (!(cmd
->dataflags
[i
] & (IWL_HCMD_DFL_NOCOPY
|
1329 if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
)
1331 phys_addr
= dma_map_single(trans
->dev
, (void *)data
,
1332 cmdlen
[i
], DMA_TO_DEVICE
);
1333 if (dma_mapping_error(trans
->dev
, phys_addr
)) {
1334 iwl_pcie_tfd_unmap(trans
, out_meta
,
1335 &txq
->tfds
[q
->write_ptr
]);
1340 iwl_pcie_txq_build_tfd(trans
, txq
, phys_addr
, cmdlen
[i
], 0);
1343 out_meta
->flags
= cmd
->flags
;
1344 if (WARN_ON_ONCE(txq
->entries
[idx
].free_buf
))
1345 kfree(txq
->entries
[idx
].free_buf
);
1346 txq
->entries
[idx
].free_buf
= dup_buf
;
1348 txq
->need_update
= 1;
1350 trace_iwlwifi_dev_hcmd(trans
->dev
, cmd
, cmd_size
, &out_cmd
->hdr
);
1352 /* start timer if queue currently empty */
1353 if (q
->read_ptr
== q
->write_ptr
&& trans_pcie
->wd_timeout
)
1354 mod_timer(&txq
->stuck_timer
, jiffies
+ trans_pcie
->wd_timeout
);
1356 /* Increment and update queue's write index */
1357 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
1358 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
1361 spin_unlock_bh(&txq
->lock
);
1369 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1370 * @rxb: Rx buffer to reclaim
1371 * @handler_status: return value of the handler of the command
1372 * (put in setup_rx_handlers)
1374 * If an Rx buffer has an async callback associated with it the callback
1375 * will be executed. The attached skb (if present) will only be freed
1376 * if the callback returns 1
1378 void iwl_pcie_hcmd_complete(struct iwl_trans
*trans
,
1379 struct iwl_rx_cmd_buffer
*rxb
, int handler_status
)
1381 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
1382 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
1383 int txq_id
= SEQ_TO_QUEUE(sequence
);
1384 int index
= SEQ_TO_INDEX(sequence
);
1386 struct iwl_device_cmd
*cmd
;
1387 struct iwl_cmd_meta
*meta
;
1388 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1389 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1391 /* If a Tx command is being handled and it isn't in the actual
1392 * command queue then there a command routing bug has been introduced
1393 * in the queue management code. */
1394 if (WARN(txq_id
!= trans_pcie
->cmd_queue
,
1395 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1396 txq_id
, trans_pcie
->cmd_queue
, sequence
,
1397 trans_pcie
->txq
[trans_pcie
->cmd_queue
].q
.read_ptr
,
1398 trans_pcie
->txq
[trans_pcie
->cmd_queue
].q
.write_ptr
)) {
1399 iwl_print_hex_error(trans
, pkt
, 32);
1403 spin_lock_bh(&txq
->lock
);
1405 cmd_index
= get_cmd_index(&txq
->q
, index
);
1406 cmd
= txq
->entries
[cmd_index
].cmd
;
1407 meta
= &txq
->entries
[cmd_index
].meta
;
1409 iwl_pcie_tfd_unmap(trans
, meta
, &txq
->tfds
[index
]);
1411 /* Input error checking is done when commands are added to queue. */
1412 if (meta
->flags
& CMD_WANT_SKB
) {
1413 struct page
*p
= rxb_steal_page(rxb
);
1415 meta
->source
->resp_pkt
= pkt
;
1416 meta
->source
->_rx_page_addr
= (unsigned long)page_address(p
);
1417 meta
->source
->_rx_page_order
= trans_pcie
->rx_page_order
;
1418 meta
->source
->handler_status
= handler_status
;
1421 iwl_pcie_cmdq_reclaim(trans
, txq_id
, index
);
1423 if (!(meta
->flags
& CMD_ASYNC
)) {
1424 if (!test_bit(STATUS_HCMD_ACTIVE
, &trans_pcie
->status
)) {
1426 "HCMD_ACTIVE already clear for command %s\n",
1427 get_cmd_string(trans_pcie
, cmd
->hdr
.cmd
));
1429 clear_bit(STATUS_HCMD_ACTIVE
, &trans_pcie
->status
);
1430 IWL_DEBUG_INFO(trans
, "Clearing HCMD_ACTIVE for command %s\n",
1431 get_cmd_string(trans_pcie
, cmd
->hdr
.cmd
));
1432 wake_up(&trans_pcie
->wait_command_queue
);
1437 spin_unlock_bh(&txq
->lock
);
1440 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
1442 static int iwl_pcie_send_hcmd_async(struct iwl_trans
*trans
,
1443 struct iwl_host_cmd
*cmd
)
1445 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1448 /* An asynchronous command can not expect an SKB to be set. */
1449 if (WARN_ON(cmd
->flags
& CMD_WANT_SKB
))
1452 ret
= iwl_pcie_enqueue_hcmd(trans
, cmd
);
1455 "Error sending %s: enqueue_hcmd failed: %d\n",
1456 get_cmd_string(trans_pcie
, cmd
->id
), ret
);
1462 static int iwl_pcie_send_hcmd_sync(struct iwl_trans
*trans
,
1463 struct iwl_host_cmd
*cmd
)
1465 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1469 IWL_DEBUG_INFO(trans
, "Attempting to send sync command %s\n",
1470 get_cmd_string(trans_pcie
, cmd
->id
));
1472 if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE
,
1473 &trans_pcie
->status
))) {
1474 IWL_ERR(trans
, "Command %s: a command is already active!\n",
1475 get_cmd_string(trans_pcie
, cmd
->id
));
1479 IWL_DEBUG_INFO(trans
, "Setting HCMD_ACTIVE for command %s\n",
1480 get_cmd_string(trans_pcie
, cmd
->id
));
1482 cmd_idx
= iwl_pcie_enqueue_hcmd(trans
, cmd
);
1485 clear_bit(STATUS_HCMD_ACTIVE
, &trans_pcie
->status
);
1487 "Error sending %s: enqueue_hcmd failed: %d\n",
1488 get_cmd_string(trans_pcie
, cmd
->id
), ret
);
1492 ret
= wait_event_timeout(trans_pcie
->wait_command_queue
,
1493 !test_bit(STATUS_HCMD_ACTIVE
,
1494 &trans_pcie
->status
),
1495 HOST_COMPLETE_TIMEOUT
);
1497 if (test_bit(STATUS_HCMD_ACTIVE
, &trans_pcie
->status
)) {
1498 struct iwl_txq
*txq
=
1499 &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1500 struct iwl_queue
*q
= &txq
->q
;
1503 "Error sending %s: time out after %dms.\n",
1504 get_cmd_string(trans_pcie
, cmd
->id
),
1505 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT
));
1508 "Current CMD queue read_ptr %d write_ptr %d\n",
1509 q
->read_ptr
, q
->write_ptr
);
1511 clear_bit(STATUS_HCMD_ACTIVE
, &trans_pcie
->status
);
1512 IWL_DEBUG_INFO(trans
,
1513 "Clearing HCMD_ACTIVE for command %s\n",
1514 get_cmd_string(trans_pcie
, cmd
->id
));
1520 if (test_bit(STATUS_FW_ERROR
, &trans_pcie
->status
)) {
1521 IWL_ERR(trans
, "FW error in SYNC CMD %s\n",
1522 get_cmd_string(trans_pcie
, cmd
->id
));
1527 if (test_bit(STATUS_RFKILL
, &trans_pcie
->status
)) {
1528 IWL_DEBUG_RF_KILL(trans
, "RFKILL in SYNC CMD... no rsp\n");
1533 if ((cmd
->flags
& CMD_WANT_SKB
) && !cmd
->resp_pkt
) {
1534 IWL_ERR(trans
, "Error: Response NULL in '%s'\n",
1535 get_cmd_string(trans_pcie
, cmd
->id
));
1543 if (cmd
->flags
& CMD_WANT_SKB
) {
1545 * Cancel the CMD_WANT_SKB flag for the cmd in the
1546 * TX cmd queue. Otherwise in case the cmd comes
1547 * in later, it will possibly set an invalid
1548 * address (cmd->meta.source).
1550 trans_pcie
->txq
[trans_pcie
->cmd_queue
].
1551 entries
[cmd_idx
].meta
.flags
&= ~CMD_WANT_SKB
;
1554 if (cmd
->resp_pkt
) {
1556 cmd
->resp_pkt
= NULL
;
1562 int iwl_trans_pcie_send_hcmd(struct iwl_trans
*trans
, struct iwl_host_cmd
*cmd
)
1564 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1566 if (test_bit(STATUS_FW_ERROR
, &trans_pcie
->status
))
1569 if (test_bit(STATUS_RFKILL
, &trans_pcie
->status
))
1572 if (cmd
->flags
& CMD_ASYNC
)
1573 return iwl_pcie_send_hcmd_async(trans
, cmd
);
1575 /* We still can fail on RFKILL that can be asserted while we wait */
1576 return iwl_pcie_send_hcmd_sync(trans
, cmd
);
1579 int iwl_trans_pcie_tx(struct iwl_trans
*trans
, struct sk_buff
*skb
,
1580 struct iwl_device_cmd
*dev_cmd
, int txq_id
)
1582 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1583 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1584 struct iwl_tx_cmd
*tx_cmd
= (struct iwl_tx_cmd
*)dev_cmd
->payload
;
1585 struct iwl_cmd_meta
*out_meta
;
1586 struct iwl_txq
*txq
;
1587 struct iwl_queue
*q
;
1588 dma_addr_t tb0_phys
, tb1_phys
, scratch_phys
;
1590 u16 len
, tb1_len
, tb2_len
;
1591 u8 wait_write_ptr
= 0;
1592 __le16 fc
= hdr
->frame_control
;
1593 u8 hdr_len
= ieee80211_hdrlen(fc
);
1594 u16 __maybe_unused wifi_seq
;
1596 txq
= &trans_pcie
->txq
[txq_id
];
1599 if (unlikely(!test_bit(txq_id
, trans_pcie
->queue_used
))) {
1604 spin_lock(&txq
->lock
);
1606 /* In AGG mode, the index in the ring must correspond to the WiFi
1607 * sequence number. This is a HW requirements to help the SCD to parse
1609 * Check here that the packets are in the right place on the ring.
1611 #ifdef CONFIG_IWLWIFI_DEBUG
1612 wifi_seq
= SEQ_TO_SN(le16_to_cpu(hdr
->seq_ctrl
));
1613 WARN_ONCE((iwl_read_prph(trans
, SCD_AGGR_SEL
) & BIT(txq_id
)) &&
1614 ((wifi_seq
& 0xff) != q
->write_ptr
),
1615 "Q: %d WiFi Seq %d tfdNum %d",
1616 txq_id
, wifi_seq
, q
->write_ptr
);
1619 /* Set up driver data for this TFD */
1620 txq
->entries
[q
->write_ptr
].skb
= skb
;
1621 txq
->entries
[q
->write_ptr
].cmd
= dev_cmd
;
1623 dev_cmd
->hdr
.cmd
= REPLY_TX
;
1624 dev_cmd
->hdr
.sequence
=
1625 cpu_to_le16((u16
)(QUEUE_TO_SEQ(txq_id
) |
1626 INDEX_TO_SEQ(q
->write_ptr
)));
1628 tb0_phys
= iwl_pcie_get_scratchbuf_dma(txq
, q
->write_ptr
);
1629 scratch_phys
= tb0_phys
+ sizeof(struct iwl_cmd_header
) +
1630 offsetof(struct iwl_tx_cmd
, scratch
);
1632 tx_cmd
->dram_lsb_ptr
= cpu_to_le32(scratch_phys
);
1633 tx_cmd
->dram_msb_ptr
= iwl_get_dma_hi_addr(scratch_phys
);
1635 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1636 out_meta
= &txq
->entries
[q
->write_ptr
].meta
;
1639 * The second TB (tb1) points to the remainder of the TX command
1640 * and the 802.11 header - dword aligned size
1641 * (This calculation modifies the TX command, so do it before the
1642 * setup of the first TB)
1644 len
= sizeof(struct iwl_tx_cmd
) + sizeof(struct iwl_cmd_header
) +
1645 hdr_len
- IWL_HCMD_SCRATCHBUF_SIZE
;
1646 tb1_len
= (len
+ 3) & ~3;
1648 /* Tell NIC about any 2-byte padding after MAC header */
1650 tx_cmd
->tx_flags
|= TX_CMD_FLG_MH_PAD_MSK
;
1652 /* The first TB points to the scratchbuf data - min_copy bytes */
1653 memcpy(&txq
->scratchbufs
[q
->write_ptr
], &dev_cmd
->hdr
,
1654 IWL_HCMD_SCRATCHBUF_SIZE
);
1655 iwl_pcie_txq_build_tfd(trans
, txq
, tb0_phys
,
1656 IWL_HCMD_SCRATCHBUF_SIZE
, 1);
1658 /* there must be data left over for TB1 or this code must be changed */
1659 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd
) < IWL_HCMD_SCRATCHBUF_SIZE
);
1661 /* map the data for TB1 */
1662 tb1_addr
= ((u8
*)&dev_cmd
->hdr
) + IWL_HCMD_SCRATCHBUF_SIZE
;
1663 tb1_phys
= dma_map_single(trans
->dev
, tb1_addr
, tb1_len
, DMA_TO_DEVICE
);
1664 if (unlikely(dma_mapping_error(trans
->dev
, tb1_phys
)))
1666 iwl_pcie_txq_build_tfd(trans
, txq
, tb1_phys
, tb1_len
, 0);
1669 * Set up TFD's third entry to point directly to remainder
1670 * of skb, if any (802.11 null frames have no payload).
1672 tb2_len
= skb
->len
- hdr_len
;
1674 dma_addr_t tb2_phys
= dma_map_single(trans
->dev
,
1675 skb
->data
+ hdr_len
,
1676 tb2_len
, DMA_TO_DEVICE
);
1677 if (unlikely(dma_mapping_error(trans
->dev
, tb2_phys
))) {
1678 iwl_pcie_tfd_unmap(trans
, out_meta
,
1679 &txq
->tfds
[q
->write_ptr
]);
1682 iwl_pcie_txq_build_tfd(trans
, txq
, tb2_phys
, tb2_len
, 0);
1685 /* Set up entry for this TFD in Tx byte-count array */
1686 iwl_pcie_txq_update_byte_cnt_tbl(trans
, txq
, le16_to_cpu(tx_cmd
->len
));
1688 trace_iwlwifi_dev_tx(trans
->dev
, skb
,
1689 &txq
->tfds
[txq
->q
.write_ptr
],
1690 sizeof(struct iwl_tfd
),
1691 &dev_cmd
->hdr
, IWL_HCMD_SCRATCHBUF_SIZE
+ tb1_len
,
1692 skb
->data
+ hdr_len
, tb2_len
);
1693 trace_iwlwifi_dev_tx_data(trans
->dev
, skb
,
1694 skb
->data
+ hdr_len
, tb2_len
);
1696 if (!ieee80211_has_morefrags(fc
)) {
1697 txq
->need_update
= 1;
1700 txq
->need_update
= 0;
1703 /* start timer if queue currently empty */
1704 if (txq
->need_update
&& q
->read_ptr
== q
->write_ptr
&&
1705 trans_pcie
->wd_timeout
)
1706 mod_timer(&txq
->stuck_timer
, jiffies
+ trans_pcie
->wd_timeout
);
1708 /* Tell device the write index *just past* this latest filled TFD */
1709 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
1710 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
1713 * At this point the frame is "transmitted" successfully
1714 * and we will get a TX status notification eventually,
1715 * regardless of the value of ret. "ret" only indicates
1716 * whether or not we should update the write pointer.
1718 if (iwl_queue_space(q
) < q
->high_mark
) {
1719 if (wait_write_ptr
) {
1720 txq
->need_update
= 1;
1721 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
1723 iwl_stop_queue(trans
, txq
);
1726 spin_unlock(&txq
->lock
);
1729 spin_unlock(&txq
->lock
);