1 /******************************************************************************
3 * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/slab.h>
31 #include <linux/sched.h>
33 #include "iwl-debug.h"
37 #include "iwl-op-mode.h"
39 /* FIXME: need to abstract out TX command (once we know what it looks like) */
40 #include "dvm/commands.h"
42 #define IWL_TX_CRC_SIZE 4
43 #define IWL_TX_DELIMITER_SIZE 4
45 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
50 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
51 * of buffer descriptors, each of which points to one or more data buffers for
52 * the device to read from or fill. Driver and device exchange status of each
53 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
54 * entries in each circular buffer, to protect against confusing empty and full
57 * The device reads or writes the data in the queues via the device's several
58 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
60 * For Tx queue, there are low mark and high mark limits. If, after queuing
61 * the packet for Tx, free space become < low mark, Tx queue stopped. When
62 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
65 ***************************************************/
66 static int iwl_queue_space(const struct iwl_queue
*q
)
68 int s
= q
->read_ptr
- q
->write_ptr
;
70 if (q
->read_ptr
> q
->write_ptr
)
75 /* keep some reserve to not confuse empty and full situations */
83 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
85 static int iwl_queue_init(struct iwl_queue
*q
, int count
, int slots_num
, u32 id
)
88 q
->n_window
= slots_num
;
91 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
92 * and iwl_queue_dec_wrap are broken. */
93 if (WARN_ON(!is_power_of_2(count
)))
96 /* slots_num must be power-of-two size, otherwise
97 * get_cmd_index is broken. */
98 if (WARN_ON(!is_power_of_2(slots_num
)))
101 q
->low_mark
= q
->n_window
/ 4;
105 q
->high_mark
= q
->n_window
/ 8;
106 if (q
->high_mark
< 2)
115 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans
*trans
,
116 struct iwl_dma_ptr
*ptr
, size_t size
)
118 if (WARN_ON(ptr
->addr
))
121 ptr
->addr
= dma_alloc_coherent(trans
->dev
, size
,
122 &ptr
->dma
, GFP_KERNEL
);
129 static void iwl_pcie_free_dma_ptr(struct iwl_trans
*trans
,
130 struct iwl_dma_ptr
*ptr
)
132 if (unlikely(!ptr
->addr
))
135 dma_free_coherent(trans
->dev
, ptr
->size
, ptr
->addr
, ptr
->dma
);
136 memset(ptr
, 0, sizeof(*ptr
));
139 static void iwl_pcie_txq_stuck_timer(unsigned long data
)
141 struct iwl_txq
*txq
= (void *)data
;
142 struct iwl_queue
*q
= &txq
->q
;
143 struct iwl_trans_pcie
*trans_pcie
= txq
->trans_pcie
;
144 struct iwl_trans
*trans
= iwl_trans_pcie_get_trans(trans_pcie
);
145 u32 scd_sram_addr
= trans_pcie
->scd_base_addr
+
146 SCD_TX_STTS_QUEUE_OFFSET(txq
->q
.id
);
150 spin_lock(&txq
->lock
);
151 /* check if triggered erroneously */
152 if (txq
->q
.read_ptr
== txq
->q
.write_ptr
) {
153 spin_unlock(&txq
->lock
);
156 spin_unlock(&txq
->lock
);
158 IWL_ERR(trans
, "Queue %d stuck for %u ms.\n", txq
->q
.id
,
159 jiffies_to_msecs(trans_pcie
->wd_timeout
));
160 IWL_ERR(trans
, "Current SW read_ptr %d write_ptr %d\n",
161 txq
->q
.read_ptr
, txq
->q
.write_ptr
);
163 iwl_read_targ_mem_bytes(trans
, scd_sram_addr
, buf
, sizeof(buf
));
165 iwl_print_hex_error(trans
, buf
, sizeof(buf
));
167 for (i
= 0; i
< FH_TCSR_CHNL_NUM
; i
++)
168 IWL_ERR(trans
, "FH TRBs(%d) = 0x%08x\n", i
,
169 iwl_read_direct32(trans
, FH_TX_TRB_REG(i
)));
171 for (i
= 0; i
< trans
->cfg
->base_params
->num_of_queues
; i
++) {
172 u32 status
= iwl_read_prph(trans
, SCD_QUEUE_STATUS_BITS(i
));
173 u8 fifo
= (status
>> SCD_QUEUE_STTS_REG_POS_TXF
) & 0x7;
174 bool active
= !!(status
& BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE
));
176 iwl_read_targ_mem(trans
,
177 trans_pcie
->scd_base_addr
+
178 SCD_TRANS_TBL_OFFSET_QUEUE(i
));
181 tbl_dw
= (tbl_dw
& 0xFFFF0000) >> 16;
183 tbl_dw
= tbl_dw
& 0x0000FFFF;
186 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
187 i
, active
? "" : "in", fifo
, tbl_dw
,
189 SCD_QUEUE_RDPTR(i
)) & (txq
->q
.n_bd
- 1),
190 iwl_read_prph(trans
, SCD_QUEUE_WRPTR(i
)));
193 for (i
= q
->read_ptr
; i
!= q
->write_ptr
;
194 i
= iwl_queue_inc_wrap(i
, q
->n_bd
)) {
195 struct iwl_tx_cmd
*tx_cmd
=
196 (struct iwl_tx_cmd
*)txq
->entries
[i
].cmd
->payload
;
197 IWL_ERR(trans
, "scratch %d = 0x%08x\n", i
,
198 get_unaligned_le32(&tx_cmd
->scratch
));
201 iwl_op_mode_nic_error(trans
->op_mode
);
205 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
207 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans
*trans
,
208 struct iwl_txq
*txq
, u16 byte_cnt
)
210 struct iwlagn_scd_bc_tbl
*scd_bc_tbl
;
211 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
212 int write_ptr
= txq
->q
.write_ptr
;
213 int txq_id
= txq
->q
.id
;
216 u16 len
= byte_cnt
+ IWL_TX_CRC_SIZE
+ IWL_TX_DELIMITER_SIZE
;
218 struct iwl_tx_cmd
*tx_cmd
=
219 (void *) txq
->entries
[txq
->q
.write_ptr
].cmd
->payload
;
221 scd_bc_tbl
= trans_pcie
->scd_bc_tbls
.addr
;
223 WARN_ON(len
> 0xFFF || write_ptr
>= TFD_QUEUE_SIZE_MAX
);
225 sta_id
= tx_cmd
->sta_id
;
226 sec_ctl
= tx_cmd
->sec_ctl
;
228 switch (sec_ctl
& TX_CMD_SEC_MSK
) {
232 case TX_CMD_SEC_TKIP
:
236 len
+= WEP_IV_LEN
+ WEP_ICV_LEN
;
240 bc_ent
= cpu_to_le16((len
& 0xFFF) | (sta_id
<< 12));
242 scd_bc_tbl
[txq_id
].tfd_offset
[write_ptr
] = bc_ent
;
244 if (write_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
246 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ write_ptr
] = bc_ent
;
249 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans
*trans
,
252 struct iwl_trans_pcie
*trans_pcie
=
253 IWL_TRANS_GET_PCIE_TRANS(trans
);
254 struct iwlagn_scd_bc_tbl
*scd_bc_tbl
= trans_pcie
->scd_bc_tbls
.addr
;
255 int txq_id
= txq
->q
.id
;
256 int read_ptr
= txq
->q
.read_ptr
;
259 struct iwl_tx_cmd
*tx_cmd
=
260 (void *)txq
->entries
[txq
->q
.read_ptr
].cmd
->payload
;
262 WARN_ON(read_ptr
>= TFD_QUEUE_SIZE_MAX
);
264 if (txq_id
!= trans_pcie
->cmd_queue
)
265 sta_id
= tx_cmd
->sta_id
;
267 bc_ent
= cpu_to_le16(1 | (sta_id
<< 12));
268 scd_bc_tbl
[txq_id
].tfd_offset
[read_ptr
] = bc_ent
;
270 if (read_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
272 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ read_ptr
] = bc_ent
;
276 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
278 void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans
*trans
, struct iwl_txq
*txq
)
281 int txq_id
= txq
->q
.id
;
283 if (txq
->need_update
== 0)
286 if (trans
->cfg
->base_params
->shadow_reg_enable
) {
287 /* shadow register enabled */
288 iwl_write32(trans
, HBUS_TARG_WRPTR
,
289 txq
->q
.write_ptr
| (txq_id
<< 8));
291 struct iwl_trans_pcie
*trans_pcie
=
292 IWL_TRANS_GET_PCIE_TRANS(trans
);
293 /* if we're trying to save power */
294 if (test_bit(STATUS_TPOWER_PMI
, &trans_pcie
->status
)) {
295 /* wake up nic if it's powered down ...
296 * uCode will wake up, and interrupt us again, so next
297 * time we'll skip this part. */
298 reg
= iwl_read32(trans
, CSR_UCODE_DRV_GP1
);
300 if (reg
& CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP
) {
301 IWL_DEBUG_INFO(trans
,
302 "Tx queue %d requesting wakeup,"
303 " GP1 = 0x%x\n", txq_id
, reg
);
304 iwl_set_bit(trans
, CSR_GP_CNTRL
,
305 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
309 iwl_write_direct32(trans
, HBUS_TARG_WRPTR
,
310 txq
->q
.write_ptr
| (txq_id
<< 8));
313 * else not in power-save mode,
314 * uCode will never sleep when we're
315 * trying to tx (during RFKILL, we're not trying to tx).
318 iwl_write32(trans
, HBUS_TARG_WRPTR
,
319 txq
->q
.write_ptr
| (txq_id
<< 8));
321 txq
->need_update
= 0;
324 static inline dma_addr_t
iwl_pcie_tfd_tb_get_addr(struct iwl_tfd
*tfd
, u8 idx
)
326 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
328 dma_addr_t addr
= get_unaligned_le32(&tb
->lo
);
329 if (sizeof(dma_addr_t
) > sizeof(u32
))
331 ((dma_addr_t
)(le16_to_cpu(tb
->hi_n_len
) & 0xF) << 16) << 16;
336 static inline u16
iwl_pcie_tfd_tb_get_len(struct iwl_tfd
*tfd
, u8 idx
)
338 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
340 return le16_to_cpu(tb
->hi_n_len
) >> 4;
343 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd
*tfd
, u8 idx
,
344 dma_addr_t addr
, u16 len
)
346 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
347 u16 hi_n_len
= len
<< 4;
349 put_unaligned_le32(addr
, &tb
->lo
);
350 if (sizeof(dma_addr_t
) > sizeof(u32
))
351 hi_n_len
|= ((addr
>> 16) >> 16) & 0xF;
353 tb
->hi_n_len
= cpu_to_le16(hi_n_len
);
355 tfd
->num_tbs
= idx
+ 1;
358 static inline u8
iwl_pcie_tfd_get_num_tbs(struct iwl_tfd
*tfd
)
360 return tfd
->num_tbs
& 0x1f;
363 static void iwl_pcie_tfd_unmap(struct iwl_trans
*trans
,
364 struct iwl_cmd_meta
*meta
, struct iwl_tfd
*tfd
,
365 enum dma_data_direction dma_dir
)
370 /* Sanity check on number of chunks */
371 num_tbs
= iwl_pcie_tfd_get_num_tbs(tfd
);
373 if (num_tbs
>= IWL_NUM_OF_TBS
) {
374 IWL_ERR(trans
, "Too many chunks: %i\n", num_tbs
);
375 /* @todo issue fatal error, it is quite serious situation */
381 dma_unmap_single(trans
->dev
,
382 dma_unmap_addr(meta
, mapping
),
383 dma_unmap_len(meta
, len
),
386 /* Unmap chunks, if any. */
387 for (i
= 1; i
< num_tbs
; i
++)
388 dma_unmap_single(trans
->dev
, iwl_pcie_tfd_tb_get_addr(tfd
, i
),
389 iwl_pcie_tfd_tb_get_len(tfd
, i
), dma_dir
);
395 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
396 * @trans - transport private data
398 * @dma_dir - the direction of the DMA mapping
400 * Does NOT advance any TFD circular buffer read/write indexes
401 * Does NOT free the TFD itself (which is within circular buffer)
403 static void iwl_pcie_txq_free_tfd(struct iwl_trans
*trans
, struct iwl_txq
*txq
,
404 enum dma_data_direction dma_dir
)
406 struct iwl_tfd
*tfd_tmp
= txq
->tfds
;
408 /* rd_ptr is bounded by n_bd and idx is bounded by n_window */
409 int rd_ptr
= txq
->q
.read_ptr
;
410 int idx
= get_cmd_index(&txq
->q
, rd_ptr
);
412 lockdep_assert_held(&txq
->lock
);
414 /* We have only q->n_window txq->entries, but we use q->n_bd tfds */
415 iwl_pcie_tfd_unmap(trans
, &txq
->entries
[idx
].meta
, &tfd_tmp
[rd_ptr
],
422 skb
= txq
->entries
[idx
].skb
;
424 /* Can be called from irqs-disabled context
425 * If skb is not NULL, it means that the whole queue is being
426 * freed and that the queue is not empty - free the skb
429 iwl_op_mode_free_skb(trans
->op_mode
, skb
);
430 txq
->entries
[idx
].skb
= NULL
;
435 static int iwl_pcie_txq_build_tfd(struct iwl_trans
*trans
, struct iwl_txq
*txq
,
436 dma_addr_t addr
, u16 len
, u8 reset
)
439 struct iwl_tfd
*tfd
, *tfd_tmp
;
444 tfd
= &tfd_tmp
[q
->write_ptr
];
447 memset(tfd
, 0, sizeof(*tfd
));
449 num_tbs
= iwl_pcie_tfd_get_num_tbs(tfd
);
451 /* Each TFD can point to a maximum 20 Tx buffers */
452 if (num_tbs
>= IWL_NUM_OF_TBS
) {
453 IWL_ERR(trans
, "Error can not send more than %d chunks\n",
458 if (WARN_ON(addr
& ~DMA_BIT_MASK(36)))
461 if (unlikely(addr
& ~IWL_TX_DMA_MASK
))
462 IWL_ERR(trans
, "Unaligned address = %llx\n",
463 (unsigned long long)addr
);
465 iwl_pcie_tfd_set_tb(tfd
, num_tbs
, addr
, len
);
470 static int iwl_pcie_txq_alloc(struct iwl_trans
*trans
,
471 struct iwl_txq
*txq
, int slots_num
,
474 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
475 size_t tfd_sz
= sizeof(struct iwl_tfd
) * TFD_QUEUE_SIZE_MAX
;
478 if (WARN_ON(txq
->entries
|| txq
->tfds
))
481 setup_timer(&txq
->stuck_timer
, iwl_pcie_txq_stuck_timer
,
483 txq
->trans_pcie
= trans_pcie
;
485 txq
->q
.n_window
= slots_num
;
487 txq
->entries
= kcalloc(slots_num
,
488 sizeof(struct iwl_pcie_txq_entry
),
494 if (txq_id
== trans_pcie
->cmd_queue
)
495 for (i
= 0; i
< slots_num
; i
++) {
496 txq
->entries
[i
].cmd
=
497 kmalloc(sizeof(struct iwl_device_cmd
),
499 if (!txq
->entries
[i
].cmd
)
503 /* Circular buffer of transmit frame descriptors (TFDs),
504 * shared with device */
505 txq
->tfds
= dma_alloc_coherent(trans
->dev
, tfd_sz
,
506 &txq
->q
.dma_addr
, GFP_KERNEL
);
508 IWL_ERR(trans
, "dma_alloc_coherent(%zd) failed\n", tfd_sz
);
515 if (txq
->entries
&& txq_id
== trans_pcie
->cmd_queue
)
516 for (i
= 0; i
< slots_num
; i
++)
517 kfree(txq
->entries
[i
].cmd
);
525 static int iwl_pcie_txq_init(struct iwl_trans
*trans
, struct iwl_txq
*txq
,
526 int slots_num
, u32 txq_id
)
530 txq
->need_update
= 0;
532 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
533 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
534 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
536 /* Initialize queue's high/low-water marks, and head/tail indexes */
537 ret
= iwl_queue_init(&txq
->q
, TFD_QUEUE_SIZE_MAX
, slots_num
,
542 spin_lock_init(&txq
->lock
);
545 * Tell nic where to find circular buffer of Tx Frame Descriptors for
546 * given Tx queue, and enable the DMA channel used for that queue.
547 * Circular buffer (TFD queue in DRAM) physical base address */
548 iwl_write_direct32(trans
, FH_MEM_CBBC_QUEUE(txq_id
),
549 txq
->q
.dma_addr
>> 8);
555 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
557 static void iwl_pcie_txq_unmap(struct iwl_trans
*trans
, int txq_id
)
559 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
560 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
561 struct iwl_queue
*q
= &txq
->q
;
562 enum dma_data_direction dma_dir
;
567 /* In the command queue, all the TBs are mapped as BIDI
568 * so unmap them as such.
570 if (txq_id
== trans_pcie
->cmd_queue
)
571 dma_dir
= DMA_BIDIRECTIONAL
;
573 dma_dir
= DMA_TO_DEVICE
;
575 spin_lock_bh(&txq
->lock
);
576 while (q
->write_ptr
!= q
->read_ptr
) {
577 iwl_pcie_txq_free_tfd(trans
, txq
, dma_dir
);
578 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
);
580 spin_unlock_bh(&txq
->lock
);
584 * iwl_pcie_txq_free - Deallocate DMA queue.
585 * @txq: Transmit queue to deallocate.
587 * Empty queue by removing and destroying all BD's.
589 * 0-fill, but do not free "txq" descriptor structure.
591 static void iwl_pcie_txq_free(struct iwl_trans
*trans
, int txq_id
)
593 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
594 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
595 struct device
*dev
= trans
->dev
;
601 iwl_pcie_txq_unmap(trans
, txq_id
);
603 /* De-alloc array of command/tx buffers */
604 if (txq_id
== trans_pcie
->cmd_queue
)
605 for (i
= 0; i
< txq
->q
.n_window
; i
++) {
606 kfree(txq
->entries
[i
].cmd
);
607 kfree(txq
->entries
[i
].copy_cmd
);
608 kfree(txq
->entries
[i
].free_buf
);
611 /* De-alloc circular buffer of TFDs */
613 dma_free_coherent(dev
, sizeof(struct iwl_tfd
) *
614 txq
->q
.n_bd
, txq
->tfds
, txq
->q
.dma_addr
);
615 memset(&txq
->q
.dma_addr
, 0, sizeof(txq
->q
.dma_addr
));
621 del_timer_sync(&txq
->stuck_timer
);
623 /* 0-fill queue descriptor structure */
624 memset(txq
, 0, sizeof(*txq
));
628 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
630 static void iwl_pcie_txq_set_sched(struct iwl_trans
*trans
, u32 mask
)
632 struct iwl_trans_pcie __maybe_unused
*trans_pcie
=
633 IWL_TRANS_GET_PCIE_TRANS(trans
);
635 iwl_write_prph(trans
, SCD_TXFACT
, mask
);
638 void iwl_pcie_tx_start(struct iwl_trans
*trans
, u32 scd_base_addr
)
640 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
645 /* make sure all queue are not stopped/used */
646 memset(trans_pcie
->queue_stopped
, 0, sizeof(trans_pcie
->queue_stopped
));
647 memset(trans_pcie
->queue_used
, 0, sizeof(trans_pcie
->queue_used
));
649 trans_pcie
->scd_base_addr
=
650 iwl_read_prph(trans
, SCD_SRAM_BASE_ADDR
);
652 WARN_ON(scd_base_addr
!= 0 &&
653 scd_base_addr
!= trans_pcie
->scd_base_addr
);
655 a
= trans_pcie
->scd_base_addr
+ SCD_CONTEXT_MEM_LOWER_BOUND
;
656 /* reset conext data memory */
657 for (; a
< trans_pcie
->scd_base_addr
+ SCD_CONTEXT_MEM_UPPER_BOUND
;
659 iwl_write_targ_mem(trans
, a
, 0);
660 /* reset tx status memory */
661 for (; a
< trans_pcie
->scd_base_addr
+ SCD_TX_STTS_MEM_UPPER_BOUND
;
663 iwl_write_targ_mem(trans
, a
, 0);
664 for (; a
< trans_pcie
->scd_base_addr
+
665 SCD_TRANS_TBL_OFFSET_QUEUE(
666 trans
->cfg
->base_params
->num_of_queues
);
668 iwl_write_targ_mem(trans
, a
, 0);
670 iwl_write_prph(trans
, SCD_DRAM_BASE_ADDR
,
671 trans_pcie
->scd_bc_tbls
.dma
>> 10);
673 /* The chain extension of the SCD doesn't work well. This feature is
674 * enabled by default by the HW, so we need to disable it manually.
676 iwl_write_prph(trans
, SCD_CHAINEXT_EN
, 0);
678 iwl_trans_ac_txq_enable(trans
, trans_pcie
->cmd_queue
,
679 trans_pcie
->cmd_fifo
);
681 /* Activate all Tx DMA/FIFO channels */
682 iwl_pcie_txq_set_sched(trans
, IWL_MASK(0, 7));
684 /* Enable DMA channel */
685 for (chan
= 0; chan
< FH_TCSR_CHNL_NUM
; chan
++)
686 iwl_write_direct32(trans
, FH_TCSR_CHNL_TX_CONFIG_REG(chan
),
687 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
688 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
);
690 /* Update FH chicken bits */
691 reg_val
= iwl_read_direct32(trans
, FH_TX_CHICKEN_BITS_REG
);
692 iwl_write_direct32(trans
, FH_TX_CHICKEN_BITS_REG
,
693 reg_val
| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
);
695 /* Enable L1-Active */
696 iwl_clear_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
697 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
701 * iwl_pcie_tx_stop - Stop all Tx DMA channels
703 int iwl_pcie_tx_stop(struct iwl_trans
*trans
)
705 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
709 /* Turn off all Tx DMA fifos */
710 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
712 iwl_pcie_txq_set_sched(trans
, 0);
714 /* Stop each Tx DMA channel, and wait for it to be idle */
715 for (ch
= 0; ch
< FH_TCSR_CHNL_NUM
; ch
++) {
716 iwl_write_direct32(trans
,
717 FH_TCSR_CHNL_TX_CONFIG_REG(ch
), 0x0);
718 ret
= iwl_poll_direct_bit(trans
, FH_TSSR_TX_STATUS_REG
,
719 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch
), 1000);
722 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
724 iwl_read_direct32(trans
,
725 FH_TSSR_TX_STATUS_REG
));
727 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
729 if (!trans_pcie
->txq
) {
731 "Stopping tx queues that aren't allocated...\n");
735 /* Unmap DMA from host system and free skb's */
736 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
738 iwl_pcie_txq_unmap(trans
, txq_id
);
744 * iwl_trans_tx_free - Free TXQ Context
746 * Destroy all TX DMA queues and structures
748 void iwl_pcie_tx_free(struct iwl_trans
*trans
)
751 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
754 if (trans_pcie
->txq
) {
756 txq_id
< trans
->cfg
->base_params
->num_of_queues
; txq_id
++)
757 iwl_pcie_txq_free(trans
, txq_id
);
760 kfree(trans_pcie
->txq
);
761 trans_pcie
->txq
= NULL
;
763 iwl_pcie_free_dma_ptr(trans
, &trans_pcie
->kw
);
765 iwl_pcie_free_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
);
769 * iwl_pcie_tx_alloc - allocate TX context
770 * Allocate all Tx DMA structures and initialize them
772 static int iwl_pcie_tx_alloc(struct iwl_trans
*trans
)
775 int txq_id
, slots_num
;
776 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
778 u16 scd_bc_tbls_size
= trans
->cfg
->base_params
->num_of_queues
*
779 sizeof(struct iwlagn_scd_bc_tbl
);
781 /*It is not allowed to alloc twice, so warn when this happens.
782 * We cannot rely on the previous allocation, so free and fail */
783 if (WARN_ON(trans_pcie
->txq
)) {
788 ret
= iwl_pcie_alloc_dma_ptr(trans
, &trans_pcie
->scd_bc_tbls
,
791 IWL_ERR(trans
, "Scheduler BC Table allocation failed\n");
795 /* Alloc keep-warm buffer */
796 ret
= iwl_pcie_alloc_dma_ptr(trans
, &trans_pcie
->kw
, IWL_KW_SIZE
);
798 IWL_ERR(trans
, "Keep Warm allocation failed\n");
802 trans_pcie
->txq
= kcalloc(trans
->cfg
->base_params
->num_of_queues
,
803 sizeof(struct iwl_txq
), GFP_KERNEL
);
804 if (!trans_pcie
->txq
) {
805 IWL_ERR(trans
, "Not enough memory for txq\n");
810 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
811 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
813 slots_num
= (txq_id
== trans_pcie
->cmd_queue
) ?
814 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
815 ret
= iwl_pcie_txq_alloc(trans
, &trans_pcie
->txq
[txq_id
],
818 IWL_ERR(trans
, "Tx %d queue alloc failed\n", txq_id
);
826 iwl_pcie_tx_free(trans
);
830 int iwl_pcie_tx_init(struct iwl_trans
*trans
)
832 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
834 int txq_id
, slots_num
;
838 if (!trans_pcie
->txq
) {
839 ret
= iwl_pcie_tx_alloc(trans
);
845 spin_lock_irqsave(&trans_pcie
->irq_lock
, flags
);
847 /* Turn off all Tx DMA fifos */
848 iwl_write_prph(trans
, SCD_TXFACT
, 0);
850 /* Tell NIC where to find the "keep warm" buffer */
851 iwl_write_direct32(trans
, FH_KW_MEM_ADDR_REG
,
852 trans_pcie
->kw
.dma
>> 4);
854 spin_unlock_irqrestore(&trans_pcie
->irq_lock
, flags
);
856 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
857 for (txq_id
= 0; txq_id
< trans
->cfg
->base_params
->num_of_queues
;
859 slots_num
= (txq_id
== trans_pcie
->cmd_queue
) ?
860 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
861 ret
= iwl_pcie_txq_init(trans
, &trans_pcie
->txq
[txq_id
],
864 IWL_ERR(trans
, "Tx %d queue init failed\n", txq_id
);
871 /*Upon error, free only if we allocated something */
873 iwl_pcie_tx_free(trans
);
877 static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie
*trans_pcie
,
880 if (!trans_pcie
->wd_timeout
)
884 * if empty delete timer, otherwise move timer forward
885 * since we're making progress on this queue
887 if (txq
->q
.read_ptr
== txq
->q
.write_ptr
)
888 del_timer(&txq
->stuck_timer
);
890 mod_timer(&txq
->stuck_timer
, jiffies
+ trans_pcie
->wd_timeout
);
893 /* Frees buffers until index _not_ inclusive */
894 void iwl_trans_pcie_reclaim(struct iwl_trans
*trans
, int txq_id
, int ssn
,
895 struct sk_buff_head
*skbs
)
897 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
898 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
899 /* n_bd is usually 256 => n_bd - 1 = 0xff */
900 int tfd_num
= ssn
& (txq
->q
.n_bd
- 1);
901 struct iwl_queue
*q
= &txq
->q
;
904 /* This function is not meant to release cmd queue*/
905 if (WARN_ON(txq_id
== trans_pcie
->cmd_queue
))
908 spin_lock(&txq
->lock
);
910 if (txq
->q
.read_ptr
== tfd_num
)
913 IWL_DEBUG_TX_REPLY(trans
, "[Q %d] %d -> %d (%d)\n",
914 txq_id
, txq
->q
.read_ptr
, tfd_num
, ssn
);
916 /*Since we free until index _not_ inclusive, the one before index is
917 * the last we will free. This one must be used */
918 last_to_free
= iwl_queue_dec_wrap(tfd_num
, q
->n_bd
);
920 if (!iwl_queue_used(q
, last_to_free
)) {
922 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
923 __func__
, txq_id
, last_to_free
, q
->n_bd
,
924 q
->write_ptr
, q
->read_ptr
);
928 if (WARN_ON(!skb_queue_empty(skbs
)))
932 q
->read_ptr
!= tfd_num
;
933 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
935 if (WARN_ON_ONCE(txq
->entries
[txq
->q
.read_ptr
].skb
== NULL
))
938 __skb_queue_tail(skbs
, txq
->entries
[txq
->q
.read_ptr
].skb
);
940 txq
->entries
[txq
->q
.read_ptr
].skb
= NULL
;
942 iwl_pcie_txq_inval_byte_cnt_tbl(trans
, txq
);
944 iwl_pcie_txq_free_tfd(trans
, txq
, DMA_TO_DEVICE
);
947 iwl_pcie_txq_progress(trans_pcie
, txq
);
949 if (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
)
950 iwl_wake_queue(trans
, txq
);
952 spin_unlock(&txq
->lock
);
956 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
958 * When FW advances 'R' index, all entries between old and new 'R' index
959 * need to be reclaimed. As result, some free space forms. If there is
960 * enough free space (> low mark), wake the stack that feeds us.
962 static void iwl_pcie_cmdq_reclaim(struct iwl_trans
*trans
, int txq_id
, int idx
)
964 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
965 struct iwl_txq
*txq
= &trans_pcie
->txq
[txq_id
];
966 struct iwl_queue
*q
= &txq
->q
;
969 lockdep_assert_held(&txq
->lock
);
971 if ((idx
>= q
->n_bd
) || (!iwl_queue_used(q
, idx
))) {
973 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
974 __func__
, txq_id
, idx
, q
->n_bd
,
975 q
->write_ptr
, q
->read_ptr
);
979 for (idx
= iwl_queue_inc_wrap(idx
, q
->n_bd
); q
->read_ptr
!= idx
;
980 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
983 IWL_ERR(trans
, "HCMD skipped: index (%d) %d %d\n",
984 idx
, q
->write_ptr
, q
->read_ptr
);
985 iwl_op_mode_nic_error(trans
->op_mode
);
989 iwl_pcie_txq_progress(trans_pcie
, txq
);
992 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans
*trans
, u16 ra_tid
,
995 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1000 scd_q2ratid
= ra_tid
& SCD_QUEUE_RA_TID_MAP_RATID_MSK
;
1002 tbl_dw_addr
= trans_pcie
->scd_base_addr
+
1003 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id
);
1005 tbl_dw
= iwl_read_targ_mem(trans
, tbl_dw_addr
);
1008 tbl_dw
= (scd_q2ratid
<< 16) | (tbl_dw
& 0x0000FFFF);
1010 tbl_dw
= scd_q2ratid
| (tbl_dw
& 0xFFFF0000);
1012 iwl_write_targ_mem(trans
, tbl_dw_addr
, tbl_dw
);
1017 static inline void iwl_pcie_txq_set_inactive(struct iwl_trans
*trans
,
1020 /* Simply stop the queue, but don't change any configuration;
1021 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1022 iwl_write_prph(trans
,
1023 SCD_QUEUE_STATUS_BITS(txq_id
),
1024 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE
)|
1025 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN
));
1028 void iwl_trans_pcie_txq_enable(struct iwl_trans
*trans
, int txq_id
, int fifo
,
1029 int sta_id
, int tid
, int frame_limit
, u16 ssn
)
1031 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1033 if (test_and_set_bit(txq_id
, trans_pcie
->queue_used
))
1034 WARN_ONCE(1, "queue %d already used - expect issues", txq_id
);
1036 /* Stop this Tx queue before configuring it */
1037 iwl_pcie_txq_set_inactive(trans
, txq_id
);
1039 /* Set this queue as a chain-building queue unless it is CMD queue */
1040 if (txq_id
!= trans_pcie
->cmd_queue
)
1041 iwl_set_bits_prph(trans
, SCD_QUEUECHAIN_SEL
, BIT(txq_id
));
1043 /* If this queue is mapped to a certain station: it is an AGG queue */
1044 if (sta_id
!= IWL_INVALID_STATION
) {
1045 u16 ra_tid
= BUILD_RAxTID(sta_id
, tid
);
1047 /* Map receiver-address / traffic-ID to this queue */
1048 iwl_pcie_txq_set_ratid_map(trans
, ra_tid
, txq_id
);
1050 /* enable aggregations for the queue */
1051 iwl_set_bits_prph(trans
, SCD_AGGR_SEL
, BIT(txq_id
));
1054 * disable aggregations for the queue, this will also make the
1055 * ra_tid mapping configuration irrelevant since it is now a
1058 iwl_clear_bits_prph(trans
, SCD_AGGR_SEL
, BIT(txq_id
));
1061 /* Place first TFD at index corresponding to start sequence number.
1062 * Assumes that ssn_idx is valid (!= 0xFFF) */
1063 trans_pcie
->txq
[txq_id
].q
.read_ptr
= (ssn
& 0xff);
1064 trans_pcie
->txq
[txq_id
].q
.write_ptr
= (ssn
& 0xff);
1066 iwl_write_direct32(trans
, HBUS_TARG_WRPTR
,
1067 (ssn
& 0xff) | (txq_id
<< 8));
1068 iwl_write_prph(trans
, SCD_QUEUE_RDPTR(txq_id
), ssn
);
1070 /* Set up Tx window size and frame limit for this queue */
1071 iwl_write_targ_mem(trans
, trans_pcie
->scd_base_addr
+
1072 SCD_CONTEXT_QUEUE_OFFSET(txq_id
), 0);
1073 iwl_write_targ_mem(trans
, trans_pcie
->scd_base_addr
+
1074 SCD_CONTEXT_QUEUE_OFFSET(txq_id
) + sizeof(u32
),
1075 ((frame_limit
<< SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
1076 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
1077 ((frame_limit
<< SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
1078 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
1080 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1081 iwl_write_prph(trans
, SCD_QUEUE_STATUS_BITS(txq_id
),
1082 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE
) |
1083 (fifo
<< SCD_QUEUE_STTS_REG_POS_TXF
) |
1084 (1 << SCD_QUEUE_STTS_REG_POS_WSL
) |
1085 SCD_QUEUE_STTS_REG_MSK
);
1086 IWL_DEBUG_TX_QUEUES(trans
, "Activate queue %d on FIFO %d WrPtr: %d\n",
1087 txq_id
, fifo
, ssn
& 0xff);
1090 void iwl_trans_pcie_txq_disable(struct iwl_trans
*trans
, int txq_id
)
1092 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1093 u32 stts_addr
= trans_pcie
->scd_base_addr
+
1094 SCD_TX_STTS_QUEUE_OFFSET(txq_id
);
1095 static const u32 zero_val
[4] = {};
1097 if (!test_and_clear_bit(txq_id
, trans_pcie
->queue_used
)) {
1098 WARN_ONCE(1, "queue %d not used", txq_id
);
1102 iwl_pcie_txq_set_inactive(trans
, txq_id
);
1104 _iwl_write_targ_mem_dwords(trans
, stts_addr
,
1105 zero_val
, ARRAY_SIZE(zero_val
));
1107 iwl_pcie_txq_unmap(trans
, txq_id
);
1109 IWL_DEBUG_TX_QUEUES(trans
, "Deactivate queue %d\n", txq_id
);
1112 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1115 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1116 * @priv: device private data point
1117 * @cmd: a point to the ucode command structure
1119 * The function returns < 0 values to indicate the operation is
1120 * failed. On success, it turns the index (> 0) of command in the
1123 static int iwl_pcie_enqueue_hcmd(struct iwl_trans
*trans
,
1124 struct iwl_host_cmd
*cmd
)
1126 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1127 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1128 struct iwl_queue
*q
= &txq
->q
;
1129 struct iwl_device_cmd
*out_cmd
;
1130 struct iwl_cmd_meta
*out_meta
;
1131 void *dup_buf
= NULL
;
1132 dma_addr_t phys_addr
;
1134 u16 copy_size
, cmd_size
;
1135 bool had_nocopy
= false;
1139 copy_size
= sizeof(out_cmd
->hdr
);
1140 cmd_size
= sizeof(out_cmd
->hdr
);
1142 /* need one for the header if the first is NOCOPY */
1143 BUILD_BUG_ON(IWL_MAX_CMD_TFDS
> IWL_NUM_OF_TBS
- 1);
1145 for (i
= 0; i
< IWL_MAX_CMD_TFDS
; i
++) {
1148 if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_NOCOPY
) {
1150 if (WARN_ON(cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
)) {
1154 } else if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
) {
1156 * This is also a chunk that isn't copied
1157 * to the static buffer so set had_nocopy.
1161 /* only allowed once */
1162 if (WARN_ON(dup_buf
)) {
1167 dup_buf
= kmemdup(cmd
->data
[i
], cmd
->len
[i
],
1172 /* NOCOPY must not be followed by normal! */
1173 if (WARN_ON(had_nocopy
)) {
1177 copy_size
+= cmd
->len
[i
];
1179 cmd_size
+= cmd
->len
[i
];
1183 * If any of the command structures end up being larger than
1184 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1185 * allocated into separate TFDs, then we will need to
1186 * increase the size of the buffers.
1188 if (WARN(copy_size
> TFD_MAX_PAYLOAD_SIZE
,
1189 "Command %s (%#x) is too large (%d bytes)\n",
1190 get_cmd_string(trans_pcie
, cmd
->id
), cmd
->id
, copy_size
)) {
1195 spin_lock_bh(&txq
->lock
);
1197 if (iwl_queue_space(q
) < ((cmd
->flags
& CMD_ASYNC
) ? 2 : 1)) {
1198 spin_unlock_bh(&txq
->lock
);
1200 IWL_ERR(trans
, "No space in command queue\n");
1201 iwl_op_mode_cmd_queue_full(trans
->op_mode
);
1206 idx
= get_cmd_index(q
, q
->write_ptr
);
1207 out_cmd
= txq
->entries
[idx
].cmd
;
1208 out_meta
= &txq
->entries
[idx
].meta
;
1210 memset(out_meta
, 0, sizeof(*out_meta
)); /* re-initialize to NULL */
1211 if (cmd
->flags
& CMD_WANT_SKB
)
1212 out_meta
->source
= cmd
;
1214 /* set up the header */
1216 out_cmd
->hdr
.cmd
= cmd
->id
;
1217 out_cmd
->hdr
.flags
= 0;
1218 out_cmd
->hdr
.sequence
=
1219 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie
->cmd_queue
) |
1220 INDEX_TO_SEQ(q
->write_ptr
));
1222 /* and copy the data that needs to be copied */
1223 cmd_pos
= offsetof(struct iwl_device_cmd
, payload
);
1224 for (i
= 0; i
< IWL_MAX_CMD_TFDS
; i
++) {
1227 if (cmd
->dataflags
[i
] & (IWL_HCMD_DFL_NOCOPY
|
1230 memcpy((u8
*)out_cmd
+ cmd_pos
, cmd
->data
[i
], cmd
->len
[i
]);
1231 cmd_pos
+= cmd
->len
[i
];
1234 WARN_ON_ONCE(txq
->entries
[idx
].copy_cmd
);
1237 * since out_cmd will be the source address of the FH, it will write
1238 * the retry count there. So when the user needs to receivce the HCMD
1239 * that corresponds to the response in the response handler, it needs
1240 * to set CMD_WANT_HCMD.
1242 if (cmd
->flags
& CMD_WANT_HCMD
) {
1243 txq
->entries
[idx
].copy_cmd
=
1244 kmemdup(out_cmd
, cmd_pos
, GFP_ATOMIC
);
1245 if (unlikely(!txq
->entries
[idx
].copy_cmd
)) {
1252 "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1253 get_cmd_string(trans_pcie
, out_cmd
->hdr
.cmd
),
1254 out_cmd
->hdr
.cmd
, le16_to_cpu(out_cmd
->hdr
.sequence
),
1255 cmd_size
, q
->write_ptr
, idx
, trans_pcie
->cmd_queue
);
1257 phys_addr
= dma_map_single(trans
->dev
, &out_cmd
->hdr
, copy_size
,
1259 if (unlikely(dma_mapping_error(trans
->dev
, phys_addr
))) {
1264 dma_unmap_addr_set(out_meta
, mapping
, phys_addr
);
1265 dma_unmap_len_set(out_meta
, len
, copy_size
);
1267 iwl_pcie_txq_build_tfd(trans
, txq
, phys_addr
, copy_size
, 1);
1269 for (i
= 0; i
< IWL_MAX_CMD_TFDS
; i
++) {
1270 const void *data
= cmd
->data
[i
];
1274 if (!(cmd
->dataflags
[i
] & (IWL_HCMD_DFL_NOCOPY
|
1277 if (cmd
->dataflags
[i
] & IWL_HCMD_DFL_DUP
)
1279 phys_addr
= dma_map_single(trans
->dev
, (void *)data
,
1280 cmd
->len
[i
], DMA_BIDIRECTIONAL
);
1281 if (dma_mapping_error(trans
->dev
, phys_addr
)) {
1282 iwl_pcie_tfd_unmap(trans
, out_meta
,
1283 &txq
->tfds
[q
->write_ptr
],
1289 iwl_pcie_txq_build_tfd(trans
, txq
, phys_addr
, cmd
->len
[i
], 0);
1292 out_meta
->flags
= cmd
->flags
;
1293 if (WARN_ON_ONCE(txq
->entries
[idx
].free_buf
))
1294 kfree(txq
->entries
[idx
].free_buf
);
1295 txq
->entries
[idx
].free_buf
= dup_buf
;
1297 txq
->need_update
= 1;
1299 trace_iwlwifi_dev_hcmd(trans
->dev
, cmd
, cmd_size
,
1300 &out_cmd
->hdr
, copy_size
);
1302 /* start timer if queue currently empty */
1303 if (q
->read_ptr
== q
->write_ptr
&& trans_pcie
->wd_timeout
)
1304 mod_timer(&txq
->stuck_timer
, jiffies
+ trans_pcie
->wd_timeout
);
1306 /* Increment and update queue's write index */
1307 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
1308 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
1311 spin_unlock_bh(&txq
->lock
);
1319 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1320 * @rxb: Rx buffer to reclaim
1321 * @handler_status: return value of the handler of the command
1322 * (put in setup_rx_handlers)
1324 * If an Rx buffer has an async callback associated with it the callback
1325 * will be executed. The attached skb (if present) will only be freed
1326 * if the callback returns 1
1328 void iwl_pcie_hcmd_complete(struct iwl_trans
*trans
,
1329 struct iwl_rx_cmd_buffer
*rxb
, int handler_status
)
1331 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
1332 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
1333 int txq_id
= SEQ_TO_QUEUE(sequence
);
1334 int index
= SEQ_TO_INDEX(sequence
);
1336 struct iwl_device_cmd
*cmd
;
1337 struct iwl_cmd_meta
*meta
;
1338 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1339 struct iwl_txq
*txq
= &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1341 /* If a Tx command is being handled and it isn't in the actual
1342 * command queue then there a command routing bug has been introduced
1343 * in the queue management code. */
1344 if (WARN(txq_id
!= trans_pcie
->cmd_queue
,
1345 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1346 txq_id
, trans_pcie
->cmd_queue
, sequence
,
1347 trans_pcie
->txq
[trans_pcie
->cmd_queue
].q
.read_ptr
,
1348 trans_pcie
->txq
[trans_pcie
->cmd_queue
].q
.write_ptr
)) {
1349 iwl_print_hex_error(trans
, pkt
, 32);
1353 spin_lock(&txq
->lock
);
1355 cmd_index
= get_cmd_index(&txq
->q
, index
);
1356 cmd
= txq
->entries
[cmd_index
].cmd
;
1357 meta
= &txq
->entries
[cmd_index
].meta
;
1359 iwl_pcie_tfd_unmap(trans
, meta
, &txq
->tfds
[index
], DMA_BIDIRECTIONAL
);
1361 /* Input error checking is done when commands are added to queue. */
1362 if (meta
->flags
& CMD_WANT_SKB
) {
1363 struct page
*p
= rxb_steal_page(rxb
);
1365 meta
->source
->resp_pkt
= pkt
;
1366 meta
->source
->_rx_page_addr
= (unsigned long)page_address(p
);
1367 meta
->source
->_rx_page_order
= trans_pcie
->rx_page_order
;
1368 meta
->source
->handler_status
= handler_status
;
1371 iwl_pcie_cmdq_reclaim(trans
, txq_id
, index
);
1373 if (!(meta
->flags
& CMD_ASYNC
)) {
1374 if (!test_bit(STATUS_HCMD_ACTIVE
, &trans_pcie
->status
)) {
1376 "HCMD_ACTIVE already clear for command %s\n",
1377 get_cmd_string(trans_pcie
, cmd
->hdr
.cmd
));
1379 clear_bit(STATUS_HCMD_ACTIVE
, &trans_pcie
->status
);
1380 IWL_DEBUG_INFO(trans
, "Clearing HCMD_ACTIVE for command %s\n",
1381 get_cmd_string(trans_pcie
, cmd
->hdr
.cmd
));
1382 wake_up(&trans_pcie
->wait_command_queue
);
1387 spin_unlock(&txq
->lock
);
1390 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
1392 static int iwl_pcie_send_hcmd_async(struct iwl_trans
*trans
,
1393 struct iwl_host_cmd
*cmd
)
1395 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1398 /* An asynchronous command can not expect an SKB to be set. */
1399 if (WARN_ON(cmd
->flags
& CMD_WANT_SKB
))
1402 ret
= iwl_pcie_enqueue_hcmd(trans
, cmd
);
1405 "Error sending %s: enqueue_hcmd failed: %d\n",
1406 get_cmd_string(trans_pcie
, cmd
->id
), ret
);
1412 static int iwl_pcie_send_hcmd_sync(struct iwl_trans
*trans
,
1413 struct iwl_host_cmd
*cmd
)
1415 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1419 IWL_DEBUG_INFO(trans
, "Attempting to send sync command %s\n",
1420 get_cmd_string(trans_pcie
, cmd
->id
));
1422 if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE
,
1423 &trans_pcie
->status
))) {
1424 IWL_ERR(trans
, "Command %s: a command is already active!\n",
1425 get_cmd_string(trans_pcie
, cmd
->id
));
1429 IWL_DEBUG_INFO(trans
, "Setting HCMD_ACTIVE for command %s\n",
1430 get_cmd_string(trans_pcie
, cmd
->id
));
1432 cmd_idx
= iwl_pcie_enqueue_hcmd(trans
, cmd
);
1435 clear_bit(STATUS_HCMD_ACTIVE
, &trans_pcie
->status
);
1437 "Error sending %s: enqueue_hcmd failed: %d\n",
1438 get_cmd_string(trans_pcie
, cmd
->id
), ret
);
1442 ret
= wait_event_timeout(trans_pcie
->wait_command_queue
,
1443 !test_bit(STATUS_HCMD_ACTIVE
,
1444 &trans_pcie
->status
),
1445 HOST_COMPLETE_TIMEOUT
);
1447 if (test_bit(STATUS_HCMD_ACTIVE
, &trans_pcie
->status
)) {
1448 struct iwl_txq
*txq
=
1449 &trans_pcie
->txq
[trans_pcie
->cmd_queue
];
1450 struct iwl_queue
*q
= &txq
->q
;
1453 "Error sending %s: time out after %dms.\n",
1454 get_cmd_string(trans_pcie
, cmd
->id
),
1455 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT
));
1458 "Current CMD queue read_ptr %d write_ptr %d\n",
1459 q
->read_ptr
, q
->write_ptr
);
1461 clear_bit(STATUS_HCMD_ACTIVE
, &trans_pcie
->status
);
1462 IWL_DEBUG_INFO(trans
,
1463 "Clearing HCMD_ACTIVE for command %s\n",
1464 get_cmd_string(trans_pcie
, cmd
->id
));
1470 if (test_bit(STATUS_FW_ERROR
, &trans_pcie
->status
)) {
1471 IWL_ERR(trans
, "FW error in SYNC CMD %s\n",
1472 get_cmd_string(trans_pcie
, cmd
->id
));
1477 if (test_bit(STATUS_RFKILL
, &trans_pcie
->status
)) {
1478 IWL_DEBUG_RF_KILL(trans
, "RFKILL in SYNC CMD... no rsp\n");
1483 if ((cmd
->flags
& CMD_WANT_SKB
) && !cmd
->resp_pkt
) {
1484 IWL_ERR(trans
, "Error: Response NULL in '%s'\n",
1485 get_cmd_string(trans_pcie
, cmd
->id
));
1493 if (cmd
->flags
& CMD_WANT_SKB
) {
1495 * Cancel the CMD_WANT_SKB flag for the cmd in the
1496 * TX cmd queue. Otherwise in case the cmd comes
1497 * in later, it will possibly set an invalid
1498 * address (cmd->meta.source).
1500 trans_pcie
->txq
[trans_pcie
->cmd_queue
].
1501 entries
[cmd_idx
].meta
.flags
&= ~CMD_WANT_SKB
;
1504 if (cmd
->resp_pkt
) {
1506 cmd
->resp_pkt
= NULL
;
1512 int iwl_trans_pcie_send_hcmd(struct iwl_trans
*trans
, struct iwl_host_cmd
*cmd
)
1514 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1516 if (test_bit(STATUS_FW_ERROR
, &trans_pcie
->status
))
1519 if (test_bit(STATUS_RFKILL
, &trans_pcie
->status
))
1522 if (cmd
->flags
& CMD_ASYNC
)
1523 return iwl_pcie_send_hcmd_async(trans
, cmd
);
1525 /* We still can fail on RFKILL that can be asserted while we wait */
1526 return iwl_pcie_send_hcmd_sync(trans
, cmd
);
1529 int iwl_trans_pcie_tx(struct iwl_trans
*trans
, struct sk_buff
*skb
,
1530 struct iwl_device_cmd
*dev_cmd
, int txq_id
)
1532 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1533 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1534 struct iwl_tx_cmd
*tx_cmd
= (struct iwl_tx_cmd
*)dev_cmd
->payload
;
1535 struct iwl_cmd_meta
*out_meta
;
1536 struct iwl_txq
*txq
;
1537 struct iwl_queue
*q
;
1538 dma_addr_t phys_addr
= 0;
1539 dma_addr_t txcmd_phys
;
1540 dma_addr_t scratch_phys
;
1541 u16 len
, firstlen
, secondlen
;
1542 u8 wait_write_ptr
= 0;
1543 __le16 fc
= hdr
->frame_control
;
1544 u8 hdr_len
= ieee80211_hdrlen(fc
);
1545 u16 __maybe_unused wifi_seq
;
1547 txq
= &trans_pcie
->txq
[txq_id
];
1550 if (unlikely(!test_bit(txq_id
, trans_pcie
->queue_used
))) {
1555 spin_lock(&txq
->lock
);
1557 /* In AGG mode, the index in the ring must correspond to the WiFi
1558 * sequence number. This is a HW requirements to help the SCD to parse
1560 * Check here that the packets are in the right place on the ring.
1562 #ifdef CONFIG_IWLWIFI_DEBUG
1563 wifi_seq
= SEQ_TO_SN(le16_to_cpu(hdr
->seq_ctrl
));
1564 WARN_ONCE((iwl_read_prph(trans
, SCD_AGGR_SEL
) & BIT(txq_id
)) &&
1565 ((wifi_seq
& 0xff) != q
->write_ptr
),
1566 "Q: %d WiFi Seq %d tfdNum %d",
1567 txq_id
, wifi_seq
, q
->write_ptr
);
1570 /* Set up driver data for this TFD */
1571 txq
->entries
[q
->write_ptr
].skb
= skb
;
1572 txq
->entries
[q
->write_ptr
].cmd
= dev_cmd
;
1574 dev_cmd
->hdr
.cmd
= REPLY_TX
;
1575 dev_cmd
->hdr
.sequence
=
1576 cpu_to_le16((u16
)(QUEUE_TO_SEQ(txq_id
) |
1577 INDEX_TO_SEQ(q
->write_ptr
)));
1579 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1580 out_meta
= &txq
->entries
[q
->write_ptr
].meta
;
1583 * Use the first empty entry in this queue's command buffer array
1584 * to contain the Tx command and MAC header concatenated together
1585 * (payload data will be in another buffer).
1586 * Size of this varies, due to varying MAC header length.
1587 * If end is not dword aligned, we'll have 2 extra bytes at the end
1588 * of the MAC header (device reads on dword boundaries).
1589 * We'll tell device about this padding later.
1591 len
= sizeof(struct iwl_tx_cmd
) +
1592 sizeof(struct iwl_cmd_header
) + hdr_len
;
1593 firstlen
= (len
+ 3) & ~3;
1595 /* Tell NIC about any 2-byte padding after MAC header */
1596 if (firstlen
!= len
)
1597 tx_cmd
->tx_flags
|= TX_CMD_FLG_MH_PAD_MSK
;
1599 /* Physical address of this Tx command's header (not MAC header!),
1600 * within command buffer array. */
1601 txcmd_phys
= dma_map_single(trans
->dev
,
1602 &dev_cmd
->hdr
, firstlen
,
1604 if (unlikely(dma_mapping_error(trans
->dev
, txcmd_phys
)))
1606 dma_unmap_addr_set(out_meta
, mapping
, txcmd_phys
);
1607 dma_unmap_len_set(out_meta
, len
, firstlen
);
1609 if (!ieee80211_has_morefrags(fc
)) {
1610 txq
->need_update
= 1;
1613 txq
->need_update
= 0;
1616 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1617 * if any (802.11 null frames have no payload). */
1618 secondlen
= skb
->len
- hdr_len
;
1619 if (secondlen
> 0) {
1620 phys_addr
= dma_map_single(trans
->dev
, skb
->data
+ hdr_len
,
1621 secondlen
, DMA_TO_DEVICE
);
1622 if (unlikely(dma_mapping_error(trans
->dev
, phys_addr
))) {
1623 dma_unmap_single(trans
->dev
,
1624 dma_unmap_addr(out_meta
, mapping
),
1625 dma_unmap_len(out_meta
, len
),
1631 /* Attach buffers to TFD */
1632 iwl_pcie_txq_build_tfd(trans
, txq
, txcmd_phys
, firstlen
, 1);
1634 iwl_pcie_txq_build_tfd(trans
, txq
, phys_addr
, secondlen
, 0);
1636 scratch_phys
= txcmd_phys
+ sizeof(struct iwl_cmd_header
) +
1637 offsetof(struct iwl_tx_cmd
, scratch
);
1639 /* take back ownership of DMA buffer to enable update */
1640 dma_sync_single_for_cpu(trans
->dev
, txcmd_phys
, firstlen
,
1642 tx_cmd
->dram_lsb_ptr
= cpu_to_le32(scratch_phys
);
1643 tx_cmd
->dram_msb_ptr
= iwl_get_dma_hi_addr(scratch_phys
);
1645 IWL_DEBUG_TX(trans
, "sequence nr = 0X%x\n",
1646 le16_to_cpu(dev_cmd
->hdr
.sequence
));
1647 IWL_DEBUG_TX(trans
, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd
->tx_flags
));
1649 /* Set up entry for this TFD in Tx byte-count array */
1650 iwl_pcie_txq_update_byte_cnt_tbl(trans
, txq
, le16_to_cpu(tx_cmd
->len
));
1652 dma_sync_single_for_device(trans
->dev
, txcmd_phys
, firstlen
,
1655 trace_iwlwifi_dev_tx(trans
->dev
, skb
,
1656 &txq
->tfds
[txq
->q
.write_ptr
],
1657 sizeof(struct iwl_tfd
),
1658 &dev_cmd
->hdr
, firstlen
,
1659 skb
->data
+ hdr_len
, secondlen
);
1660 trace_iwlwifi_dev_tx_data(trans
->dev
, skb
,
1661 skb
->data
+ hdr_len
, secondlen
);
1663 /* start timer if queue currently empty */
1664 if (txq
->need_update
&& q
->read_ptr
== q
->write_ptr
&&
1665 trans_pcie
->wd_timeout
)
1666 mod_timer(&txq
->stuck_timer
, jiffies
+ trans_pcie
->wd_timeout
);
1668 /* Tell device the write index *just past* this latest filled TFD */
1669 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
1670 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
1673 * At this point the frame is "transmitted" successfully
1674 * and we will get a TX status notification eventually,
1675 * regardless of the value of ret. "ret" only indicates
1676 * whether or not we should update the write pointer.
1678 if (iwl_queue_space(q
) < q
->high_mark
) {
1679 if (wait_write_ptr
) {
1680 txq
->need_update
= 1;
1681 iwl_pcie_txq_inc_wr_ptr(trans
, txq
);
1683 iwl_stop_queue(trans
, txq
);
1686 spin_unlock(&txq
->lock
);
1689 spin_unlock(&txq
->lock
);