drivers/net/wireless/mediatek/mt76/mt76x2.h

   1 /*
   2  * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef __MT76x2_H
  18 #define __MT76x2_H
  19
  20 #include <linux/device.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/irq.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/mutex.h>
  28 #include <linux/bitops.h>
  29 #include <linux/kfifo.h>
  30
  31 #define MT7662_FIRMWARE         "mt7662.bin"
  32 #define MT7662_ROM_PATCH        "mt7662_rom_patch.bin"
  33 #define MT7662_EEPROM_SIZE      512
  34
  35 #define MT76x2_RX_RING_SIZE     256
  36 #define MT_RX_HEADROOM          32
  37
  38 #define MT_MAX_CHAINS           2
  39
  40 #define MT_CALIBRATE_INTERVAL   HZ
  41
  42 #include "mt76.h"
  43 #include "mt76x2_regs.h"
  44 #include "mt76x2_mac.h"
  45 #include "mt76x2_dfs.h"
  46
  47 struct mt76x2_mcu {
  48         struct mutex mutex;
  49
  50         wait_queue_head_t wait;
  51         struct sk_buff_head res_q;
  52
  53         u32 msg_seq;
  54 };
  55
  56 struct mt76x2_rx_freq_cal {
  57         s8 high_gain[MT_MAX_CHAINS];
  58         s8 rssi_offset[MT_MAX_CHAINS];
  59         s8 lna_gain;
  60         u32 mcu_gain;
  61 };
  62
  63 struct mt76x2_calibration {
  64         struct mt76x2_rx_freq_cal rx;
  65
  66         u8 agc_gain_init[MT_MAX_CHAINS];
  67         u8 agc_gain_cur[MT_MAX_CHAINS];
  68
  69         int avg_rssi[MT_MAX_CHAINS];
  70         int avg_rssi_all;
  71
  72         s8 agc_gain_adjust;
  73         s8 low_gain;
  74
  75         u8 temp;
  76
  77         bool init_cal_done;
  78         bool tssi_cal_done;
  79         bool tssi_comp_pending;
  80         bool dpd_cal_done;
  81         bool channel_cal_done;
  82 };
  83
  84 struct mt76x2_dev {
  85         struct mt76_dev mt76; /* must be first */
  86
  87         struct mac_address macaddr_list[8];
  88
  89         struct mutex mutex;
  90
  91         const u16 *beacon_offsets;
  92         unsigned long wcid_mask[128 / BITS_PER_LONG];
  93
  94         int txpower_conf;
  95         int txpower_cur;
  96
  97         u8 txdone_seq;
  98         DECLARE_KFIFO_PTR(txstatus_fifo, struct mt76x2_tx_status);
  99
 100         struct mt76x2_mcu mcu;
 101         struct sk_buff *rx_head;
 102
 103         struct tasklet_struct tx_tasklet;
 104         struct tasklet_struct pre_tbtt_tasklet;
 105         struct delayed_work cal_work;
 106         struct delayed_work mac_work;
 107
 108         u32 aggr_stats[32];
 109
 110         struct mt76_wcid global_wcid;
 111         struct mt76_wcid __rcu *wcid[128];
 112
 113         spinlock_t irq_lock;
 114         u32 irqmask;
 115
 116         struct sk_buff *beacons[8];
 117         u8 beacon_mask;
 118         u8 beacon_data_mask;
 119
 120         u32 rev;
 121         u32 rxfilter;
 122
 123         u16 chainmask;
 124
 125         struct mt76x2_calibration cal;
 126
 127         s8 target_power;
 128         s8 target_power_delta[2];
 129         struct mt76_rate_power rate_power;
 130         bool enable_tpc;
 131
 132         u8 coverage_class;
 133         u8 slottime;
 134
 135         struct mt76x2_dfs_pattern_detector dfs_pd;
 136 };
 137
 138 struct mt76x2_vif {
 139         u8 idx;
 140
 141         struct mt76_wcid group_wcid;
 142 };
 143
 144 struct mt76x2_sta {
 145         struct mt76_wcid wcid; /* must be first */
 146
 147         struct mt76x2_vif *vif;
 148         struct mt76x2_tx_status status;
 149         int n_frames;
 150 };
 151
 152 static inline bool is_mt7612(struct mt76x2_dev *dev)
 153 {
 154         return (dev->rev >> 16) == 0x7612;
 155 }
 156
 157 void mt76x2_set_irq_mask(struct mt76x2_dev *dev, u32 clear, u32 set);
 158
 159 static inline void mt76x2_irq_enable(struct mt76x2_dev *dev, u32 mask)
 160 {
 161         mt76x2_set_irq_mask(dev, 0, mask);
 162 }
 163
 164 static inline void mt76x2_irq_disable(struct mt76x2_dev *dev, u32 mask)
 165 {
 166         mt76x2_set_irq_mask(dev, mask, 0);
 167 }
 168
 169 extern const struct ieee80211_ops mt76x2_ops;
 170
 171 struct mt76x2_dev *mt76x2_alloc_device(struct device *pdev);
 172 int mt76x2_register_device(struct mt76x2_dev *dev);
 173 void mt76x2_init_debugfs(struct mt76x2_dev *dev);
 174
 175 irqreturn_t mt76x2_irq_handler(int irq, void *dev_instance);
 176 void mt76x2_phy_power_on(struct mt76x2_dev *dev);
 177 int mt76x2_init_hardware(struct mt76x2_dev *dev);
 178 void mt76x2_stop_hardware(struct mt76x2_dev *dev);
 179 int mt76x2_eeprom_init(struct mt76x2_dev *dev);
 180 int mt76x2_apply_calibration_data(struct mt76x2_dev *dev, int channel);
 181 void mt76x2_set_tx_ackto(struct mt76x2_dev *dev);
 182
 183 int mt76x2_phy_start(struct mt76x2_dev *dev);
 184 int mt76x2_phy_set_channel(struct mt76x2_dev *dev,
 185                          struct cfg80211_chan_def *chandef);
 186 int mt76x2_phy_get_rssi(struct mt76x2_dev *dev, s8 rssi, int chain);
 187 void mt76x2_phy_calibrate(struct work_struct *work);
 188 void mt76x2_phy_set_txpower(struct mt76x2_dev *dev);
 189
 190 int mt76x2_mcu_init(struct mt76x2_dev *dev);
 191 int mt76x2_mcu_set_channel(struct mt76x2_dev *dev, u8 channel, u8 bw,
 192                            u8 bw_index, bool scan);
 193 int mt76x2_mcu_set_radio_state(struct mt76x2_dev *dev, bool on);
 194 int mt76x2_mcu_load_cr(struct mt76x2_dev *dev, u8 type, u8 temp_level,
 195                        u8 channel);
 196 int mt76x2_mcu_cleanup(struct mt76x2_dev *dev);
 197
 198 int mt76x2_dma_init(struct mt76x2_dev *dev);
 199 void mt76x2_dma_cleanup(struct mt76x2_dev *dev);
 200
 201 void mt76x2_cleanup(struct mt76x2_dev *dev);
 202
 203 int mt76x2_tx_queue_mcu(struct mt76x2_dev *dev, enum mt76_txq_id qid,
 204                         struct sk_buff *skb, int cmd, int seq);
 205 void mt76x2_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
 206                struct sk_buff *skb);
 207 void mt76x2_tx_complete(struct mt76x2_dev *dev, struct sk_buff *skb);
 208 int mt76x2_tx_prepare_skb(struct mt76_dev *mdev, void *txwi,
 209                           struct sk_buff *skb, struct mt76_queue *q,
 210                           struct mt76_wcid *wcid, struct ieee80211_sta *sta,
 211                           u32 *tx_info);
 212 void mt76x2_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue *q,
 213                             struct mt76_queue_entry *e, bool flush);
 214
 215 void mt76x2_pre_tbtt_tasklet(unsigned long arg);
 216
 217 void mt76x2_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
 218 void mt76x2_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
 219                          struct sk_buff *skb);
 220
 221 void mt76x2_sta_ps(struct mt76_dev *dev, struct ieee80211_sta *sta, bool ps);
 222
 223 void mt76x2_update_channel(struct mt76_dev *mdev);
 224
 225 s8 mt76x2_tx_get_max_txpwr_adj(struct mt76x2_dev *dev,
 226                                const struct ieee80211_tx_rate *rate);
 227 s8 mt76x2_tx_get_txpwr_adj(struct mt76x2_dev *dev, s8 txpwr, s8 max_txpwr_adj);
 228 void mt76x2_tx_set_txpwr_auto(struct mt76x2_dev *dev, s8 txpwr);
 229
 230 #endif