1 /* @file mwifiex_pcie.h
3 * @brief This file contains definitions for PCI-E interface.
6 * Copyright (C) 2011, Marvell International Ltd.
8 * This software file (the "File") is distributed by Marvell International
9 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
10 * (the "License"). You may use, redistribute and/or modify this File in
11 * accordance with the terms and conditions of the License, a copy of which
12 * is available by writing to the Free Software Foundation, Inc.,
13 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
14 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
16 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
18 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
19 * this warranty disclaimer.
22 #ifndef _MWIFIEX_PCIE_H
23 #define _MWIFIEX_PCIE_H
25 #include <linux/pci.h>
26 #include <linux/pcieport_if.h>
27 #include <linux/interrupt.h>
31 #define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin"
33 /* Constants for Buffer Descriptor (BD) rings */
34 #define MWIFIEX_MAX_TXRX_BD 0x20
35 #define MWIFIEX_TXBD_MASK 0x3F
36 #define MWIFIEX_RXBD_MASK 0x3F
38 #define MWIFIEX_MAX_EVT_BD 0x04
39 #define MWIFIEX_EVTBD_MASK 0x07
41 /* PCIE INTERNAL REGISTERS */
42 #define PCIE_SCRATCH_0_REG 0xC10
43 #define PCIE_SCRATCH_1_REG 0xC14
44 #define PCIE_CPU_INT_EVENT 0xC18
45 #define PCIE_CPU_INT_STATUS 0xC1C
46 #define PCIE_HOST_INT_STATUS 0xC30
47 #define PCIE_HOST_INT_MASK 0xC34
48 #define PCIE_HOST_INT_STATUS_MASK 0xC3C
49 #define PCIE_SCRATCH_2_REG 0xC40
50 #define PCIE_SCRATCH_3_REG 0xC44
51 #define PCIE_SCRATCH_4_REG 0xCD0
52 #define PCIE_SCRATCH_5_REG 0xCD4
53 #define PCIE_SCRATCH_6_REG 0xCD8
54 #define PCIE_SCRATCH_7_REG 0xCDC
55 #define PCIE_SCRATCH_8_REG 0xCE0
56 #define PCIE_SCRATCH_9_REG 0xCE4
57 #define PCIE_SCRATCH_10_REG 0xCE8
58 #define PCIE_SCRATCH_11_REG 0xCEC
59 #define PCIE_SCRATCH_12_REG 0xCF0
61 #define CPU_INTR_DNLD_RDY BIT(0)
62 #define CPU_INTR_DOOR_BELL BIT(1)
63 #define CPU_INTR_SLEEP_CFM_DONE BIT(2)
64 #define CPU_INTR_RESET BIT(3)
66 #define HOST_INTR_DNLD_DONE BIT(0)
67 #define HOST_INTR_UPLD_RDY BIT(1)
68 #define HOST_INTR_CMD_DONE BIT(2)
69 #define HOST_INTR_EVENT_RDY BIT(3)
70 #define HOST_INTR_MASK (HOST_INTR_DNLD_DONE | \
71 HOST_INTR_UPLD_RDY | \
72 HOST_INTR_CMD_DONE | \
75 #define MWIFIEX_BD_FLAG_ROLLOVER_IND BIT(7)
76 #define MWIFIEX_BD_FLAG_FIRST_DESC BIT(0)
77 #define MWIFIEX_BD_FLAG_LAST_DESC BIT(1)
79 /* Max retry number of command write */
80 #define MAX_WRITE_IOMEM_RETRY 2
81 /* Define PCIE block size for firmware download */
82 #define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD 256
83 /* FW awake cookie after FW ready */
84 #define FW_AWAKE_COOKIE (0xAA55AA55)
86 struct mwifiex_pcie_card_reg
{
107 u32 evt_rollover_ind
;
112 u32 ring_tx_start_ptr
;
116 static const struct mwifiex_pcie_card_reg mwifiex_reg_8766
= {
117 .cmd_addr_lo
= PCIE_SCRATCH_0_REG
,
118 .cmd_addr_hi
= PCIE_SCRATCH_1_REG
,
119 .cmd_size
= PCIE_SCRATCH_2_REG
,
120 .fw_status
= PCIE_SCRATCH_3_REG
,
121 .cmdrsp_addr_lo
= PCIE_SCRATCH_4_REG
,
122 .cmdrsp_addr_hi
= PCIE_SCRATCH_5_REG
,
123 .tx_rdptr
= PCIE_SCRATCH_6_REG
,
124 .tx_wrptr
= PCIE_SCRATCH_7_REG
,
125 .rx_rdptr
= PCIE_SCRATCH_8_REG
,
126 .rx_wrptr
= PCIE_SCRATCH_9_REG
,
127 .evt_rdptr
= PCIE_SCRATCH_10_REG
,
128 .evt_wrptr
= PCIE_SCRATCH_11_REG
,
129 .drv_rdy
= PCIE_SCRATCH_12_REG
,
131 .tx_mask
= MWIFIEX_TXBD_MASK
,
133 .rx_mask
= MWIFIEX_RXBD_MASK
,
135 .tx_rollover_ind
= MWIFIEX_BD_FLAG_ROLLOVER_IND
,
136 .rx_rollover_ind
= MWIFIEX_BD_FLAG_ROLLOVER_IND
,
137 .evt_rollover_ind
= MWIFIEX_BD_FLAG_ROLLOVER_IND
,
140 .ring_flag_xs_sop
= 0,
141 .ring_flag_xs_eop
= 0,
142 .ring_tx_start_ptr
= 0,
146 struct mwifiex_pcie_device
{
147 const char *firmware
;
148 const struct mwifiex_pcie_card_reg
*reg
;
152 static const struct mwifiex_pcie_device mwifiex_pcie8766
= {
153 .firmware
= PCIE8766_DEFAULT_FW_NAME
,
154 .reg
= &mwifiex_reg_8766
,
155 .blksz_fw_dl
= MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD
,
158 struct mwifiex_pcie_buf_desc
{
164 struct pcie_service_card
{
166 struct mwifiex_adapter
*adapter
;
167 struct mwifiex_pcie_device pcie
;
174 dma_addr_t txbd_ring_pbase
;
175 struct mwifiex_pcie_buf_desc
*txbd_ring
[MWIFIEX_MAX_TXRX_BD
];
176 struct sk_buff
*tx_buf_list
[MWIFIEX_MAX_TXRX_BD
];
182 dma_addr_t rxbd_ring_pbase
;
183 struct mwifiex_pcie_buf_desc
*rxbd_ring
[MWIFIEX_MAX_TXRX_BD
];
184 struct sk_buff
*rx_buf_list
[MWIFIEX_MAX_TXRX_BD
];
189 u8
*evtbd_ring_vbase
;
190 dma_addr_t evtbd_ring_pbase
;
191 struct mwifiex_pcie_buf_desc
*evtbd_ring
[MWIFIEX_MAX_EVT_BD
];
192 struct sk_buff
*evt_buf_list
[MWIFIEX_MAX_EVT_BD
];
194 struct sk_buff
*cmd_buf
;
195 struct sk_buff
*cmdrsp_buf
;
196 u8
*sleep_cookie_vbase
;
197 dma_addr_t sleep_cookie_pbase
;
198 void __iomem
*pci_mmap
;
199 void __iomem
*pci_mmap1
;
203 mwifiex_pcie_txbd_empty(struct pcie_service_card
*card
, u32 rdptr
)
205 const struct mwifiex_pcie_card_reg
*reg
= card
->pcie
.reg
;
207 if (((card
->txbd_wrptr
& reg
->tx_mask
) == (rdptr
& reg
->tx_mask
)) &&
208 ((card
->txbd_wrptr
& reg
->tx_rollover_ind
) !=
209 (rdptr
& reg
->tx_rollover_ind
)))
216 mwifiex_pcie_txbd_not_full(struct pcie_service_card
*card
)
218 const struct mwifiex_pcie_card_reg
*reg
= card
->pcie
.reg
;
220 if (((card
->txbd_wrptr
& reg
->tx_mask
) !=
221 (card
->txbd_rdptr
& reg
->tx_mask
)) ||
222 ((card
->txbd_wrptr
& reg
->tx_rollover_ind
) !=
223 (card
->txbd_rdptr
& reg
->tx_rollover_ind
)))
228 #endif /* _MWIFIEX_PCIE_H */