drivers/net/wireless/mwifiex/sdio.h

   1 /*
   2  * Marvell Wireless LAN device driver: SDIO specific definitions
   3  *
   4  * Copyright (C) 2011-2014, Marvell International Ltd.
   5  *
   6  * This software file (the "File") is distributed by Marvell International
   7  * Ltd. under the terms of the GNU General Public License Version 2, June 1991
   8  * (the "License").  You may use, redistribute and/or modify this File in
   9  * accordance with the terms and conditions of the License, a copy of which
  10  * is available by writing to the Free Software Foundation, Inc.,
  11  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
  12  * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
  13  *
  14  * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
  17  * this warranty disclaimer.
  18  */
  19
  20 #ifndef _MWIFIEX_SDIO_H
  21 #define _MWIFIEX_SDIO_H
  22
  23
  24 #include <linux/mmc/sdio.h>
  25 #include <linux/mmc/sdio_ids.h>
  26 #include <linux/mmc/sdio_func.h>
  27 #include <linux/mmc/card.h>
  28 #include <linux/mmc/host.h>
  29
  30 #include "main.h"
  31
  32 #define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
  33 #define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
  34 #define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
  35 #define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"
  36
  37 #define BLOCK_MODE      1
  38 #define BYTE_MODE       0
  39
  40 #define REG_PORT                        0
  41
  42 #define MWIFIEX_SDIO_IO_PORT_MASK               0xfffff
  43
  44 #define MWIFIEX_SDIO_BYTE_MODE_MASK     0x80000000
  45
  46 #define SDIO_MPA_ADDR_BASE              0x1000
  47 #define CTRL_PORT                       0
  48 #define CTRL_PORT_MASK                  0x0001
  49
  50 #define CMD_PORT_UPLD_INT_MASK          (0x1U<<6)
  51 #define CMD_PORT_DNLD_INT_MASK          (0x1U<<7)
  52 #define HOST_TERM_CMD53                 (0x1U << 2)
  53 #define REG_PORT                        0
  54 #define MEM_PORT                        0x10000
  55 #define CMD_RD_LEN_0                    0xB4
  56 #define CMD_RD_LEN_1                    0xB5
  57 #define CARD_CONFIG_2_1_REG             0xCD
  58 #define CMD53_NEW_MODE                  (0x1U << 0)
  59 #define CMD_CONFIG_0                    0xB8
  60 #define CMD_PORT_RD_LEN_EN              (0x1U << 2)
  61 #define CMD_CONFIG_1                    0xB9
  62 #define CMD_PORT_AUTO_EN                (0x1U << 0)
  63 #define CMD_PORT_SLCT                   0x8000
  64 #define UP_LD_CMD_PORT_HOST_INT_STATUS  (0x40U)
  65 #define DN_LD_CMD_PORT_HOST_INT_STATUS  (0x80U)
  66
  67 #define MWIFIEX_MP_AGGR_BUF_SIZE_16K    (16384)
  68 #define MWIFIEX_MP_AGGR_BUF_SIZE_32K    (32768)
  69
  70 /* Misc. Config Register : Auto Re-enable interrupts */
  71 #define AUTO_RE_ENABLE_INT              BIT(4)
  72
  73 /* Host Control Registers */
  74 /* Host Control Registers : I/O port 0 */
  75 #define IO_PORT_0_REG                   0x78
  76 /* Host Control Registers : I/O port 1 */
  77 #define IO_PORT_1_REG                   0x79
  78 /* Host Control Registers : I/O port 2 */
  79 #define IO_PORT_2_REG                   0x7A
  80
  81 /* Host Control Registers : Configuration */
  82 #define CONFIGURATION_REG               0x00
  83 /* Host Control Registers : Host power up */
  84 #define HOST_POWER_UP                   (0x1U << 1)
  85
  86 /* Host Control Registers : Host interrupt mask */
  87 #define HOST_INT_MASK_REG               0x02
  88 /* Host Control Registers : Upload host interrupt mask */
  89 #define UP_LD_HOST_INT_MASK             (0x1U)
  90 /* Host Control Registers : Download host interrupt mask */
  91 #define DN_LD_HOST_INT_MASK             (0x2U)
  92
  93 /* Host Control Registers : Host interrupt status */
  94 #define HOST_INTSTATUS_REG              0x03
  95 /* Host Control Registers : Upload host interrupt status */
  96 #define UP_LD_HOST_INT_STATUS           (0x1U)
  97 /* Host Control Registers : Download host interrupt status */
  98 #define DN_LD_HOST_INT_STATUS           (0x2U)
  99
 100 /* Host Control Registers : Host interrupt RSR */
 101 #define HOST_INT_RSR_REG                0x01
 102
 103 /* Host Control Registers : Host interrupt status */
 104 #define HOST_INT_STATUS_REG             0x28
 105
 106 /* Card Control Registers : Card I/O ready */
 107 #define CARD_IO_READY                   (0x1U << 3)
 108 /* Card Control Registers : Download card ready */
 109 #define DN_LD_CARD_RDY                  (0x1U << 0)
 110
 111 /* Max retry number of CMD53 write */
 112 #define MAX_WRITE_IOMEM_RETRY           2
 113
 114 /* SDIO Tx aggregation in progress ? */
 115 #define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
 116
 117 /* SDIO Tx aggregation buffer room for next packet ? */
 118 #define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len)        \
 119                                                 <= a->mpa_tx.buf_size)
 120
 121 /* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
 122 #define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do {              \
 123         memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len],                      \
 124                         payload, pkt_len);                              \
 125         a->mpa_tx.buf_len += pkt_len;                                   \
 126         if (!a->mpa_tx.pkt_cnt)                                         \
 127                 a->mpa_tx.start_port = port;                            \
 128         if (a->mpa_tx.start_port <= port)                               \
 129                 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt));            \
 130         else                                                            \
 131                 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+            \
 132                                                 (a->max_ports - \
 133                                                 a->mp_end_port)));      \
 134         a->mpa_tx.pkt_cnt++;                                            \
 135 } while (0)
 136
 137 /* SDIO Tx aggregation limit ? */
 138 #define MP_TX_AGGR_PKT_LIMIT_REACHED(a)                                 \
 139                         (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
 140
 141 /* Reset SDIO Tx aggregation buffer parameters */
 142 #define MP_TX_AGGR_BUF_RESET(a) do {                                    \
 143         a->mpa_tx.pkt_cnt = 0;                                          \
 144         a->mpa_tx.buf_len = 0;                                          \
 145         a->mpa_tx.ports = 0;                                            \
 146         a->mpa_tx.start_port = 0;                                       \
 147 } while (0)
 148
 149 /* SDIO Rx aggregation limit ? */
 150 #define MP_RX_AGGR_PKT_LIMIT_REACHED(a)                                 \
 151                         (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
 152
 153 /* SDIO Rx aggregation in progress ? */
 154 #define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
 155
 156 /* SDIO Rx aggregation buffer room for next packet ? */
 157 #define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len)                              \
 158                         ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
 159
 160 /* Reset SDIO Rx aggregation buffer parameters */
 161 #define MP_RX_AGGR_BUF_RESET(a) do {                                    \
 162         a->mpa_rx.pkt_cnt = 0;                                          \
 163         a->mpa_rx.buf_len = 0;                                          \
 164         a->mpa_rx.ports = 0;                                            \
 165         a->mpa_rx.start_port = 0;                                       \
 166 } while (0)
 167
 168 /* data structure for SDIO MPA TX */
 169 struct mwifiex_sdio_mpa_tx {
 170         /* multiport tx aggregation buffer pointer */
 171         u8 *buf;
 172         u32 buf_len;
 173         u32 pkt_cnt;
 174         u32 ports;
 175         u16 start_port;
 176         u8 enabled;
 177         u32 buf_size;
 178         u32 pkt_aggr_limit;
 179 };
 180
 181 struct mwifiex_sdio_mpa_rx {
 182         u8 *buf;
 183         u32 buf_len;
 184         u32 pkt_cnt;
 185         u32 ports;
 186         u16 start_port;
 187
 188         struct sk_buff **skb_arr;
 189         u32 *len_arr;
 190
 191         u8 enabled;
 192         u32 buf_size;
 193         u32 pkt_aggr_limit;
 194 };
 195
 196 int mwifiex_bus_register(void);
 197 void mwifiex_bus_unregister(void);
 198
 199 struct mwifiex_sdio_card_reg {
 200         u8 start_rd_port;
 201         u8 start_wr_port;
 202         u8 base_0_reg;
 203         u8 base_1_reg;
 204         u8 poll_reg;
 205         u8 host_int_enable;
 206         u8 status_reg_0;
 207         u8 status_reg_1;
 208         u8 sdio_int_mask;
 209         u32 data_port_mask;
 210         u8 max_mp_regs;
 211         u8 rd_bitmap_l;
 212         u8 rd_bitmap_u;
 213         u8 rd_bitmap_1l;
 214         u8 rd_bitmap_1u;
 215         u8 wr_bitmap_l;
 216         u8 wr_bitmap_u;
 217         u8 wr_bitmap_1l;
 218         u8 wr_bitmap_1u;
 219         u8 rd_len_p0_l;
 220         u8 rd_len_p0_u;
 221         u8 card_misc_cfg_reg;
 222         u8 fw_dump_ctrl;
 223         u8 fw_dump_start;
 224         u8 fw_dump_end;
 225 };
 226
 227 struct sdio_mmc_card {
 228         struct sdio_func *func;
 229         struct mwifiex_adapter *adapter;
 230
 231         const char *firmware;
 232         const struct mwifiex_sdio_card_reg *reg;
 233         u8 max_ports;
 234         u8 mp_agg_pkt_limit;
 235         bool supports_sdio_new_mode;
 236         bool has_control_mask;
 237         bool supports_fw_dump;
 238         u16 tx_buf_size;
 239         u32 mp_tx_agg_buf_size;
 240         u32 mp_rx_agg_buf_size;
 241
 242         u32 mp_rd_bitmap;
 243         u32 mp_wr_bitmap;
 244
 245         u16 mp_end_port;
 246         u32 mp_data_port_mask;
 247
 248         u8 curr_rd_port;
 249         u8 curr_wr_port;
 250
 251         u8 *mp_regs;
 252
 253         struct mwifiex_sdio_mpa_tx mpa_tx;
 254         struct mwifiex_sdio_mpa_rx mpa_rx;
 255 };
 256
 257 struct mwifiex_sdio_device {
 258         const char *firmware;
 259         const struct mwifiex_sdio_card_reg *reg;
 260         u8 max_ports;
 261         u8 mp_agg_pkt_limit;
 262         bool supports_sdio_new_mode;
 263         bool has_control_mask;
 264         bool supports_fw_dump;
 265         u16 tx_buf_size;
 266         u32 mp_tx_agg_buf_size;
 267         u32 mp_rx_agg_buf_size;
 268 };
 269
 270 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = {
 271         .start_rd_port = 1,
 272         .start_wr_port = 1,
 273         .base_0_reg = 0x0040,
 274         .base_1_reg = 0x0041,
 275         .poll_reg = 0x30,
 276         .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK,
 277         .status_reg_0 = 0x60,
 278         .status_reg_1 = 0x61,
 279         .sdio_int_mask = 0x3f,
 280         .data_port_mask = 0x0000fffe,
 281         .max_mp_regs = 64,
 282         .rd_bitmap_l = 0x04,
 283         .rd_bitmap_u = 0x05,
 284         .wr_bitmap_l = 0x06,
 285         .wr_bitmap_u = 0x07,
 286         .rd_len_p0_l = 0x08,
 287         .rd_len_p0_u = 0x09,
 288         .card_misc_cfg_reg = 0x6c,
 289 };
 290
 291 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = {
 292         .start_rd_port = 0,
 293         .start_wr_port = 0,
 294         .base_0_reg = 0x60,
 295         .base_1_reg = 0x61,
 296         .poll_reg = 0x50,
 297         .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
 298                         CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
 299         .status_reg_0 = 0xc0,
 300         .status_reg_1 = 0xc1,
 301         .sdio_int_mask = 0xff,
 302         .data_port_mask = 0xffffffff,
 303         .max_mp_regs = 184,
 304         .rd_bitmap_l = 0x04,
 305         .rd_bitmap_u = 0x05,
 306         .rd_bitmap_1l = 0x06,
 307         .rd_bitmap_1u = 0x07,
 308         .wr_bitmap_l = 0x08,
 309         .wr_bitmap_u = 0x09,
 310         .wr_bitmap_1l = 0x0a,
 311         .wr_bitmap_1u = 0x0b,
 312         .rd_len_p0_l = 0x0c,
 313         .rd_len_p0_u = 0x0d,
 314         .card_misc_cfg_reg = 0xcc,
 315         .fw_dump_ctrl = 0xe2,
 316         .fw_dump_start = 0xe3,
 317         .fw_dump_end = 0xea,
 318 };
 319
 320 static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = {
 321         .firmware = SD8786_DEFAULT_FW_NAME,
 322         .reg = &mwifiex_reg_sd87xx,
 323         .max_ports = 16,
 324         .mp_agg_pkt_limit = 8,
 325         .supports_sdio_new_mode = false,
 326         .has_control_mask = true,
 327         .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
 328         .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
 329         .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
 330         .supports_fw_dump = false,
 331 };
 332
 333 static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = {
 334         .firmware = SD8787_DEFAULT_FW_NAME,
 335         .reg = &mwifiex_reg_sd87xx,
 336         .max_ports = 16,
 337         .mp_agg_pkt_limit = 8,
 338         .supports_sdio_new_mode = false,
 339         .has_control_mask = true,
 340         .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
 341         .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
 342         .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
 343         .supports_fw_dump = false,
 344 };
 345
 346 static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = {
 347         .firmware = SD8797_DEFAULT_FW_NAME,
 348         .reg = &mwifiex_reg_sd87xx,
 349         .max_ports = 16,
 350         .mp_agg_pkt_limit = 8,
 351         .supports_sdio_new_mode = false,
 352         .has_control_mask = true,
 353         .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
 354         .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
 355         .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
 356         .supports_fw_dump = false,
 357 };
 358
 359 static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = {
 360         .firmware = SD8897_DEFAULT_FW_NAME,
 361         .reg = &mwifiex_reg_sd8897,
 362         .max_ports = 32,
 363         .mp_agg_pkt_limit = 16,
 364         .supports_sdio_new_mode = true,
 365         .has_control_mask = false,
 366         .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
 367         .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
 368         .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
 369         .supports_fw_dump = true,
 370 };
 371
 372 /*
 373  * .cmdrsp_complete handler
 374  */
 375 static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
 376                                                struct sk_buff *skb)
 377 {
 378         dev_kfree_skb_any(skb);
 379         return 0;
 380 }
 381
 382 /*
 383  * .event_complete handler
 384  */
 385 static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
 386                                               struct sk_buff *skb)
 387 {
 388         dev_kfree_skb_any(skb);
 389         return 0;
 390 }
 391
 392 static inline bool
 393 mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card)
 394 {
 395         u8 tmp;
 396
 397         if (card->curr_rd_port < card->mpa_rx.start_port) {
 398                 if (card->supports_sdio_new_mode)
 399                         tmp = card->mp_end_port >> 1;
 400                 else
 401                         tmp = card->mp_agg_pkt_limit;
 402
 403                 if (((card->max_ports - card->mpa_rx.start_port) +
 404                     card->curr_rd_port) >= tmp)
 405                         return true;
 406         }
 407
 408         if (!card->supports_sdio_new_mode)
 409                 return false;
 410
 411         if ((card->curr_rd_port - card->mpa_rx.start_port) >=
 412             (card->mp_end_port >> 1))
 413                 return true;
 414
 415         return false;
 416 }
 417
 418 static inline bool
 419 mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card)
 420 {
 421         u16 tmp;
 422
 423         if (card->curr_wr_port < card->mpa_tx.start_port) {
 424                 if (card->supports_sdio_new_mode)
 425                         tmp = card->mp_end_port >> 1;
 426                 else
 427                         tmp = card->mp_agg_pkt_limit;
 428
 429                 if (((card->max_ports - card->mpa_tx.start_port) +
 430                     card->curr_wr_port) >= tmp)
 431                         return true;
 432         }
 433
 434         if (!card->supports_sdio_new_mode)
 435                 return false;
 436
 437         if ((card->curr_wr_port - card->mpa_tx.start_port) >=
 438             (card->mp_end_port >> 1))
 439                 return true;
 440
 441         return false;
 442 }
 443
 444 /* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
 445 static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card,
 446                                     struct sk_buff *skb, u8 port)
 447 {
 448         card->mpa_rx.buf_len += skb->len;
 449
 450         if (!card->mpa_rx.pkt_cnt)
 451                 card->mpa_rx.start_port = port;
 452
 453         if (card->supports_sdio_new_mode) {
 454                 card->mpa_rx.ports |= (1 << port);
 455         } else {
 456                 if (card->mpa_rx.start_port <= port)
 457                         card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt);
 458                 else
 459                         card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1);
 460         }
 461         card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = skb;
 462         card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = skb->len;
 463         card->mpa_rx.pkt_cnt++;
 464 }
 465 #endif /* _MWIFIEX_SDIO_H */