]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/net/wireless/mwl8k.c
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ALSA: usbmixer - use MAX_ID_ELEMS where possible
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / mwl8k.c
1 /*
2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
4 *
5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/spinlock.h>
17 #include <linux/list.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/completion.h>
21 #include <linux/etherdevice.h>
22 #include <net/mac80211.h>
23 #include <linux/moduleparam.h>
24 #include <linux/firmware.h>
25 #include <linux/workqueue.h>
26
27 #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28 #define MWL8K_NAME KBUILD_MODNAME
29 #define MWL8K_VERSION "0.10"
30
31 /* Register definitions */
32 #define MWL8K_HIU_GEN_PTR 0x00000c10
33 #define MWL8K_MODE_STA 0x0000005a
34 #define MWL8K_MODE_AP 0x000000a5
35 #define MWL8K_HIU_INT_CODE 0x00000c14
36 #define MWL8K_FWSTA_READY 0xf0f1f2f4
37 #define MWL8K_FWAP_READY 0xf1f2f4a5
38 #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
39 #define MWL8K_HIU_SCRATCH 0x00000c40
40
41 /* Host->device communications */
42 #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43 #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44 #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45 #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46 #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
47 #define MWL8K_H2A_INT_DUMMY (1 << 20)
48 #define MWL8K_H2A_INT_RESET (1 << 15)
49 #define MWL8K_H2A_INT_DOORBELL (1 << 1)
50 #define MWL8K_H2A_INT_PPA_READY (1 << 0)
51
52 /* Device->host communications */
53 #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54 #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55 #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56 #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57 #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
58 #define MWL8K_A2H_INT_DUMMY (1 << 20)
59 #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60 #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61 #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62 #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63 #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64 #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65 #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66 #define MWL8K_A2H_INT_RX_READY (1 << 1)
67 #define MWL8K_A2H_INT_TX_DONE (1 << 0)
68
69 #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
80 #define MWL8K_RX_QUEUES 1
81 #define MWL8K_TX_QUEUES 4
82
83 struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
88 __le16 *qos);
89 };
90
91 struct mwl8k_device_info {
92 char *part_name;
93 char *helper_image;
94 char *fw_image;
95 struct rxd_ops *rxd_ops;
96 u16 modes;
97 };
98
99 struct mwl8k_rx_queue {
100 int rxd_count;
101
102 /* hw receives here */
103 int head;
104
105 /* refill descs here */
106 int tail;
107
108 void *rxd;
109 dma_addr_t rxd_dma;
110 struct {
111 struct sk_buff *skb;
112 DECLARE_PCI_UNMAP_ADDR(dma)
113 } *buf;
114 };
115
116 struct mwl8k_tx_queue {
117 /* hw transmits here */
118 int head;
119
120 /* sw appends here */
121 int tail;
122
123 struct ieee80211_tx_queue_stats stats;
124 struct mwl8k_tx_desc *txd;
125 dma_addr_t txd_dma;
126 struct sk_buff **skb;
127 };
128
129 /* Pointers to the firmware data and meta information about it. */
130 struct mwl8k_firmware {
131 /* Boot helper code */
132 struct firmware *helper;
133
134 /* Microcode */
135 struct firmware *ucode;
136 };
137
138 struct mwl8k_priv {
139 void __iomem *sram;
140 void __iomem *regs;
141 struct ieee80211_hw *hw;
142
143 struct pci_dev *pdev;
144
145 struct mwl8k_device_info *device_info;
146 bool ap_fw;
147 struct rxd_ops *rxd_ops;
148
149 /* firmware files and meta data */
150 struct mwl8k_firmware fw;
151
152 /* firmware access */
153 struct mutex fw_mutex;
154 struct task_struct *fw_mutex_owner;
155 int fw_mutex_depth;
156 struct completion *hostcmd_wait;
157
158 /* lock held over TX and TX reap */
159 spinlock_t tx_lock;
160
161 /* TX quiesce completion, protected by fw_mutex and tx_lock */
162 struct completion *tx_wait;
163
164 struct ieee80211_vif *vif;
165
166 struct ieee80211_channel *current_channel;
167
168 /* power management status cookie from firmware */
169 u32 *cookie;
170 dma_addr_t cookie_dma;
171
172 u16 num_mcaddrs;
173 u8 hw_rev;
174 u32 fw_rev;
175
176 /*
177 * Running count of TX packets in flight, to avoid
178 * iterating over the transmit rings each time.
179 */
180 int pending_tx_pkts;
181
182 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
183 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
184
185 /* PHY parameters */
186 struct ieee80211_supported_band band;
187 struct ieee80211_channel channels[14];
188 struct ieee80211_rate rates[14];
189
190 bool radio_on;
191 bool radio_short_preamble;
192 bool sniffer_enabled;
193 bool wmm_enabled;
194
195 /* XXX need to convert this to handle multiple interfaces */
196 bool capture_beacon;
197 u8 capture_bssid[ETH_ALEN];
198 struct sk_buff *beacon_skb;
199
200 /*
201 * This FJ worker has to be global as it is scheduled from the
202 * RX handler. At this point we don't know which interface it
203 * belongs to until the list of bssids waiting to complete join
204 * is checked.
205 */
206 struct work_struct finalize_join_worker;
207
208 /* Tasklet to reclaim TX descriptors and buffers after tx */
209 struct tasklet_struct tx_reclaim_task;
210 };
211
212 /* Per interface specific private data */
213 struct mwl8k_vif {
214 /* backpointer to parent config block */
215 struct mwl8k_priv *priv;
216
217 /* BSS config of AP or IBSS from mac80211*/
218 struct ieee80211_bss_conf bss_info;
219
220 /* BSSID of AP or IBSS */
221 u8 bssid[ETH_ALEN];
222 u8 mac_addr[ETH_ALEN];
223
224 /* Index into station database.Returned by update_sta_db call */
225 u8 peer_id;
226
227 /* Non AMPDU sequence number assigned by driver */
228 u16 seqno;
229 };
230
231 #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
232
233 static const struct ieee80211_channel mwl8k_channels[] = {
234 { .center_freq = 2412, .hw_value = 1, },
235 { .center_freq = 2417, .hw_value = 2, },
236 { .center_freq = 2422, .hw_value = 3, },
237 { .center_freq = 2427, .hw_value = 4, },
238 { .center_freq = 2432, .hw_value = 5, },
239 { .center_freq = 2437, .hw_value = 6, },
240 { .center_freq = 2442, .hw_value = 7, },
241 { .center_freq = 2447, .hw_value = 8, },
242 { .center_freq = 2452, .hw_value = 9, },
243 { .center_freq = 2457, .hw_value = 10, },
244 { .center_freq = 2462, .hw_value = 11, },
245 };
246
247 static const struct ieee80211_rate mwl8k_rates[] = {
248 { .bitrate = 10, .hw_value = 2, },
249 { .bitrate = 20, .hw_value = 4, },
250 { .bitrate = 55, .hw_value = 11, },
251 { .bitrate = 110, .hw_value = 22, },
252 { .bitrate = 220, .hw_value = 44, },
253 { .bitrate = 60, .hw_value = 12, },
254 { .bitrate = 90, .hw_value = 18, },
255 { .bitrate = 120, .hw_value = 24, },
256 { .bitrate = 180, .hw_value = 36, },
257 { .bitrate = 240, .hw_value = 48, },
258 { .bitrate = 360, .hw_value = 72, },
259 { .bitrate = 480, .hw_value = 96, },
260 { .bitrate = 540, .hw_value = 108, },
261 { .bitrate = 720, .hw_value = 144, },
262 };
263
264 static const u8 mwl8k_rateids[12] = {
265 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108,
266 };
267
268 /* Set or get info from Firmware */
269 #define MWL8K_CMD_SET 0x0001
270 #define MWL8K_CMD_GET 0x0000
271
272 /* Firmware command codes */
273 #define MWL8K_CMD_CODE_DNLD 0x0001
274 #define MWL8K_CMD_GET_HW_SPEC 0x0003
275 #define MWL8K_CMD_SET_HW_SPEC 0x0004
276 #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
277 #define MWL8K_CMD_GET_STAT 0x0014
278 #define MWL8K_CMD_RADIO_CONTROL 0x001c
279 #define MWL8K_CMD_RF_TX_POWER 0x001e
280 #define MWL8K_CMD_RF_ANTENNA 0x0020
281 #define MWL8K_CMD_SET_PRE_SCAN 0x0107
282 #define MWL8K_CMD_SET_POST_SCAN 0x0108
283 #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
284 #define MWL8K_CMD_SET_AID 0x010d
285 #define MWL8K_CMD_SET_RATE 0x0110
286 #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
287 #define MWL8K_CMD_RTS_THRESHOLD 0x0113
288 #define MWL8K_CMD_SET_SLOT 0x0114
289 #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
290 #define MWL8K_CMD_SET_WMM_MODE 0x0123
291 #define MWL8K_CMD_MIMO_CONFIG 0x0125
292 #define MWL8K_CMD_USE_FIXED_RATE 0x0126
293 #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
294 #define MWL8K_CMD_SET_MAC_ADDR 0x0202
295 #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
296 #define MWL8K_CMD_UPDATE_STADB 0x1123
297
298 static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
299 {
300 #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
301 snprintf(buf, bufsize, "%s", #x);\
302 return buf;\
303 } while (0)
304 switch (cmd & ~0x8000) {
305 MWL8K_CMDNAME(CODE_DNLD);
306 MWL8K_CMDNAME(GET_HW_SPEC);
307 MWL8K_CMDNAME(SET_HW_SPEC);
308 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
309 MWL8K_CMDNAME(GET_STAT);
310 MWL8K_CMDNAME(RADIO_CONTROL);
311 MWL8K_CMDNAME(RF_TX_POWER);
312 MWL8K_CMDNAME(RF_ANTENNA);
313 MWL8K_CMDNAME(SET_PRE_SCAN);
314 MWL8K_CMDNAME(SET_POST_SCAN);
315 MWL8K_CMDNAME(SET_RF_CHANNEL);
316 MWL8K_CMDNAME(SET_AID);
317 MWL8K_CMDNAME(SET_RATE);
318 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
319 MWL8K_CMDNAME(RTS_THRESHOLD);
320 MWL8K_CMDNAME(SET_SLOT);
321 MWL8K_CMDNAME(SET_EDCA_PARAMS);
322 MWL8K_CMDNAME(SET_WMM_MODE);
323 MWL8K_CMDNAME(MIMO_CONFIG);
324 MWL8K_CMDNAME(USE_FIXED_RATE);
325 MWL8K_CMDNAME(ENABLE_SNIFFER);
326 MWL8K_CMDNAME(SET_MAC_ADDR);
327 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
328 MWL8K_CMDNAME(UPDATE_STADB);
329 default:
330 snprintf(buf, bufsize, "0x%x", cmd);
331 }
332 #undef MWL8K_CMDNAME
333
334 return buf;
335 }
336
337 /* Hardware and firmware reset */
338 static void mwl8k_hw_reset(struct mwl8k_priv *priv)
339 {
340 iowrite32(MWL8K_H2A_INT_RESET,
341 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
342 iowrite32(MWL8K_H2A_INT_RESET,
343 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
344 msleep(20);
345 }
346
347 /* Release fw image */
348 static void mwl8k_release_fw(struct firmware **fw)
349 {
350 if (*fw == NULL)
351 return;
352 release_firmware(*fw);
353 *fw = NULL;
354 }
355
356 static void mwl8k_release_firmware(struct mwl8k_priv *priv)
357 {
358 mwl8k_release_fw(&priv->fw.ucode);
359 mwl8k_release_fw(&priv->fw.helper);
360 }
361
362 /* Request fw image */
363 static int mwl8k_request_fw(struct mwl8k_priv *priv,
364 const char *fname, struct firmware **fw)
365 {
366 /* release current image */
367 if (*fw != NULL)
368 mwl8k_release_fw(fw);
369
370 return request_firmware((const struct firmware **)fw,
371 fname, &priv->pdev->dev);
372 }
373
374 static int mwl8k_request_firmware(struct mwl8k_priv *priv)
375 {
376 struct mwl8k_device_info *di = priv->device_info;
377 int rc;
378
379 if (di->helper_image != NULL) {
380 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw.helper);
381 if (rc) {
382 printk(KERN_ERR "%s: Error requesting helper "
383 "firmware file %s\n", pci_name(priv->pdev),
384 di->helper_image);
385 return rc;
386 }
387 }
388
389 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw.ucode);
390 if (rc) {
391 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
392 pci_name(priv->pdev), di->fw_image);
393 mwl8k_release_fw(&priv->fw.helper);
394 return rc;
395 }
396
397 return 0;
398 }
399
400 MODULE_FIRMWARE("mwl8k/helper_8687.fw");
401 MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
402
403 struct mwl8k_cmd_pkt {
404 __le16 code;
405 __le16 length;
406 __le16 seq_num;
407 __le16 result;
408 char payload[0];
409 } __attribute__((packed));
410
411 /*
412 * Firmware loading.
413 */
414 static int
415 mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
416 {
417 void __iomem *regs = priv->regs;
418 dma_addr_t dma_addr;
419 int loops;
420
421 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
422 if (pci_dma_mapping_error(priv->pdev, dma_addr))
423 return -ENOMEM;
424
425 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
426 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
427 iowrite32(MWL8K_H2A_INT_DOORBELL,
428 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
429 iowrite32(MWL8K_H2A_INT_DUMMY,
430 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
431
432 loops = 1000;
433 do {
434 u32 int_code;
435
436 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
437 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
438 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
439 break;
440 }
441
442 cond_resched();
443 udelay(1);
444 } while (--loops);
445
446 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
447
448 return loops ? 0 : -ETIMEDOUT;
449 }
450
451 static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
452 const u8 *data, size_t length)
453 {
454 struct mwl8k_cmd_pkt *cmd;
455 int done;
456 int rc = 0;
457
458 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
459 if (cmd == NULL)
460 return -ENOMEM;
461
462 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
463 cmd->seq_num = 0;
464 cmd->result = 0;
465
466 done = 0;
467 while (length) {
468 int block_size = length > 256 ? 256 : length;
469
470 memcpy(cmd->payload, data + done, block_size);
471 cmd->length = cpu_to_le16(block_size);
472
473 rc = mwl8k_send_fw_load_cmd(priv, cmd,
474 sizeof(*cmd) + block_size);
475 if (rc)
476 break;
477
478 done += block_size;
479 length -= block_size;
480 }
481
482 if (!rc) {
483 cmd->length = 0;
484 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
485 }
486
487 kfree(cmd);
488
489 return rc;
490 }
491
492 static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
493 const u8 *data, size_t length)
494 {
495 unsigned char *buffer;
496 int may_continue, rc = 0;
497 u32 done, prev_block_size;
498
499 buffer = kmalloc(1024, GFP_KERNEL);
500 if (buffer == NULL)
501 return -ENOMEM;
502
503 done = 0;
504 prev_block_size = 0;
505 may_continue = 1000;
506 while (may_continue > 0) {
507 u32 block_size;
508
509 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
510 if (block_size & 1) {
511 block_size &= ~1;
512 may_continue--;
513 } else {
514 done += prev_block_size;
515 length -= prev_block_size;
516 }
517
518 if (block_size > 1024 || block_size > length) {
519 rc = -EOVERFLOW;
520 break;
521 }
522
523 if (length == 0) {
524 rc = 0;
525 break;
526 }
527
528 if (block_size == 0) {
529 rc = -EPROTO;
530 may_continue--;
531 udelay(1);
532 continue;
533 }
534
535 prev_block_size = block_size;
536 memcpy(buffer, data + done, block_size);
537
538 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
539 if (rc)
540 break;
541 }
542
543 if (!rc && length != 0)
544 rc = -EREMOTEIO;
545
546 kfree(buffer);
547
548 return rc;
549 }
550
551 static int mwl8k_load_firmware(struct ieee80211_hw *hw)
552 {
553 struct mwl8k_priv *priv = hw->priv;
554 struct firmware *fw = priv->fw.ucode;
555 struct mwl8k_device_info *di = priv->device_info;
556 int rc;
557 int loops;
558
559 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
560 struct firmware *helper = priv->fw.helper;
561
562 if (helper == NULL) {
563 printk(KERN_ERR "%s: helper image needed but none "
564 "given\n", pci_name(priv->pdev));
565 return -EINVAL;
566 }
567
568 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
569 if (rc) {
570 printk(KERN_ERR "%s: unable to load firmware "
571 "helper image\n", pci_name(priv->pdev));
572 return rc;
573 }
574 msleep(5);
575
576 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
577 } else {
578 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
579 }
580
581 if (rc) {
582 printk(KERN_ERR "%s: unable to load firmware image\n",
583 pci_name(priv->pdev));
584 return rc;
585 }
586
587 if (di->modes & BIT(NL80211_IFTYPE_AP))
588 iowrite32(MWL8K_MODE_AP, priv->regs + MWL8K_HIU_GEN_PTR);
589 else
590 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
591
592 loops = 500000;
593 do {
594 u32 ready_code;
595
596 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
597 if (ready_code == MWL8K_FWAP_READY) {
598 priv->ap_fw = 1;
599 break;
600 } else if (ready_code == MWL8K_FWSTA_READY) {
601 priv->ap_fw = 0;
602 break;
603 }
604
605 cond_resched();
606 udelay(1);
607 } while (--loops);
608
609 return loops ? 0 : -ETIMEDOUT;
610 }
611
612
613 /*
614 * Defines shared between transmission and reception.
615 */
616 /* HT control fields for firmware */
617 struct ewc_ht_info {
618 __le16 control1;
619 __le16 control2;
620 __le16 control3;
621 } __attribute__((packed));
622
623 /* Firmware Station database operations */
624 #define MWL8K_STA_DB_ADD_ENTRY 0
625 #define MWL8K_STA_DB_MODIFY_ENTRY 1
626 #define MWL8K_STA_DB_DEL_ENTRY 2
627 #define MWL8K_STA_DB_FLUSH 3
628
629 /* Peer Entry flags - used to define the type of the peer node */
630 #define MWL8K_PEER_TYPE_ACCESSPOINT 2
631
632 struct peer_capability_info {
633 /* Peer type - AP vs. STA. */
634 __u8 peer_type;
635
636 /* Basic 802.11 capabilities from assoc resp. */
637 __le16 basic_caps;
638
639 /* Set if peer supports 802.11n high throughput (HT). */
640 __u8 ht_support;
641
642 /* Valid if HT is supported. */
643 __le16 ht_caps;
644 __u8 extended_ht_caps;
645 struct ewc_ht_info ewc_info;
646
647 /* Legacy rate table. Intersection of our rates and peer rates. */
648 __u8 legacy_rates[12];
649
650 /* HT rate table. Intersection of our rates and peer rates. */
651 __u8 ht_rates[16];
652 __u8 pad[16];
653
654 /* If set, interoperability mode, no proprietary extensions. */
655 __u8 interop;
656 __u8 pad2;
657 __u8 station_id;
658 __le16 amsdu_enabled;
659 } __attribute__((packed));
660
661 /* Inline functions to manipulate QoS field in data descriptor. */
662 static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
663 {
664 u16 val_mask = 1 << 4;
665
666 /* End of Service Period Bit 4 */
667 return qos | val_mask;
668 }
669
670 static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
671 {
672 u16 val_mask = 0x3;
673 u8 shift = 5;
674 u16 qos_mask = ~(val_mask << shift);
675
676 /* Ack Policy Bit 5-6 */
677 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
678 }
679
680 static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
681 {
682 u16 val_mask = 1 << 7;
683
684 /* AMSDU present Bit 7 */
685 return qos | val_mask;
686 }
687
688 static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
689 {
690 u16 val_mask = 0xff;
691 u8 shift = 8;
692 u16 qos_mask = ~(val_mask << shift);
693
694 /* Queue Length Bits 8-15 */
695 return (qos & qos_mask) | ((len & val_mask) << shift);
696 }
697
698 /* DMA header used by firmware and hardware. */
699 struct mwl8k_dma_data {
700 __le16 fwlen;
701 struct ieee80211_hdr wh;
702 char data[0];
703 } __attribute__((packed));
704
705 /* Routines to add/remove DMA header from skb. */
706 static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
707 {
708 struct mwl8k_dma_data *tr;
709 int hdrlen;
710
711 tr = (struct mwl8k_dma_data *)skb->data;
712 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
713
714 if (hdrlen != sizeof(tr->wh)) {
715 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
716 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
717 *((__le16 *)(tr->data - 2)) = qos;
718 } else {
719 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
720 }
721 }
722
723 if (hdrlen != sizeof(*tr))
724 skb_pull(skb, sizeof(*tr) - hdrlen);
725 }
726
727 static inline void mwl8k_add_dma_header(struct sk_buff *skb)
728 {
729 struct ieee80211_hdr *wh;
730 int hdrlen;
731 struct mwl8k_dma_data *tr;
732
733 /*
734 * Add a firmware DMA header; the firmware requires that we
735 * present a 2-byte payload length followed by a 4-address
736 * header (without QoS field), followed (optionally) by any
737 * WEP/ExtIV header (but only filled in for CCMP).
738 */
739 wh = (struct ieee80211_hdr *)skb->data;
740
741 hdrlen = ieee80211_hdrlen(wh->frame_control);
742 if (hdrlen != sizeof(*tr))
743 skb_push(skb, sizeof(*tr) - hdrlen);
744
745 if (ieee80211_is_data_qos(wh->frame_control))
746 hdrlen -= 2;
747
748 tr = (struct mwl8k_dma_data *)skb->data;
749 if (wh != &tr->wh)
750 memmove(&tr->wh, wh, hdrlen);
751 if (hdrlen != sizeof(tr->wh))
752 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
753
754 /*
755 * Firmware length is the length of the fully formed "802.11
756 * payload". That is, everything except for the 802.11 header.
757 * This includes all crypto material including the MIC.
758 */
759 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
760 }
761
762
763 /*
764 * Packet reception for 88w8366.
765 */
766 struct mwl8k_rxd_8366 {
767 __le16 pkt_len;
768 __u8 sq2;
769 __u8 rate;
770 __le32 pkt_phys_addr;
771 __le32 next_rxd_phys_addr;
772 __le16 qos_control;
773 __le16 htsig2;
774 __le32 hw_rssi_info;
775 __le32 hw_noise_floor_info;
776 __u8 noise_floor;
777 __u8 pad0[3];
778 __u8 rssi;
779 __u8 rx_status;
780 __u8 channel;
781 __u8 rx_ctrl;
782 } __attribute__((packed));
783
784 #define MWL8K_8366_RATE_INFO_MCS_FORMAT 0x80
785 #define MWL8K_8366_RATE_INFO_40MHZ 0x40
786 #define MWL8K_8366_RATE_INFO_RATEID(x) ((x) & 0x3f)
787
788 #define MWL8K_8366_RX_CTRL_OWNED_BY_HOST 0x80
789
790 static void mwl8k_rxd_8366_init(void *_rxd, dma_addr_t next_dma_addr)
791 {
792 struct mwl8k_rxd_8366 *rxd = _rxd;
793
794 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
795 rxd->rx_ctrl = MWL8K_8366_RX_CTRL_OWNED_BY_HOST;
796 }
797
798 static void mwl8k_rxd_8366_refill(void *_rxd, dma_addr_t addr, int len)
799 {
800 struct mwl8k_rxd_8366 *rxd = _rxd;
801
802 rxd->pkt_len = cpu_to_le16(len);
803 rxd->pkt_phys_addr = cpu_to_le32(addr);
804 wmb();
805 rxd->rx_ctrl = 0;
806 }
807
808 static int
809 mwl8k_rxd_8366_process(void *_rxd, struct ieee80211_rx_status *status,
810 __le16 *qos)
811 {
812 struct mwl8k_rxd_8366 *rxd = _rxd;
813
814 if (!(rxd->rx_ctrl & MWL8K_8366_RX_CTRL_OWNED_BY_HOST))
815 return -1;
816 rmb();
817
818 memset(status, 0, sizeof(*status));
819
820 status->signal = -rxd->rssi;
821 status->noise = -rxd->noise_floor;
822
823 if (rxd->rate & MWL8K_8366_RATE_INFO_MCS_FORMAT) {
824 status->flag |= RX_FLAG_HT;
825 if (rxd->rate & MWL8K_8366_RATE_INFO_40MHZ)
826 status->flag |= RX_FLAG_40MHZ;
827 status->rate_idx = MWL8K_8366_RATE_INFO_RATEID(rxd->rate);
828 } else {
829 int i;
830
831 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
832 if (mwl8k_rates[i].hw_value == rxd->rate) {
833 status->rate_idx = i;
834 break;
835 }
836 }
837 }
838
839 status->band = IEEE80211_BAND_2GHZ;
840 status->freq = ieee80211_channel_to_frequency(rxd->channel);
841
842 *qos = rxd->qos_control;
843
844 return le16_to_cpu(rxd->pkt_len);
845 }
846
847 static struct rxd_ops rxd_8366_ops = {
848 .rxd_size = sizeof(struct mwl8k_rxd_8366),
849 .rxd_init = mwl8k_rxd_8366_init,
850 .rxd_refill = mwl8k_rxd_8366_refill,
851 .rxd_process = mwl8k_rxd_8366_process,
852 };
853
854 /*
855 * Packet reception for 88w8687.
856 */
857 struct mwl8k_rxd_8687 {
858 __le16 pkt_len;
859 __u8 link_quality;
860 __u8 noise_level;
861 __le32 pkt_phys_addr;
862 __le32 next_rxd_phys_addr;
863 __le16 qos_control;
864 __le16 rate_info;
865 __le32 pad0[4];
866 __u8 rssi;
867 __u8 channel;
868 __le16 pad1;
869 __u8 rx_ctrl;
870 __u8 rx_status;
871 __u8 pad2[2];
872 } __attribute__((packed));
873
874 #define MWL8K_8687_RATE_INFO_SHORTPRE 0x8000
875 #define MWL8K_8687_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
876 #define MWL8K_8687_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
877 #define MWL8K_8687_RATE_INFO_40MHZ 0x0004
878 #define MWL8K_8687_RATE_INFO_SHORTGI 0x0002
879 #define MWL8K_8687_RATE_INFO_MCS_FORMAT 0x0001
880
881 #define MWL8K_8687_RX_CTRL_OWNED_BY_HOST 0x02
882
883 static void mwl8k_rxd_8687_init(void *_rxd, dma_addr_t next_dma_addr)
884 {
885 struct mwl8k_rxd_8687 *rxd = _rxd;
886
887 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
888 rxd->rx_ctrl = MWL8K_8687_RX_CTRL_OWNED_BY_HOST;
889 }
890
891 static void mwl8k_rxd_8687_refill(void *_rxd, dma_addr_t addr, int len)
892 {
893 struct mwl8k_rxd_8687 *rxd = _rxd;
894
895 rxd->pkt_len = cpu_to_le16(len);
896 rxd->pkt_phys_addr = cpu_to_le32(addr);
897 wmb();
898 rxd->rx_ctrl = 0;
899 }
900
901 static int
902 mwl8k_rxd_8687_process(void *_rxd, struct ieee80211_rx_status *status,
903 __le16 *qos)
904 {
905 struct mwl8k_rxd_8687 *rxd = _rxd;
906 u16 rate_info;
907
908 if (!(rxd->rx_ctrl & MWL8K_8687_RX_CTRL_OWNED_BY_HOST))
909 return -1;
910 rmb();
911
912 rate_info = le16_to_cpu(rxd->rate_info);
913
914 memset(status, 0, sizeof(*status));
915
916 status->signal = -rxd->rssi;
917 status->noise = -rxd->noise_level;
918 status->antenna = MWL8K_8687_RATE_INFO_ANTSELECT(rate_info);
919 status->rate_idx = MWL8K_8687_RATE_INFO_RATEID(rate_info);
920
921 if (rate_info & MWL8K_8687_RATE_INFO_SHORTPRE)
922 status->flag |= RX_FLAG_SHORTPRE;
923 if (rate_info & MWL8K_8687_RATE_INFO_40MHZ)
924 status->flag |= RX_FLAG_40MHZ;
925 if (rate_info & MWL8K_8687_RATE_INFO_SHORTGI)
926 status->flag |= RX_FLAG_SHORT_GI;
927 if (rate_info & MWL8K_8687_RATE_INFO_MCS_FORMAT)
928 status->flag |= RX_FLAG_HT;
929
930 status->band = IEEE80211_BAND_2GHZ;
931 status->freq = ieee80211_channel_to_frequency(rxd->channel);
932
933 *qos = rxd->qos_control;
934
935 return le16_to_cpu(rxd->pkt_len);
936 }
937
938 static struct rxd_ops rxd_8687_ops = {
939 .rxd_size = sizeof(struct mwl8k_rxd_8687),
940 .rxd_init = mwl8k_rxd_8687_init,
941 .rxd_refill = mwl8k_rxd_8687_refill,
942 .rxd_process = mwl8k_rxd_8687_process,
943 };
944
945
946 #define MWL8K_RX_DESCS 256
947 #define MWL8K_RX_MAXSZ 3800
948
949 static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
950 {
951 struct mwl8k_priv *priv = hw->priv;
952 struct mwl8k_rx_queue *rxq = priv->rxq + index;
953 int size;
954 int i;
955
956 rxq->rxd_count = 0;
957 rxq->head = 0;
958 rxq->tail = 0;
959
960 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
961
962 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
963 if (rxq->rxd == NULL) {
964 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
965 wiphy_name(hw->wiphy));
966 return -ENOMEM;
967 }
968 memset(rxq->rxd, 0, size);
969
970 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
971 if (rxq->buf == NULL) {
972 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
973 wiphy_name(hw->wiphy));
974 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
975 return -ENOMEM;
976 }
977 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
978
979 for (i = 0; i < MWL8K_RX_DESCS; i++) {
980 int desc_size;
981 void *rxd;
982 int nexti;
983 dma_addr_t next_dma_addr;
984
985 desc_size = priv->rxd_ops->rxd_size;
986 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
987
988 nexti = i + 1;
989 if (nexti == MWL8K_RX_DESCS)
990 nexti = 0;
991 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
992
993 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
994 }
995
996 return 0;
997 }
998
999 static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
1000 {
1001 struct mwl8k_priv *priv = hw->priv;
1002 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1003 int refilled;
1004
1005 refilled = 0;
1006 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
1007 struct sk_buff *skb;
1008 dma_addr_t addr;
1009 int rx;
1010 void *rxd;
1011
1012 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
1013 if (skb == NULL)
1014 break;
1015
1016 addr = pci_map_single(priv->pdev, skb->data,
1017 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
1018
1019 rxq->rxd_count++;
1020 rx = rxq->tail++;
1021 if (rxq->tail == MWL8K_RX_DESCS)
1022 rxq->tail = 0;
1023 rxq->buf[rx].skb = skb;
1024 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
1025
1026 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
1027 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
1028
1029 refilled++;
1030 }
1031
1032 return refilled;
1033 }
1034
1035 /* Must be called only when the card's reception is completely halted */
1036 static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
1037 {
1038 struct mwl8k_priv *priv = hw->priv;
1039 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1040 int i;
1041
1042 for (i = 0; i < MWL8K_RX_DESCS; i++) {
1043 if (rxq->buf[i].skb != NULL) {
1044 pci_unmap_single(priv->pdev,
1045 pci_unmap_addr(&rxq->buf[i], dma),
1046 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1047 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
1048
1049 kfree_skb(rxq->buf[i].skb);
1050 rxq->buf[i].skb = NULL;
1051 }
1052 }
1053
1054 kfree(rxq->buf);
1055 rxq->buf = NULL;
1056
1057 pci_free_consistent(priv->pdev,
1058 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
1059 rxq->rxd, rxq->rxd_dma);
1060 rxq->rxd = NULL;
1061 }
1062
1063
1064 /*
1065 * Scan a list of BSSIDs to process for finalize join.
1066 * Allows for extension to process multiple BSSIDs.
1067 */
1068 static inline int
1069 mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1070 {
1071 return priv->capture_beacon &&
1072 ieee80211_is_beacon(wh->frame_control) &&
1073 !compare_ether_addr(wh->addr3, priv->capture_bssid);
1074 }
1075
1076 static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1077 struct sk_buff *skb)
1078 {
1079 struct mwl8k_priv *priv = hw->priv;
1080
1081 priv->capture_beacon = false;
1082 memset(priv->capture_bssid, 0, ETH_ALEN);
1083
1084 /*
1085 * Use GFP_ATOMIC as rxq_process is called from
1086 * the primary interrupt handler, memory allocation call
1087 * must not sleep.
1088 */
1089 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1090 if (priv->beacon_skb != NULL)
1091 ieee80211_queue_work(hw, &priv->finalize_join_worker);
1092 }
1093
1094 static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1095 {
1096 struct mwl8k_priv *priv = hw->priv;
1097 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1098 int processed;
1099
1100 processed = 0;
1101 while (rxq->rxd_count && limit--) {
1102 struct sk_buff *skb;
1103 void *rxd;
1104 int pkt_len;
1105 struct ieee80211_rx_status status;
1106 __le16 qos;
1107
1108 skb = rxq->buf[rxq->head].skb;
1109 if (skb == NULL)
1110 break;
1111
1112 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1113
1114 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
1115 if (pkt_len < 0)
1116 break;
1117
1118 rxq->buf[rxq->head].skb = NULL;
1119
1120 pci_unmap_single(priv->pdev,
1121 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1122 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1123 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
1124
1125 rxq->head++;
1126 if (rxq->head == MWL8K_RX_DESCS)
1127 rxq->head = 0;
1128
1129 rxq->rxd_count--;
1130
1131 skb_put(skb, pkt_len);
1132 mwl8k_remove_dma_header(skb, qos);
1133
1134 /*
1135 * Check for a pending join operation. Save a
1136 * copy of the beacon and schedule a tasklet to
1137 * send a FINALIZE_JOIN command to the firmware.
1138 */
1139 if (mwl8k_capture_bssid(priv, (void *)skb->data))
1140 mwl8k_save_beacon(hw, skb);
1141
1142 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1143 ieee80211_rx_irqsafe(hw, skb);
1144
1145 processed++;
1146 }
1147
1148 return processed;
1149 }
1150
1151
1152 /*
1153 * Packet transmission.
1154 */
1155
1156 /* Transmit packet ACK policy */
1157 #define MWL8K_TXD_ACK_POLICY_NORMAL 0
1158 #define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
1159
1160 #define MWL8K_TXD_STATUS_OK 0x00000001
1161 #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1162 #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1163 #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
1164 #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
1165
1166 struct mwl8k_tx_desc {
1167 __le32 status;
1168 __u8 data_rate;
1169 __u8 tx_priority;
1170 __le16 qos_control;
1171 __le32 pkt_phys_addr;
1172 __le16 pkt_len;
1173 __u8 dest_MAC_addr[ETH_ALEN];
1174 __le32 next_txd_phys_addr;
1175 __le32 reserved;
1176 __le16 rate_info;
1177 __u8 peer_id;
1178 __u8 tx_frag_cnt;
1179 } __attribute__((packed));
1180
1181 #define MWL8K_TX_DESCS 128
1182
1183 static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1184 {
1185 struct mwl8k_priv *priv = hw->priv;
1186 struct mwl8k_tx_queue *txq = priv->txq + index;
1187 int size;
1188 int i;
1189
1190 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1191 txq->stats.limit = MWL8K_TX_DESCS;
1192 txq->head = 0;
1193 txq->tail = 0;
1194
1195 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1196
1197 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1198 if (txq->txd == NULL) {
1199 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1200 wiphy_name(hw->wiphy));
1201 return -ENOMEM;
1202 }
1203 memset(txq->txd, 0, size);
1204
1205 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1206 if (txq->skb == NULL) {
1207 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1208 wiphy_name(hw->wiphy));
1209 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
1210 return -ENOMEM;
1211 }
1212 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
1213
1214 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1215 struct mwl8k_tx_desc *tx_desc;
1216 int nexti;
1217
1218 tx_desc = txq->txd + i;
1219 nexti = (i + 1) % MWL8K_TX_DESCS;
1220
1221 tx_desc->status = 0;
1222 tx_desc->next_txd_phys_addr =
1223 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
1224 }
1225
1226 return 0;
1227 }
1228
1229 static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1230 {
1231 iowrite32(MWL8K_H2A_INT_PPA_READY,
1232 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1233 iowrite32(MWL8K_H2A_INT_DUMMY,
1234 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1235 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1236 }
1237
1238 static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
1239 {
1240 struct mwl8k_priv *priv = hw->priv;
1241 int i;
1242
1243 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
1244 struct mwl8k_tx_queue *txq = priv->txq + i;
1245 int fw_owned = 0;
1246 int drv_owned = 0;
1247 int unused = 0;
1248 int desc;
1249
1250 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1251 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1252 u32 status;
1253
1254 status = le32_to_cpu(tx_desc->status);
1255 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1256 fw_owned++;
1257 else
1258 drv_owned++;
1259
1260 if (tx_desc->pkt_len == 0)
1261 unused++;
1262 }
1263
1264 printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
1265 "fw_owned=%d drv_owned=%d unused=%d\n",
1266 wiphy_name(hw->wiphy), i,
1267 txq->stats.len, txq->head, txq->tail,
1268 fw_owned, drv_owned, unused);
1269 }
1270 }
1271
1272 /*
1273 * Must be called with priv->fw_mutex held and tx queues stopped.
1274 */
1275 #define MWL8K_TX_WAIT_TIMEOUT_MS 1000
1276
1277 static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1278 {
1279 struct mwl8k_priv *priv = hw->priv;
1280 DECLARE_COMPLETION_ONSTACK(tx_wait);
1281 int retry;
1282 int rc;
1283
1284 might_sleep();
1285
1286 /*
1287 * The TX queues are stopped at this point, so this test
1288 * doesn't need to take ->tx_lock.
1289 */
1290 if (!priv->pending_tx_pkts)
1291 return 0;
1292
1293 retry = 0;
1294 rc = 0;
1295
1296 spin_lock_bh(&priv->tx_lock);
1297 priv->tx_wait = &tx_wait;
1298 while (!rc) {
1299 int oldcount;
1300 unsigned long timeout;
1301
1302 oldcount = priv->pending_tx_pkts;
1303
1304 spin_unlock_bh(&priv->tx_lock);
1305 timeout = wait_for_completion_timeout(&tx_wait,
1306 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
1307 spin_lock_bh(&priv->tx_lock);
1308
1309 if (timeout) {
1310 WARN_ON(priv->pending_tx_pkts);
1311 if (retry) {
1312 printk(KERN_NOTICE "%s: tx rings drained\n",
1313 wiphy_name(hw->wiphy));
1314 }
1315 break;
1316 }
1317
1318 if (priv->pending_tx_pkts < oldcount) {
1319 printk(KERN_NOTICE "%s: timeout waiting for tx "
1320 "rings to drain (%d -> %d pkts), retrying\n",
1321 wiphy_name(hw->wiphy), oldcount,
1322 priv->pending_tx_pkts);
1323 retry = 1;
1324 continue;
1325 }
1326
1327 priv->tx_wait = NULL;
1328
1329 printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
1330 wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
1331 mwl8k_dump_tx_rings(hw);
1332
1333 rc = -ETIMEDOUT;
1334 }
1335 spin_unlock_bh(&priv->tx_lock);
1336
1337 return rc;
1338 }
1339
1340 #define MWL8K_TXD_SUCCESS(status) \
1341 ((status) & (MWL8K_TXD_STATUS_OK | \
1342 MWL8K_TXD_STATUS_OK_RETRY | \
1343 MWL8K_TXD_STATUS_OK_MORE_RETRY))
1344
1345 static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1346 {
1347 struct mwl8k_priv *priv = hw->priv;
1348 struct mwl8k_tx_queue *txq = priv->txq + index;
1349 int wake = 0;
1350
1351 while (txq->stats.len > 0) {
1352 int tx;
1353 struct mwl8k_tx_desc *tx_desc;
1354 unsigned long addr;
1355 int size;
1356 struct sk_buff *skb;
1357 struct ieee80211_tx_info *info;
1358 u32 status;
1359
1360 tx = txq->head;
1361 tx_desc = txq->txd + tx;
1362
1363 status = le32_to_cpu(tx_desc->status);
1364
1365 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1366 if (!force)
1367 break;
1368 tx_desc->status &=
1369 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1370 }
1371
1372 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1373 BUG_ON(txq->stats.len == 0);
1374 txq->stats.len--;
1375 priv->pending_tx_pkts--;
1376
1377 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1378 size = le16_to_cpu(tx_desc->pkt_len);
1379 skb = txq->skb[tx];
1380 txq->skb[tx] = NULL;
1381
1382 BUG_ON(skb == NULL);
1383 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1384
1385 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
1386
1387 /* Mark descriptor as unused */
1388 tx_desc->pkt_phys_addr = 0;
1389 tx_desc->pkt_len = 0;
1390
1391 info = IEEE80211_SKB_CB(skb);
1392 ieee80211_tx_info_clear_status(info);
1393 if (MWL8K_TXD_SUCCESS(status))
1394 info->flags |= IEEE80211_TX_STAT_ACK;
1395
1396 ieee80211_tx_status_irqsafe(hw, skb);
1397
1398 wake = 1;
1399 }
1400
1401 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
1402 ieee80211_wake_queue(hw, index);
1403 }
1404
1405 /* must be called only when the card's transmit is completely halted */
1406 static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1407 {
1408 struct mwl8k_priv *priv = hw->priv;
1409 struct mwl8k_tx_queue *txq = priv->txq + index;
1410
1411 mwl8k_txq_reclaim(hw, index, 1);
1412
1413 kfree(txq->skb);
1414 txq->skb = NULL;
1415
1416 pci_free_consistent(priv->pdev,
1417 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1418 txq->txd, txq->txd_dma);
1419 txq->txd = NULL;
1420 }
1421
1422 static int
1423 mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1424 {
1425 struct mwl8k_priv *priv = hw->priv;
1426 struct ieee80211_tx_info *tx_info;
1427 struct mwl8k_vif *mwl8k_vif;
1428 struct ieee80211_hdr *wh;
1429 struct mwl8k_tx_queue *txq;
1430 struct mwl8k_tx_desc *tx;
1431 dma_addr_t dma;
1432 u32 txstatus;
1433 u8 txdatarate;
1434 u16 qos;
1435
1436 wh = (struct ieee80211_hdr *)skb->data;
1437 if (ieee80211_is_data_qos(wh->frame_control))
1438 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1439 else
1440 qos = 0;
1441
1442 mwl8k_add_dma_header(skb);
1443 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
1444
1445 tx_info = IEEE80211_SKB_CB(skb);
1446 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1447
1448 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1449 u16 seqno = mwl8k_vif->seqno;
1450
1451 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1452 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1453 mwl8k_vif->seqno = seqno++ % 4096;
1454 }
1455
1456 /* Setup firmware control bit fields for each frame type. */
1457 txstatus = 0;
1458 txdatarate = 0;
1459 if (ieee80211_is_mgmt(wh->frame_control) ||
1460 ieee80211_is_ctl(wh->frame_control)) {
1461 txdatarate = 0;
1462 qos = mwl8k_qos_setbit_eosp(qos);
1463 /* Set Queue size to unspecified */
1464 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1465 } else if (ieee80211_is_data(wh->frame_control)) {
1466 txdatarate = 1;
1467 if (is_multicast_ether_addr(wh->addr1))
1468 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1469
1470 /* Send pkt in an aggregate if AMPDU frame. */
1471 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1472 qos = mwl8k_qos_setbit_ack(qos,
1473 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1474 else
1475 qos = mwl8k_qos_setbit_ack(qos,
1476 MWL8K_TXD_ACK_POLICY_NORMAL);
1477
1478 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1479 qos = mwl8k_qos_setbit_amsdu(qos);
1480 }
1481
1482 dma = pci_map_single(priv->pdev, skb->data,
1483 skb->len, PCI_DMA_TODEVICE);
1484
1485 if (pci_dma_mapping_error(priv->pdev, dma)) {
1486 printk(KERN_DEBUG "%s: failed to dma map skb, "
1487 "dropping TX frame.\n", wiphy_name(hw->wiphy));
1488 dev_kfree_skb(skb);
1489 return NETDEV_TX_OK;
1490 }
1491
1492 spin_lock_bh(&priv->tx_lock);
1493
1494 txq = priv->txq + index;
1495
1496 BUG_ON(txq->skb[txq->tail] != NULL);
1497 txq->skb[txq->tail] = skb;
1498
1499 tx = txq->txd + txq->tail;
1500 tx->data_rate = txdatarate;
1501 tx->tx_priority = index;
1502 tx->qos_control = cpu_to_le16(qos);
1503 tx->pkt_phys_addr = cpu_to_le32(dma);
1504 tx->pkt_len = cpu_to_le16(skb->len);
1505 tx->rate_info = 0;
1506 tx->peer_id = mwl8k_vif->peer_id;
1507 wmb();
1508 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1509
1510 txq->stats.count++;
1511 txq->stats.len++;
1512 priv->pending_tx_pkts++;
1513
1514 txq->tail++;
1515 if (txq->tail == MWL8K_TX_DESCS)
1516 txq->tail = 0;
1517
1518 if (txq->head == txq->tail)
1519 ieee80211_stop_queue(hw, index);
1520
1521 mwl8k_tx_start(priv);
1522
1523 spin_unlock_bh(&priv->tx_lock);
1524
1525 return NETDEV_TX_OK;
1526 }
1527
1528
1529 /*
1530 * Firmware access.
1531 *
1532 * We have the following requirements for issuing firmware commands:
1533 * - Some commands require that the packet transmit path is idle when
1534 * the command is issued. (For simplicity, we'll just quiesce the
1535 * transmit path for every command.)
1536 * - There are certain sequences of commands that need to be issued to
1537 * the hardware sequentially, with no other intervening commands.
1538 *
1539 * This leads to an implementation of a "firmware lock" as a mutex that
1540 * can be taken recursively, and which is taken by both the low-level
1541 * command submission function (mwl8k_post_cmd) as well as any users of
1542 * that function that require issuing of an atomic sequence of commands,
1543 * and quiesces the transmit path whenever it's taken.
1544 */
1545 static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1546 {
1547 struct mwl8k_priv *priv = hw->priv;
1548
1549 if (priv->fw_mutex_owner != current) {
1550 int rc;
1551
1552 mutex_lock(&priv->fw_mutex);
1553 ieee80211_stop_queues(hw);
1554
1555 rc = mwl8k_tx_wait_empty(hw);
1556 if (rc) {
1557 ieee80211_wake_queues(hw);
1558 mutex_unlock(&priv->fw_mutex);
1559
1560 return rc;
1561 }
1562
1563 priv->fw_mutex_owner = current;
1564 }
1565
1566 priv->fw_mutex_depth++;
1567
1568 return 0;
1569 }
1570
1571 static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1572 {
1573 struct mwl8k_priv *priv = hw->priv;
1574
1575 if (!--priv->fw_mutex_depth) {
1576 ieee80211_wake_queues(hw);
1577 priv->fw_mutex_owner = NULL;
1578 mutex_unlock(&priv->fw_mutex);
1579 }
1580 }
1581
1582
1583 /*
1584 * Command processing.
1585 */
1586
1587 /* Timeout firmware commands after 10s */
1588 #define MWL8K_CMD_TIMEOUT_MS 10000
1589
1590 static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1591 {
1592 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1593 struct mwl8k_priv *priv = hw->priv;
1594 void __iomem *regs = priv->regs;
1595 dma_addr_t dma_addr;
1596 unsigned int dma_size;
1597 int rc;
1598 unsigned long timeout = 0;
1599 u8 buf[32];
1600
1601 cmd->result = 0xffff;
1602 dma_size = le16_to_cpu(cmd->length);
1603 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1604 PCI_DMA_BIDIRECTIONAL);
1605 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1606 return -ENOMEM;
1607
1608 rc = mwl8k_fw_lock(hw);
1609 if (rc) {
1610 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1611 PCI_DMA_BIDIRECTIONAL);
1612 return rc;
1613 }
1614
1615 priv->hostcmd_wait = &cmd_wait;
1616 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1617 iowrite32(MWL8K_H2A_INT_DOORBELL,
1618 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1619 iowrite32(MWL8K_H2A_INT_DUMMY,
1620 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1621
1622 timeout = wait_for_completion_timeout(&cmd_wait,
1623 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1624
1625 priv->hostcmd_wait = NULL;
1626
1627 mwl8k_fw_unlock(hw);
1628
1629 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1630 PCI_DMA_BIDIRECTIONAL);
1631
1632 if (!timeout) {
1633 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1634 wiphy_name(hw->wiphy),
1635 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1636 MWL8K_CMD_TIMEOUT_MS);
1637 rc = -ETIMEDOUT;
1638 } else {
1639 int ms;
1640
1641 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
1642
1643 rc = cmd->result ? -EINVAL : 0;
1644 if (rc)
1645 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1646 wiphy_name(hw->wiphy),
1647 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1648 le16_to_cpu(cmd->result));
1649 else if (ms > 2000)
1650 printk(KERN_NOTICE "%s: Command %s took %d ms\n",
1651 wiphy_name(hw->wiphy),
1652 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1653 ms);
1654 }
1655
1656 return rc;
1657 }
1658
1659 /*
1660 * CMD_GET_HW_SPEC (STA version).
1661 */
1662 struct mwl8k_cmd_get_hw_spec_sta {
1663 struct mwl8k_cmd_pkt header;
1664 __u8 hw_rev;
1665 __u8 host_interface;
1666 __le16 num_mcaddrs;
1667 __u8 perm_addr[ETH_ALEN];
1668 __le16 region_code;
1669 __le32 fw_rev;
1670 __le32 ps_cookie;
1671 __le32 caps;
1672 __u8 mcs_bitmap[16];
1673 __le32 rx_queue_ptr;
1674 __le32 num_tx_queues;
1675 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1676 __le32 caps2;
1677 __le32 num_tx_desc_per_queue;
1678 __le32 total_rxd;
1679 } __attribute__((packed));
1680
1681 static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
1682 {
1683 struct mwl8k_priv *priv = hw->priv;
1684 struct mwl8k_cmd_get_hw_spec_sta *cmd;
1685 int rc;
1686 int i;
1687
1688 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1689 if (cmd == NULL)
1690 return -ENOMEM;
1691
1692 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1693 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1694
1695 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1696 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1697 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1698 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1699 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1700 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1701 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1702 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1703
1704 rc = mwl8k_post_cmd(hw, &cmd->header);
1705
1706 if (!rc) {
1707 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1708 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1709 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1710 priv->hw_rev = cmd->hw_rev;
1711 }
1712
1713 kfree(cmd);
1714 return rc;
1715 }
1716
1717 /*
1718 * CMD_GET_HW_SPEC (AP version).
1719 */
1720 struct mwl8k_cmd_get_hw_spec_ap {
1721 struct mwl8k_cmd_pkt header;
1722 __u8 hw_rev;
1723 __u8 host_interface;
1724 __le16 num_wcb;
1725 __le16 num_mcaddrs;
1726 __u8 perm_addr[ETH_ALEN];
1727 __le16 region_code;
1728 __le16 num_antenna;
1729 __le32 fw_rev;
1730 __le32 wcbbase0;
1731 __le32 rxwrptr;
1732 __le32 rxrdptr;
1733 __le32 ps_cookie;
1734 __le32 wcbbase1;
1735 __le32 wcbbase2;
1736 __le32 wcbbase3;
1737 } __attribute__((packed));
1738
1739 static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1740 {
1741 struct mwl8k_priv *priv = hw->priv;
1742 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1743 int rc;
1744
1745 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1746 if (cmd == NULL)
1747 return -ENOMEM;
1748
1749 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1750 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1751
1752 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1753 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1754
1755 rc = mwl8k_post_cmd(hw, &cmd->header);
1756
1757 if (!rc) {
1758 int off;
1759
1760 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1761 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1762 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1763 priv->hw_rev = cmd->hw_rev;
1764
1765 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1766 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1767
1768 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1769 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1770
1771 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1772 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1773
1774 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1775 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1776
1777 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1778 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1779
1780 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1781 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1782 }
1783
1784 kfree(cmd);
1785 return rc;
1786 }
1787
1788 /*
1789 * CMD_SET_HW_SPEC.
1790 */
1791 struct mwl8k_cmd_set_hw_spec {
1792 struct mwl8k_cmd_pkt header;
1793 __u8 hw_rev;
1794 __u8 host_interface;
1795 __le16 num_mcaddrs;
1796 __u8 perm_addr[ETH_ALEN];
1797 __le16 region_code;
1798 __le32 fw_rev;
1799 __le32 ps_cookie;
1800 __le32 caps;
1801 __le32 rx_queue_ptr;
1802 __le32 num_tx_queues;
1803 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1804 __le32 flags;
1805 __le32 num_tx_desc_per_queue;
1806 __le32 total_rxd;
1807 } __attribute__((packed));
1808
1809 #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1810
1811 static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1812 {
1813 struct mwl8k_priv *priv = hw->priv;
1814 struct mwl8k_cmd_set_hw_spec *cmd;
1815 int rc;
1816 int i;
1817
1818 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1819 if (cmd == NULL)
1820 return -ENOMEM;
1821
1822 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1823 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1824
1825 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1826 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1827 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1828 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1829 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1830 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT);
1831 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1832 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1833
1834 rc = mwl8k_post_cmd(hw, &cmd->header);
1835 kfree(cmd);
1836
1837 return rc;
1838 }
1839
1840 /*
1841 * CMD_MAC_MULTICAST_ADR.
1842 */
1843 struct mwl8k_cmd_mac_multicast_adr {
1844 struct mwl8k_cmd_pkt header;
1845 __le16 action;
1846 __le16 numaddr;
1847 __u8 addr[0][ETH_ALEN];
1848 };
1849
1850 #define MWL8K_ENABLE_RX_DIRECTED 0x0001
1851 #define MWL8K_ENABLE_RX_MULTICAST 0x0002
1852 #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1853 #define MWL8K_ENABLE_RX_BROADCAST 0x0008
1854
1855 static struct mwl8k_cmd_pkt *
1856 __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
1857 int mc_count, struct dev_addr_list *mclist)
1858 {
1859 struct mwl8k_priv *priv = hw->priv;
1860 struct mwl8k_cmd_mac_multicast_adr *cmd;
1861 int size;
1862
1863 if (allmulti || mc_count > priv->num_mcaddrs) {
1864 allmulti = 1;
1865 mc_count = 0;
1866 }
1867
1868 size = sizeof(*cmd) + mc_count * ETH_ALEN;
1869
1870 cmd = kzalloc(size, GFP_ATOMIC);
1871 if (cmd == NULL)
1872 return NULL;
1873
1874 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1875 cmd->header.length = cpu_to_le16(size);
1876 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1877 MWL8K_ENABLE_RX_BROADCAST);
1878
1879 if (allmulti) {
1880 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1881 } else if (mc_count) {
1882 int i;
1883
1884 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1885 cmd->numaddr = cpu_to_le16(mc_count);
1886 for (i = 0; i < mc_count && mclist; i++) {
1887 if (mclist->da_addrlen != ETH_ALEN) {
1888 kfree(cmd);
1889 return NULL;
1890 }
1891 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1892 mclist = mclist->next;
1893 }
1894 }
1895
1896 return &cmd->header;
1897 }
1898
1899 /*
1900 * CMD_802_11_GET_STAT.
1901 */
1902 struct mwl8k_cmd_802_11_get_stat {
1903 struct mwl8k_cmd_pkt header;
1904 __le32 stats[64];
1905 } __attribute__((packed));
1906
1907 #define MWL8K_STAT_ACK_FAILURE 9
1908 #define MWL8K_STAT_RTS_FAILURE 12
1909 #define MWL8K_STAT_FCS_ERROR 24
1910 #define MWL8K_STAT_RTS_SUCCESS 11
1911
1912 static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1913 struct ieee80211_low_level_stats *stats)
1914 {
1915 struct mwl8k_cmd_802_11_get_stat *cmd;
1916 int rc;
1917
1918 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1919 if (cmd == NULL)
1920 return -ENOMEM;
1921
1922 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1923 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1924
1925 rc = mwl8k_post_cmd(hw, &cmd->header);
1926 if (!rc) {
1927 stats->dot11ACKFailureCount =
1928 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1929 stats->dot11RTSFailureCount =
1930 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1931 stats->dot11FCSErrorCount =
1932 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1933 stats->dot11RTSSuccessCount =
1934 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1935 }
1936 kfree(cmd);
1937
1938 return rc;
1939 }
1940
1941 /*
1942 * CMD_802_11_RADIO_CONTROL.
1943 */
1944 struct mwl8k_cmd_802_11_radio_control {
1945 struct mwl8k_cmd_pkt header;
1946 __le16 action;
1947 __le16 control;
1948 __le16 radio_on;
1949 } __attribute__((packed));
1950
1951 static int
1952 mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
1953 {
1954 struct mwl8k_priv *priv = hw->priv;
1955 struct mwl8k_cmd_802_11_radio_control *cmd;
1956 int rc;
1957
1958 if (enable == priv->radio_on && !force)
1959 return 0;
1960
1961 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1962 if (cmd == NULL)
1963 return -ENOMEM;
1964
1965 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1966 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1967 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1968 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
1969 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1970
1971 rc = mwl8k_post_cmd(hw, &cmd->header);
1972 kfree(cmd);
1973
1974 if (!rc)
1975 priv->radio_on = enable;
1976
1977 return rc;
1978 }
1979
1980 static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1981 {
1982 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1983 }
1984
1985 static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1986 {
1987 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1988 }
1989
1990 static int
1991 mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1992 {
1993 struct mwl8k_priv *priv;
1994
1995 if (hw == NULL || hw->priv == NULL)
1996 return -EINVAL;
1997 priv = hw->priv;
1998
1999 priv->radio_short_preamble = short_preamble;
2000
2001 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
2002 }
2003
2004 /*
2005 * CMD_802_11_RF_TX_POWER.
2006 */
2007 #define MWL8K_TX_POWER_LEVEL_TOTAL 8
2008
2009 struct mwl8k_cmd_802_11_rf_tx_power {
2010 struct mwl8k_cmd_pkt header;
2011 __le16 action;
2012 __le16 support_level;
2013 __le16 current_level;
2014 __le16 reserved;
2015 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
2016 } __attribute__((packed));
2017
2018 static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
2019 {
2020 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
2021 int rc;
2022
2023 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2024 if (cmd == NULL)
2025 return -ENOMEM;
2026
2027 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2028 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2029 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2030 cmd->support_level = cpu_to_le16(dBm);
2031
2032 rc = mwl8k_post_cmd(hw, &cmd->header);
2033 kfree(cmd);
2034
2035 return rc;
2036 }
2037
2038 /*
2039 * CMD_RF_ANTENNA.
2040 */
2041 struct mwl8k_cmd_rf_antenna {
2042 struct mwl8k_cmd_pkt header;
2043 __le16 antenna;
2044 __le16 mode;
2045 } __attribute__((packed));
2046
2047 #define MWL8K_RF_ANTENNA_RX 1
2048 #define MWL8K_RF_ANTENNA_TX 2
2049
2050 static int
2051 mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2052 {
2053 struct mwl8k_cmd_rf_antenna *cmd;
2054 int rc;
2055
2056 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2057 if (cmd == NULL)
2058 return -ENOMEM;
2059
2060 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2061 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2062 cmd->antenna = cpu_to_le16(antenna);
2063 cmd->mode = cpu_to_le16(mask);
2064
2065 rc = mwl8k_post_cmd(hw, &cmd->header);
2066 kfree(cmd);
2067
2068 return rc;
2069 }
2070
2071 /*
2072 * CMD_SET_PRE_SCAN.
2073 */
2074 struct mwl8k_cmd_set_pre_scan {
2075 struct mwl8k_cmd_pkt header;
2076 } __attribute__((packed));
2077
2078 static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2079 {
2080 struct mwl8k_cmd_set_pre_scan *cmd;
2081 int rc;
2082
2083 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2084 if (cmd == NULL)
2085 return -ENOMEM;
2086
2087 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2088 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2089
2090 rc = mwl8k_post_cmd(hw, &cmd->header);
2091 kfree(cmd);
2092
2093 return rc;
2094 }
2095
2096 /*
2097 * CMD_SET_POST_SCAN.
2098 */
2099 struct mwl8k_cmd_set_post_scan {
2100 struct mwl8k_cmd_pkt header;
2101 __le32 isibss;
2102 __u8 bssid[ETH_ALEN];
2103 } __attribute__((packed));
2104
2105 static int
2106 mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
2107 {
2108 struct mwl8k_cmd_set_post_scan *cmd;
2109 int rc;
2110
2111 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2112 if (cmd == NULL)
2113 return -ENOMEM;
2114
2115 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2116 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2117 cmd->isibss = 0;
2118 memcpy(cmd->bssid, mac, ETH_ALEN);
2119
2120 rc = mwl8k_post_cmd(hw, &cmd->header);
2121 kfree(cmd);
2122
2123 return rc;
2124 }
2125
2126 /*
2127 * CMD_SET_RF_CHANNEL.
2128 */
2129 struct mwl8k_cmd_set_rf_channel {
2130 struct mwl8k_cmd_pkt header;
2131 __le16 action;
2132 __u8 current_channel;
2133 __le32 channel_flags;
2134 } __attribute__((packed));
2135
2136 static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
2137 struct ieee80211_channel *channel)
2138 {
2139 struct mwl8k_cmd_set_rf_channel *cmd;
2140 int rc;
2141
2142 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2143 if (cmd == NULL)
2144 return -ENOMEM;
2145
2146 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2147 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2148 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2149 cmd->current_channel = channel->hw_value;
2150 if (channel->band == IEEE80211_BAND_2GHZ)
2151 cmd->channel_flags = cpu_to_le32(0x00000081);
2152 else
2153 cmd->channel_flags = cpu_to_le32(0x00000000);
2154
2155 rc = mwl8k_post_cmd(hw, &cmd->header);
2156 kfree(cmd);
2157
2158 return rc;
2159 }
2160
2161 /*
2162 * CMD_SET_SLOT.
2163 */
2164 struct mwl8k_cmd_set_slot {
2165 struct mwl8k_cmd_pkt header;
2166 __le16 action;
2167 __u8 short_slot;
2168 } __attribute__((packed));
2169
2170 static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
2171 {
2172 struct mwl8k_cmd_set_slot *cmd;
2173 int rc;
2174
2175 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2176 if (cmd == NULL)
2177 return -ENOMEM;
2178
2179 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
2180 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2181 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2182 cmd->short_slot = short_slot_time;
2183
2184 rc = mwl8k_post_cmd(hw, &cmd->header);
2185 kfree(cmd);
2186
2187 return rc;
2188 }
2189
2190 /*
2191 * CMD_MIMO_CONFIG.
2192 */
2193 struct mwl8k_cmd_mimo_config {
2194 struct mwl8k_cmd_pkt header;
2195 __le32 action;
2196 __u8 rx_antenna_map;
2197 __u8 tx_antenna_map;
2198 } __attribute__((packed));
2199
2200 static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
2201 {
2202 struct mwl8k_cmd_mimo_config *cmd;
2203 int rc;
2204
2205 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2206 if (cmd == NULL)
2207 return -ENOMEM;
2208
2209 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
2210 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2211 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2212 cmd->rx_antenna_map = rx;
2213 cmd->tx_antenna_map = tx;
2214
2215 rc = mwl8k_post_cmd(hw, &cmd->header);
2216 kfree(cmd);
2217
2218 return rc;
2219 }
2220
2221 /*
2222 * CMD_ENABLE_SNIFFER.
2223 */
2224 struct mwl8k_cmd_enable_sniffer {
2225 struct mwl8k_cmd_pkt header;
2226 __le32 action;
2227 } __attribute__((packed));
2228
2229 static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2230 {
2231 struct mwl8k_cmd_enable_sniffer *cmd;
2232 int rc;
2233
2234 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2235 if (cmd == NULL)
2236 return -ENOMEM;
2237
2238 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2239 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2240 cmd->action = cpu_to_le32(!!enable);
2241
2242 rc = mwl8k_post_cmd(hw, &cmd->header);
2243 kfree(cmd);
2244
2245 return rc;
2246 }
2247
2248 /*
2249 * CMD_SET_MAC_ADDR.
2250 */
2251 struct mwl8k_cmd_set_mac_addr {
2252 struct mwl8k_cmd_pkt header;
2253 union {
2254 struct {
2255 __le16 mac_type;
2256 __u8 mac_addr[ETH_ALEN];
2257 } mbss;
2258 __u8 mac_addr[ETH_ALEN];
2259 };
2260 } __attribute__((packed));
2261
2262 static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2263 {
2264 struct mwl8k_priv *priv = hw->priv;
2265 struct mwl8k_cmd_set_mac_addr *cmd;
2266 int rc;
2267
2268 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2269 if (cmd == NULL)
2270 return -ENOMEM;
2271
2272 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2273 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2274 if (priv->ap_fw) {
2275 cmd->mbss.mac_type = 0;
2276 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2277 } else {
2278 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2279 }
2280
2281 rc = mwl8k_post_cmd(hw, &cmd->header);
2282 kfree(cmd);
2283
2284 return rc;
2285 }
2286
2287
2288 /*
2289 * CMD_SET_RATEADAPT_MODE.
2290 */
2291 struct mwl8k_cmd_set_rate_adapt_mode {
2292 struct mwl8k_cmd_pkt header;
2293 __le16 action;
2294 __le16 mode;
2295 } __attribute__((packed));
2296
2297 static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
2298 {
2299 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2300 int rc;
2301
2302 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2303 if (cmd == NULL)
2304 return -ENOMEM;
2305
2306 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2307 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2308 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2309 cmd->mode = cpu_to_le16(mode);
2310
2311 rc = mwl8k_post_cmd(hw, &cmd->header);
2312 kfree(cmd);
2313
2314 return rc;
2315 }
2316
2317 /*
2318 * CMD_SET_WMM_MODE.
2319 */
2320 struct mwl8k_cmd_set_wmm {
2321 struct mwl8k_cmd_pkt header;
2322 __le16 action;
2323 } __attribute__((packed));
2324
2325 static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
2326 {
2327 struct mwl8k_priv *priv = hw->priv;
2328 struct mwl8k_cmd_set_wmm *cmd;
2329 int rc;
2330
2331 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2332 if (cmd == NULL)
2333 return -ENOMEM;
2334
2335 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
2336 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2337 cmd->action = cpu_to_le16(!!enable);
2338
2339 rc = mwl8k_post_cmd(hw, &cmd->header);
2340 kfree(cmd);
2341
2342 if (!rc)
2343 priv->wmm_enabled = enable;
2344
2345 return rc;
2346 }
2347
2348 /*
2349 * CMD_SET_RTS_THRESHOLD.
2350 */
2351 struct mwl8k_cmd_rts_threshold {
2352 struct mwl8k_cmd_pkt header;
2353 __le16 action;
2354 __le16 threshold;
2355 } __attribute__((packed));
2356
2357 static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
2358 u16 action, u16 threshold)
2359 {
2360 struct mwl8k_cmd_rts_threshold *cmd;
2361 int rc;
2362
2363 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2364 if (cmd == NULL)
2365 return -ENOMEM;
2366
2367 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2368 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2369 cmd->action = cpu_to_le16(action);
2370 cmd->threshold = cpu_to_le16(threshold);
2371
2372 rc = mwl8k_post_cmd(hw, &cmd->header);
2373 kfree(cmd);
2374
2375 return rc;
2376 }
2377
2378 /*
2379 * CMD_SET_EDCA_PARAMS.
2380 */
2381 struct mwl8k_cmd_set_edca_params {
2382 struct mwl8k_cmd_pkt header;
2383
2384 /* See MWL8K_SET_EDCA_XXX below */
2385 __le16 action;
2386
2387 /* TX opportunity in units of 32 us */
2388 __le16 txop;
2389
2390 union {
2391 struct {
2392 /* Log exponent of max contention period: 0...15 */
2393 __le32 log_cw_max;
2394
2395 /* Log exponent of min contention period: 0...15 */
2396 __le32 log_cw_min;
2397
2398 /* Adaptive interframe spacing in units of 32us */
2399 __u8 aifs;
2400
2401 /* TX queue to configure */
2402 __u8 txq;
2403 } ap;
2404 struct {
2405 /* Log exponent of max contention period: 0...15 */
2406 __u8 log_cw_max;
2407
2408 /* Log exponent of min contention period: 0...15 */
2409 __u8 log_cw_min;
2410
2411 /* Adaptive interframe spacing in units of 32us */
2412 __u8 aifs;
2413
2414 /* TX queue to configure */
2415 __u8 txq;
2416 } sta;
2417 };
2418 } __attribute__((packed));
2419
2420 #define MWL8K_SET_EDCA_CW 0x01
2421 #define MWL8K_SET_EDCA_TXOP 0x02
2422 #define MWL8K_SET_EDCA_AIFS 0x04
2423
2424 #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2425 MWL8K_SET_EDCA_TXOP | \
2426 MWL8K_SET_EDCA_AIFS)
2427
2428 static int
2429 mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2430 __u16 cw_min, __u16 cw_max,
2431 __u8 aifs, __u16 txop)
2432 {
2433 struct mwl8k_priv *priv = hw->priv;
2434 struct mwl8k_cmd_set_edca_params *cmd;
2435 int rc;
2436
2437 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2438 if (cmd == NULL)
2439 return -ENOMEM;
2440
2441 /*
2442 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2443 * this call.
2444 */
2445 qnum ^= !(qnum >> 1);
2446
2447 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2448 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2449 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2450 cmd->txop = cpu_to_le16(txop);
2451 if (priv->ap_fw) {
2452 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2453 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2454 cmd->ap.aifs = aifs;
2455 cmd->ap.txq = qnum;
2456 } else {
2457 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2458 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2459 cmd->sta.aifs = aifs;
2460 cmd->sta.txq = qnum;
2461 }
2462
2463 rc = mwl8k_post_cmd(hw, &cmd->header);
2464 kfree(cmd);
2465
2466 return rc;
2467 }
2468
2469 /*
2470 * CMD_FINALIZE_JOIN.
2471 */
2472 #define MWL8K_FJ_BEACON_MAXLEN 128
2473
2474 struct mwl8k_cmd_finalize_join {
2475 struct mwl8k_cmd_pkt header;
2476 __le32 sleep_interval; /* Number of beacon periods to sleep */
2477 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2478 } __attribute__((packed));
2479
2480 static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2481 int framelen, int dtim)
2482 {
2483 struct mwl8k_cmd_finalize_join *cmd;
2484 struct ieee80211_mgmt *payload = frame;
2485 int payload_len;
2486 int rc;
2487
2488 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2489 if (cmd == NULL)
2490 return -ENOMEM;
2491
2492 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2493 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2494 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2495
2496 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
2497 if (payload_len < 0)
2498 payload_len = 0;
2499 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2500 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2501
2502 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2503
2504 rc = mwl8k_post_cmd(hw, &cmd->header);
2505 kfree(cmd);
2506
2507 return rc;
2508 }
2509
2510 /*
2511 * CMD_UPDATE_STADB.
2512 */
2513 struct mwl8k_cmd_update_sta_db {
2514 struct mwl8k_cmd_pkt header;
2515
2516 /* See STADB_ACTION_TYPE */
2517 __le32 action;
2518
2519 /* Peer MAC address */
2520 __u8 peer_addr[ETH_ALEN];
2521
2522 __le32 reserved;
2523
2524 /* Peer info - valid during add/update. */
2525 struct peer_capability_info peer_info;
2526 } __attribute__((packed));
2527
2528 static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2529 struct ieee80211_vif *vif, __u32 action)
2530 {
2531 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2532 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2533 struct mwl8k_cmd_update_sta_db *cmd;
2534 struct peer_capability_info *peer_info;
2535 int rc;
2536
2537 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2538 if (cmd == NULL)
2539 return -ENOMEM;
2540
2541 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2542 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2543
2544 cmd->action = cpu_to_le32(action);
2545 peer_info = &cmd->peer_info;
2546 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
2547
2548 switch (action) {
2549 case MWL8K_STA_DB_ADD_ENTRY:
2550 case MWL8K_STA_DB_MODIFY_ENTRY:
2551 /* Build peer_info block */
2552 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2553 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2554 memcpy(peer_info->legacy_rates, mwl8k_rateids,
2555 sizeof(mwl8k_rateids));
2556 peer_info->interop = 1;
2557 peer_info->amsdu_enabled = 0;
2558
2559 rc = mwl8k_post_cmd(hw, &cmd->header);
2560 if (rc == 0)
2561 mv_vif->peer_id = peer_info->station_id;
2562
2563 break;
2564
2565 case MWL8K_STA_DB_DEL_ENTRY:
2566 case MWL8K_STA_DB_FLUSH:
2567 default:
2568 rc = mwl8k_post_cmd(hw, &cmd->header);
2569 if (rc == 0)
2570 mv_vif->peer_id = 0;
2571 break;
2572 }
2573 kfree(cmd);
2574
2575 return rc;
2576 }
2577
2578 /*
2579 * CMD_SET_AID.
2580 */
2581 #define MWL8K_FRAME_PROT_DISABLED 0x00
2582 #define MWL8K_FRAME_PROT_11G 0x07
2583 #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2584 #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
2585
2586 struct mwl8k_cmd_update_set_aid {
2587 struct mwl8k_cmd_pkt header;
2588 __le16 aid;
2589
2590 /* AP's MAC address (BSSID) */
2591 __u8 bssid[ETH_ALEN];
2592 __le16 protection_mode;
2593 __u8 supp_rates[14];
2594 } __attribute__((packed));
2595
2596 static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2597 struct ieee80211_vif *vif)
2598 {
2599 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2600 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2601 struct mwl8k_cmd_update_set_aid *cmd;
2602 u16 prot_mode;
2603 int rc;
2604
2605 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2606 if (cmd == NULL)
2607 return -ENOMEM;
2608
2609 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2610 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2611 cmd->aid = cpu_to_le16(info->aid);
2612
2613 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
2614
2615 if (info->use_cts_prot) {
2616 prot_mode = MWL8K_FRAME_PROT_11G;
2617 } else {
2618 switch (info->ht_operation_mode &
2619 IEEE80211_HT_OP_MODE_PROTECTION) {
2620 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2621 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2622 break;
2623 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2624 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2625 break;
2626 default:
2627 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2628 break;
2629 }
2630 }
2631 cmd->protection_mode = cpu_to_le16(prot_mode);
2632
2633 memcpy(cmd->supp_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
2634
2635 rc = mwl8k_post_cmd(hw, &cmd->header);
2636 kfree(cmd);
2637
2638 return rc;
2639 }
2640
2641 /*
2642 * CMD_SET_RATE.
2643 */
2644 struct mwl8k_cmd_update_rateset {
2645 struct mwl8k_cmd_pkt header;
2646 __u8 legacy_rates[14];
2647
2648 /* Bitmap for supported MCS codes. */
2649 __u8 mcs_set[16];
2650 __u8 reserved[16];
2651 } __attribute__((packed));
2652
2653 static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2654 struct ieee80211_vif *vif)
2655 {
2656 struct mwl8k_cmd_update_rateset *cmd;
2657 int rc;
2658
2659 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2660 if (cmd == NULL)
2661 return -ENOMEM;
2662
2663 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2664 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2665 memcpy(cmd->legacy_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
2666
2667 rc = mwl8k_post_cmd(hw, &cmd->header);
2668 kfree(cmd);
2669
2670 return rc;
2671 }
2672
2673 /*
2674 * CMD_USE_FIXED_RATE.
2675 */
2676 #define MWL8K_RATE_TABLE_SIZE 8
2677 #define MWL8K_UCAST_RATE 0
2678 #define MWL8K_USE_AUTO_RATE 0x0002
2679
2680 struct mwl8k_rate_entry {
2681 /* Set to 1 if HT rate, 0 if legacy. */
2682 __le32 is_ht_rate;
2683
2684 /* Set to 1 to use retry_count field. */
2685 __le32 enable_retry;
2686
2687 /* Specified legacy rate or MCS. */
2688 __le32 rate;
2689
2690 /* Number of allowed retries. */
2691 __le32 retry_count;
2692 } __attribute__((packed));
2693
2694 struct mwl8k_rate_table {
2695 /* 1 to allow specified rate and below */
2696 __le32 allow_rate_drop;
2697 __le32 num_rates;
2698 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2699 } __attribute__((packed));
2700
2701 struct mwl8k_cmd_use_fixed_rate {
2702 struct mwl8k_cmd_pkt header;
2703 __le32 action;
2704 struct mwl8k_rate_table rate_table;
2705
2706 /* Unicast, Broadcast or Multicast */
2707 __le32 rate_type;
2708 __le32 reserved1;
2709 __le32 reserved2;
2710 } __attribute__((packed));
2711
2712 static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2713 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2714 {
2715 struct mwl8k_cmd_use_fixed_rate *cmd;
2716 int count;
2717 int rc;
2718
2719 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2720 if (cmd == NULL)
2721 return -ENOMEM;
2722
2723 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2724 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2725
2726 cmd->action = cpu_to_le32(action);
2727 cmd->rate_type = cpu_to_le32(rate_type);
2728
2729 if (rate_table != NULL) {
2730 /*
2731 * Copy over each field manually so that endian
2732 * conversion can be done.
2733 */
2734 cmd->rate_table.allow_rate_drop =
2735 cpu_to_le32(rate_table->allow_rate_drop);
2736 cmd->rate_table.num_rates =
2737 cpu_to_le32(rate_table->num_rates);
2738
2739 for (count = 0; count < rate_table->num_rates; count++) {
2740 struct mwl8k_rate_entry *dst =
2741 &cmd->rate_table.rate_entry[count];
2742 struct mwl8k_rate_entry *src =
2743 &rate_table->rate_entry[count];
2744
2745 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2746 dst->enable_retry = cpu_to_le32(src->enable_retry);
2747 dst->rate = cpu_to_le32(src->rate);
2748 dst->retry_count = cpu_to_le32(src->retry_count);
2749 }
2750 }
2751
2752 rc = mwl8k_post_cmd(hw, &cmd->header);
2753 kfree(cmd);
2754
2755 return rc;
2756 }
2757
2758
2759 /*
2760 * Interrupt handling.
2761 */
2762 static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2763 {
2764 struct ieee80211_hw *hw = dev_id;
2765 struct mwl8k_priv *priv = hw->priv;
2766 u32 status;
2767
2768 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2769 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2770
2771 if (!status)
2772 return IRQ_NONE;
2773
2774 if (status & MWL8K_A2H_INT_TX_DONE)
2775 tasklet_schedule(&priv->tx_reclaim_task);
2776
2777 if (status & MWL8K_A2H_INT_RX_READY) {
2778 while (rxq_process(hw, 0, 1))
2779 rxq_refill(hw, 0, 1);
2780 }
2781
2782 if (status & MWL8K_A2H_INT_OPC_DONE) {
2783 if (priv->hostcmd_wait != NULL)
2784 complete(priv->hostcmd_wait);
2785 }
2786
2787 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2788 if (!mutex_is_locked(&priv->fw_mutex) &&
2789 priv->radio_on && priv->pending_tx_pkts)
2790 mwl8k_tx_start(priv);
2791 }
2792
2793 return IRQ_HANDLED;
2794 }
2795
2796
2797 /*
2798 * Core driver operations.
2799 */
2800 static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2801 {
2802 struct mwl8k_priv *priv = hw->priv;
2803 int index = skb_get_queue_mapping(skb);
2804 int rc;
2805
2806 if (priv->current_channel == NULL) {
2807 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2808 "disabled\n", wiphy_name(hw->wiphy));
2809 dev_kfree_skb(skb);
2810 return NETDEV_TX_OK;
2811 }
2812
2813 rc = mwl8k_txq_xmit(hw, index, skb);
2814
2815 return rc;
2816 }
2817
2818 static int mwl8k_start(struct ieee80211_hw *hw)
2819 {
2820 struct mwl8k_priv *priv = hw->priv;
2821 int rc;
2822
2823 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
2824 IRQF_SHARED, MWL8K_NAME, hw);
2825 if (rc) {
2826 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2827 wiphy_name(hw->wiphy));
2828 return -EIO;
2829 }
2830
2831 /* Enable tx reclaim tasklet */
2832 tasklet_enable(&priv->tx_reclaim_task);
2833
2834 /* Enable interrupts */
2835 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2836
2837 rc = mwl8k_fw_lock(hw);
2838 if (!rc) {
2839 rc = mwl8k_cmd_802_11_radio_enable(hw);
2840
2841 if (!priv->ap_fw) {
2842 if (!rc)
2843 rc = mwl8k_enable_sniffer(hw, 0);
2844
2845 if (!rc)
2846 rc = mwl8k_cmd_set_pre_scan(hw);
2847
2848 if (!rc)
2849 rc = mwl8k_cmd_set_post_scan(hw,
2850 "\x00\x00\x00\x00\x00\x00");
2851 }
2852
2853 if (!rc)
2854 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
2855
2856 if (!rc)
2857 rc = mwl8k_set_wmm(hw, 0);
2858
2859 mwl8k_fw_unlock(hw);
2860 }
2861
2862 if (rc) {
2863 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2864 free_irq(priv->pdev->irq, hw);
2865 tasklet_disable(&priv->tx_reclaim_task);
2866 }
2867
2868 return rc;
2869 }
2870
2871 static void mwl8k_stop(struct ieee80211_hw *hw)
2872 {
2873 struct mwl8k_priv *priv = hw->priv;
2874 int i;
2875
2876 mwl8k_cmd_802_11_radio_disable(hw);
2877
2878 ieee80211_stop_queues(hw);
2879
2880 /* Disable interrupts */
2881 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2882 free_irq(priv->pdev->irq, hw);
2883
2884 /* Stop finalize join worker */
2885 cancel_work_sync(&priv->finalize_join_worker);
2886 if (priv->beacon_skb != NULL)
2887 dev_kfree_skb(priv->beacon_skb);
2888
2889 /* Stop tx reclaim tasklet */
2890 tasklet_disable(&priv->tx_reclaim_task);
2891
2892 /* Return all skbs to mac80211 */
2893 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2894 mwl8k_txq_reclaim(hw, i, 1);
2895 }
2896
2897 static int mwl8k_add_interface(struct ieee80211_hw *hw,
2898 struct ieee80211_if_init_conf *conf)
2899 {
2900 struct mwl8k_priv *priv = hw->priv;
2901 struct mwl8k_vif *mwl8k_vif;
2902
2903 /*
2904 * We only support one active interface at a time.
2905 */
2906 if (priv->vif != NULL)
2907 return -EBUSY;
2908
2909 /*
2910 * We only support managed interfaces for now.
2911 */
2912 if (conf->type != NL80211_IFTYPE_STATION)
2913 return -EINVAL;
2914
2915 /*
2916 * Reject interface creation if sniffer mode is active, as
2917 * STA operation is mutually exclusive with hardware sniffer
2918 * mode.
2919 */
2920 if (priv->sniffer_enabled) {
2921 printk(KERN_INFO "%s: unable to create STA "
2922 "interface due to sniffer mode being enabled\n",
2923 wiphy_name(hw->wiphy));
2924 return -EINVAL;
2925 }
2926
2927 /* Clean out driver private area */
2928 mwl8k_vif = MWL8K_VIF(conf->vif);
2929 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2930
2931 /* Set and save the mac address */
2932 mwl8k_set_mac_addr(hw, conf->mac_addr);
2933 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
2934
2935 /* Back pointer to parent config block */
2936 mwl8k_vif->priv = priv;
2937
2938 /* Set Initial sequence number to zero */
2939 mwl8k_vif->seqno = 0;
2940
2941 priv->vif = conf->vif;
2942 priv->current_channel = NULL;
2943
2944 return 0;
2945 }
2946
2947 static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2948 struct ieee80211_if_init_conf *conf)
2949 {
2950 struct mwl8k_priv *priv = hw->priv;
2951
2952 if (priv->vif == NULL)
2953 return;
2954
2955 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2956
2957 priv->vif = NULL;
2958 }
2959
2960 static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2961 {
2962 struct ieee80211_conf *conf = &hw->conf;
2963 struct mwl8k_priv *priv = hw->priv;
2964 int rc;
2965
2966 if (conf->flags & IEEE80211_CONF_IDLE) {
2967 mwl8k_cmd_802_11_radio_disable(hw);
2968 priv->current_channel = NULL;
2969 return 0;
2970 }
2971
2972 rc = mwl8k_fw_lock(hw);
2973 if (rc)
2974 return rc;
2975
2976 rc = mwl8k_cmd_802_11_radio_enable(hw);
2977 if (rc)
2978 goto out;
2979
2980 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2981 if (rc)
2982 goto out;
2983
2984 priv->current_channel = conf->channel;
2985
2986 if (conf->power_level > 18)
2987 conf->power_level = 18;
2988 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2989 if (rc)
2990 goto out;
2991
2992 if (priv->ap_fw) {
2993 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
2994 if (!rc)
2995 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
2996 } else {
2997 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
2998 }
2999
3000 out:
3001 mwl8k_fw_unlock(hw);
3002
3003 return rc;
3004 }
3005
3006 static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
3007 struct ieee80211_vif *vif,
3008 struct ieee80211_bss_conf *info,
3009 u32 changed)
3010 {
3011 struct mwl8k_priv *priv = hw->priv;
3012 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3013 int rc;
3014
3015 if ((changed & BSS_CHANGED_ASSOC) == 0)
3016 return;
3017
3018 priv->capture_beacon = false;
3019
3020 rc = mwl8k_fw_lock(hw);
3021 if (rc)
3022 return;
3023
3024 if (info->assoc) {
3025 memcpy(&mwl8k_vif->bss_info, info,
3026 sizeof(struct ieee80211_bss_conf));
3027
3028 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
3029
3030 /* Install rates */
3031 rc = mwl8k_update_rateset(hw, vif);
3032 if (rc)
3033 goto out;
3034
3035 /* Turn on rate adaptation */
3036 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
3037 MWL8K_UCAST_RATE, NULL);
3038 if (rc)
3039 goto out;
3040
3041 /* Set radio preamble */
3042 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
3043 if (rc)
3044 goto out;
3045
3046 /* Set slot time */
3047 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
3048 if (rc)
3049 goto out;
3050
3051 /* Update peer rate info */
3052 rc = mwl8k_cmd_update_sta_db(hw, vif,
3053 MWL8K_STA_DB_MODIFY_ENTRY);
3054 if (rc)
3055 goto out;
3056
3057 /* Set AID */
3058 rc = mwl8k_cmd_set_aid(hw, vif);
3059 if (rc)
3060 goto out;
3061
3062 /*
3063 * Finalize the join. Tell rx handler to process
3064 * next beacon from our BSSID.
3065 */
3066 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
3067 priv->capture_beacon = true;
3068 } else {
3069 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
3070 memset(&mwl8k_vif->bss_info, 0,
3071 sizeof(struct ieee80211_bss_conf));
3072 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
3073 }
3074
3075 out:
3076 mwl8k_fw_unlock(hw);
3077 }
3078
3079 static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3080 int mc_count, struct dev_addr_list *mclist)
3081 {
3082 struct mwl8k_cmd_pkt *cmd;
3083
3084 /*
3085 * Synthesize and return a command packet that programs the
3086 * hardware multicast address filter. At this point we don't
3087 * know whether FIF_ALLMULTI is being requested, but if it is,
3088 * we'll end up throwing this packet away and creating a new
3089 * one in mwl8k_configure_filter().
3090 */
3091 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
3092
3093 return (unsigned long)cmd;
3094 }
3095
3096 static int
3097 mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3098 unsigned int changed_flags,
3099 unsigned int *total_flags)
3100 {
3101 struct mwl8k_priv *priv = hw->priv;
3102
3103 /*
3104 * Hardware sniffer mode is mutually exclusive with STA
3105 * operation, so refuse to enable sniffer mode if a STA
3106 * interface is active.
3107 */
3108 if (priv->vif != NULL) {
3109 if (net_ratelimit())
3110 printk(KERN_INFO "%s: not enabling sniffer "
3111 "mode because STA interface is active\n",
3112 wiphy_name(hw->wiphy));
3113 return 0;
3114 }
3115
3116 if (!priv->sniffer_enabled) {
3117 if (mwl8k_enable_sniffer(hw, 1))
3118 return 0;
3119 priv->sniffer_enabled = true;
3120 }
3121
3122 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3123 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3124 FIF_OTHER_BSS;
3125
3126 return 1;
3127 }
3128
3129 static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3130 unsigned int changed_flags,
3131 unsigned int *total_flags,
3132 u64 multicast)
3133 {
3134 struct mwl8k_priv *priv = hw->priv;
3135 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3136
3137 /*
3138 * AP firmware doesn't allow fine-grained control over
3139 * the receive filter.
3140 */
3141 if (priv->ap_fw) {
3142 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3143 kfree(cmd);
3144 return;
3145 }
3146
3147 /*
3148 * Enable hardware sniffer mode if FIF_CONTROL or
3149 * FIF_OTHER_BSS is requested.
3150 */
3151 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3152 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3153 kfree(cmd);
3154 return;
3155 }
3156
3157 /* Clear unsupported feature flags */
3158 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3159
3160 if (mwl8k_fw_lock(hw))
3161 return;
3162
3163 if (priv->sniffer_enabled) {
3164 mwl8k_enable_sniffer(hw, 0);
3165 priv->sniffer_enabled = false;
3166 }
3167
3168 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
3169 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3170 /*
3171 * Disable the BSS filter.
3172 */
3173 mwl8k_cmd_set_pre_scan(hw);
3174 } else {
3175 u8 *bssid;
3176
3177 /*
3178 * Enable the BSS filter.
3179 *
3180 * If there is an active STA interface, use that
3181 * interface's BSSID, otherwise use a dummy one
3182 * (where the OUI part needs to be nonzero for
3183 * the BSSID to be accepted by POST_SCAN).
3184 */
3185 bssid = "\x01\x00\x00\x00\x00\x00";
3186 if (priv->vif != NULL)
3187 bssid = MWL8K_VIF(priv->vif)->bssid;
3188
3189 mwl8k_cmd_set_post_scan(hw, bssid);
3190 }
3191 }
3192
3193 /*
3194 * If FIF_ALLMULTI is being requested, throw away the command
3195 * packet that ->prepare_multicast() built and replace it with
3196 * a command packet that enables reception of all multicast
3197 * packets.
3198 */
3199 if (*total_flags & FIF_ALLMULTI) {
3200 kfree(cmd);
3201 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3202 }
3203
3204 if (cmd != NULL) {
3205 mwl8k_post_cmd(hw, cmd);
3206 kfree(cmd);
3207 }
3208
3209 mwl8k_fw_unlock(hw);
3210 }
3211
3212 static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3213 {
3214 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
3215 }
3216
3217 static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3218 const struct ieee80211_tx_queue_params *params)
3219 {
3220 struct mwl8k_priv *priv = hw->priv;
3221 int rc;
3222
3223 rc = mwl8k_fw_lock(hw);
3224 if (!rc) {
3225 if (!priv->wmm_enabled)
3226 rc = mwl8k_set_wmm(hw, 1);
3227
3228 if (!rc)
3229 rc = mwl8k_set_edca_params(hw, queue,
3230 params->cw_min,
3231 params->cw_max,
3232 params->aifs,
3233 params->txop);
3234
3235 mwl8k_fw_unlock(hw);
3236 }
3237
3238 return rc;
3239 }
3240
3241 static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3242 struct ieee80211_tx_queue_stats *stats)
3243 {
3244 struct mwl8k_priv *priv = hw->priv;
3245 struct mwl8k_tx_queue *txq;
3246 int index;
3247
3248 spin_lock_bh(&priv->tx_lock);
3249 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3250 txq = priv->txq + index;
3251 memcpy(&stats[index], &txq->stats,
3252 sizeof(struct ieee80211_tx_queue_stats));
3253 }
3254 spin_unlock_bh(&priv->tx_lock);
3255
3256 return 0;
3257 }
3258
3259 static int mwl8k_get_stats(struct ieee80211_hw *hw,
3260 struct ieee80211_low_level_stats *stats)
3261 {
3262 return mwl8k_cmd_802_11_get_stat(hw, stats);
3263 }
3264
3265 static const struct ieee80211_ops mwl8k_ops = {
3266 .tx = mwl8k_tx,
3267 .start = mwl8k_start,
3268 .stop = mwl8k_stop,
3269 .add_interface = mwl8k_add_interface,
3270 .remove_interface = mwl8k_remove_interface,
3271 .config = mwl8k_config,
3272 .bss_info_changed = mwl8k_bss_info_changed,
3273 .prepare_multicast = mwl8k_prepare_multicast,
3274 .configure_filter = mwl8k_configure_filter,
3275 .set_rts_threshold = mwl8k_set_rts_threshold,
3276 .conf_tx = mwl8k_conf_tx,
3277 .get_tx_stats = mwl8k_get_tx_stats,
3278 .get_stats = mwl8k_get_stats,
3279 };
3280
3281 static void mwl8k_tx_reclaim_handler(unsigned long data)
3282 {
3283 int i;
3284 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3285 struct mwl8k_priv *priv = hw->priv;
3286
3287 spin_lock_bh(&priv->tx_lock);
3288 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3289 mwl8k_txq_reclaim(hw, i, 0);
3290
3291 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
3292 complete(priv->tx_wait);
3293 priv->tx_wait = NULL;
3294 }
3295 spin_unlock_bh(&priv->tx_lock);
3296 }
3297
3298 static void mwl8k_finalize_join_worker(struct work_struct *work)
3299 {
3300 struct mwl8k_priv *priv =
3301 container_of(work, struct mwl8k_priv, finalize_join_worker);
3302 struct sk_buff *skb = priv->beacon_skb;
3303 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
3304
3305 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
3306 dev_kfree_skb(skb);
3307
3308 priv->beacon_skb = NULL;
3309 }
3310
3311 enum {
3312 MWL8687 = 0,
3313 MWL8366,
3314 };
3315
3316 static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
3317 {
3318 .part_name = "88w8687",
3319 .helper_image = "mwl8k/helper_8687.fw",
3320 .fw_image = "mwl8k/fmimage_8687.fw",
3321 .rxd_ops = &rxd_8687_ops,
3322 .modes = BIT(NL80211_IFTYPE_STATION),
3323 },
3324 {
3325 .part_name = "88w8366",
3326 .helper_image = "mwl8k/helper_8366.fw",
3327 .fw_image = "mwl8k/fmimage_8366.fw",
3328 .rxd_ops = &rxd_8366_ops,
3329 .modes = 0,
3330 },
3331 };
3332
3333 static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
3334 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3335 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3336 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
3337 { },
3338 };
3339 MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3340
3341 static int __devinit mwl8k_probe(struct pci_dev *pdev,
3342 const struct pci_device_id *id)
3343 {
3344 static int printed_version = 0;
3345 struct ieee80211_hw *hw;
3346 struct mwl8k_priv *priv;
3347 int rc;
3348 int i;
3349
3350 if (!printed_version) {
3351 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3352 printed_version = 1;
3353 }
3354
3355 rc = pci_enable_device(pdev);
3356 if (rc) {
3357 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3358 MWL8K_NAME);
3359 return rc;
3360 }
3361
3362 rc = pci_request_regions(pdev, MWL8K_NAME);
3363 if (rc) {
3364 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3365 MWL8K_NAME);
3366 goto err_disable_device;
3367 }
3368
3369 pci_set_master(pdev);
3370
3371 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3372 if (hw == NULL) {
3373 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3374 rc = -ENOMEM;
3375 goto err_free_reg;
3376 }
3377
3378 priv = hw->priv;
3379 priv->hw = hw;
3380 priv->pdev = pdev;
3381 priv->device_info = &mwl8k_info_tbl[id->driver_data];
3382 priv->rxd_ops = priv->device_info->rxd_ops;
3383 priv->sniffer_enabled = false;
3384 priv->wmm_enabled = false;
3385 priv->pending_tx_pkts = 0;
3386
3387 SET_IEEE80211_DEV(hw, &pdev->dev);
3388 pci_set_drvdata(pdev, hw);
3389
3390 priv->sram = pci_iomap(pdev, 0, 0x10000);
3391 if (priv->sram == NULL) {
3392 printk(KERN_ERR "%s: Cannot map device SRAM\n",
3393 wiphy_name(hw->wiphy));
3394 goto err_iounmap;
3395 }
3396
3397 /*
3398 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3399 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3400 */
3401 priv->regs = pci_iomap(pdev, 1, 0x10000);
3402 if (priv->regs == NULL) {
3403 priv->regs = pci_iomap(pdev, 2, 0x10000);
3404 if (priv->regs == NULL) {
3405 printk(KERN_ERR "%s: Cannot map device registers\n",
3406 wiphy_name(hw->wiphy));
3407 goto err_iounmap;
3408 }
3409 }
3410
3411 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3412 priv->band.band = IEEE80211_BAND_2GHZ;
3413 priv->band.channels = priv->channels;
3414 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3415 priv->band.bitrates = priv->rates;
3416 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3417 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3418
3419 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3420 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3421
3422 /*
3423 * Extra headroom is the size of the required DMA header
3424 * minus the size of the smallest 802.11 frame (CTS frame).
3425 */
3426 hw->extra_tx_headroom =
3427 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3428
3429 hw->channel_change_time = 10;
3430
3431 hw->queues = MWL8K_TX_QUEUES;
3432
3433 hw->wiphy->interface_modes = priv->device_info->modes;
3434
3435 /* Set rssi and noise values to dBm */
3436 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
3437 hw->vif_data_size = sizeof(struct mwl8k_vif);
3438 priv->vif = NULL;
3439
3440 /* Set default radio state and preamble */
3441 priv->radio_on = 0;
3442 priv->radio_short_preamble = 0;
3443
3444 /* Finalize join worker */
3445 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3446
3447 /* TX reclaim tasklet */
3448 tasklet_init(&priv->tx_reclaim_task,
3449 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3450 tasklet_disable(&priv->tx_reclaim_task);
3451
3452 /* Power management cookie */
3453 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3454 if (priv->cookie == NULL)
3455 goto err_iounmap;
3456
3457 rc = mwl8k_rxq_init(hw, 0);
3458 if (rc)
3459 goto err_iounmap;
3460 rxq_refill(hw, 0, INT_MAX);
3461
3462 mutex_init(&priv->fw_mutex);
3463 priv->fw_mutex_owner = NULL;
3464 priv->fw_mutex_depth = 0;
3465 priv->hostcmd_wait = NULL;
3466
3467 spin_lock_init(&priv->tx_lock);
3468
3469 priv->tx_wait = NULL;
3470
3471 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3472 rc = mwl8k_txq_init(hw, i);
3473 if (rc)
3474 goto err_free_queues;
3475 }
3476
3477 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3478 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3479 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3480 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3481
3482 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
3483 IRQF_SHARED, MWL8K_NAME, hw);
3484 if (rc) {
3485 printk(KERN_ERR "%s: failed to register IRQ handler\n",
3486 wiphy_name(hw->wiphy));
3487 goto err_free_queues;
3488 }
3489
3490 /* Reset firmware and hardware */
3491 mwl8k_hw_reset(priv);
3492
3493 /* Ask userland hotplug daemon for the device firmware */
3494 rc = mwl8k_request_firmware(priv);
3495 if (rc) {
3496 printk(KERN_ERR "%s: Firmware files not found\n",
3497 wiphy_name(hw->wiphy));
3498 goto err_free_irq;
3499 }
3500
3501 /* Load firmware into hardware */
3502 rc = mwl8k_load_firmware(hw);
3503 if (rc) {
3504 printk(KERN_ERR "%s: Cannot start firmware\n",
3505 wiphy_name(hw->wiphy));
3506 goto err_stop_firmware;
3507 }
3508
3509 /* Reclaim memory once firmware is successfully loaded */
3510 mwl8k_release_firmware(priv);
3511
3512 /*
3513 * Temporarily enable interrupts. Initial firmware host
3514 * commands use interrupts and avoids polling. Disable
3515 * interrupts when done.
3516 */
3517 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3518
3519 /* Get config data, mac addrs etc */
3520 if (priv->ap_fw) {
3521 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3522 if (!rc)
3523 rc = mwl8k_cmd_set_hw_spec(hw);
3524 } else {
3525 rc = mwl8k_cmd_get_hw_spec_sta(hw);
3526 }
3527 if (rc) {
3528 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3529 wiphy_name(hw->wiphy));
3530 goto err_stop_firmware;
3531 }
3532
3533 /* Turn radio off */
3534 rc = mwl8k_cmd_802_11_radio_disable(hw);
3535 if (rc) {
3536 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
3537 goto err_stop_firmware;
3538 }
3539
3540 /* Clear MAC address */
3541 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3542 if (rc) {
3543 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3544 wiphy_name(hw->wiphy));
3545 goto err_stop_firmware;
3546 }
3547
3548 /* Disable interrupts */
3549 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3550 free_irq(priv->pdev->irq, hw);
3551
3552 rc = ieee80211_register_hw(hw);
3553 if (rc) {
3554 printk(KERN_ERR "%s: Cannot register device\n",
3555 wiphy_name(hw->wiphy));
3556 goto err_stop_firmware;
3557 }
3558
3559 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
3560 wiphy_name(hw->wiphy), priv->device_info->part_name,
3561 priv->hw_rev, hw->wiphy->perm_addr,
3562 priv->ap_fw ? "AP" : "STA",
3563 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3564 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
3565
3566 return 0;
3567
3568 err_stop_firmware:
3569 mwl8k_hw_reset(priv);
3570 mwl8k_release_firmware(priv);
3571
3572 err_free_irq:
3573 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3574 free_irq(priv->pdev->irq, hw);
3575
3576 err_free_queues:
3577 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3578 mwl8k_txq_deinit(hw, i);
3579 mwl8k_rxq_deinit(hw, 0);
3580
3581 err_iounmap:
3582 if (priv->cookie != NULL)
3583 pci_free_consistent(priv->pdev, 4,
3584 priv->cookie, priv->cookie_dma);
3585
3586 if (priv->regs != NULL)
3587 pci_iounmap(pdev, priv->regs);
3588
3589 if (priv->sram != NULL)
3590 pci_iounmap(pdev, priv->sram);
3591
3592 pci_set_drvdata(pdev, NULL);
3593 ieee80211_free_hw(hw);
3594
3595 err_free_reg:
3596 pci_release_regions(pdev);
3597
3598 err_disable_device:
3599 pci_disable_device(pdev);
3600
3601 return rc;
3602 }
3603
3604 static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
3605 {
3606 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3607 }
3608
3609 static void __devexit mwl8k_remove(struct pci_dev *pdev)
3610 {
3611 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3612 struct mwl8k_priv *priv;
3613 int i;
3614
3615 if (hw == NULL)
3616 return;
3617 priv = hw->priv;
3618
3619 ieee80211_stop_queues(hw);
3620
3621 ieee80211_unregister_hw(hw);
3622
3623 /* Remove tx reclaim tasklet */
3624 tasklet_kill(&priv->tx_reclaim_task);
3625
3626 /* Stop hardware */
3627 mwl8k_hw_reset(priv);
3628
3629 /* Return all skbs to mac80211 */
3630 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3631 mwl8k_txq_reclaim(hw, i, 1);
3632
3633 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3634 mwl8k_txq_deinit(hw, i);
3635
3636 mwl8k_rxq_deinit(hw, 0);
3637
3638 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
3639
3640 pci_iounmap(pdev, priv->regs);
3641 pci_iounmap(pdev, priv->sram);
3642 pci_set_drvdata(pdev, NULL);
3643 ieee80211_free_hw(hw);
3644 pci_release_regions(pdev);
3645 pci_disable_device(pdev);
3646 }
3647
3648 static struct pci_driver mwl8k_driver = {
3649 .name = MWL8K_NAME,
3650 .id_table = mwl8k_pci_id_table,
3651 .probe = mwl8k_probe,
3652 .remove = __devexit_p(mwl8k_remove),
3653 .shutdown = __devexit_p(mwl8k_shutdown),
3654 };
3655
3656 static int __init mwl8k_init(void)
3657 {
3658 return pci_register_driver(&mwl8k_driver);
3659 }
3660
3661 static void __exit mwl8k_exit(void)
3662 {
3663 pci_unregister_driver(&mwl8k_driver);
3664 }
3665
3666 module_init(mwl8k_init);
3667 module_exit(mwl8k_exit);
3668
3669 MODULE_DESCRIPTION(MWL8K_DESC);
3670 MODULE_VERSION(MWL8K_VERSION);
3671 MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3672 MODULE_LICENSE("GPL");
Ubuntu Artful kernel mirror