5 * Common code specific definitions for mac80211 Prism54 drivers
7 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
8 * Copyright (c) 2007, Christian Lamparter <chunkeey@web.de>
11 * - the islsm (softmac prism54) driver, which is:
12 * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
14 * - LMAC API interface header file for STLC4560 (lmac_longbow.h)
15 * Copyright (C) 2007 Conexant Systems, Inc.
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
26 } __attribute__((packed
));
28 #define PDR_SYNTH_FRONTEND_MASK 0x0007
29 #define PDR_SYNTH_IQ_CAL_MASK 0x0018
30 #define PDR_SYNTH_IQ_CAL_PA_DETECTOR 0x0000
31 #define PDR_SYNTH_IQ_CAL_DISABLED 0x0008
32 #define PDR_SYNTH_IQ_CAL_ZIF 0x0010
33 #define PDR_SYNTH_FAA_SWITCH_MASK 0x0020
34 #define PDR_SYNTH_FAA_SWITCH_ENABLED 0x0001
35 #define PDR_SYNTH_24_GHZ_MASK 0x0040
36 #define PDR_SYNTH_24_GHZ_DISABLED 0x0040
37 #define PDR_SYNTH_5_GHZ_MASK 0x0080
38 #define PDR_SYNTH_5_GHZ_DISABLED 0x0080
39 #define PDR_SYNTH_RX_DIV_MASK 0x0100
40 #define PDR_SYNTH_RX_DIV_SUPPORTED 0x0100
41 #define PDR_SYNTH_TX_DIV_MASK 0x0200
42 #define PDR_SYNTH_TX_DIV_SUPPORTED 0x0200
44 struct bootrec_exp_if
{
50 } __attribute__((packed
));
52 #define BR_DESC_PRIV_CAP_WEP BIT(0)
53 #define BR_DESC_PRIV_CAP_TKIP BIT(1)
54 #define BR_DESC_PRIV_CAP_MICHAEL BIT(2)
55 #define BR_DESC_PRIV_CAP_CCX_CP BIT(3)
56 #define BR_DESC_PRIV_CAP_CCX_MIC BIT(4)
57 #define BR_DESC_PRIV_CAP_AESCCMP BIT(5)
75 } __attribute__((packed
));
77 #define BR_CODE_MIN 0x80000000
78 #define BR_CODE_COMPONENT_ID 0x80000001
79 #define BR_CODE_COMPONENT_VERSION 0x80000002
80 #define BR_CODE_DEPENDENT_IF 0x80000003
81 #define BR_CODE_EXPOSED_IF 0x80000004
82 #define BR_CODE_DESCR 0x80000101
83 #define BR_CODE_MAX 0x8FFFFFFF
84 #define BR_CODE_END_OF_BRA 0xFF0000FF
85 #define LEGACY_BR_CODE_END_OF_BRA 0xFFFFFFFF
87 #define P54_HDR_FLAG_CONTROL BIT(15)
88 #define P54_HDR_FLAG_CONTROL_OPSET (BIT(15) + BIT(0))
90 #define P54_HDR_FLAG_DATA_ALIGN BIT(14)
91 #define P54_HDR_FLAG_DATA_OUT_PROMISC BIT(0)
92 #define P54_HDR_FLAG_DATA_OUT_TIMESTAMP BIT(1)
93 #define P54_HDR_FLAG_DATA_OUT_SEQNR BIT(2)
94 #define P54_HDR_FLAG_DATA_OUT_BIT3 BIT(3)
95 #define P54_HDR_FLAG_DATA_OUT_BURST BIT(4)
96 #define P54_HDR_FLAG_DATA_OUT_NOCANCEL BIT(5)
97 #define P54_HDR_FLAG_DATA_OUT_CLEARTIM BIT(6)
98 #define P54_HDR_FLAG_DATA_OUT_HITCHHIKE BIT(7)
99 #define P54_HDR_FLAG_DATA_OUT_COMPRESS BIT(8)
100 #define P54_HDR_FLAG_DATA_OUT_CONCAT BIT(9)
101 #define P54_HDR_FLAG_DATA_OUT_PCS_ACCEPT BIT(10)
102 #define P54_HDR_FLAG_DATA_OUT_WAITEOSP BIT(11)
104 #define P54_HDR_FLAG_DATA_IN_FCS_GOOD BIT(0)
105 #define P54_HDR_FLAG_DATA_IN_MATCH_MAC BIT(1)
106 #define P54_HDR_FLAG_DATA_IN_MCBC BIT(2)
107 #define P54_HDR_FLAG_DATA_IN_BEACON BIT(3)
108 #define P54_HDR_FLAG_DATA_IN_MATCH_BSS BIT(4)
109 #define P54_HDR_FLAG_DATA_IN_BCAST_BSS BIT(5)
110 #define P54_HDR_FLAG_DATA_IN_DATA BIT(6)
111 #define P54_HDR_FLAG_DATA_IN_TRUNCATED BIT(7)
112 #define P54_HDR_FLAG_DATA_IN_BIT8 BIT(8)
113 #define P54_HDR_FLAG_DATA_IN_TRANSPARENT BIT(9)
115 /* PDA defines are Copyright (C) 2005 Nokia Corporation (taken from islsm_pda.h) */
118 __le16 len
; /* includes both code and data */
121 } __attribute__ ((packed
));
123 struct eeprom_pda_wrap
{
129 } __attribute__ ((packed
));
131 struct pda_iq_autocal_entry
{
134 } __attribute__ ((packed
));
136 struct pda_channel_output_limit
{
144 } __attribute__ ((packed
));
146 struct pda_pa_curve_data_sample_rev0
{
150 } __attribute__ ((packed
));
152 struct pda_pa_curve_data_sample_rev1
{
160 } __attribute__ ((packed
));
162 struct p54_pa_curve_data_sample
{
171 } __attribute__ ((packed
));
173 struct pda_pa_curve_data
{
176 u8 points_per_channel
;
179 } __attribute__ ((packed
));
182 * this defines the PDR codes used to build PDAs as defined in document
183 * number 553155. The current implementation mirrors version 1.1 of the
184 * document and lists only PDRs supported by the ARM platform.
187 /* common and choice range (0x0000 - 0x0fff) */
188 #define PDR_END 0x0000
189 #define PDR_MANUFACTURING_PART_NUMBER 0x0001
190 #define PDR_PDA_VERSION 0x0002
191 #define PDR_NIC_SERIAL_NUMBER 0x0003
193 #define PDR_MAC_ADDRESS 0x0101
194 #define PDR_REGULATORY_DOMAIN_LIST 0x0103
195 #define PDR_TEMPERATURE_TYPE 0x0107
197 #define PDR_PRISM_PCI_IDENTIFIER 0x0402
199 /* ARM range (0x1000 - 0x1fff) */
200 #define PDR_COUNTRY_INFORMATION 0x1000
201 #define PDR_INTERFACE_LIST 0x1001
202 #define PDR_HARDWARE_PLATFORM_COMPONENT_ID 0x1002
203 #define PDR_OEM_NAME 0x1003
204 #define PDR_PRODUCT_NAME 0x1004
205 #define PDR_UTF8_OEM_NAME 0x1005
206 #define PDR_UTF8_PRODUCT_NAME 0x1006
207 #define PDR_COUNTRY_LIST 0x1007
208 #define PDR_DEFAULT_COUNTRY 0x1008
210 #define PDR_ANTENNA_GAIN 0x1100
212 #define PDR_PRISM_INDIGO_PA_CALIBRATION_DATA 0x1901
213 #define PDR_RSSI_LINEAR_APPROXIMATION 0x1902
214 #define PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS 0x1903
215 #define PDR_PRISM_PA_CAL_CURVE_DATA 0x1904
216 #define PDR_RSSI_LINEAR_APPROXIMATION_DUAL_BAND 0x1905
217 #define PDR_PRISM_ZIF_TX_IQ_CALIBRATION 0x1906
218 #define PDR_REGULATORY_POWER_LIMITS 0x1907
219 #define PDR_RSSI_LINEAR_APPROXIMATION_EXTENDED 0x1908
220 #define PDR_RADIATED_TRANSMISSION_CORRECTION 0x1909
221 #define PDR_PRISM_TX_IQ_CALIBRATION 0x190a
223 /* reserved range (0x2000 - 0x7fff) */
225 /* customer range (0x8000 - 0xffff) */
226 #define PDR_BASEBAND_REGISTERS 0x8000
227 #define PDR_PER_CHANNEL_BASEBAND_REGISTERS 0x8001
229 /* PDR definitions for default country & country list */
230 #define PDR_COUNTRY_CERT_CODE 0x80
231 #define PDR_COUNTRY_CERT_CODE_REAL 0x00
232 #define PDR_COUNTRY_CERT_CODE_PSEUDO 0x80
233 #define PDR_COUNTRY_CERT_BAND 0x40
234 #define PDR_COUNTRY_CERT_BAND_2GHZ 0x00
235 #define PDR_COUNTRY_CERT_BAND_5GHZ 0x40
236 #define PDR_COUNTRY_CERT_IODOOR 0x30
237 #define PDR_COUNTRY_CERT_IODOOR_BOTH 0x00
238 #define PDR_COUNTRY_CERT_IODOOR_INDOOR 0x20
239 #define PDR_COUNTRY_CERT_IODOOR_OUTDOOR 0x30
240 #define PDR_COUNTRY_CERT_INDEX 0x0F
242 /* stored in skb->cb */
248 struct p54_eeprom_lm86
{
252 } __attribute__ ((packed
));
254 enum p54_rx_decrypt_status
{
255 P54_DECRYPT_NONE
= 0,
258 P54_DECRYPT_NOMICHAEL
,
259 P54_DECRYPT_NOCKIPMIC
,
260 P54_DECRYPT_FAIL_WEP
,
261 P54_DECRYPT_FAIL_TKIP
,
262 P54_DECRYPT_FAIL_MICHAEL
,
263 P54_DECRYPT_FAIL_CKIPKP
,
264 P54_DECRYPT_FAIL_CKIPMIC
,
265 P54_DECRYPT_FAIL_AESCCMP
281 } __attribute__ ((packed
));
287 P54_TRAP_FAA_RADIO_ON
,
288 P54_TRAP_FAA_RADIO_OFF
,
299 } __attribute__ ((packed
));
301 enum p54_frame_sent_status
{
308 struct p54_frame_sent
{
316 } __attribute__ ((packed
));
318 enum p54_tx_data_crypt
{
322 P54_CRYPTO_TKIPMICHAEL
,
323 P54_CRYPTO_CCX_WEPMIC
,
324 P54_CRYPTO_CCX_KPMIC
,
344 } __attribute__ ((packed
));
346 #define P54_FILTER_TYPE_NONE 0
347 #define P54_FILTER_TYPE_STATION BIT(0)
348 #define P54_FILTER_TYPE_IBSS BIT(1)
349 #define P54_FILTER_TYPE_AP BIT(2)
350 #define P54_FILTER_TYPE_TRANSPARENT BIT(3)
351 #define P54_FILTER_TYPE_PROMISCUOUS BIT(4)
352 #define P54_FILTER_TYPE_HIBERNATE BIT(5)
353 #define P54_FILTER_TYPE_NOACK BIT(6)
354 #define P54_FILTER_TYPE_RX_DISABLED BIT(7)
356 struct p54_setup_mac
{
358 u8 mac_addr
[ETH_ALEN
];
364 __le32 basic_rate_mask
;
371 } v1
__attribute__ ((packed
));
378 __le32 basic_rate_mask
;
381 u8 rx_rssi_threshold
;
384 __le16 lpf_bandwidth
;
385 __le16 osc_start_delay
;
386 } v2
__attribute__ ((packed
));
387 } __attribute__ ((packed
));
388 } __attribute__ ((packed
));
390 #define P54_SETUP_V1_LEN 40
391 #define P54_SETUP_V2_LEN (sizeof(struct p54_setup_mac))
393 #define P54_SCAN_EXIT BIT(0)
394 #define P54_SCAN_TRAP BIT(1)
395 #define P54_SCAN_ACTIVE BIT(2)
396 #define P54_SCAN_FILTER BIT(3)
402 struct pda_iq_autocal_entry iq_autocal
;
403 u8 pa_points_per_curve
;
409 struct p54_pa_curve_data_sample curve_data
[8];
418 } v1
__attribute__ ((packed
));
421 __le32 basic_rate_mask
;
425 } v2
__attribute__ ((packed
));
426 } __attribute__ ((packed
));
427 } __attribute__ ((packed
));
429 #define P54_SCAN_V1_LEN (sizeof(struct p54_scan)-12)
430 #define P54_SCAN_V2_LEN (sizeof(struct p54_scan))
434 __le16 led_temporary
;
435 __le16 led_permanent
;
437 } __attribute__ ((packed
));
444 struct p54_edcf_queue_param queue
[8];
447 __le16 round_trip_delay
;
448 } __attribute__ ((packed
));
450 struct p54_statistics
{
460 __le32 sample_noise
[8];
463 } __attribute__ ((packed
));
465 struct p54_xbow_synth
{
470 } __attribute__ ((packed
));
474 } __attribute__ ((packed
));
476 struct p54_keycache
{
484 } __attribute__ ((packed
));
491 __le16 durations
[32];
492 } __attribute__ ((packed
));
494 struct p54_psm_interval
{
497 } __attribute__ ((packed
));
499 #define P54_PSM BIT(0)
500 #define P54_PSM_DTIM BIT(1)
501 #define P54_PSM_MCBC BIT(2)
502 #define P54_PSM_CHECKSUM BIT(3)
503 #define P54_PSM_SKIP_MORE_DATA BIT(4)
504 #define P54_PSM_BEACON_TIMEOUT BIT(5)
505 #define P54_PSM_HFOSLEEP BIT(6)
506 #define P54_PSM_AUTOSWITCH_SLEEP BIT(7)
507 #define P54_PSM_LPIT BIT(8)
508 #define P54_PSM_BF_UCAST_SKIP BIT(9)
509 #define P54_PSM_BF_MCAST_SKIP BIT(10)
514 struct p54_psm_interval intervals
[4];
515 u8 beacon_rssi_skip_max
;
516 u8 rssi_delta_threshold
;
519 } __attribute__ ((packed
));
521 #define MC_FILTER_ADDRESS_NUM 4
523 struct p54_group_address_table
{
524 __le16 filter_enable
;
526 u8 mac_list
[MC_FILTER_ADDRESS_NUM
][ETH_ALEN
];
527 } __attribute__ ((packed
));
529 struct p54_txcancel
{
531 } __attribute__ ((packed
));
533 struct p54_sta_unlock
{
536 } __attribute__ ((packed
));
538 #define P54_TIM_CLEAR BIT(15)
543 } __attribute__ ((packed
));
545 struct p54_cce_quiet
{
547 } __attribute__ ((packed
));
549 struct p54_bt_balancer
{
552 } __attribute__ ((packed
));
554 struct p54_arp_table
{
555 __le16 filter_enable
;
557 } __attribute__ ((packed
));
559 #endif /* P54COMMON_H */