drivers/net/wireless/p54/p54pci.c

   1
   2 /*
   3  * Linux device driver for PCI based Prism54
   4  *
   5  * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
   6  * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
   7  *
   8  * Based on the islsm (softmac prism54) driver, which is:
   9  * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/pci.h>
  18 #include <linux/firmware.h>
  19 #include <linux/etherdevice.h>
  20 #include <linux/delay.h>
  21 #include <linux/completion.h>
  22 #include <net/mac80211.h>
  23
  24 #include "p54.h"
  25 #include "p54pci.h"
  26
  27 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  28 MODULE_DESCRIPTION("Prism54 PCI wireless driver");
  29 MODULE_LICENSE("GPL");
  30 MODULE_ALIAS("prism54pci");
  31 MODULE_FIRMWARE("isl3886pci");
  32
  33 static struct pci_device_id p54p_table[] __devinitdata = {
  34         /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
  35         { PCI_DEVICE(0x1260, 0x3890) },
  36         /* 3COM 3CRWE154G72 Wireless LAN adapter */
  37         { PCI_DEVICE(0x10b7, 0x6001) },
  38         /* Intersil PRISM Indigo Wireless LAN adapter */
  39         { PCI_DEVICE(0x1260, 0x3877) },
  40         /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
  41         { PCI_DEVICE(0x1260, 0x3886) },
  42         { },
  43 };
  44
  45 MODULE_DEVICE_TABLE(pci, p54p_table);
  46
  47 static int p54p_upload_firmware(struct ieee80211_hw *dev)
  48 {
  49         struct p54p_priv *priv = dev->priv;
  50         __le32 reg;
  51         int err;
  52         __le32 *data;
  53         u32 remains, left, device_addr;
  54
  55         P54P_WRITE(int_enable, cpu_to_le32(0));
  56         P54P_READ(int_enable);
  57         udelay(10);
  58
  59         reg = P54P_READ(ctrl_stat);
  60         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  61         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
  62         P54P_WRITE(ctrl_stat, reg);
  63         P54P_READ(ctrl_stat);
  64         udelay(10);
  65
  66         reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  67         P54P_WRITE(ctrl_stat, reg);
  68         wmb();
  69         udelay(10);
  70
  71         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  72         P54P_WRITE(ctrl_stat, reg);
  73         wmb();
  74
  75         /* wait for the firmware to reset properly */
  76         mdelay(10);
  77
  78         err = p54_parse_firmware(dev, priv->firmware);
  79         if (err)
  80                 return err;
  81
  82         if (priv->common.fw_interface != FW_LM86) {
  83                 dev_err(&priv->pdev->dev, "wrong firmware, "
  84                         "please get a LM86(PCI) firmware a try again.\n");
  85                 return -EINVAL;
  86         }
  87
  88         data = (__le32 *) priv->firmware->data;
  89         remains = priv->firmware->size;
  90         device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
  91         while (remains) {
  92                 u32 i = 0;
  93                 left = min((u32)0x1000, remains);
  94                 P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
  95                 P54P_READ(int_enable);
  96
  97                 device_addr += 0x1000;
  98                 while (i < left) {
  99                         P54P_WRITE(direct_mem_win[i], *data++);
 100                         i += sizeof(u32);
 101                 }
 102
 103                 remains -= left;
 104                 P54P_READ(int_enable);
 105         }
 106
 107         reg = P54P_READ(ctrl_stat);
 108         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
 109         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
 110         reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
 111         P54P_WRITE(ctrl_stat, reg);
 112         P54P_READ(ctrl_stat);
 113         udelay(10);
 114
 115         reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
 116         P54P_WRITE(ctrl_stat, reg);
 117         wmb();
 118         udelay(10);
 119
 120         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
 121         P54P_WRITE(ctrl_stat, reg);
 122         wmb();
 123         udelay(10);
 124
 125         /* wait for the firmware to boot properly */
 126         mdelay(100);
 127
 128         return 0;
 129 }
 130
 131 static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
 132         int ring_index, struct p54p_desc *ring, u32 ring_limit,
 133         struct sk_buff **rx_buf)
 134 {
 135         struct p54p_priv *priv = dev->priv;
 136         struct p54p_ring_control *ring_control = priv->ring_control;
 137         u32 limit, idx, i;
 138
 139         idx = le32_to_cpu(ring_control->host_idx[ring_index]);
 140         limit = idx;
 141         limit -= le32_to_cpu(ring_control->device_idx[ring_index]);
 142         limit = ring_limit - limit;
 143
 144         i = idx % ring_limit;
 145         while (limit-- > 1) {
 146                 struct p54p_desc *desc = &ring[i];
 147
 148                 if (!desc->host_addr) {
 149                         struct sk_buff *skb;
 150                         dma_addr_t mapping;
 151                         skb = dev_alloc_skb(priv->common.rx_mtu + 32);
 152                         if (!skb)
 153                                 break;
 154
 155                         mapping = pci_map_single(priv->pdev,
 156                                                  skb_tail_pointer(skb),
 157                                                  priv->common.rx_mtu + 32,
 158                                                  PCI_DMA_FROMDEVICE);
 159                         desc->host_addr = cpu_to_le32(mapping);
 160                         desc->device_addr = 0;  // FIXME: necessary?
 161                         desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
 162                         desc->flags = 0;
 163                         rx_buf[i] = skb;
 164                 }
 165
 166                 i++;
 167                 idx++;
 168                 i %= ring_limit;
 169         }
 170
 171         wmb();
 172         ring_control->host_idx[ring_index] = cpu_to_le32(idx);
 173 }
 174
 175 static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
 176         int ring_index, struct p54p_desc *ring, u32 ring_limit,
 177         struct sk_buff **rx_buf)
 178 {
 179         struct p54p_priv *priv = dev->priv;
 180         struct p54p_ring_control *ring_control = priv->ring_control;
 181         struct p54p_desc *desc;
 182         u32 idx, i;
 183
 184         i = (*index) % ring_limit;
 185         (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
 186         idx %= ring_limit;
 187         while (i != idx) {
 188                 u16 len;
 189                 struct sk_buff *skb;
 190                 desc = &ring[i];
 191                 len = le16_to_cpu(desc->len);
 192                 skb = rx_buf[i];
 193
 194                 if (!skb) {
 195                         i++;
 196                         i %= ring_limit;
 197                         continue;
 198                 }
 199                 skb_put(skb, len);
 200
 201                 if (p54_rx(dev, skb)) {
 202                         pci_unmap_single(priv->pdev,
 203                                          le32_to_cpu(desc->host_addr),
 204                                          priv->common.rx_mtu + 32,
 205                                          PCI_DMA_FROMDEVICE);
 206                         rx_buf[i] = NULL;
 207                         desc->host_addr = 0;
 208                 } else {
 209                         skb_trim(skb, 0);
 210                         desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
 211                 }
 212
 213                 i++;
 214                 i %= ring_limit;
 215         }
 216
 217         p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf);
 218 }
 219
 220 /* caller must hold priv->lock */
 221 static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
 222         int ring_index, struct p54p_desc *ring, u32 ring_limit,
 223         void **tx_buf)
 224 {
 225         struct p54p_priv *priv = dev->priv;
 226         struct p54p_ring_control *ring_control = priv->ring_control;
 227         struct p54p_desc *desc;
 228         u32 idx, i;
 229
 230         i = (*index) % ring_limit;
 231         (*index) = idx = le32_to_cpu(ring_control->device_idx[1]);
 232         idx %= ring_limit;
 233
 234         while (i != idx) {
 235                 desc = &ring[i];
 236                 if (tx_buf[i])
 237                         if (FREE_AFTER_TX((struct sk_buff *) tx_buf[i]))
 238                                 p54_free_skb(dev, tx_buf[i]);
 239                 tx_buf[i] = NULL;
 240
 241                 pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
 242                                  le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
 243
 244                 desc->host_addr = 0;
 245                 desc->device_addr = 0;
 246                 desc->len = 0;
 247                 desc->flags = 0;
 248
 249                 i++;
 250                 i %= ring_limit;
 251         }
 252 }
 253
 254 static void p54p_rx_tasklet(unsigned long dev_id)
 255 {
 256         struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
 257         struct p54p_priv *priv = dev->priv;
 258         struct p54p_ring_control *ring_control = priv->ring_control;
 259
 260         p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
 261                 ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
 262
 263         p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
 264                 ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
 265
 266         wmb();
 267         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
 268 }
 269
 270 static irqreturn_t p54p_interrupt(int irq, void *dev_id)
 271 {
 272         struct ieee80211_hw *dev = dev_id;
 273         struct p54p_priv *priv = dev->priv;
 274         struct p54p_ring_control *ring_control = priv->ring_control;
 275         __le32 reg;
 276
 277         spin_lock(&priv->lock);
 278         reg = P54P_READ(int_ident);
 279         if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
 280                 spin_unlock(&priv->lock);
 281                 return IRQ_HANDLED;
 282         }
 283
 284         P54P_WRITE(int_ack, reg);
 285
 286         reg &= P54P_READ(int_enable);
 287
 288         if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)) {
 289                 p54p_check_tx_ring(dev, &priv->tx_idx_mgmt,
 290                                    3, ring_control->tx_mgmt,
 291                                    ARRAY_SIZE(ring_control->tx_mgmt),
 292                                    priv->tx_buf_mgmt);
 293
 294                 p54p_check_tx_ring(dev, &priv->tx_idx_data,
 295                                    1, ring_control->tx_data,
 296                                    ARRAY_SIZE(ring_control->tx_data),
 297                                    priv->tx_buf_data);
 298
 299                 tasklet_schedule(&priv->rx_tasklet);
 300
 301         } else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
 302                 complete(&priv->boot_comp);
 303
 304         spin_unlock(&priv->lock);
 305
 306         return reg ? IRQ_HANDLED : IRQ_NONE;
 307 }
 308
 309 static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
 310 {
 311         struct p54p_priv *priv = dev->priv;
 312         struct p54p_ring_control *ring_control = priv->ring_control;
 313         unsigned long flags;
 314         struct p54p_desc *desc;
 315         dma_addr_t mapping;
 316         u32 device_idx, idx, i;
 317
 318         spin_lock_irqsave(&priv->lock, flags);
 319
 320         device_idx = le32_to_cpu(ring_control->device_idx[1]);
 321         idx = le32_to_cpu(ring_control->host_idx[1]);
 322         i = idx % ARRAY_SIZE(ring_control->tx_data);
 323
 324         priv->tx_buf_data[i] = skb;
 325         mapping = pci_map_single(priv->pdev, skb->data, skb->len,
 326                                  PCI_DMA_TODEVICE);
 327         desc = &ring_control->tx_data[i];
 328         desc->host_addr = cpu_to_le32(mapping);
 329         desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
 330         desc->len = cpu_to_le16(skb->len);
 331         desc->flags = 0;
 332
 333         wmb();
 334         ring_control->host_idx[1] = cpu_to_le32(idx + 1);
 335         spin_unlock_irqrestore(&priv->lock, flags);
 336
 337         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
 338         P54P_READ(dev_int);
 339 }
 340
 341 static void p54p_stop(struct ieee80211_hw *dev)
 342 {
 343         struct p54p_priv *priv = dev->priv;
 344         struct p54p_ring_control *ring_control = priv->ring_control;
 345         unsigned int i;
 346         struct p54p_desc *desc;
 347
 348         tasklet_kill(&priv->rx_tasklet);
 349
 350         P54P_WRITE(int_enable, cpu_to_le32(0));
 351         P54P_READ(int_enable);
 352         udelay(10);
 353
 354         free_irq(priv->pdev->irq, dev);
 355
 356         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
 357
 358         for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
 359                 desc = &ring_control->rx_data[i];
 360                 if (desc->host_addr)
 361                         pci_unmap_single(priv->pdev,
 362                                          le32_to_cpu(desc->host_addr),
 363                                          priv->common.rx_mtu + 32,
 364                                          PCI_DMA_FROMDEVICE);
 365                 kfree_skb(priv->rx_buf_data[i]);
 366                 priv->rx_buf_data[i] = NULL;
 367         }
 368
 369         for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
 370                 desc = &ring_control->rx_mgmt[i];
 371                 if (desc->host_addr)
 372                         pci_unmap_single(priv->pdev,
 373                                          le32_to_cpu(desc->host_addr),
 374                                          priv->common.rx_mtu + 32,
 375                                          PCI_DMA_FROMDEVICE);
 376                 kfree_skb(priv->rx_buf_mgmt[i]);
 377                 priv->rx_buf_mgmt[i] = NULL;
 378         }
 379
 380         for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
 381                 desc = &ring_control->tx_data[i];
 382                 if (desc->host_addr)
 383                         pci_unmap_single(priv->pdev,
 384                                          le32_to_cpu(desc->host_addr),
 385                                          le16_to_cpu(desc->len),
 386                                          PCI_DMA_TODEVICE);
 387
 388                 p54_free_skb(dev, priv->tx_buf_data[i]);
 389                 priv->tx_buf_data[i] = NULL;
 390         }
 391
 392         for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
 393                 desc = &ring_control->tx_mgmt[i];
 394                 if (desc->host_addr)
 395                         pci_unmap_single(priv->pdev,
 396                                          le32_to_cpu(desc->host_addr),
 397                                          le16_to_cpu(desc->len),
 398                                          PCI_DMA_TODEVICE);
 399
 400                 p54_free_skb(dev, priv->tx_buf_mgmt[i]);
 401                 priv->tx_buf_mgmt[i] = NULL;
 402         }
 403
 404         memset(ring_control, 0, sizeof(*ring_control));
 405 }
 406
 407 static int p54p_open(struct ieee80211_hw *dev)
 408 {
 409         struct p54p_priv *priv = dev->priv;
 410         int err;
 411
 412         init_completion(&priv->boot_comp);
 413         err = request_irq(priv->pdev->irq, &p54p_interrupt,
 414                           IRQF_SHARED, "p54pci", dev);
 415         if (err) {
 416                 dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
 417                 return err;
 418         }
 419
 420         memset(priv->ring_control, 0, sizeof(*priv->ring_control));
 421         err = p54p_upload_firmware(dev);
 422         if (err) {
 423                 free_irq(priv->pdev->irq, dev);
 424                 return err;
 425         }
 426         priv->rx_idx_data = priv->tx_idx_data = 0;
 427         priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
 428
 429         p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
 430                 ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data);
 431
 432         p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
 433                 ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt);
 434
 435         P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
 436         P54P_READ(ring_control_base);
 437         wmb();
 438         udelay(10);
 439
 440         P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
 441         P54P_READ(int_enable);
 442         wmb();
 443         udelay(10);
 444
 445         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
 446         P54P_READ(dev_int);
 447
 448         if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
 449                 printk(KERN_ERR "%s: Cannot boot firmware!\n",
 450                        wiphy_name(dev->wiphy));
 451                 p54p_stop(dev);
 452                 return -ETIMEDOUT;
 453         }
 454
 455         P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
 456         P54P_READ(int_enable);
 457         wmb();
 458         udelay(10);
 459
 460         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
 461         P54P_READ(dev_int);
 462         wmb();
 463         udelay(10);
 464
 465         return 0;
 466 }
 467
 468 static int __devinit p54p_probe(struct pci_dev *pdev,
 469                                 const struct pci_device_id *id)
 470 {
 471         struct p54p_priv *priv;
 472         struct ieee80211_hw *dev;
 473         unsigned long mem_addr, mem_len;
 474         int err;
 475
 476         err = pci_enable_device(pdev);
 477         if (err) {
 478                 dev_err(&pdev->dev, "Cannot enable new PCI device\n");
 479                 return err;
 480         }
 481
 482         mem_addr = pci_resource_start(pdev, 0);
 483         mem_len = pci_resource_len(pdev, 0);
 484         if (mem_len < sizeof(struct p54p_csr)) {
 485                 dev_err(&pdev->dev, "Too short PCI resources\n");
 486                 goto err_disable_dev;
 487         }
 488
 489         err = pci_request_regions(pdev, "p54pci");
 490         if (err) {
 491                 dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
 492                 goto err_disable_dev;
 493         }
 494
 495         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
 496             pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
 497                 dev_err(&pdev->dev, "No suitable DMA available\n");
 498                 goto err_free_reg;
 499         }
 500
 501         pci_set_master(pdev);
 502         pci_try_set_mwi(pdev);
 503
 504         pci_write_config_byte(pdev, 0x40, 0);
 505         pci_write_config_byte(pdev, 0x41, 0);
 506
 507         dev = p54_init_common(sizeof(*priv));
 508         if (!dev) {
 509                 dev_err(&pdev->dev, "ieee80211 alloc failed\n");
 510                 err = -ENOMEM;
 511                 goto err_free_reg;
 512         }
 513
 514         priv = dev->priv;
 515         priv->pdev = pdev;
 516
 517         SET_IEEE80211_DEV(dev, &pdev->dev);
 518         pci_set_drvdata(pdev, dev);
 519
 520         priv->map = ioremap(mem_addr, mem_len);
 521         if (!priv->map) {
 522                 dev_err(&pdev->dev, "Cannot map device memory\n");
 523                 err = -ENOMEM;
 524                 goto err_free_dev;
 525         }
 526
 527         priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
 528                                                   &priv->ring_control_dma);
 529         if (!priv->ring_control) {
 530                 dev_err(&pdev->dev, "Cannot allocate rings\n");
 531                 err = -ENOMEM;
 532                 goto err_iounmap;
 533         }
 534         priv->common.open = p54p_open;
 535         priv->common.stop = p54p_stop;
 536         priv->common.tx = p54p_tx;
 537
 538         spin_lock_init(&priv->lock);
 539         tasklet_init(&priv->rx_tasklet, p54p_rx_tasklet, (unsigned long)dev);
 540
 541         err = request_firmware(&priv->firmware, "isl3886pci",
 542                                &priv->pdev->dev);
 543         if (err) {
 544                 dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
 545                 err = request_firmware(&priv->firmware, "isl3886",
 546                                        &priv->pdev->dev);
 547                 if (err)
 548                         goto err_free_common;
 549         }
 550
 551         err = p54p_open(dev);
 552         if (err)
 553                 goto err_free_common;
 554         err = p54_read_eeprom(dev);
 555         p54p_stop(dev);
 556         if (err)
 557                 goto err_free_common;
 558
 559         err = p54_register_common(dev, &pdev->dev);
 560         if (err)
 561                 goto err_free_common;
 562
 563         return 0;
 564
 565  err_free_common:
 566         release_firmware(priv->firmware);
 567         p54_free_common(dev);
 568         pci_free_consistent(pdev, sizeof(*priv->ring_control),
 569                             priv->ring_control, priv->ring_control_dma);
 570
 571  err_iounmap:
 572         iounmap(priv->map);
 573
 574  err_free_dev:
 575         pci_set_drvdata(pdev, NULL);
 576         ieee80211_free_hw(dev);
 577
 578  err_free_reg:
 579         pci_release_regions(pdev);
 580  err_disable_dev:
 581         pci_disable_device(pdev);
 582         return err;
 583 }
 584
 585 static void __devexit p54p_remove(struct pci_dev *pdev)
 586 {
 587         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
 588         struct p54p_priv *priv;
 589
 590         if (!dev)
 591                 return;
 592
 593         ieee80211_unregister_hw(dev);
 594         priv = dev->priv;
 595         release_firmware(priv->firmware);
 596         pci_free_consistent(pdev, sizeof(*priv->ring_control),
 597                             priv->ring_control, priv->ring_control_dma);
 598         p54_free_common(dev);
 599         iounmap(priv->map);
 600         pci_release_regions(pdev);
 601         pci_disable_device(pdev);
 602         ieee80211_free_hw(dev);
 603 }
 604
 605 #ifdef CONFIG_PM
 606 static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
 607 {
 608         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
 609         struct p54p_priv *priv = dev->priv;
 610
 611         if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
 612                 ieee80211_stop_queues(dev);
 613                 p54p_stop(dev);
 614         }
 615
 616         pci_save_state(pdev);
 617         pci_set_power_state(pdev, pci_choose_state(pdev, state));
 618         return 0;
 619 }
 620
 621 static int p54p_resume(struct pci_dev *pdev)
 622 {
 623         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
 624         struct p54p_priv *priv = dev->priv;
 625
 626         pci_set_power_state(pdev, PCI_D0);
 627         pci_restore_state(pdev);
 628
 629         if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
 630                 p54p_open(dev);
 631                 ieee80211_wake_queues(dev);
 632         }
 633
 634         return 0;
 635 }
 636 #endif /* CONFIG_PM */
 637
 638 static struct pci_driver p54p_driver = {
 639         .name           = "p54pci",
 640         .id_table       = p54p_table,
 641         .probe          = p54p_probe,
 642         .remove         = __devexit_p(p54p_remove),
 643 #ifdef CONFIG_PM
 644         .suspend        = p54p_suspend,
 645         .resume         = p54p_resume,
 646 #endif /* CONFIG_PM */
 647 };
 648
 649 static int __init p54p_init(void)
 650 {
 651         return pci_register_driver(&p54p_driver);
 652 }
 653
 654 static void __exit p54p_exit(void)
 655 {
 656         pci_unregister_driver(&p54p_driver);
 657 }
 658
 659 module_init(p54p_init);
 660 module_exit(p54p_exit);