2 /* Linux device driver for RTL8180 / RTL8185 / RTL8187SE
4 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
5 * Copyright 2007,2014 Andrea Merello <andrea.merello@gmail.com>
7 * Based on the r8180 driver, which is:
8 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
10 * Thanks to Realtek for their support!
12 ************************************************************************
14 * The driver was extended to the RTL8187SE in 2014 by
15 * Andrea Merello <andrea.merello@gmail.com>
18 * - portions of rtl8187se Linux staging driver, Copyright Realtek corp.
19 * (available in drivers/staging/rtl8187se directory of Linux 3.14)
20 * - other GPL, unpublished (until now), Linux driver code,
21 * Copyright Larry Finger <Larry.Finger@lwfinger.net>
23 * A huge thanks goes to Sara V. Nari who forgives me when I'm
24 * sitting in front of my laptop at evening, week-end, night...
26 * A special thanks goes to Antonio Cuni, who helped me with
27 * some python userspace stuff I used to debug RTL8187SE code, and who
28 * bought a laptop with an unsupported Wi-Fi card some years ago...
30 * Thanks to Larry Finger for writing some code for rtl8187se and for
33 * Thanks to Dan Carpenter for reviewing my initial patch and for his
36 * Thanks to Bernhard Schiffner for his help in testing and for his
39 ************************************************************************
41 * This program is free software; you can redistribute it and/or modify
42 * it under the terms of the GNU General Public License version 2 as
43 * published by the Free Software Foundation.
46 #include <linux/interrupt.h>
47 #include <linux/pci.h>
48 #include <linux/slab.h>
49 #include <linux/delay.h>
50 #include <linux/etherdevice.h>
51 #include <linux/eeprom_93cx6.h>
52 #include <linux/module.h>
53 #include <net/mac80211.h>
60 #include "rtl8225se.h"
62 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
63 MODULE_AUTHOR("Andrea Merello <andrea.merello@gmail.com>");
64 MODULE_DESCRIPTION("RTL8180 / RTL8185 / RTL8187SE PCI wireless driver");
65 MODULE_LICENSE("GPL");
67 static const struct pci_device_id rtl8180_table
[] = {
70 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8199) },
73 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8185) },
74 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN
, 0x700f) },
75 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN
, 0x701f) },
78 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8180) },
79 { PCI_DEVICE(0x1799, 0x6001) },
80 { PCI_DEVICE(0x1799, 0x6020) },
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x3300) },
82 { PCI_DEVICE(0x1186, 0x3301) },
83 { PCI_DEVICE(0x1432, 0x7106) },
87 MODULE_DEVICE_TABLE(pci
, rtl8180_table
);
89 static const struct ieee80211_rate rtl818x_rates
[] = {
90 { .bitrate
= 10, .hw_value
= 0, },
91 { .bitrate
= 20, .hw_value
= 1, },
92 { .bitrate
= 55, .hw_value
= 2, },
93 { .bitrate
= 110, .hw_value
= 3, },
94 { .bitrate
= 60, .hw_value
= 4, },
95 { .bitrate
= 90, .hw_value
= 5, },
96 { .bitrate
= 120, .hw_value
= 6, },
97 { .bitrate
= 180, .hw_value
= 7, },
98 { .bitrate
= 240, .hw_value
= 8, },
99 { .bitrate
= 360, .hw_value
= 9, },
100 { .bitrate
= 480, .hw_value
= 10, },
101 { .bitrate
= 540, .hw_value
= 11, },
104 static const struct ieee80211_channel rtl818x_channels
[] = {
105 { .center_freq
= 2412 },
106 { .center_freq
= 2417 },
107 { .center_freq
= 2422 },
108 { .center_freq
= 2427 },
109 { .center_freq
= 2432 },
110 { .center_freq
= 2437 },
111 { .center_freq
= 2442 },
112 { .center_freq
= 2447 },
113 { .center_freq
= 2452 },
114 { .center_freq
= 2457 },
115 { .center_freq
= 2462 },
116 { .center_freq
= 2467 },
117 { .center_freq
= 2472 },
118 { .center_freq
= 2484 },
121 /* Queues for rtl8187se card
132 * The complete map for DMA kick reg using use all queue is:
133 * static const int rtl8187se_queues_map[RTL8187SE_NR_TX_QUEUES] =
134 * {1, 6, 5, 4, 3, 2, 7};
136 * .. but.. Because for mac80211 4 queues are enough for QoS we use this
139 * BC | 7 | 4 <- currently not used yet
140 * MG | 1 | x <- Not used
141 * HI | 6 | x <- Not used
147 * Beacon queue could be used, but this is not finished yet.
149 * I thougth about using the other two queues but I decided not to do this:
151 * - I'm unsure whether the mac80211 will ever try to use more than 4 queues
154 * - I could route MGMT frames (currently sent over VO queue) to the MGMT
155 * queue but since mac80211 will do not know about it, I will probably gain
156 * some HW priority whenever the VO queue is not empty, but this gain is
157 * limited by the fact that I had to stop the mac80211 queue whenever one of
158 * the VO or MGMT queues is full, stopping also submitting of MGMT frame
161 * - I don't know how to set in the HW the contention window params for MGMT
162 * and HI-prio queues.
165 static const int rtl8187se_queues_map
[RTL8187SE_NR_TX_QUEUES
] = {5, 4, 3, 2, 7};
167 /* Queues for rtl8180/rtl8185 cards
175 * The complete map for DMA kick reg using all queue is:
176 * static const int rtl8180_queues_map[RTL8180_NR_TX_QUEUES] = {6, 5, 4, 7};
178 * .. but .. Because the mac80211 needs at least 4 queues for QoS or
179 * otherwise QoS can't be done, we use just one.
180 * Beacon queue could be used, but this is not finished yet.
184 * BC | 7 | 1 <- currently not used yet.
185 * HI | 6 | x <- not used
186 * NO | 5 | x <- not used
190 static const int rtl8180_queues_map
[RTL8180_NR_TX_QUEUES
] = {4, 7};
192 /* LNA gain table for rtl8187se */
193 static const u8 rtl8187se_lna_gain
[4] = {02, 17, 29, 39};
195 void rtl8180_write_phy(struct ieee80211_hw
*dev
, u8 addr
, u32 data
)
197 struct rtl8180_priv
*priv
= dev
->priv
;
201 buf
= (data
<< 8) | addr
;
203 rtl818x_iowrite32(priv
, (__le32 __iomem
*)&priv
->map
->PHY
[0], buf
| 0x80);
205 rtl818x_iowrite32(priv
, (__le32 __iomem
*)&priv
->map
->PHY
[0], buf
);
206 if (rtl818x_ioread8(priv
, &priv
->map
->PHY
[2]) == (data
& 0xFF))
211 static void rtl8180_handle_rx(struct ieee80211_hw
*dev
)
213 struct rtl8180_priv
*priv
= dev
->priv
;
214 struct rtl818x_rx_cmd_desc
*cmd_desc
;
215 unsigned int count
= 32;
221 void *entry
= priv
->rx_ring
+ priv
->rx_idx
* priv
->rx_ring_sz
;
222 struct sk_buff
*skb
= priv
->rx_buf
[priv
->rx_idx
];
223 u32 flags
, flags2
, flags3
= 0;
226 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
227 struct rtl8187se_rx_desc
*desc
= entry
;
229 flags
= le32_to_cpu(desc
->flags
);
230 /* if ownership flag is set, then we can trust the
231 * HW has written other fields. We must not trust
232 * other descriptor data read before we checked (read)
236 flags3
= le32_to_cpu(desc
->flags3
);
237 flags2
= le32_to_cpu(desc
->flags2
);
238 tsft
= le64_to_cpu(desc
->tsft
);
240 struct rtl8180_rx_desc
*desc
= entry
;
242 flags
= le32_to_cpu(desc
->flags
);
245 flags2
= le32_to_cpu(desc
->flags2
);
246 tsft
= le64_to_cpu(desc
->tsft
);
249 if (flags
& RTL818X_RX_DESC_FLAG_OWN
)
252 if (unlikely(flags
& (RTL818X_RX_DESC_FLAG_DMA_FAIL
|
253 RTL818X_RX_DESC_FLAG_FOF
|
254 RTL818X_RX_DESC_FLAG_RX_ERR
)))
257 struct ieee80211_rx_status rx_status
= {0};
258 struct sk_buff
*new_skb
= dev_alloc_skb(MAX_RX_SIZE
);
260 if (unlikely(!new_skb
))
263 mapping
= pci_map_single(priv
->pdev
,
264 skb_tail_pointer(new_skb
),
265 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
267 if (pci_dma_mapping_error(priv
->pdev
, mapping
)) {
269 dev_err(&priv
->pdev
->dev
, "RX DMA map error\n");
274 pci_unmap_single(priv
->pdev
,
275 *((dma_addr_t
*)skb
->cb
),
276 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
277 skb_put(skb
, flags
& 0xFFF);
279 rx_status
.antenna
= (flags2
>> 15) & 1;
280 rx_status
.rate_idx
= (flags
>> 20) & 0xF;
281 agc
= (flags2
>> 17) & 0x7F;
283 switch (priv
->chip_family
) {
284 case RTL818X_CHIP_FAMILY_RTL8185
:
285 if (rx_status
.rate_idx
> 3)
286 signal
= -clamp_t(u8
, agc
, 25, 90) - 9;
288 signal
= -clamp_t(u8
, agc
, 30, 95);
290 case RTL818X_CHIP_FAMILY_RTL8180
:
292 signal
= priv
->rf
->calc_rssi(agc
, sq
);
294 case RTL818X_CHIP_FAMILY_RTL8187SE
:
295 /* OFDM measure reported by HW is signed,
296 * in 0.5dBm unit, with zero centered @ -41dBm
299 if (rx_status
.rate_idx
> 3) {
300 signal
= (s8
)((flags3
>> 16) & 0xff);
301 signal
= signal
/ 2 - 41;
305 idx
= (agc
& 0x60) >> 5;
306 bb
= (agc
& 0x1F) * 2;
307 /* bias + BB gain + LNA gain */
308 signal
= 4 - bb
- rtl8187se_lna_gain
[idx
];
312 rx_status
.signal
= signal
;
313 rx_status
.freq
= dev
->conf
.chandef
.chan
->center_freq
;
314 rx_status
.band
= dev
->conf
.chandef
.chan
->band
;
315 rx_status
.mactime
= tsft
;
316 rx_status
.flag
|= RX_FLAG_MACTIME_START
;
317 if (flags
& RTL818X_RX_DESC_FLAG_SPLCP
)
318 rx_status
.flag
|= RX_FLAG_SHORTPRE
;
319 if (flags
& RTL818X_RX_DESC_FLAG_CRC32_ERR
)
320 rx_status
.flag
|= RX_FLAG_FAILED_FCS_CRC
;
322 memcpy(IEEE80211_SKB_RXCB(skb
), &rx_status
, sizeof(rx_status
));
323 ieee80211_rx_irqsafe(dev
, skb
);
326 priv
->rx_buf
[priv
->rx_idx
] = skb
;
327 *((dma_addr_t
*) skb
->cb
) = mapping
;
332 cmd_desc
->rx_buf
= cpu_to_le32(*((dma_addr_t
*)skb
->cb
));
333 cmd_desc
->flags
= cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN
|
335 if (priv
->rx_idx
== 31)
337 cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR
);
338 priv
->rx_idx
= (priv
->rx_idx
+ 1) % 32;
342 static void rtl8180_handle_tx(struct ieee80211_hw
*dev
, unsigned int prio
)
344 struct rtl8180_priv
*priv
= dev
->priv
;
345 struct rtl8180_tx_ring
*ring
= &priv
->tx_ring
[prio
];
347 while (skb_queue_len(&ring
->queue
)) {
348 struct rtl8180_tx_desc
*entry
= &ring
->desc
[ring
->idx
];
350 struct ieee80211_tx_info
*info
;
351 u32 flags
= le32_to_cpu(entry
->flags
);
353 if (flags
& RTL818X_TX_DESC_FLAG_OWN
)
356 ring
->idx
= (ring
->idx
+ 1) % ring
->entries
;
357 skb
= __skb_dequeue(&ring
->queue
);
358 pci_unmap_single(priv
->pdev
, le32_to_cpu(entry
->tx_buf
),
359 skb
->len
, PCI_DMA_TODEVICE
);
361 info
= IEEE80211_SKB_CB(skb
);
362 ieee80211_tx_info_clear_status(info
);
364 if (!(info
->flags
& IEEE80211_TX_CTL_NO_ACK
) &&
365 (flags
& RTL818X_TX_DESC_FLAG_TX_OK
))
366 info
->flags
|= IEEE80211_TX_STAT_ACK
;
368 info
->status
.rates
[0].count
= (flags
& 0xFF) + 1;
370 ieee80211_tx_status_irqsafe(dev
, skb
);
371 if (ring
->entries
- skb_queue_len(&ring
->queue
) == 2)
372 ieee80211_wake_queue(dev
, prio
);
376 static irqreturn_t
rtl8187se_interrupt(int irq
, void *dev_id
)
378 struct ieee80211_hw
*dev
= dev_id
;
379 struct rtl8180_priv
*priv
= dev
->priv
;
384 spin_lock_irqsave(&priv
->lock
, flags
);
385 /* Note: 32-bit interrupt status */
386 reg
= rtl818x_ioread32(priv
, &priv
->map
->INT_STATUS_SE
);
387 if (unlikely(reg
== 0xFFFFFFFF)) {
388 spin_unlock_irqrestore(&priv
->lock
, flags
);
392 rtl818x_iowrite32(priv
, &priv
->map
->INT_STATUS_SE
, reg
);
394 if (reg
& IMR_TIMEOUT1
)
395 rtl818x_iowrite32(priv
, &priv
->map
->INT_TIMEOUT
, 0);
397 if (reg
& (IMR_TBDOK
| IMR_TBDER
))
398 rtl8180_handle_tx(dev
, 4);
400 if (reg
& (IMR_TVODOK
| IMR_TVODER
))
401 rtl8180_handle_tx(dev
, 0);
403 if (reg
& (IMR_TVIDOK
| IMR_TVIDER
))
404 rtl8180_handle_tx(dev
, 1);
406 if (reg
& (IMR_TBEDOK
| IMR_TBEDER
))
407 rtl8180_handle_tx(dev
, 2);
409 if (reg
& (IMR_TBKDOK
| IMR_TBKDER
))
410 rtl8180_handle_tx(dev
, 3);
412 if (reg
& (IMR_ROK
| IMR_RER
| RTL818X_INT_SE_RX_DU
| IMR_RQOSOK
))
413 rtl8180_handle_rx(dev
);
414 /* The interface sometimes generates several RX DMA descriptor errors
415 * at startup. Do not report these.
417 if ((reg
& RTL818X_INT_SE_RX_DU
) && desc_err
++ > 2)
419 wiphy_err(dev
->wiphy
, "No RX DMA Descriptor avail\n");
421 spin_unlock_irqrestore(&priv
->lock
, flags
);
425 static irqreturn_t
rtl8180_interrupt(int irq
, void *dev_id
)
427 struct ieee80211_hw
*dev
= dev_id
;
428 struct rtl8180_priv
*priv
= dev
->priv
;
431 spin_lock(&priv
->lock
);
432 reg
= rtl818x_ioread16(priv
, &priv
->map
->INT_STATUS
);
433 if (unlikely(reg
== 0xFFFF)) {
434 spin_unlock(&priv
->lock
);
438 rtl818x_iowrite16(priv
, &priv
->map
->INT_STATUS
, reg
);
440 if (reg
& (RTL818X_INT_TXB_OK
| RTL818X_INT_TXB_ERR
))
441 rtl8180_handle_tx(dev
, 1);
443 if (reg
& (RTL818X_INT_TXL_OK
| RTL818X_INT_TXL_ERR
))
444 rtl8180_handle_tx(dev
, 0);
446 if (reg
& (RTL818X_INT_RX_OK
| RTL818X_INT_RX_ERR
))
447 rtl8180_handle_rx(dev
);
449 spin_unlock(&priv
->lock
);
454 static void rtl8180_tx(struct ieee80211_hw
*dev
,
455 struct ieee80211_tx_control
*control
,
458 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
459 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
460 struct rtl8180_priv
*priv
= dev
->priv
;
461 struct rtl8180_tx_ring
*ring
;
462 struct rtl8180_tx_desc
*entry
;
464 unsigned int idx
, prio
, hw_prio
;
469 __le16 rts_duration
= 0;
470 /* do arithmetic and then convert to le16 */
471 u16 frame_duration
= 0;
473 prio
= skb_get_queue_mapping(skb
);
474 ring
= &priv
->tx_ring
[prio
];
476 mapping
= pci_map_single(priv
->pdev
, skb
->data
,
477 skb
->len
, PCI_DMA_TODEVICE
);
479 if (pci_dma_mapping_error(priv
->pdev
, mapping
)) {
481 dev_err(&priv
->pdev
->dev
, "TX DMA mapping error\n");
485 tx_flags
= RTL818X_TX_DESC_FLAG_OWN
| RTL818X_TX_DESC_FLAG_FS
|
486 RTL818X_TX_DESC_FLAG_LS
|
487 (ieee80211_get_tx_rate(dev
, info
)->hw_value
<< 24) |
490 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
)
491 tx_flags
|= RTL818X_TX_DESC_FLAG_DMA
|
492 RTL818X_TX_DESC_FLAG_NO_ENC
;
494 rc_flags
= info
->control
.rates
[0].flags
;
496 /* HW will perform RTS-CTS when only RTS flags is set.
497 * HW will perform CTS-to-self when both RTS and CTS flags are set.
498 * RTS rate and RTS duration will be used also for CTS-to-self.
500 if (rc_flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
501 tx_flags
|= RTL818X_TX_DESC_FLAG_RTS
;
502 tx_flags
|= ieee80211_get_rts_cts_rate(dev
, info
)->hw_value
<< 19;
503 rts_duration
= ieee80211_rts_duration(dev
, priv
->vif
,
505 } else if (rc_flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
506 tx_flags
|= RTL818X_TX_DESC_FLAG_RTS
| RTL818X_TX_DESC_FLAG_CTS
;
507 tx_flags
|= ieee80211_get_rts_cts_rate(dev
, info
)->hw_value
<< 19;
508 rts_duration
= ieee80211_ctstoself_duration(dev
, priv
->vif
,
512 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
) {
513 unsigned int remainder
;
515 plcp_len
= DIV_ROUND_UP(16 * (skb
->len
+ 4),
516 (ieee80211_get_tx_rate(dev
, info
)->bitrate
* 2) / 10);
517 remainder
= (16 * (skb
->len
+ 4)) %
518 ((ieee80211_get_tx_rate(dev
, info
)->bitrate
* 2) / 10);
523 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
525 /* SIFS time (required by HW) is already included by
526 * ieee80211_generic_frame_duration
528 duration
= ieee80211_generic_frame_duration(dev
, priv
->vif
,
529 NL80211_BAND_2GHZ
, skb
->len
,
530 ieee80211_get_tx_rate(dev
, info
));
532 frame_duration
= priv
->ack_time
+ le16_to_cpu(duration
);
535 spin_lock_irqsave(&priv
->lock
, flags
);
537 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
538 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
540 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
541 hdr
->seq_ctrl
|= cpu_to_le16(priv
->seqno
);
544 idx
= (ring
->idx
+ skb_queue_len(&ring
->queue
)) % ring
->entries
;
545 entry
= &ring
->desc
[idx
];
547 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
548 entry
->frame_duration
= cpu_to_le16(frame_duration
);
549 entry
->frame_len_se
= cpu_to_le16(skb
->len
);
552 entry
->flags3
= cpu_to_le16(1<<4);
554 entry
->frame_len
= cpu_to_le32(skb
->len
);
556 entry
->rts_duration
= rts_duration
;
557 entry
->plcp_len
= cpu_to_le16(plcp_len
);
558 entry
->tx_buf
= cpu_to_le32(mapping
);
560 entry
->retry_limit
= info
->control
.rates
[0].count
- 1;
562 /* We must be sure that tx_flags is written last because the HW
563 * looks at it to check if the rest of data is valid or not
566 entry
->flags
= cpu_to_le32(tx_flags
);
567 /* We must be sure this has been written before followings HW
568 * register write, because this write will made the HW attempts
569 * to DMA the just-written data
573 __skb_queue_tail(&ring
->queue
, skb
);
574 if (ring
->entries
- skb_queue_len(&ring
->queue
) < 2)
575 ieee80211_stop_queue(dev
, prio
);
577 spin_unlock_irqrestore(&priv
->lock
, flags
);
579 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
580 /* just poll: rings are stopped with TPPollStop reg */
581 hw_prio
= rtl8187se_queues_map
[prio
];
582 rtl818x_iowrite8(priv
, &priv
->map
->TX_DMA_POLLING
,
585 hw_prio
= rtl8180_queues_map
[prio
];
586 rtl818x_iowrite8(priv
, &priv
->map
->TX_DMA_POLLING
,
587 (1 << hw_prio
) | /* ring to poll */
588 (1<<1) | (1<<2));/* stopped rings */
592 static void rtl8180_set_anaparam3(struct rtl8180_priv
*priv
, u16 anaparam3
)
596 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
597 RTL818X_EEPROM_CMD_CONFIG
);
599 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
600 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
601 reg
| RTL818X_CONFIG3_ANAPARAM_WRITE
);
603 rtl818x_iowrite16(priv
, &priv
->map
->ANAPARAM3
, anaparam3
);
605 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
606 reg
& ~RTL818X_CONFIG3_ANAPARAM_WRITE
);
608 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
609 RTL818X_EEPROM_CMD_NORMAL
);
612 void rtl8180_set_anaparam2(struct rtl8180_priv
*priv
, u32 anaparam2
)
616 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
617 RTL818X_EEPROM_CMD_CONFIG
);
619 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
620 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
621 reg
| RTL818X_CONFIG3_ANAPARAM_WRITE
);
623 rtl818x_iowrite32(priv
, &priv
->map
->ANAPARAM2
, anaparam2
);
625 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
626 reg
& ~RTL818X_CONFIG3_ANAPARAM_WRITE
);
628 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
629 RTL818X_EEPROM_CMD_NORMAL
);
632 void rtl8180_set_anaparam(struct rtl8180_priv
*priv
, u32 anaparam
)
636 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
637 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
638 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
639 reg
| RTL818X_CONFIG3_ANAPARAM_WRITE
);
640 rtl818x_iowrite32(priv
, &priv
->map
->ANAPARAM
, anaparam
);
641 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
,
642 reg
& ~RTL818X_CONFIG3_ANAPARAM_WRITE
);
643 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
646 static void rtl8187se_mac_config(struct ieee80211_hw
*dev
)
648 struct rtl8180_priv
*priv
= dev
->priv
;
651 rtl818x_iowrite32(priv
, REG_ADDR4(0x1F0), 0);
652 rtl818x_ioread32(priv
, REG_ADDR4(0x1F0));
653 rtl818x_iowrite32(priv
, REG_ADDR4(0x1F4), 0);
654 rtl818x_ioread32(priv
, REG_ADDR4(0x1F4));
655 rtl818x_iowrite8(priv
, REG_ADDR1(0x1F8), 0);
656 rtl818x_ioread8(priv
, REG_ADDR1(0x1F8));
657 /* Enable DA10 TX power saving */
658 reg
= rtl818x_ioread8(priv
, &priv
->map
->PHY_PR
);
659 rtl818x_iowrite8(priv
, &priv
->map
->PHY_PR
, reg
| 0x04);
661 rtl818x_iowrite16(priv
, PI_DATA_REG
, 0x1000);
662 rtl818x_iowrite16(priv
, SI_DATA_REG
, 0x1000);
663 /* AFE - default to power ON */
664 rtl818x_iowrite16(priv
, REG_ADDR2(0x370), 0x0560);
665 rtl818x_iowrite16(priv
, REG_ADDR2(0x372), 0x0560);
666 rtl818x_iowrite16(priv
, REG_ADDR2(0x374), 0x0DA4);
667 rtl818x_iowrite16(priv
, REG_ADDR2(0x376), 0x0DA4);
668 rtl818x_iowrite16(priv
, REG_ADDR2(0x378), 0x0560);
669 rtl818x_iowrite16(priv
, REG_ADDR2(0x37A), 0x0560);
670 rtl818x_iowrite16(priv
, REG_ADDR2(0x37C), 0x00EC);
671 rtl818x_iowrite16(priv
, REG_ADDR2(0x37E), 0x00EC);
672 rtl818x_iowrite8(priv
, REG_ADDR1(0x24E), 0x01);
673 /* unknown, needed for suspend to RAM resume */
674 rtl818x_iowrite8(priv
, REG_ADDR1(0x0A), 0x72);
677 static void rtl8187se_set_antenna_config(struct ieee80211_hw
*dev
, u8 def_ant
,
680 struct rtl8180_priv
*priv
= dev
->priv
;
682 rtl8225_write_phy_cck(dev
, 0x0C, 0x09);
685 rtl818x_iowrite8(priv
, &priv
->map
->TX_ANTENNA
, 0x00);
686 rtl8225_write_phy_cck(dev
, 0x11, 0xBB);
687 rtl8225_write_phy_cck(dev
, 0x01, 0xC7);
688 rtl8225_write_phy_ofdm(dev
, 0x0D, 0x54);
689 rtl8225_write_phy_ofdm(dev
, 0x18, 0xB2);
690 } else { /* main antenna */
691 rtl818x_iowrite8(priv
, &priv
->map
->TX_ANTENNA
, 0x03);
692 rtl8225_write_phy_cck(dev
, 0x11, 0x9B);
693 rtl8225_write_phy_cck(dev
, 0x01, 0xC7);
694 rtl8225_write_phy_ofdm(dev
, 0x0D, 0x5C);
695 rtl8225_write_phy_ofdm(dev
, 0x18, 0xB2);
697 } else { /* disable antenna diversity */
699 rtl818x_iowrite8(priv
, &priv
->map
->TX_ANTENNA
, 0x00);
700 rtl8225_write_phy_cck(dev
, 0x11, 0xBB);
701 rtl8225_write_phy_cck(dev
, 0x01, 0x47);
702 rtl8225_write_phy_ofdm(dev
, 0x0D, 0x54);
703 rtl8225_write_phy_ofdm(dev
, 0x18, 0x32);
704 } else { /* main antenna */
705 rtl818x_iowrite8(priv
, &priv
->map
->TX_ANTENNA
, 0x03);
706 rtl8225_write_phy_cck(dev
, 0x11, 0x9B);
707 rtl8225_write_phy_cck(dev
, 0x01, 0x47);
708 rtl8225_write_phy_ofdm(dev
, 0x0D, 0x5C);
709 rtl8225_write_phy_ofdm(dev
, 0x18, 0x32);
712 /* priv->curr_ant = def_ant; */
715 static void rtl8180_int_enable(struct ieee80211_hw
*dev
)
717 struct rtl8180_priv
*priv
= dev
->priv
;
719 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
720 rtl818x_iowrite32(priv
, &priv
->map
->IMR
,
721 IMR_TBDER
| IMR_TBDOK
|
722 IMR_TVODER
| IMR_TVODOK
|
723 IMR_TVIDER
| IMR_TVIDOK
|
724 IMR_TBEDER
| IMR_TBEDOK
|
725 IMR_TBKDER
| IMR_TBKDOK
|
727 IMR_ROK
| IMR_RQOSOK
);
729 rtl818x_iowrite16(priv
, &priv
->map
->INT_MASK
, 0xFFFF);
733 static void rtl8180_int_disable(struct ieee80211_hw
*dev
)
735 struct rtl8180_priv
*priv
= dev
->priv
;
737 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
738 rtl818x_iowrite32(priv
, &priv
->map
->IMR
, 0);
740 rtl818x_iowrite16(priv
, &priv
->map
->INT_MASK
, 0);
744 static void rtl8180_conf_basic_rates(struct ieee80211_hw
*dev
,
747 struct rtl8180_priv
*priv
= dev
->priv
;
751 u8 resp_max
, resp_min
;
753 resp_mask
= basic_mask
;
754 /* IEEE80211 says the response rate should be equal to the highest basic
755 * rate that is not faster than received frame. But it says also that if
756 * the basic rate set does not contains any rate for the current
757 * modulation class then mandatory rate set must be used for that
758 * modulation class. Eventually add OFDM mandatory rates..
760 if ((resp_mask
& 0xf) == resp_mask
)
761 resp_mask
|= 0x150; /* 6, 12, 24Mbps */
763 switch (priv
->chip_family
) {
765 case RTL818X_CHIP_FAMILY_RTL8180
:
766 /* in 8180 this is NOT a BITMAP */
767 basic_max
= fls(basic_mask
) - 1;
768 reg
= rtl818x_ioread16(priv
, &priv
->map
->BRSR
);
771 rtl818x_iowrite16(priv
, &priv
->map
->BRSR
, reg
);
774 case RTL818X_CHIP_FAMILY_RTL8185
:
775 resp_max
= fls(resp_mask
) - 1;
776 resp_min
= ffs(resp_mask
) - 1;
777 /* in 8185 this is a BITMAP */
778 rtl818x_iowrite16(priv
, &priv
->map
->BRSR
, basic_mask
);
779 rtl818x_iowrite8(priv
, &priv
->map
->RESP_RATE
, (resp_max
<< 4) |
783 case RTL818X_CHIP_FAMILY_RTL8187SE
:
784 /* in 8187se this is a BITMAP. BRSR reg actually sets
787 rtl818x_iowrite16(priv
, &priv
->map
->BRSR_8187SE
, resp_mask
);
792 static void rtl8180_config_cardbus(struct ieee80211_hw
*dev
)
794 struct rtl8180_priv
*priv
= dev
->priv
;
798 reg8
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
800 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
, reg8
);
802 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
803 rtl818x_iowrite16(priv
, FEMR_SE
, 0xffff);
805 reg16
= rtl818x_ioread16(priv
, &priv
->map
->FEMR
);
806 reg16
|= (1 << 15) | (1 << 14) | (1 << 4);
807 rtl818x_iowrite16(priv
, &priv
->map
->FEMR
, reg16
);
812 static int rtl8180_init_hw(struct ieee80211_hw
*dev
)
814 struct rtl8180_priv
*priv
= dev
->priv
;
818 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, 0);
819 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
823 rtl8180_int_disable(dev
);
824 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
826 reg
= rtl818x_ioread8(priv
, &priv
->map
->CMD
);
828 reg
|= RTL818X_CMD_RESET
;
829 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, RTL818X_CMD_RESET
);
830 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
833 /* check success of reset */
834 if (rtl818x_ioread8(priv
, &priv
->map
->CMD
) & RTL818X_CMD_RESET
) {
835 wiphy_err(dev
->wiphy
, "reset timeout!\n");
839 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_LOAD
);
840 rtl818x_ioread8(priv
, &priv
->map
->CMD
);
843 if (rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
) & (1 << 3)) {
844 rtl8180_config_cardbus(dev
);
847 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
)
848 rtl818x_iowrite8(priv
, &priv
->map
->MSR
, RTL818X_MSR_ENEDCA
);
850 rtl818x_iowrite8(priv
, &priv
->map
->MSR
, 0);
852 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
)
853 rtl8180_set_anaparam(priv
, priv
->anaparam
);
855 rtl818x_iowrite32(priv
, &priv
->map
->RDSAR
, priv
->rx_ring_dma
);
856 /* mac80211 queue have higher prio for lower index. The last queue
857 * (that mac80211 is not aware of) is reserved for beacons (and have
858 * the highest priority on the NIC)
860 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8187SE
) {
861 rtl818x_iowrite32(priv
, &priv
->map
->TBDA
,
862 priv
->tx_ring
[1].dma
);
863 rtl818x_iowrite32(priv
, &priv
->map
->TLPDA
,
864 priv
->tx_ring
[0].dma
);
866 rtl818x_iowrite32(priv
, &priv
->map
->TBDA
,
867 priv
->tx_ring
[4].dma
);
868 rtl818x_iowrite32(priv
, &priv
->map
->TVODA
,
869 priv
->tx_ring
[0].dma
);
870 rtl818x_iowrite32(priv
, &priv
->map
->TVIDA
,
871 priv
->tx_ring
[1].dma
);
872 rtl818x_iowrite32(priv
, &priv
->map
->TBEDA
,
873 priv
->tx_ring
[2].dma
);
874 rtl818x_iowrite32(priv
, &priv
->map
->TBKDA
,
875 priv
->tx_ring
[3].dma
);
878 /* TODO: necessary? specs indicate not */
879 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
880 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG2
);
881 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG2
, reg
& ~(1 << 3));
882 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8185
) {
883 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG2
);
884 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG2
, reg
| (1 << 4));
886 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
888 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
890 /* TODO: turn off hw wep on rtl8180 */
892 rtl818x_iowrite32(priv
, &priv
->map
->INT_TIMEOUT
, 0);
894 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
) {
895 rtl818x_iowrite8(priv
, &priv
->map
->WPA_CONF
, 0);
896 rtl818x_iowrite8(priv
, &priv
->map
->RATE_FALLBACK
, 0);
898 rtl818x_iowrite8(priv
, &priv
->map
->SECURITY
, 0);
900 rtl818x_iowrite8(priv
, &priv
->map
->PHY_DELAY
, 0x6);
901 rtl818x_iowrite8(priv
, &priv
->map
->CARRIER_SENSE_COUNTER
, 0x4C);
904 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8185
) {
905 /* TODO: set ClkRun enable? necessary? */
906 reg
= rtl818x_ioread8(priv
, &priv
->map
->GP_ENABLE
);
907 rtl818x_iowrite8(priv
, &priv
->map
->GP_ENABLE
, reg
& ~(1 << 6));
908 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
909 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG3
);
910 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG3
, reg
| (1 << 2));
911 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
912 /* fix eccessive IFS after CTS-to-self */
916 reg
= rtl818x_ioread8(priv
, &priv
->map
->PGSELECT
);
917 rtl818x_iowrite8(priv
, &priv
->map
->PGSELECT
, reg
| 1);
918 rtl818x_iowrite8(priv
, REG_ADDR1(0xff), 0x35);
919 rtl818x_iowrite8(priv
, &priv
->map
->PGSELECT
, reg
);
921 rtl818x_iowrite8(priv
, REG_ADDR1(0x1ff), 0x35);
924 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
926 /* the set auto rate fallback bitmask from 1M to 54 Mb/s */
927 rtl818x_iowrite16(priv
, ARFR
, 0xFFF);
928 rtl818x_ioread16(priv
, ARFR
);
930 /* stop unused queus (no dma alloc) */
931 rtl818x_iowrite8(priv
, &priv
->map
->TPPOLL_STOP
,
932 RTL818x_TPPOLL_STOP_MG
| RTL818x_TPPOLL_STOP_HI
);
934 rtl818x_iowrite8(priv
, &priv
->map
->ACM_CONTROL
, 0x00);
935 rtl818x_iowrite16(priv
, &priv
->map
->TID_AC_MAP
, 0xFA50);
937 rtl818x_iowrite16(priv
, &priv
->map
->INT_MIG
, 0);
939 /* some black magic here.. */
940 rtl8187se_mac_config(dev
);
942 rtl818x_iowrite16(priv
, RFSW_CTRL
, 0x569A);
943 rtl818x_ioread16(priv
, RFSW_CTRL
);
945 rtl8180_set_anaparam(priv
, RTL8225SE_ANAPARAM_ON
);
946 rtl8180_set_anaparam2(priv
, RTL8225SE_ANAPARAM2_ON
);
947 rtl8180_set_anaparam3(priv
, RTL8225SE_ANAPARAM3
);
950 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG5
,
951 rtl818x_ioread8(priv
, &priv
->map
->CONFIG5
) & 0x7F);
953 /*probably this switch led on */
954 rtl818x_iowrite8(priv
, &priv
->map
->PGSELECT
,
955 rtl818x_ioread8(priv
, &priv
->map
->PGSELECT
) | 0x08);
957 rtl818x_iowrite16(priv
, &priv
->map
->RFPinsOutput
, 0x0480);
958 rtl818x_iowrite16(priv
, &priv
->map
->RFPinsEnable
, 0x1BFF);
959 rtl818x_iowrite16(priv
, &priv
->map
->RFPinsSelect
, 0x2488);
961 rtl818x_iowrite32(priv
, &priv
->map
->RF_TIMING
, 0x4003);
963 /* the reference code mac hardcode table write
964 * this reg by doing byte-wide accesses.
965 * It does it just for lowest and highest byte..
967 reg32
= rtl818x_ioread32(priv
, &priv
->map
->RF_PARA
);
970 rtl818x_iowrite32(priv
, &priv
->map
->RF_PARA
, reg32
);
972 /* stop unused queus (no dma alloc) */
973 rtl818x_iowrite8(priv
, &priv
->map
->TX_DMA_POLLING
,
978 /* default basic rates are 1,2 Mbps for rtl8180. 1,2,6,9,12,18,24 Mbps
979 * otherwise. bitmask 0x3 and 0x01f3 respectively.
980 * NOTE: currenty rtl8225 RF code changes basic rates, so we need to do
981 * this after rf init.
982 * TODO: try to find out whether RF code really needs to do this..
984 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
)
985 rtl8180_conf_basic_rates(dev
, 0x3);
987 rtl8180_conf_basic_rates(dev
, 0x1f3);
989 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
)
990 rtl8187se_set_antenna_config(dev
,
991 priv
->antenna_diversity_default
,
992 priv
->antenna_diversity_en
);
996 static int rtl8180_init_rx_ring(struct ieee80211_hw
*dev
)
998 struct rtl8180_priv
*priv
= dev
->priv
;
999 struct rtl818x_rx_cmd_desc
*entry
;
1002 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
)
1003 priv
->rx_ring_sz
= sizeof(struct rtl8187se_rx_desc
);
1005 priv
->rx_ring_sz
= sizeof(struct rtl8180_rx_desc
);
1007 priv
->rx_ring
= pci_zalloc_consistent(priv
->pdev
, priv
->rx_ring_sz
* 32,
1008 &priv
->rx_ring_dma
);
1009 if (!priv
->rx_ring
|| (unsigned long)priv
->rx_ring
& 0xFF) {
1010 wiphy_err(dev
->wiphy
, "Cannot allocate RX ring\n");
1016 for (i
= 0; i
< 32; i
++) {
1017 struct sk_buff
*skb
= dev_alloc_skb(MAX_RX_SIZE
);
1018 dma_addr_t
*mapping
;
1019 entry
= priv
->rx_ring
+ priv
->rx_ring_sz
*i
;
1021 pci_free_consistent(priv
->pdev
, priv
->rx_ring_sz
* 32,
1022 priv
->rx_ring
, priv
->rx_ring_dma
);
1023 wiphy_err(dev
->wiphy
, "Cannot allocate RX skb\n");
1026 priv
->rx_buf
[i
] = skb
;
1027 mapping
= (dma_addr_t
*)skb
->cb
;
1028 *mapping
= pci_map_single(priv
->pdev
, skb_tail_pointer(skb
),
1029 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
1031 if (pci_dma_mapping_error(priv
->pdev
, *mapping
)) {
1033 pci_free_consistent(priv
->pdev
, priv
->rx_ring_sz
* 32,
1034 priv
->rx_ring
, priv
->rx_ring_dma
);
1035 wiphy_err(dev
->wiphy
, "Cannot map DMA for RX skb\n");
1039 entry
->rx_buf
= cpu_to_le32(*mapping
);
1040 entry
->flags
= cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN
|
1043 entry
->flags
|= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR
);
1047 static void rtl8180_free_rx_ring(struct ieee80211_hw
*dev
)
1049 struct rtl8180_priv
*priv
= dev
->priv
;
1052 for (i
= 0; i
< 32; i
++) {
1053 struct sk_buff
*skb
= priv
->rx_buf
[i
];
1057 pci_unmap_single(priv
->pdev
,
1058 *((dma_addr_t
*)skb
->cb
),
1059 MAX_RX_SIZE
, PCI_DMA_FROMDEVICE
);
1063 pci_free_consistent(priv
->pdev
, priv
->rx_ring_sz
* 32,
1064 priv
->rx_ring
, priv
->rx_ring_dma
);
1065 priv
->rx_ring
= NULL
;
1068 static int rtl8180_init_tx_ring(struct ieee80211_hw
*dev
,
1069 unsigned int prio
, unsigned int entries
)
1071 struct rtl8180_priv
*priv
= dev
->priv
;
1072 struct rtl8180_tx_desc
*ring
;
1076 ring
= pci_zalloc_consistent(priv
->pdev
, sizeof(*ring
) * entries
,
1078 if (!ring
|| (unsigned long)ring
& 0xFF) {
1079 wiphy_err(dev
->wiphy
, "Cannot allocate TX ring (prio = %d)\n",
1084 priv
->tx_ring
[prio
].desc
= ring
;
1085 priv
->tx_ring
[prio
].dma
= dma
;
1086 priv
->tx_ring
[prio
].idx
= 0;
1087 priv
->tx_ring
[prio
].entries
= entries
;
1088 skb_queue_head_init(&priv
->tx_ring
[prio
].queue
);
1090 for (i
= 0; i
< entries
; i
++)
1091 ring
[i
].next_tx_desc
=
1092 cpu_to_le32((u32
)dma
+ ((i
+ 1) % entries
) * sizeof(*ring
));
1097 static void rtl8180_free_tx_ring(struct ieee80211_hw
*dev
, unsigned int prio
)
1099 struct rtl8180_priv
*priv
= dev
->priv
;
1100 struct rtl8180_tx_ring
*ring
= &priv
->tx_ring
[prio
];
1102 while (skb_queue_len(&ring
->queue
)) {
1103 struct rtl8180_tx_desc
*entry
= &ring
->desc
[ring
->idx
];
1104 struct sk_buff
*skb
= __skb_dequeue(&ring
->queue
);
1106 pci_unmap_single(priv
->pdev
, le32_to_cpu(entry
->tx_buf
),
1107 skb
->len
, PCI_DMA_TODEVICE
);
1109 ring
->idx
= (ring
->idx
+ 1) % ring
->entries
;
1112 pci_free_consistent(priv
->pdev
, sizeof(*ring
->desc
)*ring
->entries
,
1113 ring
->desc
, ring
->dma
);
1117 static int rtl8180_start(struct ieee80211_hw
*dev
)
1119 struct rtl8180_priv
*priv
= dev
->priv
;
1123 ret
= rtl8180_init_rx_ring(dev
);
1127 for (i
= 0; i
< (dev
->queues
+ 1); i
++)
1128 if ((ret
= rtl8180_init_tx_ring(dev
, i
, 16)))
1129 goto err_free_rings
;
1131 ret
= rtl8180_init_hw(dev
);
1133 goto err_free_rings
;
1135 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
1136 ret
= request_irq(priv
->pdev
->irq
, rtl8187se_interrupt
,
1137 IRQF_SHARED
, KBUILD_MODNAME
, dev
);
1139 ret
= request_irq(priv
->pdev
->irq
, rtl8180_interrupt
,
1140 IRQF_SHARED
, KBUILD_MODNAME
, dev
);
1144 wiphy_err(dev
->wiphy
, "failed to register IRQ handler\n");
1145 goto err_free_rings
;
1148 rtl8180_int_enable(dev
);
1150 /* in rtl8187se at MAR regs offset there is the management
1151 * TX descriptor DMA addres..
1153 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8187SE
) {
1154 rtl818x_iowrite32(priv
, &priv
->map
->MAR
[0], ~0);
1155 rtl818x_iowrite32(priv
, &priv
->map
->MAR
[1], ~0);
1158 reg
= RTL818X_RX_CONF_ONLYERLPKT
|
1159 RTL818X_RX_CONF_RX_AUTORESETPHY
|
1160 RTL818X_RX_CONF_MGMT
|
1161 RTL818X_RX_CONF_DATA
|
1162 (7 << 8 /* MAX RX DMA */) |
1163 RTL818X_RX_CONF_BROADCAST
|
1164 RTL818X_RX_CONF_NICMAC
;
1166 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8185
)
1167 reg
|= RTL818X_RX_CONF_CSDM1
| RTL818X_RX_CONF_CSDM2
;
1168 else if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
) {
1169 reg
|= (priv
->rfparam
& RF_PARAM_CARRIERSENSE1
)
1170 ? RTL818X_RX_CONF_CSDM1
: 0;
1171 reg
|= (priv
->rfparam
& RF_PARAM_CARRIERSENSE2
)
1172 ? RTL818X_RX_CONF_CSDM2
: 0;
1174 reg
&= ~(RTL818X_RX_CONF_CSDM1
| RTL818X_RX_CONF_CSDM2
);
1177 priv
->rx_conf
= reg
;
1178 rtl818x_iowrite32(priv
, &priv
->map
->RX_CONF
, reg
);
1180 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
) {
1181 reg
= rtl818x_ioread8(priv
, &priv
->map
->CW_CONF
);
1183 /* CW is not on per-packet basis.
1184 * in rtl8185 the CW_VALUE reg is used.
1185 * in rtl8187se the AC param regs are used.
1187 reg
&= ~RTL818X_CW_CONF_PERPACKET_CW
;
1188 /* retry limit IS on per-packet basis.
1189 * the short and long retry limit in TX_CONF
1192 reg
|= RTL818X_CW_CONF_PERPACKET_RETRY
;
1193 rtl818x_iowrite8(priv
, &priv
->map
->CW_CONF
, reg
);
1195 reg
= rtl818x_ioread8(priv
, &priv
->map
->TX_AGC_CTL
);
1196 /* TX antenna and TX gain are not on per-packet basis.
1197 * TX Antenna is selected by ANTSEL reg (RX in BB regs).
1198 * TX gain is selected with CCK_TX_AGC and OFDM_TX_AGC regs
1200 reg
&= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN
;
1201 reg
&= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL
;
1202 reg
|= RTL818X_TX_AGC_CTL_FEEDBACK_ANT
;
1203 rtl818x_iowrite8(priv
, &priv
->map
->TX_AGC_CTL
, reg
);
1205 /* disable early TX */
1206 rtl818x_iowrite8(priv
, (u8 __iomem
*)priv
->map
+ 0xec, 0x3f);
1209 reg
= rtl818x_ioread32(priv
, &priv
->map
->TX_CONF
);
1210 reg
|= (6 << 21 /* MAX TX DMA */) |
1211 RTL818X_TX_CONF_NO_ICV
;
1213 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
)
1214 reg
|= 1<<30; /* "duration procedure mode" */
1216 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
)
1217 reg
&= ~RTL818X_TX_CONF_PROBE_DTS
;
1219 reg
&= ~RTL818X_TX_CONF_HW_SEQNUM
;
1221 reg
&= ~RTL818X_TX_CONF_DISCW
;
1223 /* different meaning, same value on both rtl8185 and rtl8180 */
1224 reg
&= ~RTL818X_TX_CONF_SAT_HWPLCP
;
1226 rtl818x_iowrite32(priv
, &priv
->map
->TX_CONF
, reg
);
1228 reg
= rtl818x_ioread8(priv
, &priv
->map
->CMD
);
1229 reg
|= RTL818X_CMD_RX_ENABLE
;
1230 reg
|= RTL818X_CMD_TX_ENABLE
;
1231 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, reg
);
1236 rtl8180_free_rx_ring(dev
);
1237 for (i
= 0; i
< (dev
->queues
+ 1); i
++)
1238 if (priv
->tx_ring
[i
].desc
)
1239 rtl8180_free_tx_ring(dev
, i
);
1244 static void rtl8180_stop(struct ieee80211_hw
*dev
)
1246 struct rtl8180_priv
*priv
= dev
->priv
;
1250 rtl8180_int_disable(dev
);
1252 reg
= rtl818x_ioread8(priv
, &priv
->map
->CMD
);
1253 reg
&= ~RTL818X_CMD_TX_ENABLE
;
1254 reg
&= ~RTL818X_CMD_RX_ENABLE
;
1255 rtl818x_iowrite8(priv
, &priv
->map
->CMD
, reg
);
1257 priv
->rf
->stop(dev
);
1259 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
1260 reg
= rtl818x_ioread8(priv
, &priv
->map
->CONFIG4
);
1261 rtl818x_iowrite8(priv
, &priv
->map
->CONFIG4
, reg
| RTL818X_CONFIG4_VCOOFF
);
1262 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
1264 free_irq(priv
->pdev
->irq
, dev
);
1266 rtl8180_free_rx_ring(dev
);
1267 for (i
= 0; i
< (dev
->queues
+ 1); i
++)
1268 rtl8180_free_tx_ring(dev
, i
);
1271 static u64
rtl8180_get_tsf(struct ieee80211_hw
*dev
,
1272 struct ieee80211_vif
*vif
)
1274 struct rtl8180_priv
*priv
= dev
->priv
;
1276 return rtl818x_ioread32(priv
, &priv
->map
->TSFT
[0]) |
1277 (u64
)(rtl818x_ioread32(priv
, &priv
->map
->TSFT
[1])) << 32;
1280 static void rtl8180_beacon_work(struct work_struct
*work
)
1282 struct rtl8180_vif
*vif_priv
=
1283 container_of(work
, struct rtl8180_vif
, beacon_work
.work
);
1284 struct ieee80211_vif
*vif
=
1285 container_of((void *)vif_priv
, struct ieee80211_vif
, drv_priv
);
1286 struct ieee80211_hw
*dev
= vif_priv
->dev
;
1287 struct ieee80211_mgmt
*mgmt
;
1288 struct sk_buff
*skb
;
1290 /* don't overflow the tx ring */
1291 if (ieee80211_queue_stopped(dev
, 0))
1294 /* grab a fresh beacon */
1295 skb
= ieee80211_beacon_get(dev
, vif
);
1300 * update beacon timestamp w/ TSF value
1301 * TODO: make hardware update beacon timestamp
1303 mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1304 mgmt
->u
.beacon
.timestamp
= cpu_to_le64(rtl8180_get_tsf(dev
, vif
));
1306 /* TODO: use actual beacon queue */
1307 skb_set_queue_mapping(skb
, 0);
1309 rtl8180_tx(dev
, NULL
, skb
);
1313 * schedule next beacon
1314 * TODO: use hardware support for beacon timing
1316 schedule_delayed_work(&vif_priv
->beacon_work
,
1317 usecs_to_jiffies(1024 * vif
->bss_conf
.beacon_int
));
1320 static int rtl8180_add_interface(struct ieee80211_hw
*dev
,
1321 struct ieee80211_vif
*vif
)
1323 struct rtl8180_priv
*priv
= dev
->priv
;
1324 struct rtl8180_vif
*vif_priv
;
1327 * We only support one active interface at a time.
1332 switch (vif
->type
) {
1333 case NL80211_IFTYPE_STATION
:
1334 case NL80211_IFTYPE_ADHOC
:
1342 /* Initialize driver private area */
1343 vif_priv
= (struct rtl8180_vif
*)&vif
->drv_priv
;
1344 vif_priv
->dev
= dev
;
1345 INIT_DELAYED_WORK(&vif_priv
->beacon_work
, rtl8180_beacon_work
);
1346 vif_priv
->enable_beacon
= false;
1348 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_CONFIG
);
1349 rtl818x_iowrite32(priv
, (__le32 __iomem
*)&priv
->map
->MAC
[0],
1350 le32_to_cpu(*(__le32
*)vif
->addr
));
1351 rtl818x_iowrite16(priv
, (__le16 __iomem
*)&priv
->map
->MAC
[4],
1352 le16_to_cpu(*(__le16
*)(vif
->addr
+ 4)));
1353 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, RTL818X_EEPROM_CMD_NORMAL
);
1358 static void rtl8180_remove_interface(struct ieee80211_hw
*dev
,
1359 struct ieee80211_vif
*vif
)
1361 struct rtl8180_priv
*priv
= dev
->priv
;
1365 static int rtl8180_config(struct ieee80211_hw
*dev
, u32 changed
)
1367 struct rtl8180_priv
*priv
= dev
->priv
;
1368 struct ieee80211_conf
*conf
= &dev
->conf
;
1370 priv
->rf
->set_chan(dev
, conf
);
1375 static void rtl8187se_conf_ac_parm(struct ieee80211_hw
*dev
, u8 queue
)
1377 const struct ieee80211_tx_queue_params
*params
;
1378 struct rtl8180_priv
*priv
= dev
->priv
;
1387 params
= &priv
->queue_param
[queue
];
1389 cw_min
= fls(params
->cw_min
);
1390 cw_max
= fls(params
->cw_max
);
1392 aifs
= 10 + params
->aifs
* priv
->slot_time
;
1394 /* TODO: check if txop HW is in us (mult by 32) */
1395 txop
= params
->txop
;
1397 ac_param
= txop
<< AC_PARAM_TXOP_LIMIT_SHIFT
|
1398 cw_max
<< AC_PARAM_ECW_MAX_SHIFT
|
1399 cw_min
<< AC_PARAM_ECW_MIN_SHIFT
|
1400 aifs
<< AC_PARAM_AIFS_SHIFT
;
1403 case IEEE80211_AC_BK
:
1404 rtl818x_iowrite32(priv
, &priv
->map
->AC_BK_PARAM
, ac_param
);
1406 case IEEE80211_AC_BE
:
1407 rtl818x_iowrite32(priv
, &priv
->map
->AC_BE_PARAM
, ac_param
);
1409 case IEEE80211_AC_VI
:
1410 rtl818x_iowrite32(priv
, &priv
->map
->AC_VI_PARAM
, ac_param
);
1412 case IEEE80211_AC_VO
:
1413 rtl818x_iowrite32(priv
, &priv
->map
->AC_VO_PARAM
, ac_param
);
1418 static int rtl8180_conf_tx(struct ieee80211_hw
*dev
,
1419 struct ieee80211_vif
*vif
, u16 queue
,
1420 const struct ieee80211_tx_queue_params
*params
)
1422 struct rtl8180_priv
*priv
= dev
->priv
;
1425 /* nothing to do ? */
1426 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
)
1429 cw_min
= fls(params
->cw_min
);
1430 cw_max
= fls(params
->cw_max
);
1432 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
1433 priv
->queue_param
[queue
] = *params
;
1434 rtl8187se_conf_ac_parm(dev
, queue
);
1436 rtl818x_iowrite8(priv
, &priv
->map
->CW_VAL
,
1437 (cw_max
<< 4) | cw_min
);
1441 static void rtl8180_conf_erp(struct ieee80211_hw
*dev
,
1442 struct ieee80211_bss_conf
*info
)
1444 struct rtl8180_priv
*priv
= dev
->priv
;
1449 /* TODO: should we do something ? */
1450 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
)
1453 /* I _hope_ this means 10uS for the HW.
1454 * In reference code it is 0x22 for
1455 * both rtl8187L and rtl8187SE
1459 if (info
->use_short_slot
)
1460 priv
->slot_time
= 9;
1462 priv
->slot_time
= 20;
1464 /* 10 is SIFS time in uS */
1465 difs
= 10 + 2 * priv
->slot_time
;
1466 eifs
= 10 + difs
+ priv
->ack_time
;
1468 /* HW should use 4uS units for EIFS (I'm sure for rtl8185)*/
1469 hw_eifs
= DIV_ROUND_UP(eifs
, 4);
1472 rtl818x_iowrite8(priv
, &priv
->map
->SLOT
, priv
->slot_time
);
1473 rtl818x_iowrite8(priv
, &priv
->map
->SIFS
, sifs
);
1474 rtl818x_iowrite8(priv
, &priv
->map
->DIFS
, difs
);
1476 /* from reference code. set ack timeout reg = eifs reg */
1477 rtl818x_iowrite8(priv
, &priv
->map
->CARRIER_SENSE_COUNTER
, hw_eifs
);
1479 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
)
1480 rtl818x_iowrite8(priv
, &priv
->map
->EIFS_8187SE
, hw_eifs
);
1481 else if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8185
) {
1482 /* rtl8187/rtl8185 HW bug. After EIFS is elapsed,
1483 * the HW still wait for DIFS.
1484 * HW uses 4uS units for EIFS.
1486 hw_eifs
= DIV_ROUND_UP(eifs
- difs
, 4);
1488 rtl818x_iowrite8(priv
, &priv
->map
->EIFS
, hw_eifs
);
1492 static void rtl8180_bss_info_changed(struct ieee80211_hw
*dev
,
1493 struct ieee80211_vif
*vif
,
1494 struct ieee80211_bss_conf
*info
,
1497 struct rtl8180_priv
*priv
= dev
->priv
;
1498 struct rtl8180_vif
*vif_priv
;
1502 vif_priv
= (struct rtl8180_vif
*)&vif
->drv_priv
;
1504 if (changed
& BSS_CHANGED_BSSID
) {
1505 rtl818x_iowrite16(priv
, (__le16 __iomem
*)&priv
->map
->BSSID
[0],
1506 le16_to_cpu(*(__le16
*)info
->bssid
));
1507 rtl818x_iowrite32(priv
, (__le32 __iomem
*)&priv
->map
->BSSID
[2],
1508 le32_to_cpu(*(__le32
*)(info
->bssid
+ 2)));
1510 if (is_valid_ether_addr(info
->bssid
)) {
1511 if (vif
->type
== NL80211_IFTYPE_ADHOC
)
1512 reg
= RTL818X_MSR_ADHOC
;
1514 reg
= RTL818X_MSR_INFRA
;
1516 reg
= RTL818X_MSR_NO_LINK
;
1518 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
)
1519 reg
|= RTL818X_MSR_ENEDCA
;
1521 rtl818x_iowrite8(priv
, &priv
->map
->MSR
, reg
);
1524 if (changed
& BSS_CHANGED_BASIC_RATES
)
1525 rtl8180_conf_basic_rates(dev
, info
->basic_rates
);
1527 if (changed
& (BSS_CHANGED_ERP_SLOT
| BSS_CHANGED_ERP_PREAMBLE
)) {
1529 /* when preamble changes, acktime duration changes, and erp must
1530 * be recalculated. ACK time is calculated at lowest rate.
1531 * Since mac80211 include SIFS time we remove it (-10)
1534 le16_to_cpu(ieee80211_generic_frame_duration(dev
,
1536 NL80211_BAND_2GHZ
, 10,
1537 &priv
->rates
[0])) - 10;
1539 rtl8180_conf_erp(dev
, info
);
1541 /* mac80211 supplies aifs_n to driver and calls
1542 * conf_tx callback whether aifs_n changes, NOT
1543 * when aifs changes.
1544 * Aifs should be recalculated if slot changes.
1546 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
1547 for (i
= 0; i
< 4; i
++)
1548 rtl8187se_conf_ac_parm(dev
, i
);
1552 if (changed
& BSS_CHANGED_BEACON_ENABLED
)
1553 vif_priv
->enable_beacon
= info
->enable_beacon
;
1555 if (changed
& (BSS_CHANGED_BEACON_ENABLED
| BSS_CHANGED_BEACON
)) {
1556 cancel_delayed_work_sync(&vif_priv
->beacon_work
);
1557 if (vif_priv
->enable_beacon
)
1558 schedule_work(&vif_priv
->beacon_work
.work
);
1562 static u64
rtl8180_prepare_multicast(struct ieee80211_hw
*dev
,
1563 struct netdev_hw_addr_list
*mc_list
)
1565 return netdev_hw_addr_list_count(mc_list
);
1568 static void rtl8180_configure_filter(struct ieee80211_hw
*dev
,
1569 unsigned int changed_flags
,
1570 unsigned int *total_flags
,
1573 struct rtl8180_priv
*priv
= dev
->priv
;
1575 if (changed_flags
& FIF_FCSFAIL
)
1576 priv
->rx_conf
^= RTL818X_RX_CONF_FCS
;
1577 if (changed_flags
& FIF_CONTROL
)
1578 priv
->rx_conf
^= RTL818X_RX_CONF_CTRL
;
1579 if (changed_flags
& FIF_OTHER_BSS
)
1580 priv
->rx_conf
^= RTL818X_RX_CONF_MONITOR
;
1581 if (*total_flags
& FIF_ALLMULTI
|| multicast
> 0)
1582 priv
->rx_conf
|= RTL818X_RX_CONF_MULTICAST
;
1584 priv
->rx_conf
&= ~RTL818X_RX_CONF_MULTICAST
;
1588 if (priv
->rx_conf
& RTL818X_RX_CONF_FCS
)
1589 *total_flags
|= FIF_FCSFAIL
;
1590 if (priv
->rx_conf
& RTL818X_RX_CONF_CTRL
)
1591 *total_flags
|= FIF_CONTROL
;
1592 if (priv
->rx_conf
& RTL818X_RX_CONF_MONITOR
)
1593 *total_flags
|= FIF_OTHER_BSS
;
1594 if (priv
->rx_conf
& RTL818X_RX_CONF_MULTICAST
)
1595 *total_flags
|= FIF_ALLMULTI
;
1597 rtl818x_iowrite32(priv
, &priv
->map
->RX_CONF
, priv
->rx_conf
);
1600 static const struct ieee80211_ops rtl8180_ops
= {
1602 .start
= rtl8180_start
,
1603 .stop
= rtl8180_stop
,
1604 .add_interface
= rtl8180_add_interface
,
1605 .remove_interface
= rtl8180_remove_interface
,
1606 .config
= rtl8180_config
,
1607 .bss_info_changed
= rtl8180_bss_info_changed
,
1608 .conf_tx
= rtl8180_conf_tx
,
1609 .prepare_multicast
= rtl8180_prepare_multicast
,
1610 .configure_filter
= rtl8180_configure_filter
,
1611 .get_tsf
= rtl8180_get_tsf
,
1614 static void rtl8180_eeprom_register_read(struct eeprom_93cx6
*eeprom
)
1616 struct rtl8180_priv
*priv
= eeprom
->data
;
1617 u8 reg
= rtl818x_ioread8(priv
, &priv
->map
->EEPROM_CMD
);
1619 eeprom
->reg_data_in
= reg
& RTL818X_EEPROM_CMD_WRITE
;
1620 eeprom
->reg_data_out
= reg
& RTL818X_EEPROM_CMD_READ
;
1621 eeprom
->reg_data_clock
= reg
& RTL818X_EEPROM_CMD_CK
;
1622 eeprom
->reg_chip_select
= reg
& RTL818X_EEPROM_CMD_CS
;
1625 static void rtl8180_eeprom_register_write(struct eeprom_93cx6
*eeprom
)
1627 struct rtl8180_priv
*priv
= eeprom
->data
;
1630 if (eeprom
->reg_data_in
)
1631 reg
|= RTL818X_EEPROM_CMD_WRITE
;
1632 if (eeprom
->reg_data_out
)
1633 reg
|= RTL818X_EEPROM_CMD_READ
;
1634 if (eeprom
->reg_data_clock
)
1635 reg
|= RTL818X_EEPROM_CMD_CK
;
1636 if (eeprom
->reg_chip_select
)
1637 reg
|= RTL818X_EEPROM_CMD_CS
;
1639 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
, reg
);
1640 rtl818x_ioread8(priv
, &priv
->map
->EEPROM_CMD
);
1644 static void rtl8180_eeprom_read(struct rtl8180_priv
*priv
)
1646 struct eeprom_93cx6 eeprom
;
1647 int eeprom_cck_table_adr
;
1652 eeprom
.register_read
= rtl8180_eeprom_register_read
;
1653 eeprom
.register_write
= rtl8180_eeprom_register_write
;
1654 if (rtl818x_ioread32(priv
, &priv
->map
->RX_CONF
) & (1 << 6))
1655 eeprom
.width
= PCI_EEPROM_WIDTH_93C66
;
1657 eeprom
.width
= PCI_EEPROM_WIDTH_93C46
;
1659 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
1660 RTL818X_EEPROM_CMD_PROGRAM
);
1661 rtl818x_ioread8(priv
, &priv
->map
->EEPROM_CMD
);
1664 eeprom_93cx6_read(&eeprom
, 0x06, &eeprom_val
);
1666 priv
->rf_type
= eeprom_val
;
1668 eeprom_93cx6_read(&eeprom
, 0x17, &eeprom_val
);
1669 priv
->csthreshold
= eeprom_val
>> 8;
1671 eeprom_93cx6_multiread(&eeprom
, 0x7, (__le16
*)priv
->mac_addr
, 3);
1673 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
)
1674 eeprom_cck_table_adr
= 0x30;
1676 eeprom_cck_table_adr
= 0x10;
1679 for (i
= 0; i
< 14; i
+= 2) {
1681 eeprom_93cx6_read(&eeprom
, eeprom_cck_table_adr
+ (i
>> 1),
1683 priv
->channels
[i
].hw_value
= txpwr
& 0xFF;
1684 priv
->channels
[i
+ 1].hw_value
= txpwr
>> 8;
1688 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
) {
1689 for (i
= 0; i
< 14; i
+= 2) {
1691 eeprom_93cx6_read(&eeprom
, 0x20 + (i
>> 1), &txpwr
);
1692 priv
->channels
[i
].hw_value
|= (txpwr
& 0xFF) << 8;
1693 priv
->channels
[i
+ 1].hw_value
|= txpwr
& 0xFF00;
1697 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8180
) {
1699 eeprom_93cx6_multiread(&eeprom
, 0xD, (__le16
*)&anaparam
, 2);
1700 priv
->anaparam
= le32_to_cpu(anaparam
);
1701 eeprom_93cx6_read(&eeprom
, 0x19, &priv
->rfparam
);
1704 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
) {
1705 eeprom_93cx6_read(&eeprom
, 0x3F, &eeprom_val
);
1706 priv
->antenna_diversity_en
= !!(eeprom_val
& 0x100);
1707 priv
->antenna_diversity_default
= (eeprom_val
& 0xC00) == 0x400;
1709 eeprom_93cx6_read(&eeprom
, 0x7C, &eeprom_val
);
1710 priv
->xtal_out
= eeprom_val
& 0xF;
1711 priv
->xtal_in
= (eeprom_val
& 0xF0) >> 4;
1712 priv
->xtal_cal
= !!(eeprom_val
& 0x1000);
1713 priv
->thermal_meter_val
= (eeprom_val
& 0xF00) >> 8;
1714 priv
->thermal_meter_en
= !!(eeprom_val
& 0x2000);
1717 rtl818x_iowrite8(priv
, &priv
->map
->EEPROM_CMD
,
1718 RTL818X_EEPROM_CMD_NORMAL
);
1721 static int rtl8180_probe(struct pci_dev
*pdev
,
1722 const struct pci_device_id
*id
)
1724 struct ieee80211_hw
*dev
;
1725 struct rtl8180_priv
*priv
;
1726 unsigned long mem_addr
, mem_len
;
1727 unsigned int io_addr
, io_len
;
1729 const char *chip_name
, *rf_name
= NULL
;
1732 err
= pci_enable_device(pdev
);
1734 printk(KERN_ERR
"%s (rtl8180): Cannot enable new PCI device\n",
1739 err
= pci_request_regions(pdev
, KBUILD_MODNAME
);
1741 printk(KERN_ERR
"%s (rtl8180): Cannot obtain PCI resources\n",
1743 goto err_disable_dev
;
1746 io_addr
= pci_resource_start(pdev
, 0);
1747 io_len
= pci_resource_len(pdev
, 0);
1748 mem_addr
= pci_resource_start(pdev
, 1);
1749 mem_len
= pci_resource_len(pdev
, 1);
1751 if (mem_len
< sizeof(struct rtl818x_csr
) ||
1752 io_len
< sizeof(struct rtl818x_csr
)) {
1753 printk(KERN_ERR
"%s (rtl8180): Too short PCI resources\n",
1759 if ((err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32))) ||
1760 (err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32)))) {
1761 printk(KERN_ERR
"%s (rtl8180): No suitable DMA available\n",
1766 pci_set_master(pdev
);
1768 dev
= ieee80211_alloc_hw(sizeof(*priv
), &rtl8180_ops
);
1770 printk(KERN_ERR
"%s (rtl8180): ieee80211 alloc failed\n",
1780 SET_IEEE80211_DEV(dev
, &pdev
->dev
);
1781 pci_set_drvdata(pdev
, dev
);
1783 priv
->map_pio
= false;
1784 priv
->map
= pci_iomap(pdev
, 1, mem_len
);
1786 priv
->map
= pci_iomap(pdev
, 0, io_len
);
1787 priv
->map_pio
= true;
1791 dev_err(&pdev
->dev
, "Cannot map device memory/PIO\n");
1796 BUILD_BUG_ON(sizeof(priv
->channels
) != sizeof(rtl818x_channels
));
1797 BUILD_BUG_ON(sizeof(priv
->rates
) != sizeof(rtl818x_rates
));
1799 memcpy(priv
->channels
, rtl818x_channels
, sizeof(rtl818x_channels
));
1800 memcpy(priv
->rates
, rtl818x_rates
, sizeof(rtl818x_rates
));
1802 priv
->band
.band
= NL80211_BAND_2GHZ
;
1803 priv
->band
.channels
= priv
->channels
;
1804 priv
->band
.n_channels
= ARRAY_SIZE(rtl818x_channels
);
1805 priv
->band
.bitrates
= priv
->rates
;
1806 priv
->band
.n_bitrates
= 4;
1807 dev
->wiphy
->bands
[NL80211_BAND_2GHZ
] = &priv
->band
;
1809 ieee80211_hw_set(dev
, HOST_BROADCAST_PS_BUFFERING
);
1810 ieee80211_hw_set(dev
, RX_INCLUDES_FCS
);
1812 dev
->vif_data_size
= sizeof(struct rtl8180_vif
);
1813 dev
->wiphy
->interface_modes
= BIT(NL80211_IFTYPE_STATION
) |
1814 BIT(NL80211_IFTYPE_ADHOC
);
1815 dev
->max_signal
= 65;
1817 reg
= rtl818x_ioread32(priv
, &priv
->map
->TX_CONF
);
1818 reg
&= RTL818X_TX_CONF_HWVER_MASK
;
1820 case RTL818X_TX_CONF_R8180_ABCD
:
1821 chip_name
= "RTL8180";
1822 priv
->chip_family
= RTL818X_CHIP_FAMILY_RTL8180
;
1825 case RTL818X_TX_CONF_R8180_F
:
1826 chip_name
= "RTL8180vF";
1827 priv
->chip_family
= RTL818X_CHIP_FAMILY_RTL8180
;
1830 case RTL818X_TX_CONF_R8185_ABC
:
1831 chip_name
= "RTL8185";
1832 priv
->chip_family
= RTL818X_CHIP_FAMILY_RTL8185
;
1835 case RTL818X_TX_CONF_R8185_D
:
1836 chip_name
= "RTL8185vD";
1837 priv
->chip_family
= RTL818X_CHIP_FAMILY_RTL8185
;
1840 case RTL818X_TX_CONF_RTL8187SE
:
1841 chip_name
= "RTL8187SE";
1842 if (priv
->map_pio
) {
1844 "MMIO failed. PIO not supported on RTL8187SE\n");
1848 priv
->chip_family
= RTL818X_CHIP_FAMILY_RTL8187SE
;
1852 printk(KERN_ERR
"%s (rtl8180): Unknown chip! (0x%x)\n",
1853 pci_name(pdev
), reg
>> 25);
1858 /* we declare to MAC80211 all the queues except for beacon queue
1859 * that will be eventually handled by DRV.
1860 * TX rings are arranged in such a way that lower is the IDX,
1861 * higher is the priority, in order to achieve direct mapping
1862 * with mac80211, however the beacon queue is an exception and it
1863 * is mapped on the highst tx ring IDX.
1865 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
)
1866 dev
->queues
= RTL8187SE_NR_TX_QUEUES
- 1;
1868 dev
->queues
= RTL8180_NR_TX_QUEUES
- 1;
1870 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
) {
1871 priv
->band
.n_bitrates
= ARRAY_SIZE(rtl818x_rates
);
1872 pci_try_set_mwi(pdev
);
1875 if (priv
->chip_family
!= RTL818X_CHIP_FAMILY_RTL8180
)
1876 ieee80211_hw_set(dev
, SIGNAL_DBM
);
1878 ieee80211_hw_set(dev
, SIGNAL_UNSPEC
);
1880 rtl8180_eeprom_read(priv
);
1882 switch (priv
->rf_type
) {
1883 case 1: rf_name
= "Intersil";
1885 case 2: rf_name
= "RFMD";
1887 case 3: priv
->rf
= &sa2400_rf_ops
;
1889 case 4: priv
->rf
= &max2820_rf_ops
;
1891 case 5: priv
->rf
= &grf5101_rf_ops
;
1894 if (priv
->chip_family
== RTL818X_CHIP_FAMILY_RTL8187SE
)
1895 priv
->rf
= rtl8187se_detect_rf(dev
);
1897 priv
->rf
= rtl8180_detect_rf(dev
);
1900 rf_name
= "RTL8255";
1903 printk(KERN_ERR
"%s (rtl8180): Unknown RF! (0x%x)\n",
1904 pci_name(pdev
), priv
->rf_type
);
1910 printk(KERN_ERR
"%s (rtl8180): %s RF frontend not supported!\n",
1911 pci_name(pdev
), rf_name
);
1916 if (!is_valid_ether_addr(priv
->mac_addr
)) {
1917 printk(KERN_WARNING
"%s (rtl8180): Invalid hwaddr! Using"
1918 " randomly generated MAC addr\n", pci_name(pdev
));
1919 eth_random_addr(priv
->mac_addr
);
1921 SET_IEEE80211_PERM_ADDR(dev
, priv
->mac_addr
);
1923 spin_lock_init(&priv
->lock
);
1925 err
= ieee80211_register_hw(dev
);
1927 printk(KERN_ERR
"%s (rtl8180): Cannot register device\n",
1932 wiphy_info(dev
->wiphy
, "hwaddr %pm, %s + %s\n",
1933 priv
->mac_addr
, chip_name
, priv
->rf
->name
);
1938 pci_iounmap(pdev
, priv
->map
);
1941 ieee80211_free_hw(dev
);
1944 pci_release_regions(pdev
);
1947 pci_disable_device(pdev
);
1951 static void rtl8180_remove(struct pci_dev
*pdev
)
1953 struct ieee80211_hw
*dev
= pci_get_drvdata(pdev
);
1954 struct rtl8180_priv
*priv
;
1959 ieee80211_unregister_hw(dev
);
1963 pci_iounmap(pdev
, priv
->map
);
1964 pci_release_regions(pdev
);
1965 pci_disable_device(pdev
);
1966 ieee80211_free_hw(dev
);
1970 static int rtl8180_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1972 pci_save_state(pdev
);
1973 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
1977 static int rtl8180_resume(struct pci_dev
*pdev
)
1979 pci_set_power_state(pdev
, PCI_D0
);
1980 pci_restore_state(pdev
);
1984 #endif /* CONFIG_PM */
1986 static struct pci_driver rtl8180_driver
= {
1987 .name
= KBUILD_MODNAME
,
1988 .id_table
= rtl8180_table
,
1989 .probe
= rtl8180_probe
,
1990 .remove
= rtl8180_remove
,
1992 .suspend
= rtl8180_suspend
,
1993 .resume
= rtl8180_resume
,
1994 #endif /* CONFIG_PM */
1997 module_pci_driver(rtl8180_driver
);