1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
20 /******************************************************************************
23 * Module: rtl8192c_rf6052.c ( Source C File)
25 * Note: Provide RF 6052 series relative API.
36 * 09/25/2008 MHC Create initial version.
37 * 11/05/2008 MHC Add API for tw power setting.
40 ******************************************************************************/
42 #define _RTL8192C_RF6052_C_
45 #include <osdep_service.h>
46 #include <drv_types.h>
47 #include <rtw_byteorder.h>
49 #include <rtl8192c_hal.h>
51 /*---------------------------Define Local Constant---------------------------*/
52 // Define local structure for debug!!!!!
53 typedef struct RF_Shadow_Compare_Map
{
54 // Shadow register value
56 // Compare or not flag
58 // Record If it had ever modified unpredicted
65 /*---------------------------Define Local Constant---------------------------*/
68 /*------------------------Define global variable-----------------------------*/
69 /*------------------------Define global variable-----------------------------*/
72 /*------------------------Define local variable------------------------------*/
73 // 2008/11/20 MH For Debug only, RF
74 //static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG] = {0};
75 static RF_SHADOW_T RF_Shadow
[RF6052_MAX_PATH
][RF6052_MAX_REG
];
76 /*------------------------Define local variable------------------------------*/
79 /*-----------------------------------------------------------------------------
80 * Function: RF_ChangeTxPath
82 * Overview: For RL6052, we must change some RF settign for 1T or 2T.
84 * Input: u2Byte DataRate // 0x80-8f, 0x90-9f
92 * 09/25/2008 MHC Create Version 0.
93 * Firmwaer support the utility later.
95 *---------------------------------------------------------------------------*/
96 void rtl8192c_RF_ChangeTxPath( IN PADAPTER Adapter
,
99 // We do not support gain table change inACUT now !!!! Delete later !!!
100 #if 0//(RTL92SE_FPGA_VERIFY == 0)
101 static u1Byte RF_Path_Type
= 2; // 1 = 1T 2= 2T
102 static u4Byte tx_gain_tbl1
[6]
103 = {0x17f50, 0x11f40, 0x0cf30, 0x08720, 0x04310, 0x00100};
104 static u4Byte tx_gain_tbl2
[6]
105 = {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030};
108 if (RF_Path_Type
== 2 && (DataRate
&0xF) <= 0x7)
110 // Set TX SYNC power G2G3 loop filter
111 PHY_SetRFReg(Adapter
, (RF_RADIO_PATH_E
)RF_PATH_A
,
112 RF_TXPA_G2
, bRFRegOffsetMask
, 0x0f000);
113 PHY_SetRFReg(Adapter
, (RF_RADIO_PATH_E
)RF_PATH_A
,
114 RF_TXPA_G3
, bRFRegOffsetMask
, 0xeacf1);
116 // Change TX AGC gain table
117 for (i
= 0; i
< 6; i
++)
118 PHY_SetRFReg(Adapter
, (RF_RADIO_PATH_E
)RF_PATH_A
,
119 RF_TX_AGC
, bRFRegOffsetMask
, tx_gain_tbl1
[i
]);
121 // Set PA to high value
122 PHY_SetRFReg(Adapter
, (RF_RADIO_PATH_E
)RF_PATH_A
,
123 RF_TXPA_G2
, bRFRegOffsetMask
, 0x01e39);
125 else if (RF_Path_Type
== 1 && (DataRate
&0xF) >= 0x8)
127 // Set TX SYNC power G2G3 loop filter
128 PHY_SetRFReg(Adapter
, (RF_RADIO_PATH_E
)RF_PATH_A
,
129 RF_TXPA_G2
, bRFRegOffsetMask
, 0x04440);
130 PHY_SetRFReg(Adapter
, (RF_RADIO_PATH_E
)RF_PATH_A
,
131 RF_TXPA_G3
, bRFRegOffsetMask
, 0xea4f1);
133 // Change TX AGC gain table
134 for (i
= 0; i
< 6; i
++)
135 PHY_SetRFReg(Adapter
, (RF_RADIO_PATH_E
)RF_PATH_A
,
136 RF_TX_AGC
, bRFRegOffsetMask
, tx_gain_tbl2
[i
]);
139 PHY_SetRFReg(Adapter
, (RF_RADIO_PATH_E
)RF_PATH_A
,
140 RF_TXPA_G2
, bRFRegOffsetMask
, 0x01e19);
144 } /* RF_ChangeTxPath */
147 /*-----------------------------------------------------------------------------
148 * Function: PHY_RF6052SetBandwidth()
150 * Overview: This function is called by SetBWModeCallback8190Pci() only
152 * Input: PADAPTER Adapter
153 * WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
159 * Note: For RF type 0222D
160 *---------------------------------------------------------------------------*/
162 rtl8192c_PHY_RF6052SetBandwidth(
164 IN HT_CHANNEL_WIDTH Bandwidth
) //20M or 40M
166 HAL_DATA_TYPE
*pHalData
= GET_HAL_DATA(Adapter
);
170 case HT_CHANNEL_WIDTH_20
:
171 pHalData
->RfRegChnlVal
[0] = ((pHalData
->RfRegChnlVal
[0] & 0xfffff3ff) | 0x0400);
172 PHY_SetRFReg(Adapter
, RF_PATH_A
, RF_CHNLBW
, bRFRegOffsetMask
, pHalData
->RfRegChnlVal
[0]);
175 case HT_CHANNEL_WIDTH_40
:
176 pHalData
->RfRegChnlVal
[0] = ((pHalData
->RfRegChnlVal
[0] & 0xfffff3ff));
177 PHY_SetRFReg(Adapter
, RF_PATH_A
, RF_CHNLBW
, bRFRegOffsetMask
, pHalData
->RfRegChnlVal
[0]);
181 //RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ));
188 /*-----------------------------------------------------------------------------
189 * Function: PHY_RF6052SetCckTxPower
201 * 11/05/2008 MHC Simulate 8192series..
203 *---------------------------------------------------------------------------*/
206 rtl8192c_PHY_RF6052SetCckTxPower(
210 HAL_DATA_TYPE
*pHalData
= GET_HAL_DATA(Adapter
);
211 struct mlme_priv
*pmlmepriv
= &Adapter
->mlmepriv
;
212 struct dm_priv
*pdmpriv
= &pHalData
->dmpriv
;
213 struct mlme_ext_priv
*pmlmeext
= &Adapter
->mlmeextpriv
;
214 //PMGNT_INFO pMgntInfo=&Adapter->MgntInfo;
215 u32 TxAGC
[2]={0, 0}, tmpval
=0;
216 BOOLEAN TurboScanOff
= _FALSE
;
220 // 2010/10/18 MH Accorsing to SD3 eechou's suggestion, we need to disable turbo scan for RU.
221 // Otherwise, external PA will be broken if power index > 0x20.
222 #ifdef CONFIG_USB_HCI
223 if (pHalData
->EEPROMRegulatory
!= 0 || pHalData
->ExternalPA
)
225 if (pHalData
->EEPROMRegulatory
!= 0)
228 //DbgPrint("TurboScanOff=1 EEPROMRegulatory=%d ExternalPA=%d\n", pHalData->EEPROMRegulatory, pHalData->ExternalPA);
229 TurboScanOff
= _TRUE
;
232 if(pmlmeext
->sitesurvey_res
.state
== SCAN_PROCESS
)
234 TxAGC
[RF_PATH_A
] = 0x3f3f3f3f;
235 TxAGC
[RF_PATH_B
] = 0x3f3f3f3f;
237 TurboScanOff
= _TRUE
;//disable turbo scan
241 for(idx1
=RF_PATH_A
; idx1
<=RF_PATH_B
; idx1
++)
244 pPowerlevel
[idx1
] | (pPowerlevel
[idx1
]<<8) |
245 (pPowerlevel
[idx1
]<<16) | (pPowerlevel
[idx1
]<<24);
246 #ifdef CONFIG_USB_HCI
247 // 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20.
248 if (TxAGC
[idx1
] > 0x20 && pHalData
->ExternalPA
)
256 // 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.
257 // Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.
258 // In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.
259 if(pdmpriv
->DynamicTxHighPowerLvl
== TxHighPwrLevel_Level1
)
261 TxAGC
[RF_PATH_A
] = 0x10101010;
262 TxAGC
[RF_PATH_B
] = 0x10101010;
264 else if(pdmpriv
->DynamicTxHighPowerLvl
== TxHighPwrLevel_Level2
)
266 TxAGC
[RF_PATH_A
] = 0x00000000;
267 TxAGC
[RF_PATH_B
] = 0x00000000;
271 for(idx1
=RF_PATH_A
; idx1
<=RF_PATH_B
; idx1
++)
274 pPowerlevel
[idx1
] | (pPowerlevel
[idx1
]<<8) |
275 (pPowerlevel
[idx1
]<<16) | (pPowerlevel
[idx1
]<<24);
278 if(pHalData
->EEPROMRegulatory
==0)
280 tmpval
= (pHalData
->MCSTxPowerLevelOriginalOffset
[0][6]) +
281 (pHalData
->MCSTxPowerLevelOriginalOffset
[0][7]<<8);
282 TxAGC
[RF_PATH_A
] += tmpval
;
284 tmpval
= (pHalData
->MCSTxPowerLevelOriginalOffset
[0][14]) +
285 (pHalData
->MCSTxPowerLevelOriginalOffset
[0][15]<<24);
286 TxAGC
[RF_PATH_B
] += tmpval
;
291 for(idx1
=RF_PATH_A
; idx1
<=RF_PATH_B
; idx1
++)
293 ptr
= (u8
*)(&(TxAGC
[idx1
]));
294 for(idx2
=0; idx2
<4; idx2
++)
296 if(*ptr
> RF6052_MAX_TX_PWR
)
297 *ptr
= RF6052_MAX_TX_PWR
;
303 tmpval
= TxAGC
[RF_PATH_A
]&0xff;
304 PHY_SetBBReg(Adapter
, rTxAGC_A_CCK1_Mcs32
, bMaskByte1
, tmpval
);
305 //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_A_CCK1_Mcs32));
306 tmpval
= TxAGC
[RF_PATH_A
]>>8;
307 PHY_SetBBReg(Adapter
, rTxAGC_B_CCK11_A_CCK2_11
, 0xffffff00, tmpval
);
308 //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11));
311 tmpval
= TxAGC
[RF_PATH_B
]>>24;
312 PHY_SetBBReg(Adapter
, rTxAGC_B_CCK11_A_CCK2_11
, bMaskByte0
, tmpval
);
313 //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11));
314 tmpval
= TxAGC
[RF_PATH_B
]&0x00ffffff;
315 PHY_SetBBReg(Adapter
, rTxAGC_B_CCK1_55_Mcs32
, 0xffffff00, tmpval
);
316 //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n",
317 // tmpval, rTxAGC_B_CCK1_55_Mcs32));
319 } /* PHY_RF6052SetCckTxPower */
322 // powerbase0 for OFDM rates
323 // powerbase1 for HT MCS rates
325 static void getPowerBase(
329 IN OUT u32
* OfdmBase
,
333 HAL_DATA_TYPE
*pHalData
= GET_HAL_DATA(Adapter
);
334 u32 powerBase0
, powerBase1
;
341 powerlevel
[i
] = pPowerLevel
[i
];
342 Legacy_pwrdiff
= pHalData
->TxPwrLegacyHtDiff
[i
][Channel
-1];
343 powerBase0
= powerlevel
[i
] + Legacy_pwrdiff
;
345 powerBase0
= (powerBase0
<<24) | (powerBase0
<<16) |(powerBase0
<<8) |powerBase0
;
346 *(OfdmBase
+i
) = powerBase0
;
347 //RTPRINT(FPHY, PHY_TXPWR, (" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i)));
352 //Check HT20 to HT40 diff
353 if(pHalData
->CurrentChannelBW
== HT_CHANNEL_WIDTH_20
)
355 HT20_pwrdiff
= pHalData
->TxPwrHt20Diff
[i
][Channel
-1];
356 powerlevel
[i
] += HT20_pwrdiff
;
358 powerBase1
= powerlevel
[i
];
359 powerBase1
= (powerBase1
<<24) | (powerBase1
<<16) |(powerBase1
<<8) |powerBase1
;
360 *(MCSBase
+i
) = powerBase1
;
361 //RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i)));
365 static void getTxPowerWriteValByRegulatory(
371 OUT u32
* pOutWriteVal
374 HAL_DATA_TYPE
*pHalData
= GET_HAL_DATA(Adapter
);
375 struct dm_priv
*pdmpriv
= &pHalData
->dmpriv
;
376 u8 i
, chnlGroup
, pwr_diff_limit
[4];
377 u32 writeVal
, customer_limit
, rf
;
380 // Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
382 for(rf
=0; rf
<2; rf
++)
384 switch(pHalData
->EEPROMRegulatory
)
386 case 0: // Realtek better performance
387 // increase power diff defined by Realtek for large power
389 //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
390 // chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
391 writeVal
= pHalData
->MCSTxPowerLevelOriginalOffset
[chnlGroup
][index
+(rf
?8:0)] +
392 ((index
<2)?powerBase0
[rf
]:powerBase1
[rf
]);
393 //RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
395 case 1: // Realtek regulatory
396 // increase power diff defined by Realtek for regulatory
398 if(pHalData
->pwrGroupCnt
== 1)
400 if(pHalData
->pwrGroupCnt
>= 3)
404 else if(Channel
>= 4 && Channel
<= 9)
409 if(pHalData
->CurrentChannelBW
== HT_CHANNEL_WIDTH_20
)
414 //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
415 //chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
416 writeVal
= pHalData
->MCSTxPowerLevelOriginalOffset
[chnlGroup
][index
+(rf
?8:0)] +
417 ((index
<2)?powerBase0
[rf
]:powerBase1
[rf
]);
418 //RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
421 case 2: // Better regulatory
422 // don't increase any power diff
423 writeVal
= ((index
<2)?powerBase0
[rf
]:powerBase1
[rf
]);
424 //RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
426 case 3: // Customer defined power diff.
427 // increase power diff defined by customer.
429 //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
430 // chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
432 if (pHalData
->CurrentChannelBW
== HT_CHANNEL_WIDTH_40
)
434 //RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 40MHz rf(%c) = 0x%x\n",
435 // ((rf==0)?'A':'B'), pHalData->PwrGroupHT40[rf][Channel-1]));
439 //RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 20MHz rf(%c) = 0x%x\n",
440 // ((rf==0)?'A':'B'), pHalData->PwrGroupHT20[rf][Channel-1]));
444 pwr_diff_limit
[i
] = (u8
)((pHalData
->MCSTxPowerLevelOriginalOffset
[chnlGroup
][index
+(rf
?8:0)]&(0x7f<<(i
*8)))>>(i
*8));
445 if (pHalData
->CurrentChannelBW
== HT_CHANNEL_WIDTH_40
)
447 if(pwr_diff_limit
[i
] > pHalData
->PwrGroupHT40
[rf
][Channel
-1])
448 pwr_diff_limit
[i
] = pHalData
->PwrGroupHT40
[rf
][Channel
-1];
452 if(pwr_diff_limit
[i
] > pHalData
->PwrGroupHT20
[rf
][Channel
-1])
453 pwr_diff_limit
[i
] = pHalData
->PwrGroupHT20
[rf
][Channel
-1];
456 customer_limit
= (pwr_diff_limit
[3]<<24) | (pwr_diff_limit
[2]<<16) |
457 (pwr_diff_limit
[1]<<8) | (pwr_diff_limit
[0]);
458 //RTPRINT(FPHY, PHY_TXPWR, ("Customer's limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_limit));
460 writeVal
= customer_limit
+ ((index
<2)?powerBase0
[rf
]:powerBase1
[rf
]);
461 //RTPRINT(FPHY, PHY_TXPWR, ("Customer, writeVal rf(%c)= 0x%x\n", ((rf==0)?'A':'B'), writeVal));
465 writeVal
= pHalData
->MCSTxPowerLevelOriginalOffset
[chnlGroup
][index
+(rf
?8:0)] +
466 ((index
<2)?powerBase0
[rf
]:powerBase1
[rf
]);
467 //RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
471 // 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.
472 // Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.
473 // In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.
475 if(pdmpriv
->DynamicTxHighPowerLvl
== TxHighPwrLevel_Level1
)
476 writeVal
= 0x14141414;
477 else if(pdmpriv
->DynamicTxHighPowerLvl
== TxHighPwrLevel_Level2
)
478 writeVal
= 0x00000000;
481 // 20100628 Joseph: High power mode for BT-Coexist mechanism.
482 // This mechanism is only applied when Driver-Highpower-Mechanism is OFF.
483 if(pdmpriv
->DynamicTxHighPowerLvl
== TxHighPwrLevel_BT1
)
485 //RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n"));
486 writeVal
= writeVal
- 0x06060606;
488 else if(pdmpriv
->DynamicTxHighPowerLvl
== TxHighPwrLevel_BT2
)
490 //RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n"));
493 *(pOutWriteVal
+rf
) = writeVal
;
497 static void writeOFDMPowerReg(
503 HAL_DATA_TYPE
*pHalData
= GET_HAL_DATA(Adapter
);
504 u16 RegOffset_A
[6] = { rTxAGC_A_Rate18_06
, rTxAGC_A_Rate54_24
,
505 rTxAGC_A_Mcs03_Mcs00
, rTxAGC_A_Mcs07_Mcs04
,
506 rTxAGC_A_Mcs11_Mcs08
, rTxAGC_A_Mcs15_Mcs12
};
507 u16 RegOffset_B
[6] = { rTxAGC_B_Rate18_06
, rTxAGC_B_Rate54_24
,
508 rTxAGC_B_Mcs03_Mcs00
, rTxAGC_B_Mcs07_Mcs04
,
509 rTxAGC_B_Mcs11_Mcs08
, rTxAGC_B_Mcs15_Mcs12
};
510 u8 i
, rf
, pwr_val
[4];
514 for(rf
=0; rf
<2; rf
++)
516 writeVal
= pValue
[rf
];
519 pwr_val
[i
] = (u8
)((writeVal
& (0x7f<<(i
*8)))>>(i
*8));
520 if (pwr_val
[i
] > RF6052_MAX_TX_PWR
)
521 pwr_val
[i
] = RF6052_MAX_TX_PWR
;
523 writeVal
= (pwr_val
[3]<<24) | (pwr_val
[2]<<16) |(pwr_val
[1]<<8) |pwr_val
[0];
526 RegOffset
= RegOffset_A
[index
];
528 RegOffset
= RegOffset_B
[index
];
530 PHY_SetBBReg(Adapter
, RegOffset
, bMaskDWord
, writeVal
);
531 //RTPRINT(FPHY, PHY_TXPWR, ("Set 0x%x = %08x\n", RegOffset, writeVal));
533 // 201005115 Joseph: Set Tx Power diff for Tx power training mechanism.
534 if(((pHalData
->rf_type
== RF_2T2R
) &&
535 (RegOffset
== rTxAGC_A_Mcs15_Mcs12
|| RegOffset
== rTxAGC_B_Mcs15_Mcs12
))||
536 ((pHalData
->rf_type
!= RF_2T2R
) &&
537 (RegOffset
== rTxAGC_A_Mcs07_Mcs04
|| RegOffset
== rTxAGC_B_Mcs07_Mcs04
)) )
539 writeVal
= pwr_val
[3];
540 if(RegOffset
== rTxAGC_A_Mcs15_Mcs12
|| RegOffset
== rTxAGC_A_Mcs07_Mcs04
)
542 if(RegOffset
== rTxAGC_B_Mcs15_Mcs12
|| RegOffset
== rTxAGC_B_Mcs07_Mcs04
)
547 writeVal
= (writeVal
>8)?(writeVal
-8):0;
549 writeVal
= (writeVal
>6)?(writeVal
-6):0;
550 rtw_write8(Adapter
, (u32
)(RegOffset
+i
), (u8
)writeVal
);
555 /*-----------------------------------------------------------------------------
556 * Function: PHY_RF6052SetOFDMTxPower
558 * Overview: For legacy and HY OFDM, we must read EEPROM TX power index for
559 * different channel and read original value in TX power register area from
560 * 0xe00. We increase offset and original value to be correct tx pwr.
570 * 11/05/2008 MHC Simulate 8192 series method.
571 * 01/06/2009 MHC 1. Prevent Path B tx power overflow or underflow dure to
572 * A/B pwr difference or legacy/HT pwr diff.
573 * 2. We concern with path B legacy/HT OFDM difference.
574 * 01/22/2009 MHC Support new EPRO format from SD3.
576 *---------------------------------------------------------------------------*/
578 rtl8192c_PHY_RF6052SetOFDMTxPower(
583 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
584 u32 writeVal
[2], powerBase0
[2], powerBase1
[2];
587 getPowerBase(Adapter
, pPowerLevel
, Channel
, &powerBase0
[0], &powerBase1
[0]);
589 for(index
=0; index
<6; index
++)
591 getTxPowerWriteValByRegulatory(Adapter
, Channel
, index
,
592 &powerBase0
[0], &powerBase1
[0], &writeVal
[0]);
594 writeOFDMPowerReg(Adapter
, index
, &writeVal
[0]);
601 phy_RF6052_Config_HardCode(
606 // Set Default Bandwidth to 20M
607 //Adapter->HalFunc .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20);
609 // TODO: Set Default Channel to channel one for RTL8225
614 phy_RF6052_Config_ParaFile(
620 BB_REGISTER_DEFINITION_T
*pPhyReg
;
622 int rtStatus
= _SUCCESS
;
623 HAL_DATA_TYPE
*pHalData
= GET_HAL_DATA(Adapter
);
624 static char sz88CRadioAFile
[] = RTL8188C_PHY_RADIO_A
;
625 static char sz88CRadioBFile
[] = RTL8188C_PHY_RADIO_B
;
626 #ifdef CONFIG_USB_HCI
627 static char sz88CRadioAFile_mCard
[] = RTL8188C_PHY_RADIO_A_mCard
;
628 static char sz88CRadioBFile_mCard
[] = RTL8188C_PHY_RADIO_B_mCard
;
629 static char sz88CRadioAFile_HP
[] = RTL8188C_PHY_RADIO_A_HP
;
631 static char sz92CRadioAFile
[] = RTL8192C_PHY_RADIO_A
;
632 static char sz92CRadioBFile
[] = RTL8192C_PHY_RADIO_B
;
633 static char sz8723RadioAFile
[] = RTL8723_PHY_RADIO_A
;
634 static char sz8723RadioBFile
[] = RTL8723_PHY_RADIO_B
;
635 char *pszRadioAFile
, *pszRadioBFile
;
638 if(IS_HARDWARE_TYPE_8192C(Adapter
))
640 if(IS_92C_SERIAL( pHalData
->VersionID
))// 88c's IPA is different from 92c's
642 pszRadioAFile
= sz92CRadioAFile
;
643 pszRadioBFile
= sz92CRadioBFile
;
647 pszRadioAFile
= sz88CRadioAFile
;
648 pszRadioBFile
= sz88CRadioBFile
;
649 #ifdef CONFIG_USB_HCI
650 if( BOARD_MINICARD
== pHalData
->BoardType
)
652 pszRadioAFile
= sz88CRadioAFile_mCard
;
653 pszRadioBFile
= sz88CRadioBFile_mCard
;
655 else if( BOARD_USB_High_PA
== pHalData
->BoardType
)
657 pszRadioAFile
= sz88CRadioAFile_HP
;
662 else if(IS_HARDWARE_TYPE_8723A(Adapter
))
664 pszRadioAFile
= sz8723RadioAFile
;
665 pszRadioBFile
= sz8723RadioBFile
;
668 //3//-----------------------------------------------------------------
669 //3// <2> Initialize RF
670 //3//-----------------------------------------------------------------
671 //for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
672 for(eRFPath
= 0; eRFPath
<pHalData
->NumTotalRFPath
; eRFPath
++)
675 pPhyReg
= &pHalData
->PHYRegDef
[eRFPath
];
677 /*----Store original RFENV control type----*/
682 u4RegValue
= PHY_QueryBBReg(Adapter
, pPhyReg
->rfintfs
, bRFSI_RFENV
);
686 u4RegValue
= PHY_QueryBBReg(Adapter
, pPhyReg
->rfintfs
, bRFSI_RFENV
<<16);
690 /*----Set RF_ENV enable----*/
691 PHY_SetBBReg(Adapter
, pPhyReg
->rfintfe
, bRFSI_RFENV
<<16, 0x1);
692 rtw_udelay_os(1);//PlatformStallExecution(1);
694 /*----Set RF_ENV output high----*/
695 PHY_SetBBReg(Adapter
, pPhyReg
->rfintfo
, bRFSI_RFENV
, 0x1);
696 rtw_udelay_os(1);//PlatformStallExecution(1);
698 /* Set bit number of Address and Data for RF register */
699 PHY_SetBBReg(Adapter
, pPhyReg
->rfHSSIPara2
, b3WireAddressLength
, 0x0); // Set 1 to 4 bits for 8255
700 rtw_udelay_os(1);//PlatformStallExecution(1);
702 PHY_SetBBReg(Adapter
, pPhyReg
->rfHSSIPara2
, b3WireDataLength
, 0x0); // Set 0 to 12 bits for 8255
703 rtw_udelay_os(1);//PlatformStallExecution(1);
705 /*----Initialize RF fom connfiguration file----*/
709 #ifdef CONFIG_EMBEDDED_FWIMG
710 rtStatus
= rtl8192c_PHY_ConfigRFWithHeaderFile(Adapter
,(RF_RADIO_PATH_E
)eRFPath
);
712 rtStatus
= rtl8192c_PHY_ConfigRFWithParaFile(Adapter
, pszRadioAFile
, (RF_RADIO_PATH_E
)eRFPath
);
716 #ifdef CONFIG_EMBEDDED_FWIMG
717 rtStatus
= rtl8192c_PHY_ConfigRFWithHeaderFile(Adapter
,(RF_RADIO_PATH_E
)eRFPath
);
719 rtStatus
= rtl8192c_PHY_ConfigRFWithParaFile(Adapter
, pszRadioBFile
, (RF_RADIO_PATH_E
)eRFPath
);
728 /*----Restore RFENV control type----*/;
733 PHY_SetBBReg(Adapter
, pPhyReg
->rfintfs
, bRFSI_RFENV
, u4RegValue
);
737 PHY_SetBBReg(Adapter
, pPhyReg
->rfintfs
, bRFSI_RFENV
<<16, u4RegValue
);
741 if(rtStatus
!= _SUCCESS
){
742 //RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath));
743 goto phy_RF6052_Config_ParaFile_Fail
;
748 //RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n"));
751 phy_RF6052_Config_ParaFile_Fail
:
757 PHY_RF6052_Config8192C(
760 HAL_DATA_TYPE
*pHalData
= GET_HAL_DATA(Adapter
);
761 int rtStatus
= _SUCCESS
;
764 // Initialize general global value
766 // TODO: Extend RF_PATH_C and RF_PATH_D in the future
767 if(pHalData
->rf_type
== RF_1T1R
)
768 pHalData
->NumTotalRFPath
= 1;
770 pHalData
->NumTotalRFPath
= 2;
775 rtStatus
= phy_RF6052_Config_ParaFile(Adapter
);
777 switch( Adapter
->MgntInfo
.bRegHwParaFile
)
780 phy_RF6052_Config_HardCode(Adapter
);
784 rtStatus
= phy_RF6052_Config_ParaFile(Adapter
);
789 phy_RF6052_Config_HardCode(Adapter
);
790 phy_RF6052_Config_ParaFile(Adapter
);
794 phy_RF6052_Config_HardCode(Adapter
);
804 // ==> RF shadow Operation API Code Section!!!
806 /*-----------------------------------------------------------------------------
807 * Function: PHY_RFShadowRead
809 * PHY_RFShadowCompare
810 * PHY_RFShadowRecorver
811 * PHY_RFShadowCompareAll
812 * PHY_RFShadowRecorverAll
813 * PHY_RFShadowCompareFlagSet
814 * PHY_RFShadowRecorverFlagSet
816 * Overview: When we set RF register, we must write shadow at first.
817 * When we are running, we must compare shadow abd locate error addr.
818 * Decide to recorver or not.
828 * 11/20/2008 MHC Create Version 0.
830 *---------------------------------------------------------------------------*/
834 IN RF_RADIO_PATH_E eRFPath
,
837 return RF_Shadow
[eRFPath
][Offset
].Value
;
839 } /* PHY_RFShadowRead */
845 IN RF_RADIO_PATH_E eRFPath
,
849 RF_Shadow
[eRFPath
][Offset
].Value
= (Data
& bRFRegOffsetMask
);
850 RF_Shadow
[eRFPath
][Offset
].Driver_Write
= _TRUE
;
852 } /* PHY_RFShadowWrite */
858 IN RF_RADIO_PATH_E eRFPath
,
862 // Check if we need to check the register
863 if (RF_Shadow
[eRFPath
][Offset
].Compare
== _TRUE
)
865 reg
= PHY_QueryRFReg(Adapter
, eRFPath
, Offset
, bRFRegOffsetMask
);
866 // Compare shadow and real rf register for 20bits!!
867 if (RF_Shadow
[eRFPath
][Offset
].Value
!= reg
)
869 // Locate error position.
870 RF_Shadow
[eRFPath
][Offset
].ErrorOrNot
= _TRUE
;
871 //RT_TRACE(COMP_INIT, DBG_LOUD,
872 //("PHY_RFShadowCompare RF-%d Addr%02lx Err = %05lx\n",
873 //eRFPath, Offset, reg));
875 return RF_Shadow
[eRFPath
][Offset
].ErrorOrNot
;
878 } /* PHY_RFShadowCompare */
882 PHY_RFShadowRecorver(
884 IN RF_RADIO_PATH_E eRFPath
,
887 // Check if the address is error
888 if (RF_Shadow
[eRFPath
][Offset
].ErrorOrNot
== _TRUE
)
890 // Check if we need to recorver the register.
891 if (RF_Shadow
[eRFPath
][Offset
].Recorver
== _TRUE
)
893 PHY_SetRFReg(Adapter
, eRFPath
, Offset
, bRFRegOffsetMask
,
894 RF_Shadow
[eRFPath
][Offset
].Value
);
895 //RT_TRACE(COMP_INIT, DBG_LOUD,
896 //("PHY_RFShadowRecorver RF-%d Addr%02lx=%05lx",
897 //eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value));
901 } /* PHY_RFShadowRecorver */
905 PHY_RFShadowCompareAll(
911 for (eRFPath
= 0; eRFPath
< RF6052_MAX_PATH
; eRFPath
++)
913 for (Offset
= 0; Offset
<= RF6052_MAX_REG
; Offset
++)
915 PHY_RFShadowCompare(Adapter
, (RF_RADIO_PATH_E
)eRFPath
, Offset
);
919 } /* PHY_RFShadowCompareAll */
923 PHY_RFShadowRecorverAll(
929 for (eRFPath
= 0; eRFPath
< RF6052_MAX_PATH
; eRFPath
++)
931 for (Offset
= 0; Offset
<= RF6052_MAX_REG
; Offset
++)
933 PHY_RFShadowRecorver(Adapter
, (RF_RADIO_PATH_E
)eRFPath
, Offset
);
937 } /* PHY_RFShadowRecorverAll */
941 PHY_RFShadowCompareFlagSet(
943 IN RF_RADIO_PATH_E eRFPath
,
947 // Set True or False!!!
948 RF_Shadow
[eRFPath
][Offset
].Compare
= Type
;
950 } /* PHY_RFShadowCompareFlagSet */
954 PHY_RFShadowRecorverFlagSet(
956 IN RF_RADIO_PATH_E eRFPath
,
960 // Set True or False!!!
961 RF_Shadow
[eRFPath
][Offset
].Recorver
= Type
;
963 } /* PHY_RFShadowRecorverFlagSet */
967 PHY_RFShadowCompareFlagSetAll(
973 for (eRFPath
= 0; eRFPath
< RF6052_MAX_PATH
; eRFPath
++)
975 for (Offset
= 0; Offset
<= RF6052_MAX_REG
; Offset
++)
977 // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!!
978 if (Offset
!= 0x26 && Offset
!= 0x27)
979 PHY_RFShadowCompareFlagSet(Adapter
, (RF_RADIO_PATH_E
)eRFPath
, Offset
, _FALSE
);
981 PHY_RFShadowCompareFlagSet(Adapter
, (RF_RADIO_PATH_E
)eRFPath
, Offset
, _TRUE
);
985 } /* PHY_RFShadowCompareFlagSetAll */
989 PHY_RFShadowRecorverFlagSetAll(
995 for (eRFPath
= 0; eRFPath
< RF6052_MAX_PATH
; eRFPath
++)
997 for (Offset
= 0; Offset
<= RF6052_MAX_REG
; Offset
++)
999 // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!!
1000 if (Offset
!= 0x26 && Offset
!= 0x27)
1001 PHY_RFShadowRecorverFlagSet(Adapter
, (RF_RADIO_PATH_E
)eRFPath
, Offset
, _FALSE
);
1003 PHY_RFShadowRecorverFlagSet(Adapter
, (RF_RADIO_PATH_E
)eRFPath
, Offset
, _TRUE
);
1007 } /* PHY_RFShadowCompareFlagSetAll */
1010 PHY_RFShadowRefresh(
1011 IN PADAPTER Adapter
)
1016 for (eRFPath
= 0; eRFPath
< RF6052_MAX_PATH
; eRFPath
++)
1018 for (Offset
= 0; Offset
< RF6052_MAX_REG
; Offset
++)
1020 RF_Shadow
[eRFPath
][Offset
].Value
= 0;
1021 RF_Shadow
[eRFPath
][Offset
].Compare
= _FALSE
;
1022 RF_Shadow
[eRFPath
][Offset
].Recorver
= _FALSE
;
1023 RF_Shadow
[eRFPath
][Offset
].ErrorOrNot
= _FALSE
;
1024 RF_Shadow
[eRFPath
][Offset
].Driver_Write
= _FALSE
;
1028 } /* PHY_RFShadowRead */
1030 /* End of HalRf6052.c */