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net: Add non-mainline source for rtl8192cu wlan
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / realtek / rtl8192cu / include / rtl8192c_hal.h
1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20 #ifndef __RTL8192C_HAL_H__
21 #define __RTL8192C_HAL_H__
22
23 #include "hal_com.h"
24 #include "rtl8192c_spec.h"
25 #include "Hal8192CPhyReg.h"
26 #include "Hal8192CPhyCfg.h"
27 #include "rtl8192c_rf.h"
28 #include "rtl8192c_dm.h"
29 #include "rtl8192c_recv.h"
30 #include "rtl8192c_xmit.h"
31 #include "rtl8192c_cmd.h"
32 #ifdef DBG_CONFIG_ERROR_DETECT
33 #include "rtl8192c_sreset.h"
34 #endif
35
36 #ifdef CONFIG_PCI_HCI
37
38 #include "Hal8192CEHWImg.h"
39
40 #define RTL819X_DEFAULT_RF_TYPE RF_2T2R
41 //#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
42 #define RTL819X_TOTAL_RF_PATH 2
43
44 //2TODO: The following need to check!!
45 #define RTL8192C_FW_TSMC_IMG "rtl8192CE\\rtl8192cfwT.bin"
46 #define RTL8192C_FW_UMC_IMG "rtl8192CE\\rtl8192cfwU.bin"
47 #define RTL8192C_FW_UMC_B_IMG "rtl8192CE\\rtl8192cfwU_B.bin"
48
49 #define RTL8188C_PHY_REG "rtl8192CE\\PHY_REG_1T.txt"
50 #define RTL8188C_PHY_RADIO_A "rtl8192CE\\radio_a_1T.txt"
51 #define RTL8188C_PHY_RADIO_B "rtl8192CE\\radio_b_1T.txt"
52 #define RTL8188C_AGC_TAB "rtl8192CE\\AGC_TAB_1T.txt"
53 #define RTL8188C_PHY_MACREG "rtl8192CE\\MACREG_1T.txt"
54
55 #define RTL8192C_PHY_REG "rtl8192CE\\PHY_REG_2T.txt"
56 #define RTL8192C_PHY_RADIO_A "rtl8192CE\\radio_a_2T.txt"
57 #define RTL8192C_PHY_RADIO_B "rtl8192CE\\radio_b_2T.txt"
58 #define RTL8192C_AGC_TAB "rtl8192CE\\AGC_TAB_2T.txt"
59 #define RTL8192C_PHY_MACREG "rtl8192CE\\MACREG_2T.txt"
60
61 #define RTL819X_PHY_MACPHY_REG "rtl8192CE\\MACPHY_reg.txt"
62 #define RTL819X_PHY_MACPHY_REG_PG "rtl8192CE\\MACPHY_reg_PG.txt"
63 #define RTL819X_PHY_MACREG "rtl8192CE\\MAC_REG.txt"
64 #define RTL819X_PHY_REG "rtl8192CE\\PHY_REG.txt"
65 #define RTL819X_PHY_REG_1T2R "rtl8192CE\\PHY_REG_1T2R.txt"
66 #define RTL819X_PHY_REG_to1T1R "rtl8192CE\\phy_to1T1R_a.txt"
67 #define RTL819X_PHY_REG_to1T2R "rtl8192CE\\phy_to1T2R.txt"
68 #define RTL819X_PHY_REG_to2T2R "rtl8192CE\\phy_to2T2R.txt"
69 #define RTL819X_PHY_REG_PG "rtl8192CE\\PHY_REG_PG.txt"
70 #define RTL819X_AGC_TAB "rtl8192CE\\AGC_TAB.txt"
71 #define RTL819X_PHY_RADIO_A "rtl8192CE\\radio_a.txt"
72 #define RTL819X_PHY_RADIO_A_1T "rtl8192CE\\radio_a_1t.txt"
73 #define RTL819X_PHY_RADIO_A_2T "rtl8192CE\\radio_a_2t.txt"
74 #define RTL819X_PHY_RADIO_B "rtl8192CE\\radio_b.txt"
75 #define RTL819X_PHY_RADIO_B_GM "rtl8192CE\\radio_b_gm.txt"
76 #define RTL819X_PHY_RADIO_C "rtl8192CE\\radio_c.txt"
77 #define RTL819X_PHY_RADIO_D "rtl8192CE\\radio_d.txt"
78 #define RTL819X_EEPROM_MAP "rtl8192CE\\8192ce.map"
79 #define RTL819X_EFUSE_MAP "rtl8192CE\\8192ce.map"
80
81 //---------------------------------------------------------------------
82 // RTL8723E From file
83 //---------------------------------------------------------------------
84 #define RTL8723_FW_UMC_IMG "rtl8723E\\rtl8723fw.bin"
85 #define RTL8723_PHY_REG "rtl8723E\\PHY_REG_1T.txt"
86 #define RTL8723_PHY_RADIO_A "rtl8723E\\radio_a_1T.txt"
87 #define RTL8723_PHY_RADIO_B "rtl8723E\\radio_b_1T.txt"
88 #define RTL8723_AGC_TAB "rtl8723E\\AGC_TAB_1T.txt"
89 #define RTL8723_PHY_MACREG "rtl8723E\\MAC_REG.txt"
90 #define RTL8723_PHY_MACREG "rtl8723E\\MAC_REG.txt"
91 #define RTL8723_PHY_REG_PG "rtl8723E\\PHY_REG_PG.txt"
92 #define RTL8723_PHY_REG_MP "rtl8723E\\PHY_REG_MP.txt"
93
94 // The file name "_2T" is for 92CE, "_1T" is for 88CE. Modified by tynli. 2009.11.24.
95 #define Rtl819XFwTSMCImageArray Rtl8192CEFwTSMCImgArray
96 #define Rtl819XFwUMCACutImageArray Rtl8192CEFwUMCACutImgArray
97 #define Rtl819XFwUMCBCutImageArray Rtl8192CEFwUMCBCutImgArray
98
99 #define Rtl8723FwUMCImageArray Rtl8192CEFwUMC8723ImgArray
100 #define Rtl819XMAC_Array Rtl8192CEMAC_2T_Array
101 #define Rtl819XAGCTAB_2TArray Rtl8192CEAGCTAB_2TArray
102 #define Rtl819XAGCTAB_1TArray Rtl8192CEAGCTAB_1TArray
103 #define Rtl819XPHY_REG_2TArray Rtl8192CEPHY_REG_2TArray
104 #define Rtl819XPHY_REG_1TArray Rtl8192CEPHY_REG_1TArray
105 #define Rtl819XRadioA_2TArray Rtl8192CERadioA_2TArray
106 #define Rtl819XRadioA_1TArray Rtl8192CERadioA_1TArray
107 #define Rtl819XRadioB_2TArray Rtl8192CERadioB_2TArray
108 #define Rtl819XRadioB_1TArray Rtl8192CERadioB_1TArray
109 #define Rtl819XPHY_REG_Array_PG Rtl8192CEPHY_REG_Array_PG
110 #define Rtl819XPHY_REG_Array_MP Rtl8192CEPHY_REG_Array_MP
111
112 #elif defined(CONFIG_USB_HCI)
113
114 #include "Hal8192CUHWImg.h"
115 #ifdef CONFIG_WOWLAN
116 #include "Hal8192CUHWImg_wowlan.h"
117 #endif //CONFIG_WOWLAN
118 //2TODO: We should define 8192S firmware related macro settings here!!
119 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
120 #define RTL819X_TOTAL_RF_PATH 2
121
122 //TODO: The following need to check!!
123 #define RTL8192C_FW_TSMC_IMG "rtl8192CU\\rtl8192cfwT.bin"
124 #define RTL8192C_FW_UMC_IMG "rtl8192CU\\rtl8192cfwU.bin"
125 #define RTL8192C_FW_UMC_B_IMG "rtl8192CU\\rtl8192cfwU_B.bin"
126 #ifdef CONFIG_WOWLAN
127 #define RTL8192C_FW_TSMC_WW_IMG "rtl8192CU\\rtl8192cfwTww.bin"
128 #define RTL8192C_FW_UMC_WW_IMG "rtl8192CU\\rtl8192cfwUww.bin"
129 #define RTL8192C_FW_UMC_B_WW_IMG "rtl8192CU\\rtl8192cfwU_Bww.bin"
130 #endif // CONFIG_WOWLAN
131 //#define RTL819X_FW_BOOT_IMG "rtl8192CU\\boot.img"
132 //#define RTL819X_FW_MAIN_IMG "rtl8192CU\\main.img"
133 //#define RTL819X_FW_DATA_IMG "rtl8192CU\\data.img"
134
135 #define RTL8188C_PHY_REG "rtl8188CU\\PHY_REG.txt"
136 #define RTL8188C_PHY_RADIO_A "rtl8188CU\\radio_a.txt"
137 #define RTL8188C_PHY_RADIO_B "rtl8188CU\\radio_b.txt"
138 #define RTL8188C_PHY_RADIO_A_mCard "rtl8192CU\\radio_a_1T_mCard.txt"
139 #define RTL8188C_PHY_RADIO_B_mCard "rtl8192CU\\radio_b_1T_mCard.txt"
140 #define RTL8188C_PHY_RADIO_A_HP "rtl8192CU\\radio_a_1T_HP.txt"
141 #define RTL8188C_AGC_TAB "rtl8188CU\\AGC_TAB.txt"
142 #define RTL8188C_PHY_MACREG "rtl8188CU\\MACREG.txt"
143
144 #define RTL8192C_PHY_REG "rtl8192CU\\PHY_REG.txt"
145 #define RTL8192C_PHY_RADIO_A "rtl8192CU\\radio_a.txt"
146 #define RTL8192C_PHY_RADIO_B "rtl8192CU\\radio_b.txt"
147 #define RTL8192C_AGC_TAB "rtl8192CU\\AGC_TAB.txt"
148 #define RTL8192C_PHY_MACREG "rtl8192CU\\MACREG.txt"
149
150 #define RTL819X_PHY_REG_PG "rtl8192CU\\PHY_REG_PG.txt"
151
152 //---------------------------------------------------------------------
153 // RTL8723U From file
154 //---------------------------------------------------------------------
155 #define RTL8723_FW_UMC_IMG "rtl8723U\\rtl8723fw.bin"
156 #define RTL8723_PHY_REG "rtl8723U\\PHY_REG_1T.txt"
157 #define RTL8723_PHY_RADIO_A "rtl8723U\\radio_a_1T.txt"
158 #define RTL8723_PHY_RADIO_B "rtl8723U\\radio_b_1T.txt"
159 #define RTL8723_AGC_TAB "rtl8723U\\AGC_TAB_1T.txt"
160 #define RTL8723_PHY_MACREG "rtl8723U\\MAC_REG.txt"
161 #define RTL8723_PHY_MACREG "rtl8723U\\MAC_REG.txt"
162 #define RTL8723_PHY_REG_PG "rtl8723U\\PHY_REG_PG.txt"
163 #define RTL8723_PHY_REG_MP "rtl8723U\\PHY_REG_MP.txt"
164
165 // The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24.
166 #define Rtl819XFwImageArray Rtl8192CUFwTSMCImgArray
167 #define Rtl819XFwTSMCImageArray Rtl8192CUFwTSMCImgArray
168 #define Rtl819XFwUMCACutImageArray Rtl8192CUFwUMCACutImgArray
169 #define Rtl819XFwUMCBCutImageArray Rtl8192CUFwUMCBCutImgArray
170 #ifdef CONFIG_WOWLAN
171 #define Rtl8192C_FwTSMCWWImageArray Rtl8192CUFwTSMCWWImgArray
172 #define Rtl8192C_FwUMCWWImageArray Rtl8192CUFwUMCACutWWImgArray
173 #define Rtl8192C_FwUMCBCutWWImageArray Rtl8192CUFwUMCBCutWWImgArray
174 #endif //CONFIG_WOWLAN
175 #define Rtl819XMAC_Array Rtl8192CUMAC_2T_Array
176 #define Rtl819XAGCTAB_2TArray Rtl8192CUAGCTAB_2TArray
177 #define Rtl819XAGCTAB_1TArray Rtl8192CUAGCTAB_1TArray
178 #define Rtl819XAGCTAB_1T_HPArray Rtl8192CUAGCTAB_1T_HPArray
179 #define Rtl819XPHY_REG_2TArray Rtl8192CUPHY_REG_2TArray
180 #define Rtl819XPHY_REG_1TArray Rtl8192CUPHY_REG_1TArray
181 #define Rtl819XPHY_REG_1T_mCardArray Rtl8192CUPHY_REG_1T_mCardArray
182 #define Rtl819XPHY_REG_2T_mCardArray Rtl8192CUPHY_REG_2T_mCardArray
183 #define Rtl819XPHY_REG_1T_HPArray Rtl8192CUPHY_REG_1T_HPArray
184 #define Rtl819XRadioA_2TArray Rtl8192CURadioA_2TArray
185 #define Rtl819XRadioA_1TArray Rtl8192CURadioA_1TArray
186 #define Rtl819XRadioA_1T_mCardArray Rtl8192CURadioA_1T_mCardArray
187 #define Rtl819XRadioB_2TArray Rtl8192CURadioB_2TArray
188 #define Rtl819XRadioB_1TArray Rtl8192CURadioB_1TArray
189 #define Rtl819XRadioB_1T_mCardArray Rtl8192CURadioB_1T_mCardArray
190 #define Rtl819XRadioA_1T_HPArray Rtl8192CURadioA_1T_HPArray
191 #define Rtl819XPHY_REG_Array_PG Rtl8192CUPHY_REG_Array_PG
192 #define Rtl819XPHY_REG_Array_PG_mCard Rtl8192CUPHY_REG_Array_PG_mCard
193 #define Rtl819XPHY_REG_Array_PG_HP Rtl8192CUPHY_REG_Array_PG_HP
194 #define Rtl819XPHY_REG_Array_MP Rtl8192CUPHY_REG_Array_MP
195 #endif
196
197 #define DRVINFO_SZ 4 // unit is 8bytes
198 #define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
199
200 #define FW_8192C_SIZE 16384+32//16k
201 #define FW_8192C_START_ADDRESS 0x1000
202 //#define FW_8192C_END_ADDRESS 0x3FFF //Filen said this is for test chip
203 #define FW_8192C_END_ADDRESS 0x1FFF
204
205 #define MAX_PAGE_SIZE 4096 // @ page : 4k bytes
206
207 #define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
208 (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\
209 (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300)
210
211 typedef enum _FIRMWARE_SOURCE{
212 FW_SOURCE_IMG_FILE = 0,
213 FW_SOURCE_HEADER_FILE = 1, //from header file
214 }FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;
215
216 typedef struct _RT_FIRMWARE{
217 FIRMWARE_SOURCE eFWSource;
218 u8* szFwBuffer;
219 u32 ulFwLength;
220 #ifdef CONFIG_WOWLAN
221 u8* szWoWLANFwBuffer;
222 u32 ulWoWLANFwLength;
223 #endif //CONFIG_WOWLAN
224 }RT_FIRMWARE, *PRT_FIRMWARE, RT_FIRMWARE_92C, *PRT_FIRMWARE_92C;
225
226 //
227 // This structure must be cared byte-ordering
228 //
229 // Added by tynli. 2009.12.04.
230 typedef struct _RT_8192C_FIRMWARE_HDR {//8-byte alinment required
231
232 //--- LONG WORD 0 ----
233 u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut
234 u8 Category; // AP/NIC and USB/PCI
235 u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions
236 u16 Version; // FW Version
237 u8 Subversion; // FW Subversion, default 0x00
238 u16 Rsvd1;
239
240
241 //--- LONG WORD 1 ----
242 u8 Month; // Release time Month field
243 u8 Date; // Release time Date field
244 u8 Hour; // Release time Hour field
245 u8 Minute; // Release time Minute field
246 u16 RamCodeSize; // The size of RAM code
247 u16 Rsvd2;
248
249 //--- LONG WORD 2 ----
250 u32 SvnIdx; // The SVN entry index
251 u32 Rsvd3;
252
253 //--- LONG WORD 3 ----
254 u32 Rsvd4;
255 u32 Rsvd5;
256
257 }RT_8192C_FIRMWARE_HDR, *PRT_8192C_FIRMWARE_HDR;
258
259 #define DRIVER_EARLY_INT_TIME 0x05
260 #define BCN_DMA_ATIME_INT_TIME 0x02
261
262 #ifdef CONFIG_USB_RX_AGGREGATION
263
264 typedef enum _USB_RX_AGG_MODE{
265 USB_RX_AGG_DISABLE,
266 USB_RX_AGG_DMA,
267 USB_RX_AGG_USB,
268 USB_RX_AGG_MIX
269 }USB_RX_AGG_MODE;
270
271 #define MAX_RX_DMA_BUFFER_SIZE 10240 // 10K for 8192C RX DMA buffer
272
273 #endif
274
275
276 #define TX_SELE_HQ BIT(0) // High Queue
277 #define TX_SELE_LQ BIT(1) // Low Queue
278 #define TX_SELE_NQ BIT(2) // Normal Queue
279
280
281 // Note: We will divide number of page equally for each queue other than public queue!
282
283 #define TX_TOTAL_PAGE_NUMBER 0xF8
284 #define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER + 1)
285
286 // For Normal Chip Setting
287 // (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER
288 #define NORMAL_PAGE_NUM_PUBQ 0xE7
289 #define NORMAL_PAGE_NUM_HPQ 0x0C
290 #define NORMAL_PAGE_NUM_LPQ 0x02
291 #define NORMAL_PAGE_NUM_NPQ 0x02
292
293
294 // For Test Chip Setting
295 // (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER
296 #define TEST_PAGE_NUM_PUBQ 0x7E
297
298
299 // For Test Chip Setting
300 #define WMM_TEST_TX_TOTAL_PAGE_NUMBER 0xF5
301 #define WMM_TEST_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
302
303 #define WMM_TEST_PAGE_NUM_PUBQ 0xA3
304 #define WMM_TEST_PAGE_NUM_HPQ 0x29
305 #define WMM_TEST_PAGE_NUM_LPQ 0x29
306
307
308 //Note: For Normal Chip Setting ,modify later
309 #define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5
310 #define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
311
312 #define WMM_NORMAL_PAGE_NUM_PUBQ 0x65
313 #define WMM_NORMAL_PAGE_NUM_HPQ 0x30
314 #define WMM_NORMAL_PAGE_NUM_LPQ 0x30
315 #define WMM_NORMAL_PAGE_NUM_NPQ 0x30
316
317 //-------------------------------------------------------------------------
318 // Chip specific
319 //-------------------------------------------------------------------------
320 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
321 #define CHIP_BONDING_92C_1T2R 0x1
322 #define CHIP_BONDING_88C_USB_MCARD 0x2
323 #define CHIP_BONDING_88C_USB_HP 0x1
324
325 //
326 // 2011.01.06. Define new structure of chip version for RTL8723 and so on. Added by tynli.
327 //
328 /*
329 | BIT15:12 | BIT11:8 | BIT 7 | BIT6:4 | BIT3 | BIT2:0 |
330 |-------------+-----------+-----------+-------+-----------+-------|
331 | IC version(CUT) | ROM version | Manufacturer | RF type | Chip type | IC Type |
332 | | | TSMC/UMC | | TEST/NORMAL| |
333 */
334 // [15:12] IC version(CUT): A-cut=0, B-cut=1, C-cut=2, D-cut=3
335 // [7] Manufacturer: TSMC=0, UMC=1
336 // [6:4] RF type: 1T1R=0, 1T2R=1, 2T2R=2
337 // [3] Chip type: TEST=0, NORMAL=1
338 // [2:0] IC type: 81xxC=0, 8723=1, 92D=2
339
340 #define CHIP_8723 BIT(0)
341 #define CHIP_92D BIT(1)
342 #define NORMAL_CHIP BIT(3)
343 #define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
344 #define RF_TYPE_1T2R BIT(4)
345 #define RF_TYPE_2T2R BIT(5)
346 #define CHIP_VENDOR_UMC BIT(7)
347 #define B_CUT_VERSION BIT(12)
348 #define C_CUT_VERSION BIT(13)
349 #define D_CUT_VERSION ((BIT(13)|BIT(14)))
350
351
352 // MASK
353 #define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2))
354 #define CHIP_TYPE_MASK BIT(3)
355 #define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6))
356 #define MANUFACTUER_MASK BIT(7)
357 #define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8))
358 #define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12))
359
360 // Get element
361 #define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK)
362 #define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
363 #define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK)
364 #define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK)
365 #define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK)
366 #define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
367
368 #define IS_81XXC(version) ((GET_CVID_IC_TYPE(version) == 0)? _TRUE : _FALSE)
369 #define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723)? _TRUE : _FALSE)
370 #define IS_92D(version) ((GET_CVID_IC_TYPE(version) == CHIP_92D)? _TRUE : _FALSE)
371 #define IS_1T1R(version) ((GET_CVID_RF_TYPE(version))? _FALSE : _TRUE)
372 #define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)? _TRUE : _FALSE)
373 #define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)? _TRUE : _FALSE)
374 #define IS_NORMAL_CHIP(version) ((GET_CVID_CHIP_TYPE(version))? _TRUE: _FALSE)
375 #define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version))? _TRUE: _FALSE)
376
377 #define IS_81XXC_TEST_CHIP(version) ((IS_81XXC(version) && (!IS_NORMAL_CHIP(version)))? _TRUE: _FALSE)
378 #define IS_92D_TEST_CHIP(version) ((IS_92D(version) && (!IS_NORMAL_CHIP(version)))? _TRUE: _FALSE)
379 #define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? _TRUE : _FALSE)
380 #define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? ((GET_CVID_CUT_VERSION(version)) ? _FALSE : _TRUE) : _FALSE)
381 #define IS_VENDOR_8723_A_CUT(version) ((IS_8723_SERIES(version)) ? ((GET_CVID_CUT_VERSION(version)) ? _FALSE : _TRUE) : _FALSE)
382 // <tynli_Note> 88/92C UMC B-cut vendor is set to TSMC so we need to check CHIP_VENDOR_UMC bit is not 1.
383 #define IS_81xxC_VENDOR_UMC_B_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? _TRUE : _FALSE):_FALSE)
384 #define IS_92D_SINGLEPHY(version) ((IS_92D(version)) ? (IS_2T2R(version) ? _TRUE: _FALSE) : _FALSE)
385 #define IS_92D_C_CUT(version) ((IS_92D(version)) ? ((GET_CVID_CUT_VERSION(version) == 0x2) ? _TRUE : _FALSE) : _FALSE)
386 #define IS_92D_D_CUT(version) ((IS_92D(version)) ? ((GET_CVID_CUT_VERSION(version) == 0x3) ? _TRUE : _FALSE) : _FALSE)
387
388 typedef enum _VERSION_8192C{
389 VERSION_TEST_CHIP_88C = 0x0000,
390 VERSION_TEST_CHIP_92C = 0x0020,
391 VERSION_TEST_UMC_CHIP_8723 = 0x0081,
392 VERSION_NORMAL_TSMC_CHIP_88C = 0x0008,
393 VERSION_NORMAL_TSMC_CHIP_92C = 0x0028,
394 VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x0018,
395 VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x0088,
396 VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x00a8,
397 VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x0098,
398 VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT = 0x0089,
399 VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT = 0x1089,
400 VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x1088,
401 VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x10a8,
402 VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x1090,
403 VERSION_TEST_CHIP_92D_SINGLEPHY= 0x0022,
404 VERSION_TEST_CHIP_92D_DUALPHY = 0x0002,
405 VERSION_NORMAL_CHIP_92D_SINGLEPHY= 0x002a,
406 VERSION_NORMAL_CHIP_92D_DUALPHY = 0x000a,
407 VERSION_NORMAL_CHIP_92D_C_CUT_SINGLEPHY = 0x202a,
408 VERSION_NORMAL_CHIP_92D_C_CUT_DUALPHY = 0x200a,
409 VERSION_NORMAL_CHIP_92D_D_CUT_SINGLEPHY = 0x302a,
410 VERSION_NORMAL_CHIP_92D_D_CUT_DUALPHY = 0x300a,
411 }VERSION_8192C,*PVERSION_8192C;
412
413
414
415 //-------------------------------------------------------------------------
416 // Channel Plan
417 //-------------------------------------------------------------------------
418 enum ChannelPlan{
419 CHPL_FCC = 0,
420 CHPL_IC = 1,
421 CHPL_ETSI = 2,
422 CHPL_SPAIN = 3,
423 CHPL_FRANCE = 4,
424 CHPL_MKK = 5,
425 CHPL_MKK1 = 6,
426 CHPL_ISRAEL = 7,
427 CHPL_TELEC = 8,
428 CHPL_GLOBAL = 9,
429 CHPL_WORLD = 10,
430 };
431
432 typedef struct _TxPowerInfo{
433 u8 CCKIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX];
434 u8 HT40_1SIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX];
435 u8 HT40_2SIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX];
436 s8 HT20IndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX];
437 u8 OFDMIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX];
438 u8 HT40MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX];
439 u8 HT20MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX];
440 u8 TSSI_A;
441 u8 TSSI_B;
442 }TxPowerInfo, *PTxPowerInfo;
443
444 #define EFUSE_REAL_CONTENT_LEN 512
445 #define EFUSE_MAP_LEN 128
446 #define EFUSE_MAX_SECTION 16
447 #define EFUSE_IC_ID_OFFSET 506 //For some inferiority IC purpose. added by Roger, 2009.09.02.
448 #define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN)
449 //
450 // <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
451 // 9bytes + 1byt + 5bytes and pre 1byte.
452 // For worst case:
453 // | 1byte|----8bytes----|1byte|--5bytes--|
454 // | | Reserved(14bytes) |
455 //
456 #define EFUSE_OOB_PROTECT_BYTES 15 // PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte.
457
458
459 #define EFUSE_MAP_LEN_8723 256
460 #define EFUSE_MAX_SECTION_8723 32
461
462 //========================================================
463 // EFUSE for BT definition
464 //========================================================
465 #define EFUSE_BT_REAL_CONTENT_LEN 1536 // 512*3
466 #define EFUSE_BT_MAP_LEN 1024 // 1k bytes
467 #define EFUSE_BT_MAX_SECTION 128 // 1024/8
468
469 #define EFUSE_PROTECT_BYTES_BANK 16
470
471 //
472 // <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06.
473 //
474 typedef enum _RT_MULTI_FUNC{
475 RT_MULTI_FUNC_NONE = 0x00,
476 RT_MULTI_FUNC_WIFI = 0x01,
477 RT_MULTI_FUNC_BT = 0x02,
478 RT_MULTI_FUNC_GPS = 0x04,
479 }RT_MULTI_FUNC,*PRT_MULTI_FUNC;
480
481 //
482 // <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08.
483 //
484 typedef enum _RT_POLARITY_CTL{
485 RT_POLARITY_LOW_ACT = 0,
486 RT_POLARITY_HIGH_ACT = 1,
487 }RT_POLARITY_CTL,*PRT_POLARITY_CTL;
488
489 // For RTL8723 regulator mode. by tynli. 2011.01.14.
490 typedef enum _RT_REGULATOR_MODE{
491 RT_SWITCHING_REGULATOR = 0,
492 RT_LDO_REGULATOR = 1,
493 }RT_REGULATOR_MODE,*PRT_REGULATOR_MODE;
494
495 enum c2h_id_8192c {
496 C2H_DBG = 0,
497 C2H_TSF = 1,
498 C2H_AP_RPT_RSP = 2,
499 C2H_CCX_TX_RPT = 3,
500 C2H_BT_RSSI = 4,
501 C2H_BT_OP_MODE = 5,
502 C2H_EXT_RA_RPT = 6,
503 C2H_HW_INFO_EXCH = 10,
504 C2H_C2H_H2C_TEST = 11,
505 C2H_BT_INFO = 12,
506 C2H_BT_MP_INFO = 15,
507 MAX_C2HEVENT
508 };
509
510 #ifdef CONFIG_PCI_HCI
511 struct hal_data_8192ce
512 {
513 VERSION_8192C VersionID;
514 RT_MULTI_FUNC MultiFunc; // For multi-function consideration.
515 RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control.
516 RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO
517 u16 CustomerID;
518
519 u16 FirmwareVersion;
520 u16 FirmwareVersionRev;
521 u16 FirmwareSubVersion;
522
523 u32 IntrMask[2];
524 u32 IntrMaskToSet[2];
525
526 u32 DisabledFunctions;
527
528 //current WIFI_PHY values
529 u32 ReceiveConfig;
530 u32 TransmitConfig;
531 WIRELESS_MODE CurrentWirelessMode;
532 HT_CHANNEL_WIDTH CurrentChannelBW;
533 u8 CurrentChannel;
534 u8 nCur40MhzPrimeSC;// Control channel sub-carrier
535
536 u16 BasicRateSet;
537
538 //rf_ctrl
539 _lock rf_lock;
540 u8 rf_chip;
541 u8 rf_type;
542 u8 NumTotalRFPath;
543
544 INTERFACE_SELECT_8192CPCIe InterfaceSel;
545
546 //
547 // EEPROM setting.
548 //
549 u16 EEPROMVID;
550 u16 EEPROMDID;
551 u16 EEPROMSVID;
552 u16 EEPROMSMID;
553 u16 EEPROMChannelPlan;
554 u16 EEPROMVersion;
555
556 u8 EEPROMChnlAreaTxPwrCCK[2][3];
557 u8 EEPROMChnlAreaTxPwrHT40_1S[2][3];
558 u8 EEPROMChnlAreaTxPwrHT40_2SDiff[2][3];
559 u8 EEPROMPwrLimitHT20[3];
560 u8 EEPROMPwrLimitHT40[3];
561
562 u8 bTXPowerDataReadFromEEPORM;
563 u8 EEPROMThermalMeter;
564 u8 EEPROMTSSI[2];
565
566 u8 EEPROMCustomerID;
567 u8 EEPROMBoardType;
568 u8 EEPROMRegulatory;
569
570 u8 bDefaultAntenna;
571 u8 bIQKInitialized;
572
573 u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
574 u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
575 u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
576 s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
577 u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
578 // For power group
579 u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
580 u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
581
582 u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff
583
584 #ifdef CONFIG_BT_COEXIST
585 struct btcoexist_priv bt_coexist;
586 #endif
587
588 // Read/write are allow for following hardware information variables
589 u8 framesync;
590 u32 framesyncC34;
591 u8 framesyncMonitor;
592 u8 DefaultInitialGain[4];
593 u8 pwrGroupCnt;
594 u32 MCSTxPowerLevelOriginalOffset[7][16];
595 u32 CCKTxPowerLevelOriginalOffset;
596
597 u32 AntennaTxPath; // Antenna path Tx
598 u32 AntennaRxPath; // Antenna path Rx
599 u8 BluetoothCoexist;
600 u8 ExternalPA;
601
602 //u32 LedControlNum;
603 //u32 LedControlMode;
604 u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
605 //u32 TxPowerTrackControl;
606 u8 b1x1RecvCombine; // for 1T1R receive combining
607
608 u8 bCurrentTurboEDCA;
609 u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo.
610
611 //vivi, for tx power tracking, 20080407
612 //u16 TSSI_13dBm;
613 //u32 Pwr_Track;
614 // The current Tx Power Level
615 u8 CurrentCckTxPwrIdx;
616 u8 CurrentOfdm24GTxPwrIdx;
617
618 BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
619
620 BOOLEAN bRFPathRxEnable[4]; // We support 4 RF path now.
621
622 u32 RfRegChnlVal[2];
623
624 u8 bCckHighPower;
625
626 //RDG enable
627 BOOLEAN bRDGEnable;
628
629 //for host message to fw
630 u8 LastHMEBoxNum;
631
632 u8 fw_ractrl;
633 u8 RegTxPause;
634 // Beacon function related global variable.
635 u32 RegBcnCtrlVal;
636 u8 RegFwHwTxQCtrl;
637 u8 RegReg542;
638 u8 CurAntenna;
639 u8 AntDivCfg;
640
641 #ifdef CONFIG_SW_ANTENNA_DIVERSITY
642 //SW Antenna Switch
643 s32 RSSI_sum_A;
644 s32 RSSI_sum_B;
645 s32 RSSI_cnt_A;
646 s32 RSSI_cnt_B;
647 BOOLEAN RSSI_test;
648 #endif
649 #ifdef CONFIG_HW_ANTENNA_DIVERSITY
650 //Hybrid Antenna Diversity
651 u32 CCK_Ant1_Cnt;
652 u32 CCK_Ant2_Cnt;
653 u32 OFDM_Ant1_Cnt;
654 u32 OFDM_Ant2_Cnt;
655 #endif
656
657 struct dm_priv dmpriv;
658 u8 bDumpRxPkt;//for debug
659 #ifdef DBG_CONFIG_ERROR_DETECT
660 struct sreset_priv srestpriv;
661 #endif
662 u8 bInterruptMigration;
663 u8 bDisableTxInt;
664 u8 bGpioHwWpsPbc;
665
666 u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
667
668 u16 EfuseUsedBytes;
669
670 #ifdef CONFIG_P2P
671 struct P2P_PS_Offload_t p2p_ps_offload;
672 #endif //CONFIG_P2P
673 };
674
675 typedef struct hal_data_8192ce HAL_DATA_TYPE, *PHAL_DATA_TYPE;
676
677 //
678 // Function disabled.
679 //
680 #define DF_TX_BIT BIT0
681 #define DF_RX_BIT BIT1
682 #define DF_IO_BIT BIT2
683 #define DF_IO_D3_BIT BIT3
684
685 #define RT_DF_TYPE u32
686 #define RT_DISABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions |= ((RT_DF_TYPE)(__FuncBits)))
687 #define RT_ENABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions &= (~((RT_DF_TYPE)(__FuncBits))))
688 #define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) )
689 #define IS_MULTI_FUNC_CHIP(_Adapter) (((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE)
690
691 void InterruptRecognized8192CE(PADAPTER Adapter, PRT_ISR_CONTENT pIsrContent);
692 VOID UpdateInterruptMask8192CE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
693 #endif
694
695 #ifdef CONFIG_USB_HCI
696 struct hal_data_8192cu
697 {
698 VERSION_8192C VersionID;
699 RT_MULTI_FUNC MultiFunc; // For multi-function consideration.
700 RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control.
701 RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO
702 u16 CustomerID;
703
704 u16 FirmwareVersion;
705 u16 FirmwareVersionRev;
706 u16 FirmwareSubVersion;
707
708 //current WIFI_PHY values
709 u32 ReceiveConfig;
710 WIRELESS_MODE CurrentWirelessMode;
711 HT_CHANNEL_WIDTH CurrentChannelBW;
712 u8 CurrentChannel;
713 u8 nCur40MhzPrimeSC;// Control channel sub-carrier
714
715 u16 BasicRateSet;
716
717 //rf_ctrl
718 u8 rf_chip;
719 u8 rf_type;
720 u8 NumTotalRFPath;
721
722 u8 BoardType;
723 //INTERFACE_SELECT_8192CUSB InterfaceSel;
724
725 //
726 // EEPROM setting.
727 //
728 u16 EEPROMVID;
729 u16 EEPROMPID;
730 u16 EEPROMSVID;
731 u16 EEPROMSDID;
732 u8 EEPROMCustomerID;
733 u8 EEPROMSubCustomerID;
734 u8 EEPROMVersion;
735 u8 EEPROMRegulatory;
736
737 u8 bTXPowerDataReadFromEEPORM;
738 u8 EEPROMThermalMeter;
739
740 u8 bIQKInitialized;
741
742 u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
743 u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
744 u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
745 s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
746 u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
747 // For power group
748 u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
749 u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
750
751 u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff
752
753 // Read/write are allow for following hardware information variables
754 u8 framesync;
755 u32 framesyncC34;
756 u8 framesyncMonitor;
757 u8 DefaultInitialGain[4];
758 u8 pwrGroupCnt;
759 u32 MCSTxPowerLevelOriginalOffset[7][16];
760 u32 CCKTxPowerLevelOriginalOffset;
761
762 u32 AntennaTxPath; // Antenna path Tx
763 u32 AntennaRxPath; // Antenna path Rx
764 u8 BluetoothCoexist;
765 u8 ExternalPA;
766
767 u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
768
769 //u32 LedControlNum;
770 //u32 LedControlMode;
771 //u32 TxPowerTrackControl;
772 u8 b1x1RecvCombine; // for 1T1R receive combining
773
774 u8 bCurrentTurboEDCA;
775 u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo.
776
777 //vivi, for tx power tracking, 20080407
778 //u16 TSSI_13dBm;
779 //u32 Pwr_Track;
780 // The current Tx Power Level
781 u8 CurrentCckTxPwrIdx;
782 u8 CurrentOfdm24GTxPwrIdx;
783
784 BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
785
786 BOOLEAN bRFPathRxEnable[4]; // We support 4 RF path now.
787
788 u32 RfRegChnlVal[2];
789
790 u8 bCckHighPower;
791
792 //RDG enable
793 BOOLEAN bRDGEnable;
794
795 //for host message to fw
796 u8 LastHMEBoxNum;
797
798 u8 fw_ractrl;
799 u8 RegTxPause;
800 // Beacon function related global variable.
801 u32 RegBcnCtrlVal;
802 u8 RegFwHwTxQCtrl;
803 u8 RegReg542;
804
805 struct dm_priv dmpriv;
806 #ifdef DBG_CONFIG_ERROR_DETECT
807 struct sreset_priv srestpriv;
808 #endif
809
810 #ifdef CONFIG_BT_COEXIST
811 struct btcoexist_priv bt_coexist;
812 #endif
813 u8 CurAntenna;
814 u8 AntDivCfg;
815
816 #ifdef CONFIG_SW_ANTENNA_DIVERSITY
817 //SW Antenna Switch
818 s32 RSSI_sum_A;
819 s32 RSSI_sum_B;
820 s32 RSSI_cnt_A;
821 s32 RSSI_cnt_B;
822 BOOLEAN RSSI_test;
823 #endif
824 #ifdef CONFIG_HW_ANTENNA_DIVERSITY
825 //Hybrid Antenna Diversity
826 u32 CCK_Ant1_Cnt;
827 u32 CCK_Ant2_Cnt;
828 u32 OFDM_Ant1_Cnt;
829 u32 OFDM_Ant2_Cnt;
830 #endif
831
832 u8 bDumpRxPkt;//for debug
833 u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
834
835 // 2010/08/09 MH Add CU power down mode.
836 BOOLEAN pwrdown;
837
838 // For 92C USB endpoint setting
839 //
840
841 u32 UsbBulkOutSize;
842
843 int RtBulkOutPipe[3];
844 int RtBulkInPipe;
845 int RtIntInPipe;
846 // Add for dual MAC 0--Mac0 1--Mac1
847 u32 interfaceIndex;
848
849 u8 OutEpQueueSel;
850 u8 OutEpNumber;
851
852 u8 Queue2EPNum[8];//for out endpoint number mapping
853
854 #ifdef CONFIG_USB_TX_AGGREGATION
855 u8 UsbTxAggMode;
856 u8 UsbTxAggDescNum;
857 #endif
858 #ifdef CONFIG_USB_RX_AGGREGATION
859 u16 HwRxPageSize; // Hardware setting
860 u32 MaxUsbRxAggBlock;
861
862 USB_RX_AGG_MODE UsbRxAggMode;
863 u8 UsbRxAggBlockCount; // USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed
864 u8 UsbRxAggBlockTimeout;
865 u8 UsbRxAggPageCount; // 8192C DMA page count
866 u8 UsbRxAggPageTimeout;
867 #endif
868
869 // 2010/12/10 MH Add for USB aggreation mode dynamic shceme.
870 BOOLEAN UsbRxHighSpeedMode;
871
872 // 2010/11/22 MH Add for slim combo debug mode selective.
873 // This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock.
874 BOOLEAN SlimComboDbg;
875
876 u16 EfuseUsedBytes;
877
878 #ifdef CONFIG_P2P
879 struct P2P_PS_Offload_t p2p_ps_offload;
880 #endif //CONFIG_P2P
881 };
882
883 typedef struct hal_data_8192cu HAL_DATA_TYPE, *PHAL_DATA_TYPE;
884 #endif
885
886 #define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData))
887 #define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type)
888
889 #define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
890 #define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
891
892 VOID rtl8192c_FirmwareSelfReset(IN PADAPTER Adapter);
893 int FirmwareDownload92C(IN PADAPTER Adapter,IN BOOLEAN bUsedWoWLANFw);
894 VOID InitializeFirmwareVars92C(PADAPTER Adapter);
895 u8 GetEEPROMSize8192C(PADAPTER Adapter);
896 void rtl8192c_EfuseParseChnlPlan(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
897 VERSION_8192C rtl8192c_ReadChipVersion(IN PADAPTER Adapter);
898 void rtl8192c_ReadBluetoothCoexistInfo(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
899 //void rtl8192c_free_hal_data(_adapter * padapter);
900 VOID rtl8192c_EfuseParseIDCode(PADAPTER pAdapter, u8 *hwinfo);
901 void rtl8192c_set_hal_ops(struct hal_ops *pHalFunc);
902
903 s32 c2h_id_filter_ccx_8192c(u8 id);
904 #endif
905
906 #ifdef CONFIG_MP_INCLUDED
907
908 extern void Hal_SetAntenna(PADAPTER pAdapter);
909 extern void Hal_SetBandwidth(PADAPTER pAdapter);
910
911 extern void Hal_SetTxPower(PADAPTER pAdapter);
912 extern void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart);
913 extern void Hal_SetSingleToneTx ( PADAPTER pAdapter , u8 bStart );
914 extern void Hal_SetSingleCarrierTx (PADAPTER pAdapter, u8 bStart);
915 extern void Hal_SetContinuousTx (PADAPTER pAdapter, u8 bStart);
916
917 extern void Hal_SetDataRate(PADAPTER pAdapter);
918 extern void Hal_SetChannel(PADAPTER pAdapter);
919 extern void Hal_SetAntennaPathPower(PADAPTER pAdapter);
920 extern s32 Hal_SetThermalMeter(PADAPTER pAdapter, u8 target_ther);
921 extern s32 Hal_SetPowerTracking(PADAPTER padapter, u8 enable);
922 extern void Hal_GetPowerTracking(PADAPTER padapter, u8 * enable);
923 extern void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value);
924 extern void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter);
925 extern void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14);
926 extern void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven);
927 extern void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 * TxPower);
928 extern void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 * TxPower);
929 extern void Hal_TriggerRFThermalMeter(PADAPTER pAdapter);
930 extern u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter);
931 extern void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart);
932 extern void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart);
933
934 #endif
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