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git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/net/wireless/realtek/rtl8192cu/include/rtw_mp_phy_regdef.h
1 /****************************************************************************** 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 19 ******************************************************************************/ 20 /***************************************************************************** 22 * Module: __RTW_MP_PHY_REGDEF_H_ 25 * Note: 1. Define PMAC/BB register map 26 * 2. Define RF register map 27 * 3. PMAC/BB register bit mask. 29 * 5. Other BB/RF relative definition. 32 * Export: Constants, macro, functions(API), global variables(None). 38 * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. 39 * 2. Reorganize code architecture. 40 * 09/25/2008 MH 1. Add RL6052 register definition 42 *****************************************************************************/ 43 #ifndef __RTW_MP_PHY_REGDEF_H_ 44 #define __RTW_MP_PHY_REGDEF_H_ 47 /*--------------------------Define Parameters-------------------------------*/ 49 //============================================================ 50 // 8192S Regsiter offset definition 51 //============================================================ 54 // BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF 55 // 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 56 // 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 57 // 3. RF register 0x00-2E 58 // 4. Bit Mask for BB/RF register 59 // 5. Other defintion for BB/RF R/W 64 // 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 67 #define rPMAC_Reset 0x100 68 #define rPMAC_TxStart 0x104 69 #define rPMAC_TxLegacySIG 0x108 70 #define rPMAC_TxHTSIG1 0x10c 71 #define rPMAC_TxHTSIG2 0x110 72 #define rPMAC_PHYDebug 0x114 73 #define rPMAC_TxPacketNum 0x118 74 #define rPMAC_TxIdle 0x11c 75 #define rPMAC_TxMACHeader0 0x120 76 #define rPMAC_TxMACHeader1 0x124 77 #define rPMAC_TxMACHeader2 0x128 78 #define rPMAC_TxMACHeader3 0x12c 79 #define rPMAC_TxMACHeader4 0x130 80 #define rPMAC_TxMACHeader5 0x134 81 #define rPMAC_TxDataType 0x138 82 #define rPMAC_TxRandomSeed 0x13c 83 #define rPMAC_CCKPLCPPreamble 0x140 84 #define rPMAC_CCKPLCPHeader 0x144 85 #define rPMAC_CCKCRC16 0x148 86 #define rPMAC_OFDMRxCRC32OK 0x170 87 #define rPMAC_OFDMRxCRC32Er 0x174 88 #define rPMAC_OFDMRxParityEr 0x178 89 #define rPMAC_OFDMRxCRC8Er 0x17c 90 #define rPMAC_CCKCRxRC16Er 0x180 91 #define rPMAC_CCKCRxRC32Er 0x184 92 #define rPMAC_CCKCRxRC32OK 0x188 93 #define rPMAC_TxStatus 0x18c 98 // The following two definition are only used for USB interface. 99 //#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address. 100 //#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data. 105 #define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? 107 #define rFPGA0_TxInfo 0x804 // Status report?? 108 #define rFPGA0_PSDFunction 0x808 110 #define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? 112 #define rFPGA0_RFTiming1 0x810 // Useless now 113 #define rFPGA0_RFTiming2 0x814 114 //#define rFPGA0_XC_RFTiming 0x818 115 //#define rFPGA0_XD_RFTiming 0x81c 117 #define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register 118 #define rFPGA0_XA_HSSIParameter2 0x824 119 #define rFPGA0_XB_HSSIParameter1 0x828 120 #define rFPGA0_XB_HSSIParameter2 0x82c 121 #define rFPGA0_XC_HSSIParameter1 0x830 122 #define rFPGA0_XC_HSSIParameter2 0x834 123 #define rFPGA0_XD_HSSIParameter1 0x838 124 #define rFPGA0_XD_HSSIParameter2 0x83c 125 #define rFPGA0_XA_LSSIParameter 0x840 126 #define rFPGA0_XB_LSSIParameter 0x844 127 #define rFPGA0_XC_LSSIParameter 0x848 128 #define rFPGA0_XD_LSSIParameter 0x84c 130 #define rFPGA0_RFWakeUpParameter 0x850 // Useless now 131 #define rFPGA0_RFSleepUpParameter 0x854 133 #define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch 134 #define rFPGA0_XCD_SwitchControl 0x85c 136 #define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch 137 #define rFPGA0_XB_RFInterfaceOE 0x864 138 #define rFPGA0_XC_RFInterfaceOE 0x868 139 #define rFPGA0_XD_RFInterfaceOE 0x86c 141 #define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control 142 #define rFPGA0_XCD_RFInterfaceSW 0x874 144 #define rFPGA0_XAB_RFParameter 0x878 // RF Parameter 145 #define rFPGA0_XCD_RFParameter 0x87c 147 #define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? 148 #define rFPGA0_AnalogParameter2 0x884 149 #define rFPGA0_AnalogParameter3 0x888 // Useless now 150 #define rFPGA0_AnalogParameter4 0x88c 152 #define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback 153 #define rFPGA0_XB_LSSIReadBack 0x8a4 154 #define rFPGA0_XC_LSSIReadBack 0x8a8 155 #define rFPGA0_XD_LSSIReadBack 0x8ac 157 #define rFPGA0_PSDReport 0x8b4 // Useless now 158 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value 159 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now 164 #define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? 166 #define rFPGA1_TxBlock 0x904 // Useless now 167 #define rFPGA1_DebugSelect 0x908 // Useless now 168 #define rFPGA1_TxInfo 0x90c // Useless now // Status report?? 173 // Set Control channel to upper or lower. These settings are required only for 40MHz 174 #define rCCK0_System 0xa00 176 #define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI 177 #define rCCK0_CCA 0xa08 // Disable init gain now // Init gain 179 #define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series 180 #define rCCK0_RxAGC2 0xa10 //AGC & DAGC 182 #define rCCK0_RxHP 0xa14 184 #define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold 185 #define rCCK0_DSPParameter2 0xa1c //SQ threshold 187 #define rCCK0_TxFilter1 0xa20 188 #define rCCK0_TxFilter2 0xa24 189 #define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 190 #define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report 191 #define rCCK0_TRSSIReport 0xa50 192 #define rCCK0_RxReport 0xa54 //0xa57 193 #define rCCK0_FACounterLower 0xa5c //0xa5b 194 #define rCCK0_FACounterUpper 0xa58 //0xa5c 199 #define rOFDM0_LSTF 0xc00 201 #define rOFDM0_TRxPathEnable 0xc04 202 #define rOFDM0_TRMuxPar 0xc08 203 #define rOFDM0_TRSWIsolation 0xc0c 205 #define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter 206 #define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix 207 #define rOFDM0_XBRxAFE 0xc18 208 #define rOFDM0_XBRxIQImbalance 0xc1c 209 #define rOFDM0_XCRxAFE 0xc20 210 #define rOFDM0_XCRxIQImbalance 0xc24 211 #define rOFDM0_XDRxAFE 0xc28 212 #define rOFDM0_XDRxIQImbalance 0xc2c 214 #define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain 215 #define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. 216 #define rOFDM0_RxDetector3 0xc38 //Frame Sync. 217 #define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI 219 #define rOFDM0_RxDSP 0xc40 //Rx Sync Path 220 #define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC 221 #define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold 222 #define rOFDM0_ECCAThreshold 0xc4c // energy CCA 224 #define rOFDM0_XAAGCCore1 0xc50 // DIG 225 #define rOFDM0_XAAGCCore2 0xc54 226 #define rOFDM0_XBAGCCore1 0xc58 227 #define rOFDM0_XBAGCCore2 0xc5c 228 #define rOFDM0_XCAGCCore1 0xc60 229 #define rOFDM0_XCAGCCore2 0xc64 230 #define rOFDM0_XDAGCCore1 0xc68 231 #define rOFDM0_XDAGCCore2 0xc6c 233 #define rOFDM0_AGCParameter1 0xc70 234 #define rOFDM0_AGCParameter2 0xc74 235 #define rOFDM0_AGCRSSITable 0xc78 236 #define rOFDM0_HTSTFAGC 0xc7c 238 #define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG 239 #define rOFDM0_XATxAFE 0xc84 240 #define rOFDM0_XBTxIQImbalance 0xc88 241 #define rOFDM0_XBTxAFE 0xc8c 242 #define rOFDM0_XCTxIQImbalance 0xc90 243 #define rOFDM0_XCTxAFE 0xc94 244 #define rOFDM0_XDTxIQImbalance 0xc98 245 #define rOFDM0_XDTxAFE 0xc9c 246 #define rOFDM0_RxIQExtAnta 0xca0 248 #define rOFDM0_RxHPParameter 0xce0 249 #define rOFDM0_TxPseudoNoiseWgt 0xce4 250 #define rOFDM0_FrameSync 0xcf0 251 #define rOFDM0_DFSReport 0xcf4 252 #define rOFDM0_TxCoeff1 0xca4 253 #define rOFDM0_TxCoeff2 0xca8 254 #define rOFDM0_TxCoeff3 0xcac 255 #define rOFDM0_TxCoeff4 0xcb0 256 #define rOFDM0_TxCoeff5 0xcb4 257 #define rOFDM0_TxCoeff6 0xcb8 263 #define rOFDM1_LSTF 0xd00 264 #define rOFDM1_TRxPathEnable 0xd04 266 #define rOFDM1_CFO 0xd08 // No setting now 267 #define rOFDM1_CSI1 0xd10 268 #define rOFDM1_SBD 0xd14 269 #define rOFDM1_CSI2 0xd18 270 #define rOFDM1_CFOTracking 0xd2c 271 #define rOFDM1_TRxMesaure1 0xd34 272 #define rOFDM1_IntfDet 0xd3c 273 #define rOFDM1_PseudoNoiseStateAB 0xd50 274 #define rOFDM1_PseudoNoiseStateCD 0xd54 275 #define rOFDM1_RxPseudoNoiseWgt 0xd58 277 #define rOFDM_PHYCounter1 0xda0 //cca, parity fail 278 #define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail 279 #define rOFDM_PHYCounter3 0xda8 //MCS not support 281 #define rOFDM_ShortCFOAB 0xdac // No setting now 282 #define rOFDM_ShortCFOCD 0xdb0 283 #define rOFDM_LongCFOAB 0xdb4 284 #define rOFDM_LongCFOCD 0xdb8 285 #define rOFDM_TailCFOAB 0xdbc 286 #define rOFDM_TailCFOCD 0xdc0 287 #define rOFDM_PWMeasure1 0xdc4 288 #define rOFDM_PWMeasure2 0xdc8 289 #define rOFDM_BWReport 0xdcc 290 #define rOFDM_AGCReport 0xdd0 291 #define rOFDM_RxSNR 0xdd4 292 #define rOFDM_RxEVMCSI 0xdd8 293 #define rOFDM_SIGReport 0xddc 299 #define rTxAGC_Rate18_06 0xe00 300 #define rTxAGC_Rate54_24 0xe04 301 #define rTxAGC_CCK_Mcs32 0xe08 302 #define rTxAGC_Mcs03_Mcs00 0xe10 303 #define rTxAGC_Mcs07_Mcs04 0xe14 304 #define rTxAGC_Mcs11_Mcs08 0xe18 305 #define rTxAGC_Mcs15_Mcs12 0xe1c 307 // Analog- control in RX_WAIT_CCA : REG: EE0 [Analog- Power & Control Register] 308 #define rRx_Wait_CCCA 0xe70 309 #define rAnapar_Ctrl_BB 0xee0 312 // 7. RF Register 0x00-0x2E (RF 8256) 316 #define RTL92SE_FPGA_VERIFY 0 317 #define rZebra1_HSSIEnable 0x0 // Useless now 318 #define rZebra1_TRxEnable1 0x1 319 #define rZebra1_TRxEnable2 0x2 320 #define rZebra1_AGC 0x4 321 #define rZebra1_ChargePump 0x5 322 //#if (RTL92SE_FPGA_VERIFY == 1) 323 #define rZebra1_Channel 0x7 // RF channel switch 327 #define rZebra1_TxGain 0x8 // Useless now 328 #define rZebra1_TxLPF 0x9 329 #define rZebra1_RxLPF 0xb 330 #define rZebra1_RxHPFCorner 0xc 333 #define rGlobalCtrl 0 // Useless now 334 #define rRTL8256_TxLPF 19 335 #define rRTL8256_RxLPF 11 338 #define rRTL8258_TxLPF 0x11 // Useless now 339 #define rRTL8258_RxLPF 0x13 340 #define rRTL8258_RSSILPF 0xa 343 // RL6052 Register definition 345 #define RF_AC 0x00 // 347 #define RF_IQADJ_G1 0x01 // 348 #define RF_IQADJ_G2 0x02 // 349 #define RF_POW_TRSW 0x05 // 351 #define RF_GAIN_RX 0x06 // 352 #define RF_GAIN_TX 0x07 // 354 #define RF_TXM_IDAC 0x08 // 355 #define RF_BS_IQGEN 0x0F // 357 #define RF_MODE1 0x10 // 358 #define RF_MODE2 0x11 // 360 #define RF_RX_AGC_HP 0x12 // 361 #define RF_TX_AGC 0x13 // 362 #define RF_BIAS 0x14 // 363 #define RF_IPA 0x15 // 364 #define RF_POW_ABILITY 0x17 // 365 #define RF_MODE_AG 0x18 // 366 #define rRfChannel 0x18 // RF channel and BW switch 367 #define RF_CHNLBW 0x18 // RF channel and BW switch 368 #define RF_TOP 0x19 // 370 #define RF_RX_G1 0x1A // 371 #define RF_RX_G2 0x1B // 373 #define RF_RX_BB2 0x1C // 374 #define RF_RX_BB1 0x1D // 376 #define RF_RCK1 0x1E // 377 #define RF_RCK2 0x1F // 379 #define RF_TX_G1 0x20 // 380 #define RF_TX_G2 0x21 // 381 #define RF_TX_G3 0x22 // 383 #define RF_TX_BB1 0x23 // 385 #define RF_T_METER 0x24 // 387 #define RF_SYN_G1 0x25 // RF TX Power control 388 #define RF_SYN_G2 0x26 // RF TX Power control 389 #define RF_SYN_G3 0x27 // RF TX Power control 390 #define RF_SYN_G4 0x28 // RF TX Power control 391 #define RF_SYN_G5 0x29 // RF TX Power control 392 #define RF_SYN_G6 0x2A // RF TX Power control 393 #define RF_SYN_G7 0x2B // RF TX Power control 394 #define RF_SYN_G8 0x2C // RF TX Power control 396 #define RF_RCK_OS 0x30 // RF TX PA control 398 #define RF_TXPA_G1 0x31 // RF TX PA control 399 #define RF_TXPA_G2 0x32 // RF TX PA control 400 #define RF_TXPA_G3 0x33 // RF TX PA control 406 #define bBBResetB 0x100 // Useless now? 407 #define bGlobalResetB 0x200 408 #define bOFDMTxStart 0x4 409 #define bCCKTxStart 0x8 410 #define bCRC32Debug 0x100 411 #define bPMACLoopback 0x10 412 #define bTxLSIG 0xffffff 413 #define bOFDMTxRate 0xf 414 #define bOFDMTxReserved 0x10 415 #define bOFDMTxLength 0x1ffe0 416 #define bOFDMTxParity 0x20000 417 #define bTxHTSIG1 0xffffff 418 #define bTxHTMCSRate 0x7f 420 #define bTxHTLength 0xffff00 421 #define bTxHTSIG2 0xffffff 422 #define bTxHTSmoothing 0x1 423 #define bTxHTSounding 0x2 424 #define bTxHTReserved 0x4 425 #define bTxHTAggreation 0x8 426 #define bTxHTSTBC 0x30 427 #define bTxHTAdvanceCoding 0x40 428 #define bTxHTShortGI 0x80 429 #define bTxHTNumberHT_LTF 0x300 430 #define bTxHTCRC8 0x3fc00 431 #define bCounterReset 0x10000 432 #define bNumOfOFDMTx 0xffff 433 #define bNumOfCCKTx 0xffff0000 434 #define bTxIdleInterval 0xffff 435 #define bOFDMService 0xffff0000 436 #define bTxMACHeader 0xffffffff 437 #define bTxDataInit 0xff 438 #define bTxHTMode 0x100 439 #define bTxDataType 0x30000 440 #define bTxRandomSeed 0xffffffff 441 #define bCCKTxPreamble 0x1 442 #define bCCKTxSFD 0xffff0000 443 #define bCCKTxSIG 0xff 444 #define bCCKTxService 0xff00 445 #define bCCKLengthExt 0x8000 446 #define bCCKTxLength 0xffff0000 447 #define bCCKTxCRC16 0xffff 448 #define bCCKTxStatus 0x1 449 #define bOFDMTxStatus 0x2 451 #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) 454 #define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD 455 #define bJapanMode 0x2 456 #define bCCKTxSC 0x30 457 #define bCCKEn 0x1000000 458 #define bOFDMEn 0x2000000 460 #define bOFDMRxADCPhase 0x10000 // Useless now 461 #define bOFDMTxDACPhase 0x40000 462 #define bXATxAGC 0x3f 464 #define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage 465 #define bXCTxAGC 0xf000 466 #define bXDTxAGC 0xf0000 468 #define bPAStart 0xf0000000 // Useless now 469 #define bTRStart 0x00f00000 470 #define bRFStart 0x0000f000 471 #define bBBStart 0x000000f0 472 #define bBBCCKStart 0x0000000f 473 #define bPAEnd 0xf //Reg0x814 474 #define bTREnd 0x0f000000 475 #define bRFEnd 0x000f0000 476 #define bCCAMask 0x000000f0 //T2R 477 #define bR2RCCAMask 0x00000f00 478 #define bHSSI_R2TDelay 0xf8000000 479 #define bHSSI_T2RDelay 0xf80000 480 #define bContTxHSSI 0x400 //chane gain at continue Tx 481 #define bIGFromCCK 0x200 482 #define bAGCAddress 0x3f 483 #define bRxHPTx 0x7000 484 #define bRxHPT2R 0x38000 485 #define bRxHPCCKIni 0xc0000 486 #define bAGCTxCode 0xc00000 487 #define bAGCRxCode 0x300000 489 #define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 490 #define b3WireAddressLength 0x400 492 #define b3WireRFPowerDown 0x1 // Useless now 493 //#define bHWSISelect 0x8 494 #define b5GPAPEPolarity 0x40000000 495 #define b2GPAPEPolarity 0x80000000 496 #define bRFSW_TxDefaultAnt 0x3 497 #define bRFSW_TxOptionAnt 0x30 498 #define bRFSW_RxDefaultAnt 0x300 499 #define bRFSW_RxOptionAnt 0x3000 500 #define bRFSI_3WireData 0x1 501 #define bRFSI_3WireClock 0x2 502 #define bRFSI_3WireLoad 0x4 503 #define bRFSI_3WireRW 0x8 504 #define bRFSI_3Wire 0xf 506 #define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW 508 #define bRFSI_TRSW 0x20 // Useless now 509 #define bRFSI_TRSWB 0x40 510 #define bRFSI_ANTSW 0x100 511 #define bRFSI_ANTSWB 0x200 512 #define bRFSI_PAPE 0x400 513 #define bRFSI_PAPE5G 0x800 514 #define bBandSelect 0x1 515 #define bHTSIG2_GI 0x80 516 #define bHTSIG2_Smoothing 0x01 517 #define bHTSIG2_Sounding 0x02 518 #define bHTSIG2_Aggreaton 0x08 519 #define bHTSIG2_STBC 0x30 520 #define bHTSIG2_AdvCoding 0x40 521 #define bHTSIG2_NumOfHTLTF 0x300 522 #define bHTSIG2_CRC8 0x3fc 523 #define bHTSIG1_MCS 0x7f 524 #define bHTSIG1_BandWidth 0x80 525 #define bHTSIG1_HTLength 0xffff 526 #define bLSIG_Rate 0xf 527 #define bLSIG_Reserved 0x10 528 #define bLSIG_Length 0x1fffe 529 #define bLSIG_Parity 0x20 530 #define bCCKRxPhase 0x4 531 #if (RTL92SE_FPGA_VERIFY == 1) 532 #define bLSSIReadAddress 0x3f000000 //LSSI "Read" Address // Reg 0x824 rFPGA0_XA_HSSIParameter2 534 #define bLSSIReadAddress 0x7f800000 // T65 RF 536 #define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal 537 #if (RTL92SE_FPGA_VERIFY == 1) 538 #define bLSSIReadBackData 0xfff // Reg 0x8a0 rFPGA0_XA_LSSIReadBack 540 #define bLSSIReadBackData 0xfffff // T65 RF 542 #define bLSSIReadOKFlag 0x1000 // Useless now 543 #define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz 544 #define bRegulator0Standby 0x1 545 #define bRegulatorPLLStandby 0x2 546 #define bRegulator1Standby 0x4 547 #define bPLLPowerUp 0x8 548 #define bDPLLPowerUp 0x10 549 #define bDA10PowerUp 0x20 550 #define bAD7PowerUp 0x200 551 #define bDA6PowerUp 0x2000 552 #define bXtalPowerUp 0x4000 553 #define b40MDClkPowerUP 0x8000 554 #define bDA6DebugMode 0x20000 555 #define bDA6Swing 0x380000 557 #define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ 559 #define b80MClkDelay 0x18000000 // Useless 560 #define bAFEWatchDogEnable 0x20000000 562 #define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap 563 #define bXtalCap23 0x3 564 #define bXtalCap92x 0x0f000000 565 #define bXtalCap 0x0f000000 567 #define bIntDifClkEnable 0x400 // Useless 568 #define bExtSigClkEnable 0x800 569 #define bBandgapMbiasPowerUp 0x10000 570 #define bAD11SHGain 0xc0000 571 #define bAD11InputRange 0x700000 572 #define bAD11OPCurrent 0x3800000 573 #define bIPathLoopback 0x4000000 574 #define bQPathLoopback 0x8000000 575 #define bAFELoopback 0x10000000 576 #define bDA10Swing 0x7e0 577 #define bDA10Reverse 0x800 578 #define bDAClkSource 0x1000 579 #define bAD7InputRange 0x6000 580 #define bAD7Gain 0x38000 581 #define bAD7OutputCMMode 0x40000 582 #define bAD7InputCMMode 0x380000 583 #define bAD7Current 0xc00000 584 #define bRegulatorAdjust 0x7000000 585 #define bAD11PowerUpAtTx 0x1 586 #define bDA10PSAtTx 0x10 587 #define bAD11PowerUpAtRx 0x100 588 #define bDA10PSAtRx 0x1000 589 #define bCCKRxAGCFormat 0x200 590 #define bPSDFFTSamplepPoint 0xc000 591 #define bPSDAverageNum 0x3000 592 #define bIQPathControl 0xc00 593 #define bPSDFreq 0x3ff 594 #define bPSDAntennaPath 0x30 595 #define bPSDIQSwitch 0x40 596 #define bPSDRxTrigger 0x400000 597 #define bPSDTxTrigger 0x80000000 598 #define bPSDSineToneScale 0x7f000000 599 #define bPSDReport 0xffff 602 #define bOFDMTxSC 0x30000000 // Useless 604 #define bOFDMTxOn 0x2 605 #define bDebugPage 0xfff //reset debug page and also HWord, LWord 606 #define bDebugItem 0xff //reset debug page and LWord 608 #define bAntNonHT 0x100 609 #define bAntHT1 0x1000 610 #define bAntHT2 0x10000 611 #define bAntHT1S1 0x100000 612 #define bAntNonHTS1 0x1000000 615 #define bCCKBBMode 0x3 // Useless 616 #define bCCKTxPowerSaving 0x80 617 #define bCCKRxPowerSaving 0x40 619 #define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch 621 #define bCCKScramble 0x8 // Useless 622 #define bCCKAntDiversity 0x8000 623 #define bCCKCarrierRecovery 0x4000 624 #define bCCKTxRate 0x3000 625 #define bCCKDCCancel 0x0800 626 #define bCCKISICancel 0x0400 627 #define bCCKMatchFilter 0x0200 628 #define bCCKEqualizer 0x0100 629 #define bCCKPreambleDetect 0x800000 630 #define bCCKFastFalseCCA 0x400000 631 #define bCCKChEstStart 0x300000 632 #define bCCKCCACount 0x080000 633 #define bCCKcs_lim 0x070000 634 #define bCCKBistMode 0x80000000 635 #define bCCKCCAMask 0x40000000 636 #define bCCKTxDACPhase 0x4 637 #define bCCKRxADCPhase 0x20000000 //r_rx_clk 638 #define bCCKr_cp_mode0 0x0100 639 #define bCCKTxDCOffset 0xf0 640 #define bCCKRxDCOffset 0xf 641 #define bCCKCCAMode 0xc000 642 #define bCCKFalseCS_lim 0x3f00 643 #define bCCKCS_ratio 0xc00000 644 #define bCCKCorgBit_sel 0x300000 645 #define bCCKPD_lim 0x0f0000 646 #define bCCKNewCCA 0x80000000 647 #define bCCKRxHPofIG 0x8000 648 #define bCCKRxIG 0x7f00 649 #define bCCKLNAPolarity 0x800000 650 #define bCCKRx1stGain 0x7f0000 651 #define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity 652 #define bCCKRxAGCSatLevel 0x1f000000 653 #define bCCKRxAGCSatCount 0xe0 654 #define bCCKRxRFSettle 0x1f //AGCsamp_dly 655 #define bCCKFixedRxAGC 0x8000 656 //#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 657 #define bCCKAntennaPolarity 0x2000 658 #define bCCKTxFilterType 0x0c00 659 #define bCCKRxAGCReportType 0x0300 660 #define bCCKRxDAGCEn 0x80000000 661 #define bCCKRxDAGCPeriod 0x20000000 662 #define bCCKRxDAGCSatLevel 0x1f000000 663 #define bCCKTimingRecovery 0x800000 664 #define bCCKTxC0 0x3f0000 665 #define bCCKTxC1 0x3f000000 666 #define bCCKTxC2 0x3f 667 #define bCCKTxC3 0x3f00 668 #define bCCKTxC4 0x3f0000 669 #define bCCKTxC5 0x3f000000 670 #define bCCKTxC6 0x3f 671 #define bCCKTxC7 0x3f00 672 #define bCCKDebugPort 0xff0000 673 #define bCCKDACDebug 0x0f000000 674 #define bCCKFalseAlarmEnable 0x8000 675 #define bCCKFalseAlarmRead 0x4000 676 #define bCCKTRSSI 0x7f 677 #define bCCKRxAGCReport 0xfe 678 #define bCCKRxReport_AntSel 0x80000000 679 #define bCCKRxReport_MFOff 0x40000000 680 #define bCCKRxRxReport_SQLoss 0x20000000 681 #define bCCKRxReport_Pktloss 0x10000000 682 #define bCCKRxReport_Lockedbit 0x08000000 683 #define bCCKRxReport_RateError 0x04000000 684 #define bCCKRxReport_RxRate 0x03000000 685 #define bCCKRxFACounterLower 0xff 686 #define bCCKRxFACounterUpper 0xff000000 687 #define bCCKRxHPAGCStart 0xe000 688 #define bCCKRxHPAGCFinal 0x1c00 689 #define bCCKRxFalseAlarmEnable 0x8000 690 #define bCCKFACounterFreeze 0x4000 691 #define bCCKTxPathSel 0x10000000 692 #define bCCKDefaultRxPath 0xc000000 693 #define bCCKOptionRxPath 0x3000000 696 #define bNumOfSTF 0x3 // Useless 697 #define bShift_L 0xc0 707 #define bTRSSIFreq 0x200 708 #define bADCBackoff 0x3000 709 #define bDFIRBackoff 0xc000 710 #define bTRSSILatchPhase 0x10000 711 #define bRxIDCOffset 0xff 712 #define bRxQDCOffset 0xff00 713 #define bRxDFIRMode 0x1800000 714 #define bRxDCNFType 0xe000000 715 #define bRXIQImb_A 0x3ff 716 #define bRXIQImb_B 0xfc00 717 #define bRXIQImb_C 0x3f0000 718 #define bRXIQImb_D 0xffc00000 719 #define bDC_dc_Notch 0x60000 720 #define bRxNBINotch 0x1f000000 722 #define bPD_TH_Opt2 0xc000 723 #define bPWED_TH 0x700 724 #define bIfMF_Win_L 0x800 725 #define bPD_Option 0x1000 726 #define bMF_Win_L 0xe000 727 #define bBW_Search_L 0x30000 728 #define bwin_enh_L 0xc0000 729 #define bBW_TH 0x700000 730 #define bED_TH2 0x3800000 731 #define bBW_option 0x4000000 732 #define bRatio_TH 0x18000000 733 #define bWindow_L 0xe0000000 734 #define bSBD_Option 0x1 735 #define bFrame_TH 0x1c 736 #define bFS_Option 0x60 737 #define bDC_Slope_check 0x80 738 #define bFGuard_Counter_DC_L 0xe00 739 #define bFrame_Weight_Short 0x7000 740 #define bSub_Tune 0xe00000 741 #define bFrame_DC_Length 0xe000000 742 #define bSBD_start_offset 0x30000000 743 #define bFrame_TH_2 0x7 744 #define bFrame_GI2_TH 0x38 745 #define bGI2_Sync_en 0x40 746 #define bSarch_Short_Early 0x300 747 #define bSarch_Short_Late 0xc00 748 #define bSarch_GI2_Late 0x70000 749 #define bCFOAntSum 0x1 751 #define bCFOStartOffset 0xc 752 #define bCFOLookBack 0x70 753 #define bCFOSumWeight 0x80 754 #define bDAGCEnable 0x10000 755 #define bTXIQImb_A 0x3ff 756 #define bTXIQImb_B 0xfc00 757 #define bTXIQImb_C 0x3f0000 758 #define bTXIQImb_D 0xffc00000 759 #define bTxIDCOffset 0xff 760 #define bTxQDCOffset 0xff00 761 #define bTxDFIRMode 0x10000 762 #define bTxPesudoNoiseOn 0x4000000 763 #define bTxPesudoNoise_A 0xff 764 #define bTxPesudoNoise_B 0xff00 765 #define bTxPesudoNoise_C 0xff0000 766 #define bTxPesudoNoise_D 0xff000000 767 #define bCCADropOption 0x20000 768 #define bCCADropThres 0xfff00000 770 #define bEDCCA_L 0xf0 771 #define bLambda_ED 0x300 772 #define bRxInitialGain 0x7f 773 #define bRxAntDivEn 0x80 774 #define bRxAGCAddressForLNA 0x7f00 775 #define bRxHighPowerFlow 0x8000 776 #define bRxAGCFreezeThres 0xc0000 777 #define bRxFreezeStep_AGC1 0x300000 778 #define bRxFreezeStep_AGC2 0xc00000 779 #define bRxFreezeStep_AGC3 0x3000000 780 #define bRxFreezeStep_AGC0 0xc000000 781 #define bRxRssi_Cmp_En 0x10000000 782 #define bRxQuickAGCEn 0x20000000 783 #define bRxAGCFreezeThresMode 0x40000000 784 #define bRxOverFlowCheckType 0x80000000 785 #define bRxAGCShift 0x7f 786 #define bTRSW_Tri_Only 0x80 787 #define bPowerThres 0x300 789 #define bRxAGCTogetherEn 0x2 790 #define bRxAGCMin 0x4 791 #define bRxHP_Ini 0x7 792 #define bRxHP_TRLNA 0x70 793 #define bRxHP_RSSI 0x700 794 #define bRxHP_BBP1 0x7000 795 #define bRxHP_BBP2 0x70000 796 #define bRxHP_BBP3 0x700000 797 #define bRSSI_H 0x7f0000 //the threshold for high power 798 #define bRSSI_Gen 0x7f000000 //the threshold for ant diversity 799 #define bRxSettle_TRSW 0x7 800 #define bRxSettle_LNA 0x38 801 #define bRxSettle_RSSI 0x1c0 802 #define bRxSettle_BBP 0xe00 803 #define bRxSettle_RxHP 0x7000 804 #define bRxSettle_AntSW_RSSI 0x38000 805 #define bRxSettle_AntSW 0xc0000 806 #define bRxProcessTime_DAGC 0x300000 807 #define bRxSettle_HSSI 0x400000 808 #define bRxProcessTime_BBPPW 0x800000 809 #define bRxAntennaPowerShift 0x3000000 810 #define bRSSITableSelect 0xc000000 811 #define bRxHP_Final 0x7000000 812 #define bRxHTSettle_BBP 0x7 813 #define bRxHTSettle_HSSI 0x8 814 #define bRxHTSettle_RxHP 0x70 815 #define bRxHTSettle_BBPPW 0x80 816 #define bRxHTSettle_Idle 0x300 817 #define bRxHTSettle_Reserved 0x1c00 818 #define bRxHTRxHPEn 0x8000 819 #define bRxHTAGCFreezeThres 0x30000 820 #define bRxHTAGCTogetherEn 0x40000 821 #define bRxHTAGCMin 0x80000 822 #define bRxHTAGCEn 0x100000 823 #define bRxHTDAGCEn 0x200000 824 #define bRxHTRxHP_BBP 0x1c00000 825 #define bRxHTRxHP_Final 0xe0000000 826 #define bRxPWRatioTH 0x3 827 #define bRxPWRatioEn 0x4 828 #define bRxMFHold 0x3800 829 #define bRxPD_Delay_TH1 0x38 830 #define bRxPD_Delay_TH2 0x1c0 831 #define bRxPD_DC_COUNT_MAX 0x600 832 //#define bRxMF_Hold 0x3800 833 #define bRxPD_Delay_TH 0x8000 834 #define bRxProcess_Delay 0xf0000 835 #define bRxSearchrange_GI2_Early 0x700000 836 #define bRxFrame_Guard_Counter_L 0x3800000 837 #define bRxSGI_Guard_L 0xc000000 838 #define bRxSGI_Search_L 0x30000000 839 #define bRxSGI_TH 0xc0000000 840 #define bDFSCnt0 0xff 841 #define bDFSCnt1 0xff00 842 #define bDFSFlag 0xf0000 843 #define bMFWeightSum 0x300000 844 #define bMinIdxTH 0x7f000000 845 #define bDAFormat 0x40000 846 #define bTxChEmuEnable 0x01000000 847 #define bTRSWIsolation_A 0x7f 848 #define bTRSWIsolation_B 0x7f00 849 #define bTRSWIsolation_C 0x7f0000 850 #define bTRSWIsolation_D 0x7f000000 851 #define bExtLNAGain 0x7c00 854 #define bSTBCEn 0x4 // Useless 855 #define bAntennaMapping 0x10 857 #define bCFOAntSumD 0x200 858 #define bPHYCounterReset 0x8000000 859 #define bCFOReportGet 0x4000000 860 #define bOFDMContinueTx 0x10000000 861 #define bOFDMSingleCarrier 0x20000000 862 #define bOFDMSingleTone 0x40000000 863 //#define bRxPath1 0x01 864 //#define bRxPath2 0x02 865 //#define bRxPath3 0x04 866 //#define bRxPath4 0x08 867 //#define bTxPath1 0x10 868 //#define bTxPath2 0x20 869 #define bHTDetect 0x100 870 #define bCFOEn 0x10000 871 #define bCFOValue 0xfff00000 872 #define bSigTone_Re 0x3f 873 #define bSigTone_Im 0x7f00 874 #define bCounter_CCA 0xffff 875 #define bCounter_ParityFail 0xffff0000 876 #define bCounter_RateIllegal 0xffff 877 #define bCounter_CRC8Fail 0xffff0000 878 #define bCounter_MCSNoSupport 0xffff 879 #define bCounter_FastSync 0xffff 880 #define bShortCFO 0xfff 881 #define bShortCFOTLength 12 //total 882 #define bShortCFOFLength 11 //fraction 883 #define bLongCFO 0x7ff 884 #define bLongCFOTLength 11 885 #define bLongCFOFLength 11 886 #define bTailCFO 0x1fff 887 #define bTailCFOTLength 13 888 #define bTailCFOFLength 12 889 #define bmax_en_pwdB 0xffff 890 #define bCC_power_dB 0xffff0000 891 #define bnoise_pwdB 0xffff 892 #define bPowerMeasTLength 10 893 #define bPowerMeasFLength 3 894 #define bRx_HT_BW 0x1 897 #define bNB_intf_det_on 0x1 898 #define bIntf_win_len_cfg 0x30 899 #define bNB_Intf_TH_cfg 0x1c0 901 #define bTableSel 0x40 903 #define bRxSNR_A 0xff 904 #define bRxSNR_B 0xff00 905 #define bRxSNR_C 0xff0000 906 #define bRxSNR_D 0xff000000 907 #define bSNREVMTLength 8 908 #define bSNREVMFLength 1 910 #define bCSI2nd 0xff00 911 #define bRxEVM1st 0xff0000 912 #define bRxEVM2nd 0xff000000 915 #define bSGIEN 0x10000 917 #define bSFactorQAM1 0xf // Useless 918 #define bSFactorQAM2 0xf0 919 #define bSFactorQAM3 0xf00 920 #define bSFactorQAM4 0xf000 921 #define bSFactorQAM5 0xf0000 922 #define bSFactorQAM6 0xf0000 923 #define bSFactorQAM7 0xf00000 924 #define bSFactorQAM8 0xf000000 925 #define bSFactorQAM9 0xf0000000 926 #define bCSIScheme 0x100000 928 #define bNoiseLvlTopSet 0x3 // Useless 929 #define bChSmooth 0x4 930 #define bChSmoothCfg1 0x38 931 #define bChSmoothCfg2 0x1c0 932 #define bChSmoothCfg3 0xe00 933 #define bChSmoothCfg4 0x7000 934 #define bMRCMode 0x800000 935 #define bTHEVMCfg 0x7000000 937 #define bLoopFitType 0x1 // Useless 939 #define bUpdCFOOffData 0x80 940 #define bAdvUpdCFO 0x100 941 #define bAdvTimeCtrl 0x800 942 #define bUpdClko 0x1000 944 #define bTrackingMode 0x8000 945 #define bPhCmpEnable 0x10000 946 #define bUpdClkoLTF 0x20000 947 #define bComChCFO 0x40000 948 #define bCSIEstiMode 0x80000 949 #define bAdvUpdEqz 0x100000 950 #define bUChCfg 0x7000000 951 #define bUpdEqz 0x8000000 953 #define bTxAGCRate18_06 0x7f7f7f7f // Useless 954 #define bTxAGCRate54_24 0x7f7f7f7f 955 #define bTxAGCRateMCS32 0x7f 956 #define bTxAGCRateCCK 0x7f00 957 #define bTxAGCRateMCS3_MCS0 0x7f7f7f7f 958 #define bTxAGCRateMCS7_MCS4 0x7f7f7f7f 959 #define bTxAGCRateMCS11_MCS8 0x7f7f7f7f 960 #define bTxAGCRateMCS15_MCS12 0x7f7f7f7f 963 #define bRxPesudoNoiseOn 0x20000000 // Useless 964 #define bRxPesudoNoise_A 0xff 965 #define bRxPesudoNoise_B 0xff00 966 #define bRxPesudoNoise_C 0xff0000 967 #define bRxPesudoNoise_D 0xff000000 968 #define bPesudoNoiseState_A 0xffff 969 #define bPesudoNoiseState_B 0xffff0000 970 #define bPesudoNoiseState_C 0xffff 971 #define bPesudoNoiseState_D 0xffff0000 975 #define bZebra1_HSSIEnable 0x8 // Useless 976 #define bZebra1_TRxControl 0xc00 977 #define bZebra1_TRxGainSetting 0x07f 978 #define bZebra1_RxCorner 0xc00 979 #define bZebra1_TxChargePump 0x38 980 #define bZebra1_RxChargePump 0x7 981 #define bZebra1_ChannelNum 0xf80 982 #define bZebra1_TxLPFBW 0x400 983 #define bZebra1_RxLPFBW 0x600 986 #define bRTL8256RegModeCtrl1 0x100 // Useless 987 #define bRTL8256RegModeCtrl0 0x40 988 #define bRTL8256_TxLPFBW 0x18 989 #define bRTL8256_RxLPFBW 0x600 992 #define bRTL8258_TxLPFBW 0xc // Useless 993 #define bRTL8258_RxLPFBW 0xc00 994 #define bRTL8258_RSSILPFBW 0xc0 1001 //byte endable for sb_write 1002 #define bByte0 0x1 // Useless 1010 //for PutRegsetting & GetRegSetting BitMask 1011 #define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f 1012 #define bMaskByte1 0xff00 1013 #define bMaskByte2 0xff0000 1014 #define bMaskByte3 0xff000000 1015 #define bMaskHWord 0xffff0000 1016 #define bMaskLWord 0x0000ffff 1017 #define bMaskDWord 0xffffffff 1018 #define bMaskH4Bits 0xf0000000 1019 #define bMaskOFDM_D 0xffc00000 1020 #define bMaskCCK 0x3f3f3f3f 1021 #define bMask12Bits 0xfff 1023 //for PutRFRegsetting & GetRFRegSetting BitMask 1024 #if (RTL92SE_FPGA_VERIFY == 1) 1025 //#define bMask12Bits 0xfff // RF Reg mask bits 1026 //#define bMask20Bits 0xfff // RF Reg mask bits T65 RF 1027 #define bRFRegOffsetMask 0xfff 1029 //#define bMask12Bits 0xfffff // RF Reg mask bits 1030 //#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF 1031 #define bRFRegOffsetMask 0xfffff 1033 #define bEnable 0x1 // Useless 1034 #define bDisable 0x0 1036 #define LeftAntenna 0x0 // Useless 1037 #define RightAntenna 0x1 1039 #define tCheckTxStatus 500 //500ms // Useless 1040 #define tUpdateRxCounter 100 //100ms 1042 #define rateCCK 0 // Useless 1046 //define Register-End 1047 #define bPMAC_End 0x1ff // Useless 1048 #define bFPGAPHY0_End 0x8ff 1049 #define bFPGAPHY1_End 0x9ff 1050 #define bCCKPHY0_End 0xaff 1051 #define bOFDMPHY0_End 0xcff 1052 #define bOFDMPHY1_End 0xdff 1054 //define max debug item in each debug page 1055 //#define bMaxItem_FPGA_PHY0 0x9 1056 //#define bMaxItem_FPGA_PHY1 0x3 1057 //#define bMaxItem_PHY_11B 0x16 1058 //#define bMaxItem_OFDM_PHY0 0x29 1059 //#define bMaxItem_OFDM_PHY1 0x0 1061 #define bPMACControl 0x0 // Useless 1062 #define bWMACControl 0x1 1063 #define bWNICControl 0x2 1066 #define ANTENNA_A 0x1 // Useless 1067 #define ANTENNA_B 0x2 1068 #define ANTENNA_AB 0x3 // ANTENNA_A|ANTENNA_B 1070 #define ANTENNA_C 0x4 1071 #define ANTENNA_D 0x8 1074 #define RCR_AAP BIT(0) // accept all physical address 1075 #define RCR_APM BIT(1) // accept physical match 1076 #define RCR_AM BIT(2) // accept multicast 1077 #define RCR_AB BIT(3) // accept broadcast 1078 #define RCR_ACRC32 BIT(5) // accept error packet 1079 #define RCR_9356SEL BIT(6) 1080 #define RCR_AICV BIT(12) // Accept ICV error packet 1081 #define RCR_RXFTH0 (BIT(13)|BIT(14)|BIT(15)) // Rx FIFO threshold 1082 #define RCR_ADF BIT(18) // Accept Data(frame type) frame 1083 #define RCR_ACF BIT(19) // Accept control frame 1084 #define RCR_AMF BIT(20) // Accept management frame 1085 #define RCR_ADD3 BIT(21) 1086 #define RCR_APWRMGT BIT(22) // Accept power management packet 1087 #define RCR_CBSSID BIT(23) // Accept BSSID match packet 1088 #define RCR_ENMARP BIT(28) // enable mac auto reset phy 1089 #define RCR_EnCS1 BIT(29) // enable carrier sense method 1 1090 #define RCR_EnCS2 BIT(30) // enable carrier sense method 2 1091 #define RCR_OnlyErlPkt BIT(31) // Rx Early mode is performed for packet size greater than 1536 1093 /*--------------------------Define Parameters-------------------------------*/ 1096 #endif //__INC_HAL8192SPHYREG_H
projects / mirror_ubuntu-bionic-kernel.git / blob