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Merge tag 'nfc-next-4.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo...
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / realtek / rtlwifi / btcoexist / halbtc8192e2ant.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25 /**************************************************************
26 * Description:
27 *
28 * This file is for RTL8192E Co-exist mechanism
29 *
30 * History
31 * 2012/11/15 Cosa first check in.
32 *
33 **************************************************************/
34
35 /**************************************************************
36 * include files
37 **************************************************************/
38 #include "halbt_precomp.h"
39 /**************************************************************
40 * Global variables, these are static variables
41 **************************************************************/
42 static struct coex_dm_8192e_2ant glcoex_dm_8192e_2ant;
43 static struct coex_dm_8192e_2ant *coex_dm = &glcoex_dm_8192e_2ant;
44 static struct coex_sta_8192e_2ant glcoex_sta_8192e_2ant;
45 static struct coex_sta_8192e_2ant *coex_sta = &glcoex_sta_8192e_2ant;
46
47 static const char *const GLBtInfoSrc8192e2Ant[] = {
48 "BT Info[wifi fw]",
49 "BT Info[bt rsp]",
50 "BT Info[bt auto report]",
51 };
52
53 static u32 glcoex_ver_date_8192e_2ant = 20130902;
54 static u32 glcoex_ver_8192e_2ant = 0x34;
55
56 /**************************************************************
57 * local function proto type if needed
58 **************************************************************/
59 /**************************************************************
60 * local function start with halbtc8192e2ant_
61 **************************************************************/
62 static u8 halbtc8192e2ant_btrssi_state(u8 level_num, u8 rssi_thresh,
63 u8 rssi_thresh1)
64 {
65 int btrssi = 0;
66 u8 btrssi_state = coex_sta->pre_bt_rssi_state;
67
68 btrssi = coex_sta->bt_rssi;
69
70 if (level_num == 2) {
71 if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
72 (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
73 btc_alg_dbg(ALGO_BT_RSSI_STATE,
74 "BT Rssi pre state = LOW\n");
75 if (btrssi >= (rssi_thresh +
76 BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) {
77 btrssi_state = BTC_RSSI_STATE_HIGH;
78 btc_alg_dbg(ALGO_BT_RSSI_STATE,
79 "BT Rssi state switch to High\n");
80 } else {
81 btrssi_state = BTC_RSSI_STATE_STAY_LOW;
82 btc_alg_dbg(ALGO_BT_RSSI_STATE,
83 "BT Rssi state stay at Low\n");
84 }
85 } else {
86 btc_alg_dbg(ALGO_BT_RSSI_STATE,
87 "BT Rssi pre state = HIGH\n");
88 if (btrssi < rssi_thresh) {
89 btrssi_state = BTC_RSSI_STATE_LOW;
90 btc_alg_dbg(ALGO_BT_RSSI_STATE,
91 "BT Rssi state switch to Low\n");
92 } else {
93 btrssi_state = BTC_RSSI_STATE_STAY_HIGH;
94 btc_alg_dbg(ALGO_BT_RSSI_STATE,
95 "BT Rssi state stay at High\n");
96 }
97 }
98 } else if (level_num == 3) {
99 if (rssi_thresh > rssi_thresh1) {
100 btc_alg_dbg(ALGO_BT_RSSI_STATE,
101 "BT Rssi thresh error!!\n");
102 return coex_sta->pre_bt_rssi_state;
103 }
104
105 if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
106 (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
107 btc_alg_dbg(ALGO_BT_RSSI_STATE,
108 "BT Rssi pre state = LOW\n");
109 if (btrssi >= (rssi_thresh +
110 BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) {
111 btrssi_state = BTC_RSSI_STATE_MEDIUM;
112 btc_alg_dbg(ALGO_BT_RSSI_STATE,
113 "BT Rssi state switch to Medium\n");
114 } else {
115 btrssi_state = BTC_RSSI_STATE_STAY_LOW;
116 btc_alg_dbg(ALGO_BT_RSSI_STATE,
117 "BT Rssi state stay at Low\n");
118 }
119 } else if ((coex_sta->pre_bt_rssi_state ==
120 BTC_RSSI_STATE_MEDIUM) ||
121 (coex_sta->pre_bt_rssi_state ==
122 BTC_RSSI_STATE_STAY_MEDIUM)) {
123 btc_alg_dbg(ALGO_BT_RSSI_STATE,
124 "[BTCoex], BT Rssi pre state = MEDIUM\n");
125 if (btrssi >= (rssi_thresh1 +
126 BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) {
127 btrssi_state = BTC_RSSI_STATE_HIGH;
128 btc_alg_dbg(ALGO_BT_RSSI_STATE,
129 "BT Rssi state switch to High\n");
130 } else if (btrssi < rssi_thresh) {
131 btrssi_state = BTC_RSSI_STATE_LOW;
132 btc_alg_dbg(ALGO_BT_RSSI_STATE,
133 "BT Rssi state switch to Low\n");
134 } else {
135 btrssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
136 btc_alg_dbg(ALGO_BT_RSSI_STATE,
137 "BT Rssi state stay at Medium\n");
138 }
139 } else {
140 btc_alg_dbg(ALGO_BT_RSSI_STATE,
141 "BT Rssi pre state = HIGH\n");
142 if (btrssi < rssi_thresh1) {
143 btrssi_state = BTC_RSSI_STATE_MEDIUM;
144 btc_alg_dbg(ALGO_BT_RSSI_STATE,
145 "BT Rssi state switch to Medium\n");
146 } else {
147 btrssi_state = BTC_RSSI_STATE_STAY_HIGH;
148 btc_alg_dbg(ALGO_BT_RSSI_STATE,
149 "BT Rssi state stay at High\n");
150 }
151 }
152 }
153
154 coex_sta->pre_bt_rssi_state = btrssi_state;
155
156 return btrssi_state;
157 }
158
159 static u8 halbtc8192e2ant_wifirssi_state(struct btc_coexist *btcoexist,
160 u8 index, u8 level_num, u8 rssi_thresh,
161 u8 rssi_thresh1)
162 {
163 int wifirssi = 0;
164 u8 wifirssi_state = coex_sta->pre_wifi_rssi_state[index];
165
166 btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifirssi);
167
168 if (level_num == 2) {
169 if ((coex_sta->pre_wifi_rssi_state[index] ==
170 BTC_RSSI_STATE_LOW) ||
171 (coex_sta->pre_wifi_rssi_state[index] ==
172 BTC_RSSI_STATE_STAY_LOW)) {
173 if (wifirssi >= (rssi_thresh +
174 BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) {
175 wifirssi_state = BTC_RSSI_STATE_HIGH;
176 btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
177 "wifi RSSI state switch to High\n");
178 } else {
179 wifirssi_state = BTC_RSSI_STATE_STAY_LOW;
180 btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
181 "wifi RSSI state stay at Low\n");
182 }
183 } else {
184 if (wifirssi < rssi_thresh) {
185 wifirssi_state = BTC_RSSI_STATE_LOW;
186 btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
187 "wifi RSSI state switch to Low\n");
188 } else {
189 wifirssi_state = BTC_RSSI_STATE_STAY_HIGH;
190 btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
191 "wifi RSSI state stay at High\n");
192 }
193 }
194 } else if (level_num == 3) {
195 if (rssi_thresh > rssi_thresh1) {
196 btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
197 "wifi RSSI thresh error!!\n");
198 return coex_sta->pre_wifi_rssi_state[index];
199 }
200
201 if ((coex_sta->pre_wifi_rssi_state[index] ==
202 BTC_RSSI_STATE_LOW) ||
203 (coex_sta->pre_wifi_rssi_state[index] ==
204 BTC_RSSI_STATE_STAY_LOW)) {
205 if (wifirssi >= (rssi_thresh +
206 BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) {
207 wifirssi_state = BTC_RSSI_STATE_MEDIUM;
208 btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
209 "wifi RSSI state switch to Medium\n");
210 } else {
211 wifirssi_state = BTC_RSSI_STATE_STAY_LOW;
212 btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
213 "wifi RSSI state stay at Low\n");
214 }
215 } else if ((coex_sta->pre_wifi_rssi_state[index] ==
216 BTC_RSSI_STATE_MEDIUM) ||
217 (coex_sta->pre_wifi_rssi_state[index] ==
218 BTC_RSSI_STATE_STAY_MEDIUM)) {
219 if (wifirssi >= (rssi_thresh1 +
220 BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) {
221 wifirssi_state = BTC_RSSI_STATE_HIGH;
222 btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
223 "wifi RSSI state switch to High\n");
224 } else if (wifirssi < rssi_thresh) {
225 wifirssi_state = BTC_RSSI_STATE_LOW;
226 btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
227 "wifi RSSI state switch to Low\n");
228 } else {
229 wifirssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
230 btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
231 "wifi RSSI state stay at Medium\n");
232 }
233 } else {
234 if (wifirssi < rssi_thresh1) {
235 wifirssi_state = BTC_RSSI_STATE_MEDIUM;
236 btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
237 "wifi RSSI state switch to Medium\n");
238 } else {
239 wifirssi_state = BTC_RSSI_STATE_STAY_HIGH;
240 btc_alg_dbg(ALGO_WIFI_RSSI_STATE,
241 "wifi RSSI state stay at High\n");
242 }
243 }
244 }
245
246 coex_sta->pre_wifi_rssi_state[index] = wifirssi_state;
247
248 return wifirssi_state;
249 }
250
251 static void btc8192e2ant_monitor_bt_enable_dis(struct btc_coexist *btcoexist)
252 {
253 static bool pre_bt_disabled;
254 static u32 bt_disable_cnt;
255 bool bt_active = true, bt_disabled = false;
256
257 /* This function check if bt is disabled */
258
259 if (coex_sta->high_priority_tx == 0 &&
260 coex_sta->high_priority_rx == 0 &&
261 coex_sta->low_priority_tx == 0 &&
262 coex_sta->low_priority_rx == 0)
263 bt_active = false;
264
265 if (coex_sta->high_priority_tx == 0xffff &&
266 coex_sta->high_priority_rx == 0xffff &&
267 coex_sta->low_priority_tx == 0xffff &&
268 coex_sta->low_priority_rx == 0xffff)
269 bt_active = false;
270
271 if (bt_active) {
272 bt_disable_cnt = 0;
273 bt_disabled = false;
274 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
275 &bt_disabled);
276 btc_alg_dbg(ALGO_BT_MONITOR,
277 "[BTCoex], BT is enabled !!\n");
278 } else {
279 bt_disable_cnt++;
280 btc_alg_dbg(ALGO_BT_MONITOR,
281 "[BTCoex], bt all counters = 0, %d times!!\n",
282 bt_disable_cnt);
283 if (bt_disable_cnt >= 2) {
284 bt_disabled = true;
285 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
286 &bt_disabled);
287 btc_alg_dbg(ALGO_BT_MONITOR,
288 "[BTCoex], BT is disabled !!\n");
289 }
290 }
291 if (pre_bt_disabled != bt_disabled) {
292 btc_alg_dbg(ALGO_BT_MONITOR,
293 "[BTCoex], BT is from %s to %s!!\n",
294 (pre_bt_disabled ? "disabled" : "enabled"),
295 (bt_disabled ? "disabled" : "enabled"));
296 pre_bt_disabled = bt_disabled;
297 }
298 }
299
300 static u32 halbtc8192e2ant_decidera_mask(struct btc_coexist *btcoexist,
301 u8 sstype, u32 ra_masktype)
302 {
303 u32 disra_mask = 0x0;
304
305 switch (ra_masktype) {
306 case 0: /* normal mode */
307 if (sstype == 2)
308 disra_mask = 0x0; /* enable 2ss */
309 else
310 disra_mask = 0xfff00000;/* disable 2ss */
311 break;
312 case 1: /* disable cck 1/2 */
313 if (sstype == 2)
314 disra_mask = 0x00000003;/* enable 2ss */
315 else
316 disra_mask = 0xfff00003;/* disable 2ss */
317 break;
318 case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
319 if (sstype == 2)
320 disra_mask = 0x0001f1f7;/* enable 2ss */
321 else
322 disra_mask = 0xfff1f1f7;/* disable 2ss */
323 break;
324 default:
325 break;
326 }
327
328 return disra_mask;
329 }
330
331 static void halbtc8192e2ant_Updatera_mask(struct btc_coexist *btcoexist,
332 bool force_exec, u32 dis_ratemask)
333 {
334 coex_dm->curra_mask = dis_ratemask;
335
336 if (force_exec || (coex_dm->prera_mask != coex_dm->curra_mask))
337 btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_ra_mask,
338 &coex_dm->curra_mask);
339 coex_dm->prera_mask = coex_dm->curra_mask;
340 }
341
342 static void btc8192e2ant_autorate_fallback_retry(struct btc_coexist *btcoexist,
343 bool force_exec, u8 type)
344 {
345 bool wifi_under_bmode = false;
346
347 coex_dm->cur_arfrtype = type;
348
349 if (force_exec || (coex_dm->pre_arfrtype != coex_dm->cur_arfrtype)) {
350 switch (coex_dm->cur_arfrtype) {
351 case 0: /* normal mode */
352 btcoexist->btc_write_4byte(btcoexist, 0x430,
353 coex_dm->backup_arfr_cnt1);
354 btcoexist->btc_write_4byte(btcoexist, 0x434,
355 coex_dm->backup_arfr_cnt2);
356 break;
357 case 1:
358 btcoexist->btc_get(btcoexist,
359 BTC_GET_BL_WIFI_UNDER_B_MODE,
360 &wifi_under_bmode);
361 if (wifi_under_bmode) {
362 btcoexist->btc_write_4byte(btcoexist, 0x430,
363 0x0);
364 btcoexist->btc_write_4byte(btcoexist, 0x434,
365 0x01010101);
366 } else {
367 btcoexist->btc_write_4byte(btcoexist, 0x430,
368 0x0);
369 btcoexist->btc_write_4byte(btcoexist, 0x434,
370 0x04030201);
371 }
372 break;
373 default:
374 break;
375 }
376 }
377
378 coex_dm->pre_arfrtype = coex_dm->cur_arfrtype;
379 }
380
381 static void halbtc8192e2ant_retrylimit(struct btc_coexist *btcoexist,
382 bool force_exec, u8 type)
383 {
384 coex_dm->cur_retrylimit_type = type;
385
386 if (force_exec || (coex_dm->pre_retrylimit_type !=
387 coex_dm->cur_retrylimit_type)) {
388 switch (coex_dm->cur_retrylimit_type) {
389 case 0: /* normal mode */
390 btcoexist->btc_write_2byte(btcoexist, 0x42a,
391 coex_dm->backup_retrylimit);
392 break;
393 case 1: /* retry limit = 8 */
394 btcoexist->btc_write_2byte(btcoexist, 0x42a,
395 0x0808);
396 break;
397 default:
398 break;
399 }
400 }
401
402 coex_dm->pre_retrylimit_type = coex_dm->cur_retrylimit_type;
403 }
404
405 static void halbtc8192e2ant_ampdu_maxtime(struct btc_coexist *btcoexist,
406 bool force_exec, u8 type)
407 {
408 coex_dm->cur_ampdutime_type = type;
409
410 if (force_exec || (coex_dm->pre_ampdutime_type !=
411 coex_dm->cur_ampdutime_type)) {
412 switch (coex_dm->cur_ampdutime_type) {
413 case 0: /* normal mode */
414 btcoexist->btc_write_1byte(btcoexist, 0x456,
415 coex_dm->backup_ampdu_maxtime);
416 break;
417 case 1: /* AMPDU timw = 0x38 * 32us */
418 btcoexist->btc_write_1byte(btcoexist, 0x456, 0x38);
419 break;
420 default:
421 break;
422 }
423 }
424
425 coex_dm->pre_ampdutime_type = coex_dm->cur_ampdutime_type;
426 }
427
428 static void halbtc8192e2ant_limited_tx(struct btc_coexist *btcoexist,
429 bool force_exec, u8 ra_masktype,
430 u8 arfr_type, u8 retrylimit_type,
431 u8 ampdutime_type)
432 {
433 u32 disra_mask = 0x0;
434
435 coex_dm->curra_masktype = ra_masktype;
436 disra_mask = halbtc8192e2ant_decidera_mask(btcoexist,
437 coex_dm->cur_sstype,
438 ra_masktype);
439 halbtc8192e2ant_Updatera_mask(btcoexist, force_exec, disra_mask);
440 btc8192e2ant_autorate_fallback_retry(btcoexist, force_exec, arfr_type);
441 halbtc8192e2ant_retrylimit(btcoexist, force_exec, retrylimit_type);
442 halbtc8192e2ant_ampdu_maxtime(btcoexist, force_exec, ampdutime_type);
443 }
444
445 static void halbtc8192e2ant_limited_rx(struct btc_coexist *btcoexist,
446 bool force_exec, bool rej_ap_agg_pkt,
447 bool bt_ctrl_agg_buf_size,
448 u8 agg_buf_size)
449 {
450 bool reject_rx_agg = rej_ap_agg_pkt;
451 bool bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
452 u8 rx_agg_size = agg_buf_size;
453
454 /*********************************************
455 * Rx Aggregation related setting
456 *********************************************/
457 btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
458 &reject_rx_agg);
459 /* decide BT control aggregation buf size or not */
460 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
461 &bt_ctrl_rx_agg_size);
462 /* aggregation buf size, only work
463 * when BT control Rx aggregation size.
464 */
465 btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
466 /* real update aggregation setting */
467 btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
468 }
469
470 static void halbtc8192e2ant_monitor_bt_ctr(struct btc_coexist *btcoexist)
471 {
472 u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
473 u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
474
475 reg_hp_txrx = 0x770;
476 reg_lp_txrx = 0x774;
477
478 u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
479 reg_hp_tx = u32tmp & MASKLWORD;
480 reg_hp_rx = (u32tmp & MASKHWORD)>>16;
481
482 u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
483 reg_lp_tx = u32tmp & MASKLWORD;
484 reg_lp_rx = (u32tmp & MASKHWORD)>>16;
485
486 coex_sta->high_priority_tx = reg_hp_tx;
487 coex_sta->high_priority_rx = reg_hp_rx;
488 coex_sta->low_priority_tx = reg_lp_tx;
489 coex_sta->low_priority_rx = reg_lp_rx;
490
491 btc_alg_dbg(ALGO_BT_MONITOR,
492 "[BTCoex] High Priority Tx/Rx (reg 0x%x) = 0x%x(%d)/0x%x(%d)\n",
493 reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx);
494 btc_alg_dbg(ALGO_BT_MONITOR,
495 "[BTCoex] Low Priority Tx/Rx (reg 0x%x) = 0x%x(%d)/0x%x(%d)\n",
496 reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx);
497
498 /* reset counter */
499 btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
500 }
501
502 static void halbtc8192e2ant_querybt_info(struct btc_coexist *btcoexist)
503 {
504 u8 h2c_parameter[1] = {0};
505
506 coex_sta->c2h_bt_info_req_sent = true;
507
508 h2c_parameter[0] |= BIT0; /* trigger */
509
510 btc_alg_dbg(ALGO_TRACE_FW_EXEC,
511 "[BTCoex], Query Bt Info, FW write 0x61 = 0x%x\n",
512 h2c_parameter[0]);
513
514 btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
515 }
516
517 static void halbtc8192e2ant_update_btlink_info(struct btc_coexist *btcoexist)
518 {
519 struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
520 bool bt_hson = false;
521
522 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hson);
523
524 bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
525 bt_link_info->sco_exist = coex_sta->sco_exist;
526 bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
527 bt_link_info->pan_exist = coex_sta->pan_exist;
528 bt_link_info->hid_exist = coex_sta->hid_exist;
529
530 /* work around for HS mode. */
531 if (bt_hson) {
532 bt_link_info->pan_exist = true;
533 bt_link_info->bt_link_exist = true;
534 }
535
536 /* check if Sco only */
537 if (bt_link_info->sco_exist &&
538 !bt_link_info->a2dp_exist &&
539 !bt_link_info->pan_exist &&
540 !bt_link_info->hid_exist)
541 bt_link_info->sco_only = true;
542 else
543 bt_link_info->sco_only = false;
544
545 /* check if A2dp only */
546 if (!bt_link_info->sco_exist &&
547 bt_link_info->a2dp_exist &&
548 !bt_link_info->pan_exist &&
549 !bt_link_info->hid_exist)
550 bt_link_info->a2dp_only = true;
551 else
552 bt_link_info->a2dp_only = false;
553
554 /* check if Pan only */
555 if (!bt_link_info->sco_exist &&
556 !bt_link_info->a2dp_exist &&
557 bt_link_info->pan_exist &&
558 !bt_link_info->hid_exist)
559 bt_link_info->pan_only = true;
560 else
561 bt_link_info->pan_only = false;
562
563 /* check if Hid only */
564 if (!bt_link_info->sco_exist &&
565 !bt_link_info->a2dp_exist &&
566 !bt_link_info->pan_exist &&
567 bt_link_info->hid_exist)
568 bt_link_info->hid_only = true;
569 else
570 bt_link_info->hid_only = false;
571 }
572
573 static u8 halbtc8192e2ant_action_algorithm(struct btc_coexist *btcoexist)
574 {
575 struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
576 struct btc_stack_info *stack_info = &btcoexist->stack_info;
577 bool bt_hson = false;
578 u8 algorithm = BT_8192E_2ANT_COEX_ALGO_UNDEFINED;
579 u8 numdiffprofile = 0;
580
581 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hson);
582
583 if (!bt_link_info->bt_link_exist) {
584 btc_alg_dbg(ALGO_TRACE,
585 "No BT link exists!!!\n");
586 return algorithm;
587 }
588
589 if (bt_link_info->sco_exist)
590 numdiffprofile++;
591 if (bt_link_info->hid_exist)
592 numdiffprofile++;
593 if (bt_link_info->pan_exist)
594 numdiffprofile++;
595 if (bt_link_info->a2dp_exist)
596 numdiffprofile++;
597
598 if (numdiffprofile == 1) {
599 if (bt_link_info->sco_exist) {
600 btc_alg_dbg(ALGO_TRACE,
601 "SCO only\n");
602 algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
603 } else {
604 if (bt_link_info->hid_exist) {
605 btc_alg_dbg(ALGO_TRACE,
606 "HID only\n");
607 algorithm = BT_8192E_2ANT_COEX_ALGO_HID;
608 } else if (bt_link_info->a2dp_exist) {
609 btc_alg_dbg(ALGO_TRACE,
610 "A2DP only\n");
611 algorithm = BT_8192E_2ANT_COEX_ALGO_A2DP;
612 } else if (bt_link_info->pan_exist) {
613 if (bt_hson) {
614 btc_alg_dbg(ALGO_TRACE,
615 "PAN(HS) only\n");
616 algorithm =
617 BT_8192E_2ANT_COEX_ALGO_PANHS;
618 } else {
619 btc_alg_dbg(ALGO_TRACE,
620 "PAN(EDR) only\n");
621 algorithm =
622 BT_8192E_2ANT_COEX_ALGO_PANEDR;
623 }
624 }
625 }
626 } else if (numdiffprofile == 2) {
627 if (bt_link_info->sco_exist) {
628 if (bt_link_info->hid_exist) {
629 btc_alg_dbg(ALGO_TRACE,
630 "SCO + HID\n");
631 algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
632 } else if (bt_link_info->a2dp_exist) {
633 btc_alg_dbg(ALGO_TRACE,
634 "SCO + A2DP ==> SCO\n");
635 algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
636 } else if (bt_link_info->pan_exist) {
637 if (bt_hson) {
638 btc_alg_dbg(ALGO_TRACE,
639 "SCO + PAN(HS)\n");
640 algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
641 } else {
642 btc_alg_dbg(ALGO_TRACE,
643 "SCO + PAN(EDR)\n");
644 algorithm =
645 BT_8192E_2ANT_COEX_ALGO_SCO_PAN;
646 }
647 }
648 } else {
649 if (bt_link_info->hid_exist &&
650 bt_link_info->a2dp_exist) {
651 if (stack_info->num_of_hid >= 2) {
652 btc_alg_dbg(ALGO_TRACE,
653 "HID*2 + A2DP\n");
654 algorithm =
655 BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
656 } else {
657 btc_alg_dbg(ALGO_TRACE,
658 "HID + A2DP\n");
659 algorithm =
660 BT_8192E_2ANT_COEX_ALGO_HID_A2DP;
661 }
662 } else if (bt_link_info->hid_exist &&
663 bt_link_info->pan_exist) {
664 if (bt_hson) {
665 btc_alg_dbg(ALGO_TRACE,
666 "HID + PAN(HS)\n");
667 algorithm = BT_8192E_2ANT_COEX_ALGO_HID;
668 } else {
669 btc_alg_dbg(ALGO_TRACE,
670 "HID + PAN(EDR)\n");
671 algorithm =
672 BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
673 }
674 } else if (bt_link_info->pan_exist &&
675 bt_link_info->a2dp_exist) {
676 if (bt_hson) {
677 btc_alg_dbg(ALGO_TRACE,
678 "A2DP + PAN(HS)\n");
679 algorithm =
680 BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS;
681 } else {
682 btc_alg_dbg(ALGO_TRACE,
683 "A2DP + PAN(EDR)\n");
684 algorithm =
685 BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP;
686 }
687 }
688 }
689 } else if (numdiffprofile == 3) {
690 if (bt_link_info->sco_exist) {
691 if (bt_link_info->hid_exist &&
692 bt_link_info->a2dp_exist) {
693 btc_alg_dbg(ALGO_TRACE,
694 "SCO + HID + A2DP ==> HID\n");
695 algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
696 } else if (bt_link_info->hid_exist &&
697 bt_link_info->pan_exist) {
698 if (bt_hson) {
699 btc_alg_dbg(ALGO_TRACE,
700 "SCO + HID + PAN(HS)\n");
701 algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
702 } else {
703 btc_alg_dbg(ALGO_TRACE,
704 "SCO + HID + PAN(EDR)\n");
705 algorithm =
706 BT_8192E_2ANT_COEX_ALGO_SCO_PAN;
707 }
708 } else if (bt_link_info->pan_exist &&
709 bt_link_info->a2dp_exist) {
710 if (bt_hson) {
711 btc_alg_dbg(ALGO_TRACE,
712 "SCO + A2DP + PAN(HS)\n");
713 algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
714 } else {
715 btc_alg_dbg(ALGO_TRACE,
716 "SCO + A2DP + PAN(EDR)\n");
717 algorithm =
718 BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
719 }
720 }
721 } else {
722 if (bt_link_info->hid_exist &&
723 bt_link_info->pan_exist &&
724 bt_link_info->a2dp_exist) {
725 if (bt_hson) {
726 btc_alg_dbg(ALGO_TRACE,
727 "HID + A2DP + PAN(HS)\n");
728 algorithm =
729 BT_8192E_2ANT_COEX_ALGO_HID_A2DP;
730 } else {
731 btc_alg_dbg(ALGO_TRACE,
732 "HID + A2DP + PAN(EDR)\n");
733 algorithm =
734 BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
735 }
736 }
737 }
738 } else if (numdiffprofile >= 3) {
739 if (bt_link_info->sco_exist) {
740 if (bt_link_info->hid_exist &&
741 bt_link_info->pan_exist &&
742 bt_link_info->a2dp_exist) {
743 if (bt_hson) {
744 btc_alg_dbg(ALGO_TRACE,
745 "ErrorSCO+HID+A2DP+PAN(HS)\n");
746
747 } else {
748 btc_alg_dbg(ALGO_TRACE,
749 "SCO+HID+A2DP+PAN(EDR)\n");
750 algorithm =
751 BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
752 }
753 }
754 }
755 }
756
757 return algorithm;
758 }
759
760 static void halbtc8192e2ant_setfw_dac_swinglevel(struct btc_coexist *btcoexist,
761 u8 dac_swinglvl)
762 {
763 u8 h2c_parameter[1] = {0};
764
765 /* There are several type of dacswing
766 * 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6
767 */
768 h2c_parameter[0] = dac_swinglvl;
769
770 btc_alg_dbg(ALGO_TRACE_FW_EXEC,
771 "[BTCoex], Set Dac Swing Level = 0x%x\n", dac_swinglvl);
772 btc_alg_dbg(ALGO_TRACE_FW_EXEC,
773 "[BTCoex], FW write 0x64 = 0x%x\n", h2c_parameter[0]);
774
775 btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter);
776 }
777
778 static void halbtc8192e2ant_set_fwdec_btpwr(struct btc_coexist *btcoexist,
779 u8 dec_btpwr_lvl)
780 {
781 u8 h2c_parameter[1] = {0};
782
783 h2c_parameter[0] = dec_btpwr_lvl;
784
785 btc_alg_dbg(ALGO_TRACE_FW_EXEC,
786 "[BTCoex] decrease Bt Power level = %d, FW write 0x62 = 0x%x\n",
787 dec_btpwr_lvl, h2c_parameter[0]);
788
789 btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter);
790 }
791
792 static void halbtc8192e2ant_dec_btpwr(struct btc_coexist *btcoexist,
793 bool force_exec, u8 dec_btpwr_lvl)
794 {
795 btc_alg_dbg(ALGO_TRACE_FW,
796 "[BTCoex], %s Dec BT power level = %d\n",
797 (force_exec ? "force to" : ""), dec_btpwr_lvl);
798 coex_dm->cur_dec_bt_pwr = dec_btpwr_lvl;
799
800 if (!force_exec) {
801 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
802 "[BTCoex], preBtDecPwrLvl=%d, curBtDecPwrLvl=%d\n",
803 coex_dm->pre_dec_bt_pwr, coex_dm->cur_dec_bt_pwr);
804 }
805 halbtc8192e2ant_set_fwdec_btpwr(btcoexist, coex_dm->cur_dec_bt_pwr);
806
807 coex_dm->pre_dec_bt_pwr = coex_dm->cur_dec_bt_pwr;
808 }
809
810 static void halbtc8192e2ant_set_bt_autoreport(struct btc_coexist *btcoexist,
811 bool enable_autoreport)
812 {
813 u8 h2c_parameter[1] = {0};
814
815 h2c_parameter[0] = 0;
816
817 if (enable_autoreport)
818 h2c_parameter[0] |= BIT0;
819
820 btc_alg_dbg(ALGO_TRACE_FW_EXEC,
821 "[BTCoex], BT FW auto report : %s, FW write 0x68 = 0x%x\n",
822 (enable_autoreport ? "Enabled!!" : "Disabled!!"),
823 h2c_parameter[0]);
824
825 btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
826 }
827
828 static void halbtc8192e2ant_bt_autoreport(struct btc_coexist *btcoexist,
829 bool force_exec,
830 bool enable_autoreport)
831 {
832 btc_alg_dbg(ALGO_TRACE_FW,
833 "[BTCoex], %s BT Auto report = %s\n",
834 (force_exec ? "force to" : ""),
835 ((enable_autoreport) ? "Enabled" : "Disabled"));
836 coex_dm->cur_bt_auto_report = enable_autoreport;
837
838 if (!force_exec) {
839 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
840 "[BTCoex] bPreBtAutoReport=%d, bCurBtAutoReport=%d\n",
841 coex_dm->pre_bt_auto_report,
842 coex_dm->cur_bt_auto_report);
843
844 if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
845 return;
846 }
847 halbtc8192e2ant_set_bt_autoreport(btcoexist,
848 coex_dm->cur_bt_auto_report);
849
850 coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
851 }
852
853 static void halbtc8192e2ant_fw_dac_swinglvl(struct btc_coexist *btcoexist,
854 bool force_exec, u8 fw_dac_swinglvl)
855 {
856 btc_alg_dbg(ALGO_TRACE_FW,
857 "[BTCoex], %s set FW Dac Swing level = %d\n",
858 (force_exec ? "force to" : ""), fw_dac_swinglvl);
859 coex_dm->cur_fw_dac_swing_lvl = fw_dac_swinglvl;
860
861 if (!force_exec) {
862 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
863 "[BTCoex] preFwDacSwingLvl=%d, curFwDacSwingLvl=%d\n",
864 coex_dm->pre_fw_dac_swing_lvl,
865 coex_dm->cur_fw_dac_swing_lvl);
866
867 if (coex_dm->pre_fw_dac_swing_lvl ==
868 coex_dm->cur_fw_dac_swing_lvl)
869 return;
870 }
871
872 halbtc8192e2ant_setfw_dac_swinglevel(btcoexist,
873 coex_dm->cur_fw_dac_swing_lvl);
874
875 coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
876 }
877
878 static void btc8192e2ant_set_sw_rf_rx_lpf_corner(struct btc_coexist *btcoexist,
879 bool rx_rf_shrink_on)
880 {
881 if (rx_rf_shrink_on) {
882 /* Shrink RF Rx LPF corner */
883 btc_alg_dbg(ALGO_TRACE_SW_EXEC,
884 "[BTCoex], Shrink RF Rx LPF corner!!\n");
885 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
886 0xfffff, 0xffffc);
887 } else {
888 /* Resume RF Rx LPF corner
889 * After initialized, we can use coex_dm->btRf0x1eBackup
890 */
891 if (btcoexist->initilized) {
892 btc_alg_dbg(ALGO_TRACE_SW_EXEC,
893 "[BTCoex], Resume RF Rx LPF corner!!\n");
894 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
895 0xfffff,
896 coex_dm->bt_rf0x1e_backup);
897 }
898 }
899 }
900
901 static void halbtc8192e2ant_rf_shrink(struct btc_coexist *btcoexist,
902 bool force_exec, bool rx_rf_shrink_on)
903 {
904 btc_alg_dbg(ALGO_TRACE_SW,
905 "[BTCoex], %s turn Rx RF Shrink = %s\n",
906 (force_exec ? "force to" : ""),
907 ((rx_rf_shrink_on) ? "ON" : "OFF"));
908 coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on;
909
910 if (!force_exec) {
911 btc_alg_dbg(ALGO_TRACE_SW_DETAIL,
912 "[BTCoex]bPreRfRxLpfShrink=%d,bCurRfRxLpfShrink=%d\n",
913 coex_dm->pre_rf_rx_lpf_shrink,
914 coex_dm->cur_rf_rx_lpf_shrink);
915
916 if (coex_dm->pre_rf_rx_lpf_shrink ==
917 coex_dm->cur_rf_rx_lpf_shrink)
918 return;
919 }
920 btc8192e2ant_set_sw_rf_rx_lpf_corner(btcoexist,
921 coex_dm->cur_rf_rx_lpf_shrink);
922
923 coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink;
924 }
925
926 static void halbtc8192e2ant_set_dac_swingreg(struct btc_coexist *btcoexist,
927 u32 level)
928 {
929 u8 val = (u8)level;
930
931 btc_alg_dbg(ALGO_TRACE_SW_EXEC,
932 "[BTCoex], Write SwDacSwing = 0x%x\n", level);
933 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x883, 0x3e, val);
934 }
935
936 static void btc8192e2ant_setsw_full_swing(struct btc_coexist *btcoexist,
937 bool sw_dac_swingon,
938 u32 sw_dac_swinglvl)
939 {
940 if (sw_dac_swingon)
941 halbtc8192e2ant_set_dac_swingreg(btcoexist, sw_dac_swinglvl);
942 else
943 halbtc8192e2ant_set_dac_swingreg(btcoexist, 0x18);
944 }
945
946 static void halbtc8192e2ant_DacSwing(struct btc_coexist *btcoexist,
947 bool force_exec, bool dac_swingon,
948 u32 dac_swinglvl)
949 {
950 btc_alg_dbg(ALGO_TRACE_SW,
951 "[BTCoex], %s turn DacSwing=%s, dac_swinglvl = 0x%x\n",
952 (force_exec ? "force to" : ""),
953 ((dac_swingon) ? "ON" : "OFF"), dac_swinglvl);
954 coex_dm->cur_dac_swing_on = dac_swingon;
955 coex_dm->cur_dac_swing_lvl = dac_swinglvl;
956
957 if (!force_exec) {
958 btc_alg_dbg(ALGO_TRACE_SW_DETAIL,
959 "[BTCoex], bPreDacSwingOn=%d, preDacSwingLvl = 0x%x, ",
960 coex_dm->pre_dac_swing_on,
961 coex_dm->pre_dac_swing_lvl);
962 btc_alg_dbg(ALGO_TRACE_SW_DETAIL,
963 "bCurDacSwingOn=%d, curDacSwingLvl = 0x%x\n",
964 coex_dm->cur_dac_swing_on,
965 coex_dm->cur_dac_swing_lvl);
966
967 if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) &&
968 (coex_dm->pre_dac_swing_lvl == coex_dm->cur_dac_swing_lvl))
969 return;
970 }
971 mdelay(30);
972 btc8192e2ant_setsw_full_swing(btcoexist, dac_swingon, dac_swinglvl);
973
974 coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on;
975 coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl;
976 }
977
978 static void halbtc8192e2ant_set_agc_table(struct btc_coexist *btcoexist,
979 bool agc_table_en)
980 {
981 /* BB AGC Gain Table */
982 if (agc_table_en) {
983 btc_alg_dbg(ALGO_TRACE_SW_EXEC,
984 "[BTCoex], BB Agc Table On!\n");
985 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x0a1A0001);
986 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x091B0001);
987 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x081C0001);
988 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x071D0001);
989 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x061E0001);
990 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x051F0001);
991 } else {
992 btc_alg_dbg(ALGO_TRACE_SW_EXEC,
993 "[BTCoex], BB Agc Table Off!\n");
994 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xaa1A0001);
995 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa91B0001);
996 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa81C0001);
997 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa71D0001);
998 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa61E0001);
999 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa51F0001);
1000 }
1001 }
1002
1003 static void halbtc8192e2ant_AgcTable(struct btc_coexist *btcoexist,
1004 bool force_exec, bool agc_table_en)
1005 {
1006 btc_alg_dbg(ALGO_TRACE_SW,
1007 "[BTCoex], %s %s Agc Table\n",
1008 (force_exec ? "force to" : ""),
1009 ((agc_table_en) ? "Enable" : "Disable"));
1010 coex_dm->cur_agc_table_en = agc_table_en;
1011
1012 if (!force_exec) {
1013 btc_alg_dbg(ALGO_TRACE_SW_DETAIL,
1014 "[BTCoex], bPreAgcTableEn=%d, bCurAgcTableEn=%d\n",
1015 coex_dm->pre_agc_table_en,
1016 coex_dm->cur_agc_table_en);
1017
1018 if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en)
1019 return;
1020 }
1021 halbtc8192e2ant_set_agc_table(btcoexist, agc_table_en);
1022
1023 coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en;
1024 }
1025
1026 static void halbtc8192e2ant_set_coex_table(struct btc_coexist *btcoexist,
1027 u32 val0x6c0, u32 val0x6c4,
1028 u32 val0x6c8, u8 val0x6cc)
1029 {
1030 btc_alg_dbg(ALGO_TRACE_SW_EXEC,
1031 "[BTCoex], set coex table, set 0x6c0 = 0x%x\n", val0x6c0);
1032 btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
1033
1034 btc_alg_dbg(ALGO_TRACE_SW_EXEC,
1035 "[BTCoex], set coex table, set 0x6c4 = 0x%x\n", val0x6c4);
1036 btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
1037
1038 btc_alg_dbg(ALGO_TRACE_SW_EXEC,
1039 "[BTCoex], set coex table, set 0x6c8 = 0x%x\n", val0x6c8);
1040 btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
1041
1042 btc_alg_dbg(ALGO_TRACE_SW_EXEC,
1043 "[BTCoex], set coex table, set 0x6cc = 0x%x\n", val0x6cc);
1044 btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
1045 }
1046
1047 static void halbtc8192e2ant_coex_table(struct btc_coexist *btcoexist,
1048 bool force_exec,
1049 u32 val0x6c0, u32 val0x6c4,
1050 u32 val0x6c8, u8 val0x6cc)
1051 {
1052 btc_alg_dbg(ALGO_TRACE_SW,
1053 "[BTCoex], %s write Coex Table 0x6c0 = 0x%x, ",
1054 (force_exec ? "force to" : ""), val0x6c0);
1055 btc_alg_dbg(ALGO_TRACE_SW,
1056 "0x6c4 = 0x%x, 0x6c8 = 0x%x, 0x6cc = 0x%x\n",
1057 val0x6c4, val0x6c8, val0x6cc);
1058 coex_dm->cur_val0x6c0 = val0x6c0;
1059 coex_dm->cur_val0x6c4 = val0x6c4;
1060 coex_dm->cur_val0x6c8 = val0x6c8;
1061 coex_dm->cur_val0x6cc = val0x6cc;
1062
1063 if (!force_exec) {
1064 btc_alg_dbg(ALGO_TRACE_SW_DETAIL,
1065 "[BTCoex], preVal0x6c0 = 0x%x, preVal0x6c4 = 0x%x, ",
1066 coex_dm->pre_val0x6c0, coex_dm->pre_val0x6c4);
1067 btc_alg_dbg(ALGO_TRACE_SW_DETAIL,
1068 "preVal0x6c8 = 0x%x, preVal0x6cc = 0x%x !!\n",
1069 coex_dm->pre_val0x6c8, coex_dm->pre_val0x6cc);
1070 btc_alg_dbg(ALGO_TRACE_SW_DETAIL,
1071 "[BTCoex], curVal0x6c0 = 0x%x, curVal0x6c4 = 0x%x\n",
1072 coex_dm->cur_val0x6c0, coex_dm->cur_val0x6c4);
1073 btc_alg_dbg(ALGO_TRACE_SW_DETAIL,
1074 "curVal0x6c8 = 0x%x, curVal0x6cc = 0x%x !!\n",
1075 coex_dm->cur_val0x6c8, coex_dm->cur_val0x6cc);
1076
1077 if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
1078 (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
1079 (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
1080 (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
1081 return;
1082 }
1083 halbtc8192e2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4,
1084 val0x6c8, val0x6cc);
1085
1086 coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
1087 coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
1088 coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
1089 coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
1090 }
1091
1092 static void btc8192e2ant_coex_tbl_w_type(struct btc_coexist *btcoexist,
1093 bool force_exec, u8 type)
1094 {
1095 switch (type) {
1096 case 0:
1097 halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x55555555,
1098 0x5a5a5a5a, 0xffffff, 0x3);
1099 break;
1100 case 1:
1101 halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x5a5a5a5a,
1102 0x5a5a5a5a, 0xffffff, 0x3);
1103 break;
1104 case 2:
1105 halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x55555555,
1106 0x5ffb5ffb, 0xffffff, 0x3);
1107 break;
1108 case 3:
1109 halbtc8192e2ant_coex_table(btcoexist, force_exec, 0xdfffdfff,
1110 0x5fdb5fdb, 0xffffff, 0x3);
1111 break;
1112 case 4:
1113 halbtc8192e2ant_coex_table(btcoexist, force_exec, 0xdfffdfff,
1114 0x5ffb5ffb, 0xffffff, 0x3);
1115 break;
1116 default:
1117 break;
1118 }
1119 }
1120
1121 static void halbtc8192e2ant_set_fw_ignore_wlanact(struct btc_coexist *btcoexist,
1122 bool enable)
1123 {
1124 u8 h2c_parameter[1] = {0};
1125
1126 if (enable)
1127 h2c_parameter[0] |= BIT0; /* function enable */
1128
1129 btc_alg_dbg(ALGO_TRACE_FW_EXEC,
1130 "[BTCoex]set FW for BT Ignore Wlan_Act, FW write 0x63 = 0x%x\n",
1131 h2c_parameter[0]);
1132
1133 btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
1134 }
1135
1136 static void halbtc8192e2ant_IgnoreWlanAct(struct btc_coexist *btcoexist,
1137 bool force_exec, bool enable)
1138 {
1139 btc_alg_dbg(ALGO_TRACE_FW,
1140 "[BTCoex], %s turn Ignore WlanAct %s\n",
1141 (force_exec ? "force to" : ""), (enable ? "ON" : "OFF"));
1142 coex_dm->cur_ignore_wlan_act = enable;
1143
1144 if (!force_exec) {
1145 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
1146 "[BTCoex], bPreIgnoreWlanAct = %d ",
1147 coex_dm->pre_ignore_wlan_act);
1148 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
1149 "bCurIgnoreWlanAct = %d!!\n",
1150 coex_dm->cur_ignore_wlan_act);
1151
1152 if (coex_dm->pre_ignore_wlan_act ==
1153 coex_dm->cur_ignore_wlan_act)
1154 return;
1155 }
1156 halbtc8192e2ant_set_fw_ignore_wlanact(btcoexist, enable);
1157
1158 coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
1159 }
1160
1161 static void halbtc8192e2ant_SetFwPstdma(struct btc_coexist *btcoexist, u8 byte1,
1162 u8 byte2, u8 byte3, u8 byte4, u8 byte5)
1163 {
1164 u8 h2c_parameter[5] = {0};
1165
1166 h2c_parameter[0] = byte1;
1167 h2c_parameter[1] = byte2;
1168 h2c_parameter[2] = byte3;
1169 h2c_parameter[3] = byte4;
1170 h2c_parameter[4] = byte5;
1171
1172 coex_dm->ps_tdma_para[0] = byte1;
1173 coex_dm->ps_tdma_para[1] = byte2;
1174 coex_dm->ps_tdma_para[2] = byte3;
1175 coex_dm->ps_tdma_para[3] = byte4;
1176 coex_dm->ps_tdma_para[4] = byte5;
1177
1178 btc_alg_dbg(ALGO_TRACE_FW_EXEC,
1179 "[BTCoex], FW write 0x60(5bytes) = 0x%x%08x\n",
1180 h2c_parameter[0],
1181 h2c_parameter[1] << 24 | h2c_parameter[2] << 16 |
1182 h2c_parameter[3] << 8 | h2c_parameter[4]);
1183
1184 btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
1185 }
1186
1187 static void btc8192e2ant_sw_mec1(struct btc_coexist *btcoexist,
1188 bool shrink_rx_lpf, bool low_penalty_ra,
1189 bool limited_dig, bool btlan_constrain)
1190 {
1191 halbtc8192e2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf);
1192 }
1193
1194 static void btc8192e2ant_sw_mec2(struct btc_coexist *btcoexist,
1195 bool agc_table_shift, bool adc_backoff,
1196 bool sw_dac_swing, u32 dac_swinglvl)
1197 {
1198 halbtc8192e2ant_AgcTable(btcoexist, NORMAL_EXEC, agc_table_shift);
1199 halbtc8192e2ant_DacSwing(btcoexist, NORMAL_EXEC, sw_dac_swing,
1200 dac_swinglvl);
1201 }
1202
1203 static void halbtc8192e2ant_ps_tdma(struct btc_coexist *btcoexist,
1204 bool force_exec, bool turn_on, u8 type)
1205 {
1206 btc_alg_dbg(ALGO_TRACE_FW,
1207 "[BTCoex], %s turn %s PS TDMA, type=%d\n",
1208 (force_exec ? "force to" : ""),
1209 (turn_on ? "ON" : "OFF"), type);
1210 coex_dm->cur_ps_tdma_on = turn_on;
1211 coex_dm->cur_ps_tdma = type;
1212
1213 if (!force_exec) {
1214 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
1215 "[BTCoex], bPrePsTdmaOn = %d, bCurPsTdmaOn = %d!!\n",
1216 coex_dm->pre_ps_tdma_on, coex_dm->cur_ps_tdma_on);
1217 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
1218 "[BTCoex], prePsTdma = %d, curPsTdma = %d!!\n",
1219 coex_dm->pre_ps_tdma, coex_dm->cur_ps_tdma);
1220
1221 if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
1222 (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
1223 return;
1224 }
1225 if (turn_on) {
1226 switch (type) {
1227 case 1:
1228 default:
1229 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1a,
1230 0x1a, 0xe1, 0x90);
1231 break;
1232 case 2:
1233 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x12,
1234 0x12, 0xe1, 0x90);
1235 break;
1236 case 3:
1237 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1c,
1238 0x3, 0xf1, 0x90);
1239 break;
1240 case 4:
1241 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x10,
1242 0x3, 0xf1, 0x90);
1243 break;
1244 case 5:
1245 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1a,
1246 0x1a, 0x60, 0x90);
1247 break;
1248 case 6:
1249 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x12,
1250 0x12, 0x60, 0x90);
1251 break;
1252 case 7:
1253 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1c,
1254 0x3, 0x70, 0x90);
1255 break;
1256 case 8:
1257 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xa3, 0x10,
1258 0x3, 0x70, 0x90);
1259 break;
1260 case 9:
1261 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1a,
1262 0x1a, 0xe1, 0x10);
1263 break;
1264 case 10:
1265 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x12,
1266 0x12, 0xe1, 0x10);
1267 break;
1268 case 11:
1269 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1c,
1270 0x3, 0xf1, 0x10);
1271 break;
1272 case 12:
1273 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x10,
1274 0x3, 0xf1, 0x10);
1275 break;
1276 case 13:
1277 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1a,
1278 0x1a, 0xe0, 0x10);
1279 break;
1280 case 14:
1281 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x12,
1282 0x12, 0xe0, 0x10);
1283 break;
1284 case 15:
1285 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1c,
1286 0x3, 0xf0, 0x10);
1287 break;
1288 case 16:
1289 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x12,
1290 0x3, 0xf0, 0x10);
1291 break;
1292 case 17:
1293 halbtc8192e2ant_SetFwPstdma(btcoexist, 0x61, 0x20,
1294 0x03, 0x10, 0x10);
1295 break;
1296 case 18:
1297 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x5,
1298 0x5, 0xe1, 0x90);
1299 break;
1300 case 19:
1301 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x25,
1302 0x25, 0xe1, 0x90);
1303 break;
1304 case 20:
1305 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x25,
1306 0x25, 0x60, 0x90);
1307 break;
1308 case 21:
1309 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x15,
1310 0x03, 0x70, 0x90);
1311 break;
1312 case 71:
1313 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1a,
1314 0x1a, 0xe1, 0x90);
1315 break;
1316 }
1317 } else {
1318 /* disable PS tdma */
1319 switch (type) {
1320 default:
1321 case 0:
1322 halbtc8192e2ant_SetFwPstdma(btcoexist, 0x8, 0x0, 0x0,
1323 0x0, 0x0);
1324 btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4);
1325 break;
1326 case 1:
1327 halbtc8192e2ant_SetFwPstdma(btcoexist, 0x0, 0x0, 0x0,
1328 0x8, 0x0);
1329 mdelay(5);
1330 btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20);
1331 break;
1332 }
1333 }
1334
1335 /* update pre state */
1336 coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
1337 coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
1338 }
1339
1340 static void halbtc8192e2ant_set_switch_sstype(struct btc_coexist *btcoexist,
1341 u8 sstype)
1342 {
1343 u8 mimops = BTC_MIMO_PS_DYNAMIC;
1344 u32 disra_mask = 0x0;
1345
1346 btc_alg_dbg(ALGO_TRACE,
1347 "[BTCoex], REAL set SS Type = %d\n", sstype);
1348
1349 disra_mask = halbtc8192e2ant_decidera_mask(btcoexist, sstype,
1350 coex_dm->curra_masktype);
1351 halbtc8192e2ant_Updatera_mask(btcoexist, FORCE_EXEC, disra_mask);
1352
1353 if (sstype == 1) {
1354 halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1);
1355 /* switch ofdm path */
1356 btcoexist->btc_write_1byte(btcoexist, 0xc04, 0x11);
1357 btcoexist->btc_write_1byte(btcoexist, 0xd04, 0x1);
1358 btcoexist->btc_write_4byte(btcoexist, 0x90c, 0x81111111);
1359 /* switch cck patch */
1360 btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe77, 0x4, 0x1);
1361 btcoexist->btc_write_1byte(btcoexist, 0xa07, 0x81);
1362 mimops = BTC_MIMO_PS_STATIC;
1363 } else if (sstype == 2) {
1364 halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
1365 btcoexist->btc_write_1byte(btcoexist, 0xc04, 0x33);
1366 btcoexist->btc_write_1byte(btcoexist, 0xd04, 0x3);
1367 btcoexist->btc_write_4byte(btcoexist, 0x90c, 0x81121313);
1368 btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe77, 0x4, 0x0);
1369 btcoexist->btc_write_1byte(btcoexist, 0xa07, 0x41);
1370 mimops = BTC_MIMO_PS_DYNAMIC;
1371 }
1372 /* set rx 1ss or 2ss */
1373 btcoexist->btc_set(btcoexist, BTC_SET_ACT_SEND_MIMO_PS, &mimops);
1374 }
1375
1376 static void halbtc8192e2ant_switch_sstype(struct btc_coexist *btcoexist,
1377 bool force_exec, u8 new_sstype)
1378 {
1379 btc_alg_dbg(ALGO_TRACE,
1380 "[BTCoex], %s Switch SS Type = %d\n",
1381 (force_exec ? "force to" : ""), new_sstype);
1382 coex_dm->cur_sstype = new_sstype;
1383
1384 if (!force_exec) {
1385 if (coex_dm->pre_sstype == coex_dm->cur_sstype)
1386 return;
1387 }
1388 halbtc8192e2ant_set_switch_sstype(btcoexist, coex_dm->cur_sstype);
1389
1390 coex_dm->pre_sstype = coex_dm->cur_sstype;
1391 }
1392
1393 static void halbtc8192e2ant_coex_alloff(struct btc_coexist *btcoexist)
1394 {
1395 /* fw all off */
1396 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
1397 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
1398 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
1399
1400 /* sw all off */
1401 btc8192e2ant_sw_mec1(btcoexist, false, false, false, false);
1402 btc8192e2ant_sw_mec2(btcoexist, false, false, false, 0x18);
1403
1404 /* hw all off */
1405 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 0);
1406 }
1407
1408 static void halbtc8192e2ant_init_coex_dm(struct btc_coexist *btcoexist)
1409 {
1410 /* force to reset coex mechanism */
1411
1412 halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1);
1413 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, FORCE_EXEC, 6);
1414 halbtc8192e2ant_dec_btpwr(btcoexist, FORCE_EXEC, 0);
1415
1416 btc8192e2ant_coex_tbl_w_type(btcoexist, FORCE_EXEC, 0);
1417 halbtc8192e2ant_switch_sstype(btcoexist, FORCE_EXEC, 2);
1418
1419 btc8192e2ant_sw_mec1(btcoexist, false, false, false, false);
1420 btc8192e2ant_sw_mec2(btcoexist, false, false, false, 0x18);
1421 }
1422
1423 static void halbtc8192e2ant_action_bt_inquiry(struct btc_coexist *btcoexist)
1424 {
1425 bool low_pwr_disable = true;
1426
1427 btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
1428 &low_pwr_disable);
1429
1430 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
1431
1432 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 2);
1433 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
1434 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
1435 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
1436
1437 btc8192e2ant_sw_mec1(btcoexist, false, false, false, false);
1438 btc8192e2ant_sw_mec2(btcoexist, false, false, false, 0x18);
1439 }
1440
1441 static bool halbtc8192e2ant_is_common_action(struct btc_coexist *btcoexist)
1442 {
1443 struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
1444 bool common = false, wifi_connected = false, wifi_busy = false;
1445 bool bt_hson = false, low_pwr_disable = false;
1446
1447 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hson);
1448 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
1449 &wifi_connected);
1450 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
1451
1452 if (bt_link_info->sco_exist || bt_link_info->hid_exist)
1453 halbtc8192e2ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 0, 0, 0);
1454 else
1455 halbtc8192e2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
1456
1457 if (!wifi_connected) {
1458 low_pwr_disable = false;
1459 btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
1460 &low_pwr_disable);
1461
1462 btc_alg_dbg(ALGO_TRACE,
1463 "[BTCoex], Wifi non-connected idle!!\n");
1464
1465 if ((BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
1466 coex_dm->bt_status) ||
1467 (BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE ==
1468 coex_dm->bt_status)) {
1469 halbtc8192e2ant_switch_sstype(btcoexist,
1470 NORMAL_EXEC, 2);
1471 btc8192e2ant_coex_tbl_w_type(btcoexist,
1472 NORMAL_EXEC, 1);
1473 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1474 false, 0);
1475 } else {
1476 halbtc8192e2ant_switch_sstype(btcoexist,
1477 NORMAL_EXEC, 1);
1478 btc8192e2ant_coex_tbl_w_type(btcoexist,
1479 NORMAL_EXEC, 0);
1480 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1481 false, 1);
1482 }
1483
1484 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
1485 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
1486
1487 btc8192e2ant_sw_mec1(btcoexist, false, false, false, false);
1488 btc8192e2ant_sw_mec2(btcoexist, false, false, false, 0x18);
1489
1490 common = true;
1491 } else {
1492 if (BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
1493 coex_dm->bt_status) {
1494 low_pwr_disable = false;
1495 btcoexist->btc_set(btcoexist,
1496 BTC_SET_ACT_DISABLE_LOW_POWER,
1497 &low_pwr_disable);
1498
1499 btc_alg_dbg(ALGO_TRACE,
1500 "Wifi connected + BT non connected-idle!!\n");
1501
1502 halbtc8192e2ant_switch_sstype(btcoexist,
1503 NORMAL_EXEC, 2);
1504 btc8192e2ant_coex_tbl_w_type(btcoexist,
1505 NORMAL_EXEC, 1);
1506 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1507 false, 0);
1508 halbtc8192e2ant_fw_dac_swinglvl(btcoexist,
1509 NORMAL_EXEC, 6);
1510 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
1511
1512 btc8192e2ant_sw_mec1(btcoexist, false, false,
1513 false, false);
1514 btc8192e2ant_sw_mec2(btcoexist, false, false,
1515 false, 0x18);
1516
1517 common = true;
1518 } else if (BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE ==
1519 coex_dm->bt_status) {
1520 low_pwr_disable = true;
1521 btcoexist->btc_set(btcoexist,
1522 BTC_SET_ACT_DISABLE_LOW_POWER,
1523 &low_pwr_disable);
1524
1525 if (bt_hson)
1526 return false;
1527 btc_alg_dbg(ALGO_TRACE,
1528 "Wifi connected + BT connected-idle!!\n");
1529
1530 halbtc8192e2ant_switch_sstype(btcoexist,
1531 NORMAL_EXEC, 2);
1532 btc8192e2ant_coex_tbl_w_type(btcoexist,
1533 NORMAL_EXEC, 1);
1534 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1535 false, 0);
1536 halbtc8192e2ant_fw_dac_swinglvl(btcoexist,
1537 NORMAL_EXEC, 6);
1538 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
1539
1540 btc8192e2ant_sw_mec1(btcoexist, true, false,
1541 false, false);
1542 btc8192e2ant_sw_mec2(btcoexist, false, false,
1543 false, 0x18);
1544
1545 common = true;
1546 } else {
1547 low_pwr_disable = true;
1548 btcoexist->btc_set(btcoexist,
1549 BTC_SET_ACT_DISABLE_LOW_POWER,
1550 &low_pwr_disable);
1551
1552 if (wifi_busy) {
1553 btc_alg_dbg(ALGO_TRACE,
1554 "Wifi Connected-Busy + BT Busy!!\n");
1555 common = false;
1556 } else {
1557 btc_alg_dbg(ALGO_TRACE,
1558 "Wifi Connected-Idle + BT Busy!!\n");
1559
1560 halbtc8192e2ant_switch_sstype(btcoexist,
1561 NORMAL_EXEC, 1);
1562 btc8192e2ant_coex_tbl_w_type(btcoexist,
1563 NORMAL_EXEC, 2);
1564 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1565 true, 21);
1566 halbtc8192e2ant_fw_dac_swinglvl(btcoexist,
1567 NORMAL_EXEC, 6);
1568 halbtc8192e2ant_dec_btpwr(btcoexist,
1569 NORMAL_EXEC, 0);
1570 btc8192e2ant_sw_mec1(btcoexist, false,
1571 false, false, false);
1572 btc8192e2ant_sw_mec2(btcoexist, false,
1573 false, false, 0x18);
1574 common = true;
1575 }
1576 }
1577 }
1578 return common;
1579 }
1580
1581 static void btc8192e_int1(struct btc_coexist *btcoexist, bool tx_pause,
1582 int result)
1583 {
1584 if (tx_pause) {
1585 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
1586 "[BTCoex], TxPause = 1\n");
1587
1588 if (coex_dm->cur_ps_tdma == 71) {
1589 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1590 true, 5);
1591 coex_dm->tdma_adj_type = 5;
1592 } else if (coex_dm->cur_ps_tdma == 1) {
1593 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1594 true, 5);
1595 coex_dm->tdma_adj_type = 5;
1596 } else if (coex_dm->cur_ps_tdma == 2) {
1597 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1598 true, 6);
1599 coex_dm->tdma_adj_type = 6;
1600 } else if (coex_dm->cur_ps_tdma == 3) {
1601 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1602 true, 7);
1603 coex_dm->tdma_adj_type = 7;
1604 } else if (coex_dm->cur_ps_tdma == 4) {
1605 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1606 true, 8);
1607 coex_dm->tdma_adj_type = 8;
1608 }
1609 if (coex_dm->cur_ps_tdma == 9) {
1610 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1611 true, 13);
1612 coex_dm->tdma_adj_type = 13;
1613 } else if (coex_dm->cur_ps_tdma == 10) {
1614 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1615 true, 14);
1616 coex_dm->tdma_adj_type = 14;
1617 } else if (coex_dm->cur_ps_tdma == 11) {
1618 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1619 true, 15);
1620 coex_dm->tdma_adj_type = 15;
1621 } else if (coex_dm->cur_ps_tdma == 12) {
1622 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1623 true, 16);
1624 coex_dm->tdma_adj_type = 16;
1625 }
1626
1627 if (result == -1) {
1628 if (coex_dm->cur_ps_tdma == 5) {
1629 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1630 true, 6);
1631 coex_dm->tdma_adj_type = 6;
1632 } else if (coex_dm->cur_ps_tdma == 6) {
1633 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1634 true, 7);
1635 coex_dm->tdma_adj_type = 7;
1636 } else if (coex_dm->cur_ps_tdma == 7) {
1637 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1638 true, 8);
1639 coex_dm->tdma_adj_type = 8;
1640 } else if (coex_dm->cur_ps_tdma == 13) {
1641 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1642 true, 14);
1643 coex_dm->tdma_adj_type = 14;
1644 } else if (coex_dm->cur_ps_tdma == 14) {
1645 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1646 true, 15);
1647 coex_dm->tdma_adj_type = 15;
1648 } else if (coex_dm->cur_ps_tdma == 15) {
1649 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1650 true, 16);
1651 coex_dm->tdma_adj_type = 16;
1652 }
1653 } else if (result == 1) {
1654 if (coex_dm->cur_ps_tdma == 8) {
1655 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1656 true, 7);
1657 coex_dm->tdma_adj_type = 7;
1658 } else if (coex_dm->cur_ps_tdma == 7) {
1659 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1660 true, 6);
1661 coex_dm->tdma_adj_type = 6;
1662 } else if (coex_dm->cur_ps_tdma == 6) {
1663 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1664 true, 5);
1665 coex_dm->tdma_adj_type = 5;
1666 } else if (coex_dm->cur_ps_tdma == 16) {
1667 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1668 true, 15);
1669 coex_dm->tdma_adj_type = 15;
1670 } else if (coex_dm->cur_ps_tdma == 15) {
1671 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1672 true, 14);
1673 coex_dm->tdma_adj_type = 14;
1674 } else if (coex_dm->cur_ps_tdma == 14) {
1675 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1676 true, 13);
1677 coex_dm->tdma_adj_type = 13;
1678 }
1679 }
1680 } else {
1681 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
1682 "[BTCoex], TxPause = 0\n");
1683 if (coex_dm->cur_ps_tdma == 5) {
1684 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1685 true, 71);
1686 coex_dm->tdma_adj_type = 71;
1687 } else if (coex_dm->cur_ps_tdma == 6) {
1688 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1689 true, 2);
1690 coex_dm->tdma_adj_type = 2;
1691 } else if (coex_dm->cur_ps_tdma == 7) {
1692 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1693 true, 3);
1694 coex_dm->tdma_adj_type = 3;
1695 } else if (coex_dm->cur_ps_tdma == 8) {
1696 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1697 true, 4);
1698 coex_dm->tdma_adj_type = 4;
1699 }
1700 if (coex_dm->cur_ps_tdma == 13) {
1701 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1702 true, 9);
1703 coex_dm->tdma_adj_type = 9;
1704 } else if (coex_dm->cur_ps_tdma == 14) {
1705 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1706 true, 10);
1707 coex_dm->tdma_adj_type = 10;
1708 } else if (coex_dm->cur_ps_tdma == 15) {
1709 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1710 true, 11);
1711 coex_dm->tdma_adj_type = 11;
1712 } else if (coex_dm->cur_ps_tdma == 16) {
1713 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1714 true, 12);
1715 coex_dm->tdma_adj_type = 12;
1716 }
1717
1718 if (result == -1) {
1719 if (coex_dm->cur_ps_tdma == 71) {
1720 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1721 true, 1);
1722 coex_dm->tdma_adj_type = 1;
1723 } else if (coex_dm->cur_ps_tdma == 1) {
1724 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1725 true, 2);
1726 coex_dm->tdma_adj_type = 2;
1727 } else if (coex_dm->cur_ps_tdma == 2) {
1728 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1729 true, 3);
1730 coex_dm->tdma_adj_type = 3;
1731 } else if (coex_dm->cur_ps_tdma == 3) {
1732 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1733 true, 4);
1734 coex_dm->tdma_adj_type = 4;
1735 } else if (coex_dm->cur_ps_tdma == 9) {
1736 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1737 true, 10);
1738 coex_dm->tdma_adj_type = 10;
1739 } else if (coex_dm->cur_ps_tdma == 10) {
1740 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1741 true, 11);
1742 coex_dm->tdma_adj_type = 11;
1743 } else if (coex_dm->cur_ps_tdma == 11) {
1744 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1745 true, 12);
1746 coex_dm->tdma_adj_type = 12;
1747 }
1748 } else if (result == 1) {
1749 if (coex_dm->cur_ps_tdma == 4) {
1750 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1751 true, 3);
1752 coex_dm->tdma_adj_type = 3;
1753 } else if (coex_dm->cur_ps_tdma == 3) {
1754 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1755 true, 2);
1756 coex_dm->tdma_adj_type = 2;
1757 } else if (coex_dm->cur_ps_tdma == 2) {
1758 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1759 true, 1);
1760 coex_dm->tdma_adj_type = 1;
1761 } else if (coex_dm->cur_ps_tdma == 1) {
1762 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1763 true, 71);
1764 coex_dm->tdma_adj_type = 71;
1765 } else if (coex_dm->cur_ps_tdma == 12) {
1766 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1767 true, 11);
1768 coex_dm->tdma_adj_type = 11;
1769 } else if (coex_dm->cur_ps_tdma == 11) {
1770 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1771 true, 10);
1772 coex_dm->tdma_adj_type = 10;
1773 } else if (coex_dm->cur_ps_tdma == 10) {
1774 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1775 true, 9);
1776 coex_dm->tdma_adj_type = 9;
1777 }
1778 }
1779 }
1780 }
1781
1782 static void btc8192e_int2(struct btc_coexist *btcoexist, bool tx_pause,
1783 int result)
1784 {
1785 if (tx_pause) {
1786 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
1787 "[BTCoex], TxPause = 1\n");
1788 if (coex_dm->cur_ps_tdma == 1) {
1789 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1790 true, 6);
1791 coex_dm->tdma_adj_type = 6;
1792 } else if (coex_dm->cur_ps_tdma == 2) {
1793 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1794 true, 6);
1795 coex_dm->tdma_adj_type = 6;
1796 } else if (coex_dm->cur_ps_tdma == 3) {
1797 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1798 true, 7);
1799 coex_dm->tdma_adj_type = 7;
1800 } else if (coex_dm->cur_ps_tdma == 4) {
1801 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1802 true, 8);
1803 coex_dm->tdma_adj_type = 8;
1804 }
1805 if (coex_dm->cur_ps_tdma == 9) {
1806 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1807 true, 14);
1808 coex_dm->tdma_adj_type = 14;
1809 } else if (coex_dm->cur_ps_tdma == 10) {
1810 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1811 true, 14);
1812 coex_dm->tdma_adj_type = 14;
1813 } else if (coex_dm->cur_ps_tdma == 11) {
1814 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1815 true, 15);
1816 coex_dm->tdma_adj_type = 15;
1817 } else if (coex_dm->cur_ps_tdma == 12) {
1818 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1819 true, 16);
1820 coex_dm->tdma_adj_type = 16;
1821 }
1822 if (result == -1) {
1823 if (coex_dm->cur_ps_tdma == 5) {
1824 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1825 true, 6);
1826 coex_dm->tdma_adj_type = 6;
1827 } else if (coex_dm->cur_ps_tdma == 6) {
1828 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1829 true, 7);
1830 coex_dm->tdma_adj_type = 7;
1831 } else if (coex_dm->cur_ps_tdma == 7) {
1832 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1833 true, 8);
1834 coex_dm->tdma_adj_type = 8;
1835 } else if (coex_dm->cur_ps_tdma == 13) {
1836 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1837 true, 14);
1838 coex_dm->tdma_adj_type = 14;
1839 } else if (coex_dm->cur_ps_tdma == 14) {
1840 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1841 true, 15);
1842 coex_dm->tdma_adj_type = 15;
1843 } else if (coex_dm->cur_ps_tdma == 15) {
1844 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1845 true, 16);
1846 coex_dm->tdma_adj_type = 16;
1847 }
1848 } else if (result == 1) {
1849 if (coex_dm->cur_ps_tdma == 8) {
1850 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1851 true, 7);
1852 coex_dm->tdma_adj_type = 7;
1853 } else if (coex_dm->cur_ps_tdma == 7) {
1854 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1855 true, 6);
1856 coex_dm->tdma_adj_type = 6;
1857 } else if (coex_dm->cur_ps_tdma == 6) {
1858 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1859 true, 6);
1860 coex_dm->tdma_adj_type = 6;
1861 } else if (coex_dm->cur_ps_tdma == 16) {
1862 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1863 true, 15);
1864 coex_dm->tdma_adj_type = 15;
1865 } else if (coex_dm->cur_ps_tdma == 15) {
1866 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1867 true, 14);
1868 coex_dm->tdma_adj_type = 14;
1869 } else if (coex_dm->cur_ps_tdma == 14) {
1870 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1871 true, 14);
1872 coex_dm->tdma_adj_type = 14;
1873 }
1874 }
1875 } else {
1876 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
1877 "[BTCoex], TxPause = 0\n");
1878 if (coex_dm->cur_ps_tdma == 5) {
1879 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1880 true, 2);
1881 coex_dm->tdma_adj_type = 2;
1882 } else if (coex_dm->cur_ps_tdma == 6) {
1883 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1884 true, 2);
1885 coex_dm->tdma_adj_type = 2;
1886 } else if (coex_dm->cur_ps_tdma == 7) {
1887 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1888 true, 3);
1889 coex_dm->tdma_adj_type = 3;
1890 } else if (coex_dm->cur_ps_tdma == 8) {
1891 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1892 true, 4);
1893 coex_dm->tdma_adj_type = 4;
1894 }
1895 if (coex_dm->cur_ps_tdma == 13) {
1896 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1897 true, 10);
1898 coex_dm->tdma_adj_type = 10;
1899 } else if (coex_dm->cur_ps_tdma == 14) {
1900 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1901 true, 10);
1902 coex_dm->tdma_adj_type = 10;
1903 } else if (coex_dm->cur_ps_tdma == 15) {
1904 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1905 true, 11);
1906 coex_dm->tdma_adj_type = 11;
1907 } else if (coex_dm->cur_ps_tdma == 16) {
1908 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1909 true, 12);
1910 coex_dm->tdma_adj_type = 12;
1911 }
1912 if (result == -1) {
1913 if (coex_dm->cur_ps_tdma == 1) {
1914 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1915 true, 2);
1916 coex_dm->tdma_adj_type = 2;
1917 } else if (coex_dm->cur_ps_tdma == 2) {
1918 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1919 true, 3);
1920 coex_dm->tdma_adj_type = 3;
1921 } else if (coex_dm->cur_ps_tdma == 3) {
1922 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1923 true, 4);
1924 coex_dm->tdma_adj_type = 4;
1925 } else if (coex_dm->cur_ps_tdma == 9) {
1926 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1927 true, 10);
1928 coex_dm->tdma_adj_type = 10;
1929 } else if (coex_dm->cur_ps_tdma == 10) {
1930 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1931 true, 11);
1932 coex_dm->tdma_adj_type = 11;
1933 } else if (coex_dm->cur_ps_tdma == 11) {
1934 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1935 true, 12);
1936 coex_dm->tdma_adj_type = 12;
1937 }
1938 } else if (result == 1) {
1939 if (coex_dm->cur_ps_tdma == 4) {
1940 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1941 true, 3);
1942 coex_dm->tdma_adj_type = 3;
1943 } else if (coex_dm->cur_ps_tdma == 3) {
1944 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1945 true, 2);
1946 coex_dm->tdma_adj_type = 2;
1947 } else if (coex_dm->cur_ps_tdma == 2) {
1948 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1949 true, 2);
1950 coex_dm->tdma_adj_type = 2;
1951 } else if (coex_dm->cur_ps_tdma == 12) {
1952 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1953 true, 11);
1954 coex_dm->tdma_adj_type = 11;
1955 } else if (coex_dm->cur_ps_tdma == 11) {
1956 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1957 true, 10);
1958 coex_dm->tdma_adj_type = 10;
1959 } else if (coex_dm->cur_ps_tdma == 10) {
1960 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1961 true, 10);
1962 coex_dm->tdma_adj_type = 10;
1963 }
1964 }
1965 }
1966 }
1967
1968 static void btc8192e_int3(struct btc_coexist *btcoexist, bool tx_pause,
1969 int result)
1970 {
1971 if (tx_pause) {
1972 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
1973 "[BTCoex], TxPause = 1\n");
1974 if (coex_dm->cur_ps_tdma == 1) {
1975 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1976 true, 7);
1977 coex_dm->tdma_adj_type = 7;
1978 } else if (coex_dm->cur_ps_tdma == 2) {
1979 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1980 true, 7);
1981 coex_dm->tdma_adj_type = 7;
1982 } else if (coex_dm->cur_ps_tdma == 3) {
1983 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1984 true, 7);
1985 coex_dm->tdma_adj_type = 7;
1986 } else if (coex_dm->cur_ps_tdma == 4) {
1987 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1988 true, 8);
1989 coex_dm->tdma_adj_type = 8;
1990 }
1991 if (coex_dm->cur_ps_tdma == 9) {
1992 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1993 true, 15);
1994 coex_dm->tdma_adj_type = 15;
1995 } else if (coex_dm->cur_ps_tdma == 10) {
1996 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1997 true, 15);
1998 coex_dm->tdma_adj_type = 15;
1999 } else if (coex_dm->cur_ps_tdma == 11) {
2000 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2001 true, 15);
2002 coex_dm->tdma_adj_type = 15;
2003 } else if (coex_dm->cur_ps_tdma == 12) {
2004 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2005 true, 16);
2006 coex_dm->tdma_adj_type = 16;
2007 }
2008 if (result == -1) {
2009 if (coex_dm->cur_ps_tdma == 5) {
2010 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2011 true, 7);
2012 coex_dm->tdma_adj_type = 7;
2013 } else if (coex_dm->cur_ps_tdma == 6) {
2014 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2015 true, 7);
2016 coex_dm->tdma_adj_type = 7;
2017 } else if (coex_dm->cur_ps_tdma == 7) {
2018 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2019 true, 8);
2020 coex_dm->tdma_adj_type = 8;
2021 } else if (coex_dm->cur_ps_tdma == 13) {
2022 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2023 true, 15);
2024 coex_dm->tdma_adj_type = 15;
2025 } else if (coex_dm->cur_ps_tdma == 14) {
2026 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2027 true, 15);
2028 coex_dm->tdma_adj_type = 15;
2029 } else if (coex_dm->cur_ps_tdma == 15) {
2030 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2031 true, 16);
2032 coex_dm->tdma_adj_type = 16;
2033 }
2034 } else if (result == 1) {
2035 if (coex_dm->cur_ps_tdma == 8) {
2036 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2037 true, 7);
2038 coex_dm->tdma_adj_type = 7;
2039 } else if (coex_dm->cur_ps_tdma == 7) {
2040 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2041 true, 7);
2042 coex_dm->tdma_adj_type = 7;
2043 } else if (coex_dm->cur_ps_tdma == 6) {
2044 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2045 true, 7);
2046 coex_dm->tdma_adj_type = 7;
2047 } else if (coex_dm->cur_ps_tdma == 16) {
2048 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2049 true, 15);
2050 coex_dm->tdma_adj_type = 15;
2051 } else if (coex_dm->cur_ps_tdma == 15) {
2052 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2053 true, 15);
2054 coex_dm->tdma_adj_type = 15;
2055 } else if (coex_dm->cur_ps_tdma == 14) {
2056 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2057 true, 15);
2058 coex_dm->tdma_adj_type = 15;
2059 }
2060 }
2061 } else {
2062 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
2063 "[BTCoex], TxPause = 0\n");
2064 if (coex_dm->cur_ps_tdma == 5) {
2065 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2066 true, 3);
2067 coex_dm->tdma_adj_type = 3;
2068 } else if (coex_dm->cur_ps_tdma == 6) {
2069 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2070 true, 3);
2071 coex_dm->tdma_adj_type = 3;
2072 } else if (coex_dm->cur_ps_tdma == 7) {
2073 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2074 true, 3);
2075 coex_dm->tdma_adj_type = 3;
2076 } else if (coex_dm->cur_ps_tdma == 8) {
2077 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2078 true, 4);
2079 coex_dm->tdma_adj_type = 4;
2080 }
2081 if (coex_dm->cur_ps_tdma == 13) {
2082 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2083 true, 11);
2084 coex_dm->tdma_adj_type = 11;
2085 } else if (coex_dm->cur_ps_tdma == 14) {
2086 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2087 true, 11);
2088 coex_dm->tdma_adj_type = 11;
2089 } else if (coex_dm->cur_ps_tdma == 15) {
2090 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2091 true, 11);
2092 coex_dm->tdma_adj_type = 11;
2093 } else if (coex_dm->cur_ps_tdma == 16) {
2094 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2095 true, 12);
2096 coex_dm->tdma_adj_type = 12;
2097 }
2098 if (result == -1) {
2099 if (coex_dm->cur_ps_tdma == 1) {
2100 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2101 true, 3);
2102 coex_dm->tdma_adj_type = 3;
2103 } else if (coex_dm->cur_ps_tdma == 2) {
2104 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2105 true, 3);
2106 coex_dm->tdma_adj_type = 3;
2107 } else if (coex_dm->cur_ps_tdma == 3) {
2108 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2109 true, 4);
2110 coex_dm->tdma_adj_type = 4;
2111 } else if (coex_dm->cur_ps_tdma == 9) {
2112 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2113 true, 11);
2114 coex_dm->tdma_adj_type = 11;
2115 } else if (coex_dm->cur_ps_tdma == 10) {
2116 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2117 true, 11);
2118 coex_dm->tdma_adj_type = 11;
2119 } else if (coex_dm->cur_ps_tdma == 11) {
2120 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2121 true, 12);
2122 coex_dm->tdma_adj_type = 12;
2123 }
2124 } else if (result == 1) {
2125 if (coex_dm->cur_ps_tdma == 4) {
2126 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2127 true, 3);
2128 coex_dm->tdma_adj_type = 3;
2129 } else if (coex_dm->cur_ps_tdma == 3) {
2130 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2131 true, 3);
2132 coex_dm->tdma_adj_type = 3;
2133 } else if (coex_dm->cur_ps_tdma == 2) {
2134 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2135 true, 3);
2136 coex_dm->tdma_adj_type = 3;
2137 } else if (coex_dm->cur_ps_tdma == 12) {
2138 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2139 true, 11);
2140 coex_dm->tdma_adj_type = 11;
2141 } else if (coex_dm->cur_ps_tdma == 11) {
2142 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2143 true, 11);
2144 coex_dm->tdma_adj_type = 11;
2145 } else if (coex_dm->cur_ps_tdma == 10) {
2146 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2147 true, 11);
2148 coex_dm->tdma_adj_type = 11;
2149 }
2150 }
2151 }
2152 }
2153
2154 static void halbtc8192e2ant_tdma_duration_adjust(struct btc_coexist *btcoexist,
2155 bool sco_hid, bool tx_pause,
2156 u8 max_interval)
2157 {
2158 static int up, dn, m, n, wait_cnt;
2159 /* 0: no change, +1: increase WiFi duration,
2160 * -1: decrease WiFi duration
2161 */
2162 int result;
2163 u8 retry_cnt = 0;
2164
2165 btc_alg_dbg(ALGO_TRACE_FW,
2166 "[BTCoex], TdmaDurationAdjust()\n");
2167
2168 if (!coex_dm->auto_tdma_adjust) {
2169 coex_dm->auto_tdma_adjust = true;
2170 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
2171 "[BTCoex], first run TdmaDurationAdjust()!!\n");
2172 if (sco_hid) {
2173 if (tx_pause) {
2174 if (max_interval == 1) {
2175 halbtc8192e2ant_ps_tdma(btcoexist,
2176 NORMAL_EXEC,
2177 true, 13);
2178 coex_dm->tdma_adj_type = 13;
2179 } else if (max_interval == 2) {
2180 halbtc8192e2ant_ps_tdma(btcoexist,
2181 NORMAL_EXEC,
2182 true, 14);
2183 coex_dm->tdma_adj_type = 14;
2184 } else if (max_interval == 3) {
2185 halbtc8192e2ant_ps_tdma(btcoexist,
2186 NORMAL_EXEC,
2187 true, 15);
2188 coex_dm->tdma_adj_type = 15;
2189 } else {
2190 halbtc8192e2ant_ps_tdma(btcoexist,
2191 NORMAL_EXEC,
2192 true, 15);
2193 coex_dm->tdma_adj_type = 15;
2194 }
2195 } else {
2196 if (max_interval == 1) {
2197 halbtc8192e2ant_ps_tdma(btcoexist,
2198 NORMAL_EXEC,
2199 true, 9);
2200 coex_dm->tdma_adj_type = 9;
2201 } else if (max_interval == 2) {
2202 halbtc8192e2ant_ps_tdma(btcoexist,
2203 NORMAL_EXEC,
2204 true, 10);
2205 coex_dm->tdma_adj_type = 10;
2206 } else if (max_interval == 3) {
2207 halbtc8192e2ant_ps_tdma(btcoexist,
2208 NORMAL_EXEC,
2209 true, 11);
2210 coex_dm->tdma_adj_type = 11;
2211 } else {
2212 halbtc8192e2ant_ps_tdma(btcoexist,
2213 NORMAL_EXEC,
2214 true, 11);
2215 coex_dm->tdma_adj_type = 11;
2216 }
2217 }
2218 } else {
2219 if (tx_pause) {
2220 if (max_interval == 1) {
2221 halbtc8192e2ant_ps_tdma(btcoexist,
2222 NORMAL_EXEC,
2223 true, 5);
2224 coex_dm->tdma_adj_type = 5;
2225 } else if (max_interval == 2) {
2226 halbtc8192e2ant_ps_tdma(btcoexist,
2227 NORMAL_EXEC,
2228 true, 6);
2229 coex_dm->tdma_adj_type = 6;
2230 } else if (max_interval == 3) {
2231 halbtc8192e2ant_ps_tdma(btcoexist,
2232 NORMAL_EXEC,
2233 true, 7);
2234 coex_dm->tdma_adj_type = 7;
2235 } else {
2236 halbtc8192e2ant_ps_tdma(btcoexist,
2237 NORMAL_EXEC,
2238 true, 7);
2239 coex_dm->tdma_adj_type = 7;
2240 }
2241 } else {
2242 if (max_interval == 1) {
2243 halbtc8192e2ant_ps_tdma(btcoexist,
2244 NORMAL_EXEC,
2245 true, 1);
2246 coex_dm->tdma_adj_type = 1;
2247 } else if (max_interval == 2) {
2248 halbtc8192e2ant_ps_tdma(btcoexist,
2249 NORMAL_EXEC,
2250 true, 2);
2251 coex_dm->tdma_adj_type = 2;
2252 } else if (max_interval == 3) {
2253 halbtc8192e2ant_ps_tdma(btcoexist,
2254 NORMAL_EXEC,
2255 true, 3);
2256 coex_dm->tdma_adj_type = 3;
2257 } else {
2258 halbtc8192e2ant_ps_tdma(btcoexist,
2259 NORMAL_EXEC,
2260 true, 3);
2261 coex_dm->tdma_adj_type = 3;
2262 }
2263 }
2264 }
2265
2266 up = 0;
2267 dn = 0;
2268 m = 1;
2269 n = 3;
2270 result = 0;
2271 wait_cnt = 0;
2272 } else {
2273 /* accquire the BT TRx retry count from BT_Info byte2 */
2274 retry_cnt = coex_sta->bt_retry_cnt;
2275 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
2276 "[BTCoex], retry_cnt = %d\n", retry_cnt);
2277 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
2278 "[BTCoex], up=%d, dn=%d, m=%d, n=%d, wait_cnt=%d\n",
2279 up, dn, m, n, wait_cnt);
2280 result = 0;
2281 wait_cnt++;
2282 /* no retry in the last 2-second duration */
2283 if (retry_cnt == 0) {
2284 up++;
2285 dn--;
2286
2287 if (dn <= 0)
2288 dn = 0;
2289
2290 if (up >= n) {
2291 wait_cnt = 0;
2292 n = 3;
2293 up = 0;
2294 dn = 0;
2295 result = 1;
2296 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
2297 "[BTCoex]Increase wifi duration!!\n");
2298 }
2299 } else if (retry_cnt <= 3) {
2300 up--;
2301 dn++;
2302
2303 if (up <= 0)
2304 up = 0;
2305
2306 if (dn == 2) {
2307 if (wait_cnt <= 2)
2308 m++;
2309 else
2310 m = 1;
2311
2312 if (m >= 20)
2313 m = 20;
2314
2315 n = 3 * m;
2316 up = 0;
2317 dn = 0;
2318 wait_cnt = 0;
2319 result = -1;
2320 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
2321 "Reduce wifi duration for retry<3\n");
2322 }
2323 } else {
2324 if (wait_cnt == 1)
2325 m++;
2326 else
2327 m = 1;
2328
2329 if (m >= 20)
2330 m = 20;
2331
2332 n = 3*m;
2333 up = 0;
2334 dn = 0;
2335 wait_cnt = 0;
2336 result = -1;
2337 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
2338 "Decrease wifi duration for retryCounter>3!!\n");
2339 }
2340
2341 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
2342 "[BTCoex], max Interval = %d\n", max_interval);
2343 if (max_interval == 1)
2344 btc8192e_int1(btcoexist, tx_pause, result);
2345 else if (max_interval == 2)
2346 btc8192e_int2(btcoexist, tx_pause, result);
2347 else if (max_interval == 3)
2348 btc8192e_int3(btcoexist, tx_pause, result);
2349 }
2350
2351 /* if current PsTdma not match with
2352 * the recorded one (when scan, dhcp...),
2353 * then we have to adjust it back to the previous record one.
2354 */
2355 if (coex_dm->cur_ps_tdma != coex_dm->tdma_adj_type) {
2356 bool scan = false, link = false, roam = false;
2357
2358 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
2359 "[BTCoex], PsTdma type dismatch!!!, ");
2360 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
2361 "curPsTdma=%d, recordPsTdma=%d\n",
2362 coex_dm->cur_ps_tdma, coex_dm->tdma_adj_type);
2363
2364 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
2365 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
2366 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
2367
2368 if (!scan && !link && !roam)
2369 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2370 true,
2371 coex_dm->tdma_adj_type);
2372 else
2373 btc_alg_dbg(ALGO_TRACE_FW_DETAIL,
2374 "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n");
2375 }
2376 }
2377
2378 /* SCO only or SCO+PAN(HS) */
2379 static void halbtc8192e2ant_action_sco(struct btc_coexist *btcoexist)
2380 {
2381 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_STAY_LOW;
2382 u32 wifi_bw;
2383
2384 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
2385
2386 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
2387 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
2388
2389 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
2390
2391 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 4);
2392
2393 btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
2394
2395 if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
2396 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
2397 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
2398 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
2399 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
2400 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
2401 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
2402 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
2403 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
2404 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2405 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
2406 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
2407 }
2408
2409 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2410
2411 /* sw mechanism */
2412 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2413 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2414 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2415 btc8192e2ant_sw_mec1(btcoexist, true, true,
2416 false, false);
2417 btc8192e2ant_sw_mec2(btcoexist, true, false,
2418 false, 0x6);
2419 } else {
2420 btc8192e2ant_sw_mec1(btcoexist, true, true,
2421 false, false);
2422 btc8192e2ant_sw_mec2(btcoexist, false, false,
2423 false, 0x6);
2424 }
2425 } else {
2426 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2427 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2428 btc8192e2ant_sw_mec1(btcoexist, false, true,
2429 false, false);
2430 btc8192e2ant_sw_mec2(btcoexist, true, false,
2431 false, 0x6);
2432 } else {
2433 btc8192e2ant_sw_mec1(btcoexist, false, true,
2434 false, false);
2435 btc8192e2ant_sw_mec2(btcoexist, false, false,
2436 false, 0x6);
2437 }
2438 }
2439 }
2440
2441 static void halbtc8192e2ant_action_sco_pan(struct btc_coexist *btcoexist)
2442 {
2443 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_STAY_LOW;
2444 u32 wifi_bw;
2445
2446 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
2447
2448 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
2449 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
2450
2451 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
2452
2453 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 4);
2454
2455 btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
2456
2457 if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
2458 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
2459 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
2460 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
2461 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
2462 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
2463 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
2464 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10);
2465 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
2466 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2467 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
2468 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10);
2469 }
2470
2471 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2472
2473 /* sw mechanism */
2474 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2475 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2476 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2477 btc8192e2ant_sw_mec1(btcoexist, true, true,
2478 false, false);
2479 btc8192e2ant_sw_mec2(btcoexist, true, false,
2480 false, 0x6);
2481 } else {
2482 btc8192e2ant_sw_mec1(btcoexist, true, true,
2483 false, false);
2484 btc8192e2ant_sw_mec2(btcoexist, false, false,
2485 false, 0x6);
2486 }
2487 } else {
2488 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2489 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2490 btc8192e2ant_sw_mec1(btcoexist, false, true,
2491 false, false);
2492 btc8192e2ant_sw_mec2(btcoexist, true, false,
2493 false, 0x6);
2494 } else {
2495 btc8192e2ant_sw_mec1(btcoexist, false, true,
2496 false, false);
2497 btc8192e2ant_sw_mec2(btcoexist, false, false,
2498 false, 0x6);
2499 }
2500 }
2501 }
2502
2503 static void halbtc8192e2ant_action_hid(struct btc_coexist *btcoexist)
2504 {
2505 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
2506 u32 wifi_bw;
2507
2508 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
2509 btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
2510
2511 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
2512 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
2513
2514 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
2515
2516 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2517
2518 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 3);
2519
2520 if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
2521 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
2522 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
2523 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
2524 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
2525 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
2526 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
2527 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
2528 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
2529 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2530 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
2531 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
2532 }
2533
2534 /* sw mechanism */
2535 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2536 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2537 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2538 btc8192e2ant_sw_mec1(btcoexist, true, true,
2539 false, false);
2540 btc8192e2ant_sw_mec2(btcoexist, true, false,
2541 false, 0x18);
2542 } else {
2543 btc8192e2ant_sw_mec1(btcoexist, true, true,
2544 false, false);
2545 btc8192e2ant_sw_mec2(btcoexist, false, false,
2546 false, 0x18);
2547 }
2548 } else {
2549 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2550 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2551 btc8192e2ant_sw_mec1(btcoexist, false, true,
2552 false, false);
2553 btc8192e2ant_sw_mec2(btcoexist, true, false,
2554 false, 0x18);
2555 } else {
2556 btc8192e2ant_sw_mec1(btcoexist, false, true,
2557 false, false);
2558 btc8192e2ant_sw_mec2(btcoexist, false, false,
2559 false, 0x18);
2560 }
2561 }
2562 }
2563
2564 /* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
2565 static void halbtc8192e2ant_action_a2dp(struct btc_coexist *btcoexist)
2566 {
2567 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
2568 u32 wifi_bw;
2569 bool long_dist = false;
2570
2571 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
2572 btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
2573
2574 if ((btrssi_state == BTC_RSSI_STATE_LOW ||
2575 btrssi_state == BTC_RSSI_STATE_STAY_LOW) &&
2576 (wifirssi_state == BTC_RSSI_STATE_LOW ||
2577 wifirssi_state == BTC_RSSI_STATE_STAY_LOW)) {
2578 btc_alg_dbg(ALGO_TRACE,
2579 "[BTCoex], A2dp, wifi/bt rssi both LOW!!\n");
2580 long_dist = true;
2581 }
2582 if (long_dist) {
2583 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 2);
2584 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true,
2585 0x4);
2586 } else {
2587 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
2588 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
2589 0x8);
2590 }
2591
2592 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
2593
2594 if (long_dist)
2595 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 0);
2596 else
2597 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 2);
2598
2599 if (long_dist) {
2600 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 17);
2601 coex_dm->auto_tdma_adjust = false;
2602 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
2603 } else {
2604 if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
2605 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
2606 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false,
2607 true, 1);
2608 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
2609 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
2610 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
2611 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false,
2612 false, 1);
2613 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
2614 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
2615 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2616 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false,
2617 false, 1);
2618 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
2619 }
2620 }
2621
2622 /* sw mechanism */
2623 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2624 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2625 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2626 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2627 btc8192e2ant_sw_mec1(btcoexist, true, false,
2628 false, false);
2629 btc8192e2ant_sw_mec2(btcoexist, true, false,
2630 false, 0x18);
2631 } else {
2632 btc8192e2ant_sw_mec1(btcoexist, true, false,
2633 false, false);
2634 btc8192e2ant_sw_mec2(btcoexist, false, false,
2635 false, 0x18);
2636 }
2637 } else {
2638 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2639 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2640 btc8192e2ant_sw_mec1(btcoexist, false, false,
2641 false, false);
2642 btc8192e2ant_sw_mec2(btcoexist, true, false,
2643 false, 0x18);
2644 } else {
2645 btc8192e2ant_sw_mec1(btcoexist, false, false,
2646 false, false);
2647 btc8192e2ant_sw_mec2(btcoexist, false, false,
2648 false, 0x18);
2649 }
2650 }
2651 }
2652
2653 static void halbtc8192e2ant_action_a2dp_pan_hs(struct btc_coexist *btcoexist)
2654 {
2655 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
2656 u32 wifi_bw;
2657
2658 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
2659 btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
2660
2661 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
2662 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
2663
2664 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
2665 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 2);
2666
2667 if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
2668 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
2669 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, true, 2);
2670 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
2671 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
2672 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
2673 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false,
2674 false, 2);
2675 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
2676 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
2677 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2678 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false,
2679 false, 2);
2680 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
2681 }
2682
2683 /* sw mechanism */
2684 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2685 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2686 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2687 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2688 btc8192e2ant_sw_mec1(btcoexist, true, false,
2689 false, false);
2690 btc8192e2ant_sw_mec2(btcoexist, true, false,
2691 true, 0x6);
2692 } else {
2693 btc8192e2ant_sw_mec1(btcoexist, true, false,
2694 false, false);
2695 btc8192e2ant_sw_mec2(btcoexist, false, false,
2696 true, 0x6);
2697 }
2698 } else {
2699 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2700 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2701 btc8192e2ant_sw_mec1(btcoexist, false, false,
2702 false, false);
2703 btc8192e2ant_sw_mec2(btcoexist, true, false,
2704 true, 0x6);
2705 } else {
2706 btc8192e2ant_sw_mec1(btcoexist, false, false,
2707 false, false);
2708 btc8192e2ant_sw_mec2(btcoexist, false, false,
2709 true, 0x6);
2710 }
2711 }
2712 }
2713
2714 static void halbtc8192e2ant_action_pan_edr(struct btc_coexist *btcoexist)
2715 {
2716 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
2717 u32 wifi_bw;
2718
2719 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
2720 btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
2721
2722 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
2723 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
2724
2725 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
2726
2727 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 2);
2728
2729 if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
2730 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
2731 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
2732 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
2733 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
2734 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
2735 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
2736 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
2737 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
2738 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2739 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
2740 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
2741 }
2742
2743 /* sw mechanism */
2744 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2745 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2746 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2747 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2748 btc8192e2ant_sw_mec1(btcoexist, true, false,
2749 false, false);
2750 btc8192e2ant_sw_mec2(btcoexist, true, false,
2751 false, 0x18);
2752 } else {
2753 btc8192e2ant_sw_mec1(btcoexist, true, false,
2754 false, false);
2755 btc8192e2ant_sw_mec2(btcoexist, false, false,
2756 false, 0x18);
2757 }
2758 } else {
2759 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2760 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2761 btc8192e2ant_sw_mec1(btcoexist, false, false,
2762 false, false);
2763 btc8192e2ant_sw_mec2(btcoexist, true, false,
2764 false, 0x18);
2765 } else {
2766 btc8192e2ant_sw_mec1(btcoexist, false, false,
2767 false, false);
2768 btc8192e2ant_sw_mec2(btcoexist, false, false,
2769 false, 0x18);
2770 }
2771 }
2772 }
2773
2774 /* PAN(HS) only */
2775 static void halbtc8192e2ant_action_pan_hs(struct btc_coexist *btcoexist)
2776 {
2777 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
2778 u32 wifi_bw;
2779
2780 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
2781 btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
2782
2783 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
2784 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
2785
2786 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
2787
2788 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 2);
2789
2790 if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
2791 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
2792 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
2793 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
2794 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
2795 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
2796 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
2797 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2798 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
2799 }
2800 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
2801
2802 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2803 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2804 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2805 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2806 btc8192e2ant_sw_mec1(btcoexist, true, false,
2807 false, false);
2808 btc8192e2ant_sw_mec2(btcoexist, true, false,
2809 false, 0x18);
2810 } else {
2811 btc8192e2ant_sw_mec1(btcoexist, true, false,
2812 false, false);
2813 btc8192e2ant_sw_mec2(btcoexist, false, false,
2814 false, 0x18);
2815 }
2816 } else {
2817 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2818 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2819 btc8192e2ant_sw_mec1(btcoexist, false, false,
2820 false, false);
2821 btc8192e2ant_sw_mec2(btcoexist, true, false,
2822 false, 0x18);
2823 } else {
2824 btc8192e2ant_sw_mec1(btcoexist, false, false,
2825 false, false);
2826 btc8192e2ant_sw_mec2(btcoexist, false, false,
2827 false, 0x18);
2828 }
2829 }
2830 }
2831
2832 /* PAN(EDR)+A2DP */
2833 static void halbtc8192e2ant_action_pan_edr_a2dp(struct btc_coexist *btcoexist)
2834 {
2835 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
2836 u32 wifi_bw;
2837
2838 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
2839 btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
2840
2841 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
2842 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
2843
2844 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
2845
2846 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 2);
2847
2848 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2849
2850 if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
2851 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
2852 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
2853 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, true, 3);
2854 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
2855 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
2856 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
2857 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false,
2858 false, 3);
2859 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
2860 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2861 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
2862 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false,
2863 false, 3);
2864 }
2865
2866 /* sw mechanism */
2867 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2868 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2869 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2870 btc8192e2ant_sw_mec1(btcoexist, true, false,
2871 false, false);
2872 btc8192e2ant_sw_mec2(btcoexist, true, false,
2873 false, 0x18);
2874 } else {
2875 btc8192e2ant_sw_mec1(btcoexist, true, false,
2876 false, false);
2877 btc8192e2ant_sw_mec2(btcoexist, false, false,
2878 false, 0x18);
2879 }
2880 } else {
2881 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2882 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2883 btc8192e2ant_sw_mec1(btcoexist, false, false,
2884 false, false);
2885 btc8192e2ant_sw_mec2(btcoexist, true, false,
2886 false, 0x18);
2887 } else {
2888 btc8192e2ant_sw_mec1(btcoexist, false, false,
2889 false, false);
2890 btc8192e2ant_sw_mec2(btcoexist, false, false,
2891 false, 0x18);
2892 }
2893 }
2894 }
2895
2896 static void halbtc8192e2ant_action_pan_edr_hid(struct btc_coexist *btcoexist)
2897 {
2898 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
2899 u32 wifi_bw;
2900
2901 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
2902 btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
2903
2904 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2905
2906 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
2907 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
2908
2909 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
2910
2911 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 3);
2912
2913 if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
2914 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
2915 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
2916 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
2917 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
2918 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
2919 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
2920 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2921 true, 10);
2922 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
2923 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2924 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
2925 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2926 true, 10);
2927 }
2928
2929 /* sw mechanism */
2930 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2931 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2932 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2933 btc8192e2ant_sw_mec1(btcoexist, true, true,
2934 false, false);
2935 btc8192e2ant_sw_mec2(btcoexist, true, false,
2936 false, 0x18);
2937 } else {
2938 btc8192e2ant_sw_mec1(btcoexist, true, true,
2939 false, false);
2940 btc8192e2ant_sw_mec2(btcoexist, false, false,
2941 false, 0x18);
2942 }
2943 } else {
2944 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2945 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2946 btc8192e2ant_sw_mec1(btcoexist, false, true,
2947 false, false);
2948 btc8192e2ant_sw_mec2(btcoexist, true, false,
2949 false, 0x18);
2950 } else {
2951 btc8192e2ant_sw_mec1(btcoexist, false, true,
2952 false, false);
2953 btc8192e2ant_sw_mec2(btcoexist, false, false,
2954 false, 0x18);
2955 }
2956 }
2957 }
2958
2959 /* HID+A2DP+PAN(EDR) */
2960 static void btc8192e2ant_action_hid_a2dp_pan_edr(struct btc_coexist *btcoexist)
2961 {
2962 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
2963 u32 wifi_bw;
2964
2965 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
2966 btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
2967
2968 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
2969 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
2970
2971 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
2972
2973 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2974
2975 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 3);
2976
2977 if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
2978 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
2979 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
2980 halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, true, 3);
2981 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
2982 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
2983 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
2984 halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 3);
2985 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
2986 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2987 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
2988 halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 3);
2989 }
2990
2991 /* sw mechanism */
2992 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2993 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2994 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2995 btc8192e2ant_sw_mec1(btcoexist, true, true,
2996 false, false);
2997 btc8192e2ant_sw_mec2(btcoexist, true, false,
2998 false, 0x18);
2999 } else {
3000 btc8192e2ant_sw_mec1(btcoexist, true, true,
3001 false, false);
3002 btc8192e2ant_sw_mec2(btcoexist, false, false,
3003 false, 0x18);
3004 }
3005 } else {
3006 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
3007 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3008 btc8192e2ant_sw_mec1(btcoexist, false, true,
3009 false, false);
3010 btc8192e2ant_sw_mec2(btcoexist, true, false,
3011 false, 0x18);
3012 } else {
3013 btc8192e2ant_sw_mec1(btcoexist, false, true,
3014 false, false);
3015 btc8192e2ant_sw_mec2(btcoexist, false, false,
3016 false, 0x18);
3017 }
3018 }
3019 }
3020
3021 static void halbtc8192e2ant_action_hid_a2dp(struct btc_coexist *btcoexist)
3022 {
3023 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
3024 u32 wifi_bw;
3025
3026 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
3027 btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
3028
3029 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
3030 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
3031
3032 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3033
3034 btc8192e2ant_coex_tbl_w_type(btcoexist, NORMAL_EXEC, 3);
3035
3036 if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
3037 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
3038 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
3039 halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, true, 2);
3040 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
3041 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
3042 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
3043 halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 2);
3044 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
3045 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3046 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
3047 halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 2);
3048 }
3049
3050 /* sw mechanism */
3051 if (BTC_WIFI_BW_HT40 == wifi_bw) {
3052 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
3053 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3054 btc8192e2ant_sw_mec1(btcoexist, true, true,
3055 false, false);
3056 btc8192e2ant_sw_mec2(btcoexist, true, false,
3057 false, 0x18);
3058 } else {
3059 btc8192e2ant_sw_mec1(btcoexist, true, true,
3060 false, false);
3061 btc8192e2ant_sw_mec2(btcoexist, false, false,
3062 false, 0x18);
3063 }
3064 } else {
3065 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
3066 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3067 btc8192e2ant_sw_mec1(btcoexist, false, true,
3068 false, false);
3069 btc8192e2ant_sw_mec2(btcoexist, true, false,
3070 false, 0x18);
3071 } else {
3072 btc8192e2ant_sw_mec1(btcoexist, false, true,
3073 false, false);
3074 btc8192e2ant_sw_mec2(btcoexist, false, false,
3075 false, 0x18);
3076 }
3077 }
3078 }
3079
3080 static void halbtc8192e2ant_run_coexist_mechanism(struct btc_coexist *btcoexist)
3081 {
3082 u8 algorithm = 0;
3083
3084 btc_alg_dbg(ALGO_TRACE,
3085 "[BTCoex], RunCoexistMechanism()===>\n");
3086
3087 if (btcoexist->manual_control) {
3088 btc_alg_dbg(ALGO_TRACE,
3089 "[BTCoex], return for Manual CTRL <===\n");
3090 return;
3091 }
3092
3093 if (coex_sta->under_ips) {
3094 btc_alg_dbg(ALGO_TRACE,
3095 "[BTCoex], wifi is under IPS !!!\n");
3096 return;
3097 }
3098
3099 algorithm = halbtc8192e2ant_action_algorithm(btcoexist);
3100 if (coex_sta->c2h_bt_inquiry_page &&
3101 (BT_8192E_2ANT_COEX_ALGO_PANHS != algorithm)) {
3102 btc_alg_dbg(ALGO_TRACE,
3103 "[BTCoex], BT is under inquiry/page scan !!\n");
3104 halbtc8192e2ant_action_bt_inquiry(btcoexist);
3105 return;
3106 }
3107
3108 coex_dm->cur_algorithm = algorithm;
3109 btc_alg_dbg(ALGO_TRACE,
3110 "[BTCoex], Algorithm = %d\n", coex_dm->cur_algorithm);
3111
3112 if (halbtc8192e2ant_is_common_action(btcoexist)) {
3113 btc_alg_dbg(ALGO_TRACE,
3114 "[BTCoex], Action 2-Ant common\n");
3115 coex_dm->auto_tdma_adjust = false;
3116 } else {
3117 if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) {
3118 btc_alg_dbg(ALGO_TRACE,
3119 "[BTCoex] preAlgorithm=%d, curAlgorithm=%d\n",
3120 coex_dm->pre_algorithm,
3121 coex_dm->cur_algorithm);
3122 coex_dm->auto_tdma_adjust = false;
3123 }
3124 switch (coex_dm->cur_algorithm) {
3125 case BT_8192E_2ANT_COEX_ALGO_SCO:
3126 btc_alg_dbg(ALGO_TRACE,
3127 "Action 2-Ant, algorithm = SCO\n");
3128 halbtc8192e2ant_action_sco(btcoexist);
3129 break;
3130 case BT_8192E_2ANT_COEX_ALGO_SCO_PAN:
3131 btc_alg_dbg(ALGO_TRACE,
3132 "Action 2-Ant, algorithm = SCO+PAN(EDR)\n");
3133 halbtc8192e2ant_action_sco_pan(btcoexist);
3134 break;
3135 case BT_8192E_2ANT_COEX_ALGO_HID:
3136 btc_alg_dbg(ALGO_TRACE,
3137 "Action 2-Ant, algorithm = HID\n");
3138 halbtc8192e2ant_action_hid(btcoexist);
3139 break;
3140 case BT_8192E_2ANT_COEX_ALGO_A2DP:
3141 btc_alg_dbg(ALGO_TRACE,
3142 "Action 2-Ant, algorithm = A2DP\n");
3143 halbtc8192e2ant_action_a2dp(btcoexist);
3144 break;
3145 case BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS:
3146 btc_alg_dbg(ALGO_TRACE,
3147 "Action 2-Ant, algorithm = A2DP+PAN(HS)\n");
3148 halbtc8192e2ant_action_a2dp_pan_hs(btcoexist);
3149 break;
3150 case BT_8192E_2ANT_COEX_ALGO_PANEDR:
3151 btc_alg_dbg(ALGO_TRACE,
3152 "Action 2-Ant, algorithm = PAN(EDR)\n");
3153 halbtc8192e2ant_action_pan_edr(btcoexist);
3154 break;
3155 case BT_8192E_2ANT_COEX_ALGO_PANHS:
3156 btc_alg_dbg(ALGO_TRACE,
3157 "Action 2-Ant, algorithm = HS mode\n");
3158 halbtc8192e2ant_action_pan_hs(btcoexist);
3159 break;
3160 case BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP:
3161 btc_alg_dbg(ALGO_TRACE,
3162 "Action 2-Ant, algorithm = PAN+A2DP\n");
3163 halbtc8192e2ant_action_pan_edr_a2dp(btcoexist);
3164 break;
3165 case BT_8192E_2ANT_COEX_ALGO_PANEDR_HID:
3166 btc_alg_dbg(ALGO_TRACE,
3167 "Action 2-Ant, algorithm = PAN(EDR)+HID\n");
3168 halbtc8192e2ant_action_pan_edr_hid(btcoexist);
3169 break;
3170 case BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR:
3171 btc_alg_dbg(ALGO_TRACE,
3172 "Action 2-Ant, algorithm = HID+A2DP+PAN\n");
3173 btc8192e2ant_action_hid_a2dp_pan_edr(btcoexist);
3174 break;
3175 case BT_8192E_2ANT_COEX_ALGO_HID_A2DP:
3176 btc_alg_dbg(ALGO_TRACE,
3177 "Action 2-Ant, algorithm = HID+A2DP\n");
3178 halbtc8192e2ant_action_hid_a2dp(btcoexist);
3179 break;
3180 default:
3181 btc_alg_dbg(ALGO_TRACE,
3182 "Action 2-Ant, algorithm = unknown!!\n");
3183 /* halbtc8192e2ant_coex_alloff(btcoexist); */
3184 break;
3185 }
3186 coex_dm->pre_algorithm = coex_dm->cur_algorithm;
3187 }
3188 }
3189
3190 static void halbtc8192e2ant_init_hwconfig(struct btc_coexist *btcoexist,
3191 bool backup)
3192 {
3193 u16 u16tmp = 0;
3194 u8 u8tmp = 0;
3195
3196 btc_iface_dbg(INTF_INIT,
3197 "[BTCoex], 2Ant Init HW Config!!\n");
3198
3199 if (backup) {
3200 /* backup rf 0x1e value */
3201 coex_dm->bt_rf0x1e_backup =
3202 btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A,
3203 0x1e, 0xfffff);
3204
3205 coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
3206 0x430);
3207 coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
3208 0x434);
3209 coex_dm->backup_retrylimit = btcoexist->btc_read_2byte(
3210 btcoexist,
3211 0x42a);
3212 coex_dm->backup_ampdu_maxtime = btcoexist->btc_read_1byte(
3213 btcoexist,
3214 0x456);
3215 }
3216
3217 /* antenna sw ctrl to bt */
3218 btcoexist->btc_write_1byte(btcoexist, 0x4f, 0x6);
3219 btcoexist->btc_write_1byte(btcoexist, 0x944, 0x24);
3220 btcoexist->btc_write_4byte(btcoexist, 0x930, 0x700700);
3221 btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20);
3222 if (btcoexist->chip_interface == BTC_INTF_USB)
3223 btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004);
3224 else
3225 btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004);
3226
3227 btc8192e2ant_coex_tbl_w_type(btcoexist, FORCE_EXEC, 0);
3228
3229 /* antenna switch control parameter */
3230 btcoexist->btc_write_4byte(btcoexist, 0x858, 0x55555555);
3231
3232 /* coex parameters */
3233 btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3);
3234 /* 0x790[5:0] = 0x5 */
3235 u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
3236 u8tmp &= 0xc0;
3237 u8tmp |= 0x5;
3238 btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
3239
3240 /* enable counter statistics */
3241 btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
3242
3243 /* enable PTA */
3244 btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20);
3245 /* enable mailbox interface */
3246 u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x40);
3247 u16tmp |= BIT9;
3248 btcoexist->btc_write_2byte(btcoexist, 0x40, u16tmp);
3249
3250 /* enable PTA I2C mailbox */
3251 u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x101);
3252 u8tmp |= BIT4;
3253 btcoexist->btc_write_1byte(btcoexist, 0x101, u8tmp);
3254
3255 /* enable bt clock when wifi is disabled. */
3256 u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x93);
3257 u8tmp |= BIT0;
3258 btcoexist->btc_write_1byte(btcoexist, 0x93, u8tmp);
3259 /* enable bt clock when suspend. */
3260 u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7);
3261 u8tmp |= BIT0;
3262 btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp);
3263 }
3264
3265 /*************************************************************
3266 * work around function start with wa_halbtc8192e2ant_
3267 *************************************************************/
3268
3269 /************************************************************
3270 * extern function start with EXhalbtc8192e2ant_
3271 ************************************************************/
3272
3273 void ex_halbtc8192e2ant_init_hwconfig(struct btc_coexist *btcoexist)
3274 {
3275 halbtc8192e2ant_init_hwconfig(btcoexist, true);
3276 }
3277
3278 void ex_halbtc8192e2ant_init_coex_dm(struct btc_coexist *btcoexist)
3279 {
3280 btc_iface_dbg(INTF_INIT,
3281 "[BTCoex], Coex Mechanism Init!!\n");
3282 halbtc8192e2ant_init_coex_dm(btcoexist);
3283 }
3284
3285 void ex_halbtc8192e2ant_display_coex_info(struct btc_coexist *btcoexist)
3286 {
3287 struct btc_board_info *board_info = &btcoexist->board_info;
3288 struct btc_stack_info *stack_info = &btcoexist->stack_info;
3289 struct rtl_priv *rtlpriv = btcoexist->adapter;
3290 u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
3291 u16 u16tmp[4];
3292 u32 u32tmp[4];
3293 bool roam = false, scan = false, link = false, wifi_under_5g = false;
3294 bool bt_hson = false, wifi_busy = false;
3295 int wifirssi = 0, bt_hs_rssi = 0;
3296 u32 wifi_bw, wifi_traffic_dir;
3297 u8 wifi_dot11_chnl, wifi_hs_chnl;
3298 u32 fw_ver = 0, bt_patch_ver = 0;
3299
3300 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3301 "\r\n ============[BT Coexist info]============");
3302
3303 if (btcoexist->manual_control) {
3304 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3305 "\r\n ===========[Under Manual Control]===========");
3306 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3307 "\r\n ==========================================");
3308 }
3309
3310 if (!board_info->bt_exist) {
3311 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n BT not exists !!!");
3312 return;
3313 }
3314
3315 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3316 "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:",
3317 board_info->pg_ant_num, board_info->btdm_ant_num);
3318
3319 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %s / %d",
3320 "BT stack/ hci ext ver",
3321 ((stack_info->profile_notified) ? "Yes" : "No"),
3322 stack_info->hci_version);
3323
3324 btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
3325 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
3326 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3327 "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)",
3328 "CoexVer/ FwVer/ PatchVer",
3329 glcoex_ver_date_8192e_2ant, glcoex_ver_8192e_2ant,
3330 fw_ver, bt_patch_ver, bt_patch_ver);
3331
3332 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hson);
3333 btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_DOT11_CHNL,
3334 &wifi_dot11_chnl);
3335 btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_HS_CHNL, &wifi_hs_chnl);
3336 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d / %d(%d)",
3337 "Dot11 channel / HsMode(HsChnl)",
3338 wifi_dot11_chnl, bt_hson, wifi_hs_chnl);
3339
3340 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %3ph ",
3341 "H2C Wifi inform bt chnl Info", coex_dm->wifi_chnl_info);
3342
3343 btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifirssi);
3344 btcoexist->btc_get(btcoexist, BTC_GET_S4_HS_RSSI, &bt_hs_rssi);
3345 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d",
3346 "Wifi rssi/ HS rssi", wifirssi, bt_hs_rssi);
3347
3348 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
3349 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
3350 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
3351 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d/ %d ",
3352 "Wifi link/ roam/ scan", link, roam, scan);
3353
3354 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
3355 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3356 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
3357 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION,
3358 &wifi_traffic_dir);
3359 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %s / %s/ %s ",
3360 "Wifi status", (wifi_under_5g ? "5G" : "2.4G"),
3361 ((BTC_WIFI_BW_LEGACY == wifi_bw) ? "Legacy" :
3362 (((BTC_WIFI_BW_HT40 == wifi_bw) ? "HT40" : "HT20"))),
3363 ((!wifi_busy) ? "idle" :
3364 ((BTC_WIFI_TRAFFIC_TX == wifi_traffic_dir) ?
3365 "uplink" : "downlink")));
3366
3367 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = [%s/ %d/ %d] ",
3368 "BT [status/ rssi/ retryCnt]",
3369 ((btcoexist->bt_info.bt_disabled) ? ("disabled") :
3370 ((coex_sta->c2h_bt_inquiry_page) ?
3371 ("inquiry/page scan") :
3372 ((BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
3373 coex_dm->bt_status) ? "non-connected idle" :
3374 ((BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE ==
3375 coex_dm->bt_status) ? "connected-idle" : "busy")))),
3376 coex_sta->bt_rssi, coex_sta->bt_retry_cnt);
3377
3378 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d / %d / %d / %d",
3379 "SCO/HID/PAN/A2DP", stack_info->sco_exist,
3380 stack_info->hid_exist, stack_info->pan_exist,
3381 stack_info->a2dp_exist);
3382 btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO);
3383
3384 bt_info_ext = coex_sta->bt_info_ext;
3385 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %s",
3386 "BT Info A2DP rate",
3387 (bt_info_ext&BIT0) ? "Basic rate" : "EDR rate");
3388
3389 for (i = 0; i < BT_INFO_SRC_8192E_2ANT_MAX; i++) {
3390 if (coex_sta->bt_info_c2h_cnt[i]) {
3391 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3392 "\r\n %-35s = %7ph(%d)",
3393 GLBtInfoSrc8192e2Ant[i],
3394 coex_sta->bt_info_c2h[i],
3395 coex_sta->bt_info_c2h_cnt[i]);
3396 }
3397 }
3398
3399 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %s/%s",
3400 "PS state, IPS/LPS",
3401 ((coex_sta->under_ips ? "IPS ON" : "IPS OFF")),
3402 ((coex_sta->under_lps ? "LPS ON" : "LPS OFF")));
3403 btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_FW_PWR_MODE_CMD);
3404
3405 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x ", "SS Type",
3406 coex_dm->cur_sstype);
3407
3408 /* Sw mechanism */
3409 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s",
3410 "============[Sw mechanism]============");
3411 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d/ %d ",
3412 "SM1[ShRf/ LpRA/ LimDig]", coex_dm->cur_rf_rx_lpf_shrink,
3413 coex_dm->cur_low_penalty_ra, coex_dm->limited_dig);
3414 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d/ %d(0x%x) ",
3415 "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]",
3416 coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off,
3417 coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl);
3418
3419 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x ", "Rate Mask",
3420 btcoexist->bt_info.ra_mask);
3421
3422 /* Fw mechanism */
3423 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s",
3424 "============[Fw mechanism]============");
3425
3426 ps_tdma_case = coex_dm->cur_ps_tdma;
3427 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3428 "\r\n %-35s = %5ph case-%d (auto:%d)",
3429 "PS TDMA", coex_dm->ps_tdma_para,
3430 ps_tdma_case, coex_dm->auto_tdma_adjust);
3431
3432 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d ",
3433 "DecBtPwr/ IgnWlanAct",
3434 coex_dm->cur_dec_bt_pwr, coex_dm->cur_ignore_wlan_act);
3435
3436 /* Hw setting */
3437 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s",
3438 "============[Hw setting]============");
3439
3440 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x",
3441 "RF-A, 0x1e initVal", coex_dm->bt_rf0x1e_backup);
3442
3443 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
3444 "backup ARFR1/ARFR2/RL/AMaxTime", coex_dm->backup_arfr_cnt1,
3445 coex_dm->backup_arfr_cnt2, coex_dm->backup_retrylimit,
3446 coex_dm->backup_ampdu_maxtime);
3447
3448 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
3449 u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
3450 u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
3451 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
3452 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
3453 "0x430/0x434/0x42a/0x456",
3454 u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
3455
3456 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc04);
3457 u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xd04);
3458 u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x90c);
3459 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
3460 "0xc04/ 0xd04/ 0x90c", u32tmp[0], u32tmp[1], u32tmp[2]);
3461
3462 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
3463 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x", "0x778",
3464 u8tmp[0]);
3465
3466 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x92c);
3467 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x930);
3468 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/ 0x%x",
3469 "0x92c/ 0x930", (u8tmp[0]), u32tmp[0]);
3470
3471 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40);
3472 u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x4f);
3473 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/ 0x%x",
3474 "0x40/ 0x4f", u8tmp[0], u8tmp[1]);
3475
3476 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
3477 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
3478 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/ 0x%x",
3479 "0x550(bcn ctrl)/0x522", u32tmp[0], u8tmp[0]);
3480
3481 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
3482 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x", "0xc50(dig)",
3483 u32tmp[0]);
3484
3485 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
3486 u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
3487 u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
3488 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc);
3489 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3490 "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
3491 "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)",
3492 u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]);
3493
3494 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d",
3495 "0x770(hp rx[31:16]/tx[15:0])",
3496 coex_sta->high_priority_rx, coex_sta->high_priority_tx);
3497 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d",
3498 "0x774(lp rx[31:16]/tx[15:0])",
3499 coex_sta->low_priority_rx, coex_sta->low_priority_tx);
3500 #if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 1)
3501 halbtc8192e2ant_monitor_bt_ctr(btcoexist);
3502 #endif
3503 btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
3504 }
3505
3506 void ex_halbtc8192e2ant_ips_notify(struct btc_coexist *btcoexist, u8 type)
3507 {
3508 if (BTC_IPS_ENTER == type) {
3509 btc_iface_dbg(INTF_NOTIFY,
3510 "[BTCoex], IPS ENTER notify\n");
3511 coex_sta->under_ips = true;
3512 halbtc8192e2ant_coex_alloff(btcoexist);
3513 } else if (BTC_IPS_LEAVE == type) {
3514 btc_iface_dbg(INTF_NOTIFY,
3515 "[BTCoex], IPS LEAVE notify\n");
3516 coex_sta->under_ips = false;
3517 }
3518 }
3519
3520 void ex_halbtc8192e2ant_lps_notify(struct btc_coexist *btcoexist, u8 type)
3521 {
3522 if (BTC_LPS_ENABLE == type) {
3523 btc_iface_dbg(INTF_NOTIFY,
3524 "[BTCoex], LPS ENABLE notify\n");
3525 coex_sta->under_lps = true;
3526 } else if (BTC_LPS_DISABLE == type) {
3527 btc_iface_dbg(INTF_NOTIFY,
3528 "[BTCoex], LPS DISABLE notify\n");
3529 coex_sta->under_lps = false;
3530 }
3531 }
3532
3533 void ex_halbtc8192e2ant_scan_notify(struct btc_coexist *btcoexist, u8 type)
3534 {
3535 if (BTC_SCAN_START == type)
3536 btc_iface_dbg(INTF_NOTIFY,
3537 "[BTCoex], SCAN START notify\n");
3538 else if (BTC_SCAN_FINISH == type)
3539 btc_iface_dbg(INTF_NOTIFY,
3540 "[BTCoex], SCAN FINISH notify\n");
3541 }
3542
3543 void ex_halbtc8192e2ant_connect_notify(struct btc_coexist *btcoexist, u8 type)
3544 {
3545 if (BTC_ASSOCIATE_START == type)
3546 btc_iface_dbg(INTF_NOTIFY,
3547 "[BTCoex], CONNECT START notify\n");
3548 else if (BTC_ASSOCIATE_FINISH == type)
3549 btc_iface_dbg(INTF_NOTIFY,
3550 "[BTCoex], CONNECT FINISH notify\n");
3551 }
3552
3553 void ex_halbtc8192e2ant_media_status_notify(struct btc_coexist *btcoexist,
3554 u8 type)
3555 {
3556 u8 h2c_parameter[3] = {0};
3557 u32 wifi_bw;
3558 u8 wifi_center_chnl;
3559
3560 if (btcoexist->manual_control ||
3561 btcoexist->stop_coex_dm ||
3562 btcoexist->bt_info.bt_disabled)
3563 return;
3564
3565 if (BTC_MEDIA_CONNECT == type)
3566 btc_iface_dbg(INTF_NOTIFY,
3567 "[BTCoex], MEDIA connect notify\n");
3568 else
3569 btc_iface_dbg(INTF_NOTIFY,
3570 "[BTCoex], MEDIA disconnect notify\n");
3571
3572 /* only 2.4G we need to inform bt the chnl mask */
3573 btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
3574 &wifi_center_chnl);
3575 if ((BTC_MEDIA_CONNECT == type) &&
3576 (wifi_center_chnl <= 14)) {
3577 h2c_parameter[0] = 0x1;
3578 h2c_parameter[1] = wifi_center_chnl;
3579 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3580 if (BTC_WIFI_BW_HT40 == wifi_bw)
3581 h2c_parameter[2] = 0x30;
3582 else
3583 h2c_parameter[2] = 0x20;
3584 }
3585
3586 coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
3587 coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
3588 coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
3589
3590 btc_alg_dbg(ALGO_TRACE_FW_EXEC,
3591 "[BTCoex], FW write 0x66 = 0x%x\n",
3592 h2c_parameter[0] << 16 | h2c_parameter[1] << 8 |
3593 h2c_parameter[2]);
3594
3595 btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
3596 }
3597
3598 void ex_halbtc8192e2ant_special_packet_notify(struct btc_coexist *btcoexist,
3599 u8 type)
3600 {
3601 if (type == BTC_PACKET_DHCP)
3602 btc_iface_dbg(INTF_NOTIFY,
3603 "[BTCoex], DHCP Packet notify\n");
3604 }
3605
3606 void ex_halbtc8192e2ant_bt_info_notify(struct btc_coexist *btcoexist,
3607 u8 *tmp_buf, u8 length)
3608 {
3609 u8 bt_info = 0;
3610 u8 i, rsp_source = 0;
3611 bool bt_busy = false, limited_dig = false;
3612 bool wifi_connected = false;
3613
3614 coex_sta->c2h_bt_info_req_sent = false;
3615
3616 rsp_source = tmp_buf[0] & 0xf;
3617 if (rsp_source >= BT_INFO_SRC_8192E_2ANT_MAX)
3618 rsp_source = BT_INFO_SRC_8192E_2ANT_WIFI_FW;
3619 coex_sta->bt_info_c2h_cnt[rsp_source]++;
3620
3621 btc_iface_dbg(INTF_NOTIFY,
3622 "[BTCoex], Bt info[%d], length=%d, hex data = [",
3623 rsp_source, length);
3624 for (i = 0; i < length; i++) {
3625 coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
3626 if (i == 1)
3627 bt_info = tmp_buf[i];
3628 if (i == length-1)
3629 btc_iface_dbg(INTF_NOTIFY,
3630 "0x%02x]\n", tmp_buf[i]);
3631 else
3632 btc_iface_dbg(INTF_NOTIFY,
3633 "0x%02x, ", tmp_buf[i]);
3634 }
3635
3636 if (BT_INFO_SRC_8192E_2ANT_WIFI_FW != rsp_source) {
3637 coex_sta->bt_retry_cnt = /* [3:0] */
3638 coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
3639
3640 coex_sta->bt_rssi =
3641 coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
3642
3643 coex_sta->bt_info_ext =
3644 coex_sta->bt_info_c2h[rsp_source][4];
3645
3646 /* Here we need to resend some wifi info to BT
3647 * because bt is reset and loss of the info.
3648 */
3649 if ((coex_sta->bt_info_ext & BIT1)) {
3650 btc_alg_dbg(ALGO_TRACE,
3651 "bit1, send wifi BW&Chnl to BT!!\n");
3652 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
3653 &wifi_connected);
3654 if (wifi_connected)
3655 ex_halbtc8192e2ant_media_status_notify(
3656 btcoexist,
3657 BTC_MEDIA_CONNECT);
3658 else
3659 ex_halbtc8192e2ant_media_status_notify(
3660 btcoexist,
3661 BTC_MEDIA_DISCONNECT);
3662 }
3663
3664 if ((coex_sta->bt_info_ext & BIT3)) {
3665 if (!btcoexist->manual_control &&
3666 !btcoexist->stop_coex_dm) {
3667 btc_alg_dbg(ALGO_TRACE,
3668 "bit3, BT NOT ignore Wlan active!\n");
3669 halbtc8192e2ant_IgnoreWlanAct(btcoexist,
3670 FORCE_EXEC,
3671 false);
3672 }
3673 } else {
3674 /* BT already NOT ignore Wlan active,
3675 * do nothing here.
3676 */
3677 }
3678
3679 #if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 0)
3680 if ((coex_sta->bt_info_ext & BIT4)) {
3681 /* BT auto report already enabled, do nothing */
3682 } else {
3683 halbtc8192e2ant_bt_autoreport(btcoexist, FORCE_EXEC,
3684 true);
3685 }
3686 #endif
3687 }
3688
3689 /* check BIT2 first ==> check if bt is under inquiry or page scan */
3690 if (bt_info & BT_INFO_8192E_2ANT_B_INQ_PAGE)
3691 coex_sta->c2h_bt_inquiry_page = true;
3692 else
3693 coex_sta->c2h_bt_inquiry_page = false;
3694
3695 /* set link exist status */
3696 if (!(bt_info&BT_INFO_8192E_2ANT_B_CONNECTION)) {
3697 coex_sta->bt_link_exist = false;
3698 coex_sta->pan_exist = false;
3699 coex_sta->a2dp_exist = false;
3700 coex_sta->hid_exist = false;
3701 coex_sta->sco_exist = false;
3702 } else {/* connection exists */
3703 coex_sta->bt_link_exist = true;
3704 if (bt_info & BT_INFO_8192E_2ANT_B_FTP)
3705 coex_sta->pan_exist = true;
3706 else
3707 coex_sta->pan_exist = false;
3708 if (bt_info & BT_INFO_8192E_2ANT_B_A2DP)
3709 coex_sta->a2dp_exist = true;
3710 else
3711 coex_sta->a2dp_exist = false;
3712 if (bt_info & BT_INFO_8192E_2ANT_B_HID)
3713 coex_sta->hid_exist = true;
3714 else
3715 coex_sta->hid_exist = false;
3716 if (bt_info & BT_INFO_8192E_2ANT_B_SCO_ESCO)
3717 coex_sta->sco_exist = true;
3718 else
3719 coex_sta->sco_exist = false;
3720 }
3721
3722 halbtc8192e2ant_update_btlink_info(btcoexist);
3723
3724 if (!(bt_info&BT_INFO_8192E_2ANT_B_CONNECTION)) {
3725 coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE;
3726 btc_alg_dbg(ALGO_TRACE,
3727 "[BTCoex], BT Non-Connected idle!!!\n");
3728 } else if (bt_info == BT_INFO_8192E_2ANT_B_CONNECTION) {
3729 coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE;
3730 btc_alg_dbg(ALGO_TRACE,
3731 "[BTCoex], bt_infoNotify(), BT Connected-idle!!!\n");
3732 } else if ((bt_info&BT_INFO_8192E_2ANT_B_SCO_ESCO) ||
3733 (bt_info&BT_INFO_8192E_2ANT_B_SCO_BUSY)) {
3734 coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_SCO_BUSY;
3735 btc_alg_dbg(ALGO_TRACE,
3736 "[BTCoex], bt_infoNotify(), BT SCO busy!!!\n");
3737 } else if (bt_info&BT_INFO_8192E_2ANT_B_ACL_BUSY) {
3738 coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_ACL_BUSY;
3739 btc_alg_dbg(ALGO_TRACE,
3740 "[BTCoex], bt_infoNotify(), BT ACL busy!!!\n");
3741 } else {
3742 coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_MAX;
3743 btc_alg_dbg(ALGO_TRACE,
3744 "[BTCoex]bt_infoNotify(), BT Non-Defined state!!!\n");
3745 }
3746
3747 if ((BT_8192E_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
3748 (BT_8192E_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
3749 (BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) {
3750 bt_busy = true;
3751 limited_dig = true;
3752 } else {
3753 bt_busy = false;
3754 limited_dig = false;
3755 }
3756
3757 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
3758
3759 coex_dm->limited_dig = limited_dig;
3760 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig);
3761
3762 halbtc8192e2ant_run_coexist_mechanism(btcoexist);
3763 }
3764
3765 void ex_halbtc8192e2ant_stack_operation_notify(struct btc_coexist *btcoexist,
3766 u8 type)
3767 {
3768 }
3769
3770 void ex_halbtc8192e2ant_halt_notify(struct btc_coexist *btcoexist)
3771 {
3772 btc_iface_dbg(INTF_NOTIFY, "[BTCoex], Halt notify\n");
3773
3774 halbtc8192e2ant_IgnoreWlanAct(btcoexist, FORCE_EXEC, true);
3775 ex_halbtc8192e2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
3776 }
3777
3778 void ex_halbtc8192e2ant_periodical(struct btc_coexist *btcoexist)
3779 {
3780 static u8 dis_ver_info_cnt;
3781 u32 fw_ver = 0, bt_patch_ver = 0;
3782 struct btc_board_info *board_info = &btcoexist->board_info;
3783 struct btc_stack_info *stack_info = &btcoexist->stack_info;
3784
3785 btc_alg_dbg(ALGO_TRACE,
3786 "=======================Periodical=======================\n");
3787 if (dis_ver_info_cnt <= 5) {
3788 dis_ver_info_cnt += 1;
3789 btc_iface_dbg(INTF_INIT,
3790 "************************************************\n");
3791 btc_iface_dbg(INTF_INIT,
3792 "Ant PG Num/ Ant Mech/ Ant Pos = %d/ %d/ %d\n",
3793 board_info->pg_ant_num, board_info->btdm_ant_num,
3794 board_info->btdm_ant_pos);
3795 btc_iface_dbg(INTF_INIT,
3796 "BT stack/ hci ext ver = %s / %d\n",
3797 ((stack_info->profile_notified) ? "Yes" : "No"),
3798 stack_info->hci_version);
3799 btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER,
3800 &bt_patch_ver);
3801 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
3802 btc_iface_dbg(INTF_INIT,
3803 "CoexVer/ FwVer/ PatchVer = %d_%x/ 0x%x/ 0x%x(%d)\n",
3804 glcoex_ver_date_8192e_2ant, glcoex_ver_8192e_2ant,
3805 fw_ver, bt_patch_ver, bt_patch_ver);
3806 btc_iface_dbg(INTF_INIT,
3807 "************************************************\n");
3808 }
3809
3810 #if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 0)
3811 halbtc8192e2ant_querybt_info(btcoexist);
3812 halbtc8192e2ant_monitor_bt_ctr(btcoexist);
3813 btc8192e2ant_monitor_bt_enable_dis(btcoexist);
3814 #else
3815 if (halbtc8192e2ant_iswifi_status_changed(btcoexist) ||
3816 coex_dm->auto_tdma_adjust)
3817 halbtc8192e2ant_run_coexist_mechanism(btcoexist);
3818 #endif
3819 }
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