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UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / realtek / rtlwifi / pci.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "wifi.h"
27 #include "core.h"
28 #include "pci.h"
29 #include "base.h"
30 #include "ps.h"
31 #include "efuse.h"
32 #include <linux/interrupt.h>
33 #include <linux/export.h>
34 #include <linux/kmemleak.h>
35 #include <linux/module.h>
36
37 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
38 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
39 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
40 MODULE_LICENSE("GPL");
41 MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
42
43 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
44 INTEL_VENDOR_ID,
45 ATI_VENDOR_ID,
46 AMD_VENDOR_ID,
47 SIS_VENDOR_ID
48 };
49
50 static const u8 ac_to_hwq[] = {
51 VO_QUEUE,
52 VI_QUEUE,
53 BE_QUEUE,
54 BK_QUEUE
55 };
56
57 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb)
58 {
59 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
60 __le16 fc = rtl_get_fc(skb);
61 u8 queue_index = skb_get_queue_mapping(skb);
62
63 if (unlikely(ieee80211_is_beacon(fc)))
64 return BEACON_QUEUE;
65 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
66 return MGNT_QUEUE;
67 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
68 if (ieee80211_is_nullfunc(fc))
69 return HIGH_QUEUE;
70
71 return ac_to_hwq[queue_index];
72 }
73
74 /* Update PCI dependent default settings*/
75 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
76 {
77 struct rtl_priv *rtlpriv = rtl_priv(hw);
78 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
79 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
80 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
81 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
82 u8 init_aspm;
83
84 ppsc->reg_rfps_level = 0;
85 ppsc->support_aspm = false;
86
87 /*Update PCI ASPM setting */
88 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
89 switch (rtlpci->const_pci_aspm) {
90 case 0:
91 /*No ASPM */
92 break;
93
94 case 1:
95 /*ASPM dynamically enabled/disable. */
96 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
97 break;
98
99 case 2:
100 /*ASPM with Clock Req dynamically enabled/disable. */
101 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
102 RT_RF_OFF_LEVL_CLK_REQ);
103 break;
104
105 case 3:
106 /* Always enable ASPM and Clock Req
107 * from initialization to halt.
108 */
109 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
110 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
111 RT_RF_OFF_LEVL_CLK_REQ);
112 break;
113
114 case 4:
115 /* Always enable ASPM without Clock Req
116 * from initialization to halt.
117 */
118 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
119 RT_RF_OFF_LEVL_CLK_REQ);
120 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
121 break;
122 }
123
124 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
125
126 /*Update Radio OFF setting */
127 switch (rtlpci->const_hwsw_rfoff_d3) {
128 case 1:
129 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
130 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
131 break;
132
133 case 2:
134 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
135 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
136 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
137 break;
138
139 case 3:
140 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
141 break;
142 }
143
144 /*Set HW definition to determine if it supports ASPM. */
145 switch (rtlpci->const_support_pciaspm) {
146 case 0:
147 /*Not support ASPM. */
148 ppsc->support_aspm = false;
149 break;
150 case 1:
151 /*Support ASPM. */
152 ppsc->support_aspm = true;
153 ppsc->support_backdoor = true;
154 break;
155 case 2:
156 /*ASPM value set by chipset. */
157 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
158 ppsc->support_aspm = true;
159 break;
160 default:
161 pr_err("switch case %#x not processed\n",
162 rtlpci->const_support_pciaspm);
163 break;
164 }
165
166 /* toshiba aspm issue, toshiba will set aspm selfly
167 * so we should not set aspm in driver
168 */
169 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
170 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
171 init_aspm == 0x43)
172 ppsc->support_aspm = false;
173 }
174
175 static bool _rtl_pci_platform_switch_device_pci_aspm(
176 struct ieee80211_hw *hw,
177 u8 value)
178 {
179 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
180 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
181
182 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
183 value |= 0x40;
184
185 pci_write_config_byte(rtlpci->pdev, 0x80, value);
186
187 return false;
188 }
189
190 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
191 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
192 {
193 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
194 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
195
196 pci_write_config_byte(rtlpci->pdev, 0x81, value);
197
198 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
199 udelay(100);
200 }
201
202 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
203 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
204 {
205 struct rtl_priv *rtlpriv = rtl_priv(hw);
206 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
207 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
208 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
209 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
210 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
211 /*Retrieve original configuration settings. */
212 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
213 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
214 pcibridge_linkctrlreg;
215 u16 aspmlevel = 0;
216 u8 tmp_u1b = 0;
217
218 if (!ppsc->support_aspm)
219 return;
220
221 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
222 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
223 "PCI(Bridge) UNKNOWN\n");
224
225 return;
226 }
227
228 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
229 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
230 _rtl_pci_switch_clk_req(hw, 0x0);
231 }
232
233 /*for promising device will in L0 state after an I/O. */
234 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
235
236 /*Set corresponding value. */
237 aspmlevel |= BIT(0) | BIT(1);
238 linkctrl_reg &= ~aspmlevel;
239 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
240
241 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
242 udelay(50);
243
244 /*4 Disable Pci Bridge ASPM */
245 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
246 pcibridge_linkctrlreg);
247
248 udelay(50);
249 }
250
251 /*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
252 *power saving We should follow the sequence to enable
253 *RTL8192SE first then enable Pci Bridge ASPM
254 *or the system will show bluescreen.
255 */
256 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
257 {
258 struct rtl_priv *rtlpriv = rtl_priv(hw);
259 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
260 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
261 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
262 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
263 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
264 u16 aspmlevel;
265 u8 u_pcibridge_aspmsetting;
266 u8 u_device_aspmsetting;
267
268 if (!ppsc->support_aspm)
269 return;
270
271 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
272 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
273 "PCI(Bridge) UNKNOWN\n");
274 return;
275 }
276
277 /*4 Enable Pci Bridge ASPM */
278
279 u_pcibridge_aspmsetting =
280 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
281 rtlpci->const_hostpci_aspm_setting;
282
283 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
284 u_pcibridge_aspmsetting &= ~BIT(0);
285
286 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
287 u_pcibridge_aspmsetting);
288
289 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
290 "PlatformEnableASPM(): Write reg[%x] = %x\n",
291 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
292 u_pcibridge_aspmsetting);
293
294 udelay(50);
295
296 /*Get ASPM level (with/without Clock Req) */
297 aspmlevel = rtlpci->const_devicepci_aspm_setting;
298 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
299
300 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
301 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
302
303 u_device_aspmsetting |= aspmlevel;
304
305 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
306
307 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
308 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
309 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
310 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
311 }
312 udelay(100);
313 }
314
315 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
316 {
317 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
318
319 bool status = false;
320 u8 offset_e0;
321 unsigned int offset_e4;
322
323 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
324
325 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
326
327 if (offset_e0 == 0xA0) {
328 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
329 if (offset_e4 & BIT(23))
330 status = true;
331 }
332
333 return status;
334 }
335
336 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
337 struct rtl_priv **buddy_priv)
338 {
339 struct rtl_priv *rtlpriv = rtl_priv(hw);
340 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
341 bool find_buddy_priv = false;
342 struct rtl_priv *tpriv;
343 struct rtl_pci_priv *tpcipriv = NULL;
344
345 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
346 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list,
347 list) {
348 tpcipriv = (struct rtl_pci_priv *)tpriv->priv;
349 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
350 "pcipriv->ndis_adapter.funcnumber %x\n",
351 pcipriv->ndis_adapter.funcnumber);
352 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
353 "tpcipriv->ndis_adapter.funcnumber %x\n",
354 tpcipriv->ndis_adapter.funcnumber);
355
356 if (pcipriv->ndis_adapter.busnumber ==
357 tpcipriv->ndis_adapter.busnumber &&
358 pcipriv->ndis_adapter.devnumber ==
359 tpcipriv->ndis_adapter.devnumber &&
360 pcipriv->ndis_adapter.funcnumber !=
361 tpcipriv->ndis_adapter.funcnumber) {
362 find_buddy_priv = true;
363 break;
364 }
365 }
366 }
367
368 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
369 "find_buddy_priv %d\n", find_buddy_priv);
370
371 if (find_buddy_priv)
372 *buddy_priv = tpriv;
373
374 return find_buddy_priv;
375 }
376
377 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
378 {
379 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
380 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
381 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
382 u8 linkctrl_reg;
383 u8 num4bbytes;
384
385 num4bbytes = (capabilityoffset + 0x10) / 4;
386
387 /*Read Link Control Register */
388 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
389
390 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
391 }
392
393 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
394 struct ieee80211_hw *hw)
395 {
396 struct rtl_priv *rtlpriv = rtl_priv(hw);
397 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
398
399 u8 tmp;
400 u16 linkctrl_reg;
401
402 /*Link Control Register */
403 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
404 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
405
406 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
407 pcipriv->ndis_adapter.linkctrl_reg);
408
409 pci_read_config_byte(pdev, 0x98, &tmp);
410 tmp |= BIT(4);
411 pci_write_config_byte(pdev, 0x98, tmp);
412
413 tmp = 0x17;
414 pci_write_config_byte(pdev, 0x70f, tmp);
415 }
416
417 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
418 {
419 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
420
421 _rtl_pci_update_default_setting(hw);
422
423 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
424 /*Always enable ASPM & Clock Req. */
425 rtl_pci_enable_aspm(hw);
426 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
427 }
428 }
429
430 static void _rtl_pci_io_handler_init(struct device *dev,
431 struct ieee80211_hw *hw)
432 {
433 struct rtl_priv *rtlpriv = rtl_priv(hw);
434
435 rtlpriv->io.dev = dev;
436
437 rtlpriv->io.write8_async = pci_write8_async;
438 rtlpriv->io.write16_async = pci_write16_async;
439 rtlpriv->io.write32_async = pci_write32_async;
440
441 rtlpriv->io.read8_sync = pci_read8_sync;
442 rtlpriv->io.read16_sync = pci_read16_sync;
443 rtlpriv->io.read32_sync = pci_read32_sync;
444 }
445
446 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
447 struct sk_buff *skb,
448 struct rtl_tcb_desc *tcb_desc, u8 tid)
449 {
450 struct rtl_priv *rtlpriv = rtl_priv(hw);
451 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
452 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
453 struct sk_buff *next_skb;
454 u8 additionlen = FCS_LEN;
455
456 /* here open is 4, wep/tkip is 8, aes is 12*/
457 if (info->control.hw_key)
458 additionlen += info->control.hw_key->icv_len;
459
460 /* The most skb num is 6 */
461 tcb_desc->empkt_num = 0;
462 spin_lock_bh(&rtlpriv->locks.waitq_lock);
463 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
464 struct ieee80211_tx_info *next_info;
465
466 next_info = IEEE80211_SKB_CB(next_skb);
467 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
468 tcb_desc->empkt_len[tcb_desc->empkt_num] =
469 next_skb->len + additionlen;
470 tcb_desc->empkt_num++;
471 } else {
472 break;
473 }
474
475 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
476 next_skb))
477 break;
478
479 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
480 break;
481 }
482 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
483
484 return true;
485 }
486
487 /* just for early mode now */
488 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
489 {
490 struct rtl_priv *rtlpriv = rtl_priv(hw);
491 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
492 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
493 struct sk_buff *skb = NULL;
494 struct ieee80211_tx_info *info = NULL;
495 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
496 int tid;
497
498 if (!rtlpriv->rtlhal.earlymode_enable)
499 return;
500
501 if (rtlpriv->dm.supp_phymode_switch &&
502 (rtlpriv->easy_concurrent_ctl.switch_in_process ||
503 (rtlpriv->buddy_priv &&
504 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
505 return;
506 /* we just use em for BE/BK/VI/VO */
507 for (tid = 7; tid >= 0; tid--) {
508 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
509 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
510
511 while (!mac->act_scanning &&
512 rtlpriv->psc.rfpwr_state == ERFON) {
513 struct rtl_tcb_desc tcb_desc;
514
515 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
516
517 spin_lock_bh(&rtlpriv->locks.waitq_lock);
518 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
519 (ring->entries - skb_queue_len(&ring->queue) >
520 rtlhal->max_earlymode_num)) {
521 skb = skb_dequeue(&mac->skb_waitq[tid]);
522 } else {
523 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
524 break;
525 }
526 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
527
528 /* Some macaddr can't do early mode. like
529 * multicast/broadcast/no_qos data
530 */
531 info = IEEE80211_SKB_CB(skb);
532 if (info->flags & IEEE80211_TX_CTL_AMPDU)
533 _rtl_update_earlymode_info(hw, skb,
534 &tcb_desc, tid);
535
536 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
537 }
538 }
539 }
540
541 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
542 {
543 struct rtl_priv *rtlpriv = rtl_priv(hw);
544 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
545
546 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
547
548 while (skb_queue_len(&ring->queue)) {
549 struct sk_buff *skb;
550 struct ieee80211_tx_info *info;
551 __le16 fc;
552 u8 tid;
553 u8 *entry;
554
555 if (rtlpriv->use_new_trx_flow)
556 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
557 else
558 entry = (u8 *)(&ring->desc[ring->idx]);
559
560 if (rtlpriv->cfg->ops->get_available_desc &&
561 rtlpriv->cfg->ops->get_available_desc(hw, prio) <= 1) {
562 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_DMESG,
563 "no available desc!\n");
564 return;
565 }
566
567 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
568 return;
569 ring->idx = (ring->idx + 1) % ring->entries;
570
571 skb = __skb_dequeue(&ring->queue);
572 pci_unmap_single(rtlpci->pdev,
573 rtlpriv->cfg->ops->
574 get_desc(hw, (u8 *)entry, true,
575 HW_DESC_TXBUFF_ADDR),
576 skb->len, PCI_DMA_TODEVICE);
577
578 /* remove early mode header */
579 if (rtlpriv->rtlhal.earlymode_enable)
580 skb_pull(skb, EM_HDR_LEN);
581
582 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
583 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
584 ring->idx,
585 skb_queue_len(&ring->queue),
586 *(u16 *)(skb->data + 22));
587
588 if (prio == TXCMD_QUEUE) {
589 dev_kfree_skb(skb);
590 goto tx_status_ok;
591 }
592
593 /* for sw LPS, just after NULL skb send out, we can
594 * sure AP knows we are sleeping, we should not let
595 * rf sleep
596 */
597 fc = rtl_get_fc(skb);
598 if (ieee80211_is_nullfunc(fc)) {
599 if (ieee80211_has_pm(fc)) {
600 rtlpriv->mac80211.offchan_delay = true;
601 rtlpriv->psc.state_inap = true;
602 } else {
603 rtlpriv->psc.state_inap = false;
604 }
605 }
606 if (ieee80211_is_action(fc)) {
607 struct ieee80211_mgmt *action_frame =
608 (struct ieee80211_mgmt *)skb->data;
609 if (action_frame->u.action.u.ht_smps.action ==
610 WLAN_HT_ACTION_SMPS) {
611 dev_kfree_skb(skb);
612 goto tx_status_ok;
613 }
614 }
615
616 /* update tid tx pkt num */
617 tid = rtl_get_tid(skb);
618 if (tid <= 7)
619 rtlpriv->link_info.tidtx_inperiod[tid]++;
620
621 info = IEEE80211_SKB_CB(skb);
622 ieee80211_tx_info_clear_status(info);
623
624 info->flags |= IEEE80211_TX_STAT_ACK;
625 /*info->status.rates[0].count = 1; */
626
627 ieee80211_tx_status_irqsafe(hw, skb);
628
629 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) {
630 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
631 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n",
632 prio, ring->idx,
633 skb_queue_len(&ring->queue));
634
635 ieee80211_wake_queue(hw, skb_get_queue_mapping(skb));
636 }
637 tx_status_ok:
638 skb = NULL;
639 }
640
641 if (((rtlpriv->link_info.num_rx_inperiod +
642 rtlpriv->link_info.num_tx_inperiod) > 8) ||
643 rtlpriv->link_info.num_rx_inperiod > 2)
644 rtl_lps_leave(hw);
645 }
646
647 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
648 struct sk_buff *new_skb, u8 *entry,
649 int rxring_idx, int desc_idx)
650 {
651 struct rtl_priv *rtlpriv = rtl_priv(hw);
652 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
653 u32 bufferaddress;
654 u8 tmp_one = 1;
655 struct sk_buff *skb;
656
657 if (likely(new_skb)) {
658 skb = new_skb;
659 goto remap;
660 }
661 skb = dev_alloc_skb(rtlpci->rxbuffersize);
662 if (!skb)
663 return 0;
664
665 remap:
666 /* just set skb->cb to mapping addr for pci_unmap_single use */
667 *((dma_addr_t *)skb->cb) =
668 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
669 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
670 bufferaddress = *((dma_addr_t *)skb->cb);
671 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress))
672 return 0;
673 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
674 if (rtlpriv->use_new_trx_flow) {
675 /* skb->cb may be 64 bit address */
676 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
677 HW_DESC_RX_PREPARE,
678 (u8 *)(dma_addr_t *)skb->cb);
679 } else {
680 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
681 HW_DESC_RXBUFF_ADDR,
682 (u8 *)&bufferaddress);
683 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
684 HW_DESC_RXPKT_LEN,
685 (u8 *)&rtlpci->rxbuffersize);
686 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
687 HW_DESC_RXOWN,
688 (u8 *)&tmp_one);
689 }
690 return 1;
691 }
692
693 /* inorder to receive 8K AMSDU we have set skb to
694 * 9100bytes in init rx ring, but if this packet is
695 * not a AMSDU, this large packet will be sent to
696 * TCP/IP directly, this cause big packet ping fail
697 * like: "ping -s 65507", so here we will realloc skb
698 * based on the true size of packet, Mac80211
699 * Probably will do it better, but does not yet.
700 *
701 * Some platform will fail when alloc skb sometimes.
702 * in this condition, we will send the old skb to
703 * mac80211 directly, this will not cause any other
704 * issues, but only this packet will be lost by TCP/IP
705 */
706 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
707 struct sk_buff *skb,
708 struct ieee80211_rx_status rx_status)
709 {
710 if (unlikely(!rtl_action_proc(hw, skb, false))) {
711 dev_kfree_skb_any(skb);
712 } else {
713 struct sk_buff *uskb = NULL;
714
715 uskb = dev_alloc_skb(skb->len + 128);
716 if (likely(uskb)) {
717 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
718 sizeof(rx_status));
719 skb_put_data(uskb, skb->data, skb->len);
720 dev_kfree_skb_any(skb);
721 ieee80211_rx_irqsafe(hw, uskb);
722 } else {
723 ieee80211_rx_irqsafe(hw, skb);
724 }
725 }
726 }
727
728 /*hsisr interrupt handler*/
729 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
730 {
731 struct rtl_priv *rtlpriv = rtl_priv(hw);
732 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
733
734 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
735 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
736 rtlpci->sys_irq_mask);
737 }
738
739 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
740 {
741 struct rtl_priv *rtlpriv = rtl_priv(hw);
742 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
743 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
744 struct ieee80211_rx_status rx_status = { 0 };
745 unsigned int count = rtlpci->rxringcount;
746 u8 own;
747 u8 tmp_one;
748 bool unicast = false;
749 u8 hw_queue = 0;
750 unsigned int rx_remained_cnt;
751 struct rtl_stats stats = {
752 .signal = 0,
753 .rate = 0,
754 };
755
756 /*RX NORMAL PKT */
757 while (count--) {
758 struct ieee80211_hdr *hdr;
759 __le16 fc;
760 u16 len;
761 /*rx buffer descriptor */
762 struct rtl_rx_buffer_desc *buffer_desc = NULL;
763 /*if use new trx flow, it means wifi info */
764 struct rtl_rx_desc *pdesc = NULL;
765 /*rx pkt */
766 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
767 rtlpci->rx_ring[rxring_idx].idx];
768 struct sk_buff *new_skb;
769
770 if (rtlpriv->use_new_trx_flow) {
771 rx_remained_cnt =
772 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
773 hw_queue);
774 if (rx_remained_cnt == 0)
775 return;
776 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
777 rtlpci->rx_ring[rxring_idx].idx];
778 pdesc = (struct rtl_rx_desc *)skb->data;
779 } else { /* rx descriptor */
780 pdesc = &rtlpci->rx_ring[rxring_idx].desc[
781 rtlpci->rx_ring[rxring_idx].idx];
782
783 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
784 false,
785 HW_DESC_OWN);
786 if (own) /* wait data to be filled by hardware */
787 return;
788 }
789
790 /* Reaching this point means: data is filled already
791 * AAAAAAttention !!!
792 * We can NOT access 'skb' before 'pci_unmap_single'
793 */
794 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
795 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
796
797 /* get a new skb - if fail, old one will be reused */
798 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
799 if (unlikely(!new_skb))
800 goto no_new;
801 memset(&rx_status, 0, sizeof(rx_status));
802 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
803 &rx_status, (u8 *)pdesc, skb);
804
805 if (rtlpriv->use_new_trx_flow)
806 rtlpriv->cfg->ops->rx_check_dma_ok(hw,
807 (u8 *)buffer_desc,
808 hw_queue);
809
810 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false,
811 HW_DESC_RXPKT_LEN);
812
813 if (skb->end - skb->tail > len) {
814 skb_put(skb, len);
815 if (rtlpriv->use_new_trx_flow)
816 skb_reserve(skb, stats.rx_drvinfo_size +
817 stats.rx_bufshift + 24);
818 else
819 skb_reserve(skb, stats.rx_drvinfo_size +
820 stats.rx_bufshift);
821 } else {
822 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
823 "skb->end - skb->tail = %d, len is %d\n",
824 skb->end - skb->tail, len);
825 dev_kfree_skb_any(skb);
826 goto new_trx_end;
827 }
828 /* handle command packet here */
829 if (rtlpriv->cfg->ops->rx_command_packet &&
830 rtlpriv->cfg->ops->rx_command_packet(hw, &stats, skb)) {
831 dev_kfree_skb_any(skb);
832 goto new_trx_end;
833 }
834
835 /* NOTICE This can not be use for mac80211,
836 * this is done in mac80211 code,
837 * if done here sec DHCP will fail
838 * skb_trim(skb, skb->len - 4);
839 */
840
841 hdr = rtl_get_hdr(skb);
842 fc = rtl_get_fc(skb);
843
844 if (!stats.crc && !stats.hwerror) {
845 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
846 sizeof(rx_status));
847
848 if (is_broadcast_ether_addr(hdr->addr1)) {
849 ;/*TODO*/
850 } else if (is_multicast_ether_addr(hdr->addr1)) {
851 ;/*TODO*/
852 } else {
853 unicast = true;
854 rtlpriv->stats.rxbytesunicast += skb->len;
855 }
856 rtl_is_special_data(hw, skb, false, true);
857
858 if (ieee80211_is_data(fc)) {
859 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
860 if (unicast)
861 rtlpriv->link_info.num_rx_inperiod++;
862 }
863
864 rtl_collect_scan_list(hw, skb);
865
866 /* static bcn for roaming */
867 rtl_beacon_statistic(hw, skb);
868 rtl_p2p_info(hw, (void *)skb->data, skb->len);
869 /* for sw lps */
870 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
871 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
872 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP &&
873 rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G &&
874 (ieee80211_is_beacon(fc) ||
875 ieee80211_is_probe_resp(fc))) {
876 dev_kfree_skb_any(skb);
877 } else {
878 _rtl_pci_rx_to_mac80211(hw, skb, rx_status);
879 }
880 } else {
881 dev_kfree_skb_any(skb);
882 }
883 new_trx_end:
884 if (rtlpriv->use_new_trx_flow) {
885 rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
886 rtlpci->rx_ring[hw_queue].next_rx_rp %=
887 RTL_PCI_MAX_RX_COUNT;
888
889 rx_remained_cnt--;
890 rtl_write_word(rtlpriv, 0x3B4,
891 rtlpci->rx_ring[hw_queue].next_rx_rp);
892 }
893 if (((rtlpriv->link_info.num_rx_inperiod +
894 rtlpriv->link_info.num_tx_inperiod) > 8) ||
895 rtlpriv->link_info.num_rx_inperiod > 2)
896 rtl_lps_leave(hw);
897 skb = new_skb;
898 no_new:
899 if (rtlpriv->use_new_trx_flow) {
900 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc,
901 rxring_idx,
902 rtlpci->rx_ring[rxring_idx].idx);
903 } else {
904 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc,
905 rxring_idx,
906 rtlpci->rx_ring[rxring_idx].idx);
907 if (rtlpci->rx_ring[rxring_idx].idx ==
908 rtlpci->rxringcount - 1)
909 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
910 false,
911 HW_DESC_RXERO,
912 (u8 *)&tmp_one);
913 }
914 rtlpci->rx_ring[rxring_idx].idx =
915 (rtlpci->rx_ring[rxring_idx].idx + 1) %
916 rtlpci->rxringcount;
917 }
918 }
919
920 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
921 {
922 struct ieee80211_hw *hw = dev_id;
923 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
924 struct rtl_priv *rtlpriv = rtl_priv(hw);
925 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
926 unsigned long flags;
927 u32 inta = 0;
928 u32 intb = 0;
929 u32 intc = 0;
930 u32 intd = 0;
931 irqreturn_t ret = IRQ_HANDLED;
932
933 if (rtlpci->irq_enabled == 0)
934 return ret;
935
936 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
937 rtlpriv->cfg->ops->disable_interrupt(hw);
938
939 /*read ISR: 4/8bytes */
940 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb, &intc, &intd);
941
942 /*Shared IRQ or HW disappeared */
943 if (!inta || inta == 0xffff)
944 goto done;
945
946 /*<1> beacon related */
947 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK])
948 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
949 "beacon ok interrupt!\n");
950
951 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER]))
952 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
953 "beacon err interrupt!\n");
954
955 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK])
956 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
957
958 if (inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
959 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
960 "prepare beacon for interrupt!\n");
961 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
962 }
963
964 /*<2> Tx related */
965 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
966 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
967
968 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
969 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
970 "Manage ok interrupt!\n");
971 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
972 }
973
974 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
975 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
976 "HIGH_QUEUE ok interrupt!\n");
977 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
978 }
979
980 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
981 rtlpriv->link_info.num_tx_inperiod++;
982
983 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
984 "BK Tx OK interrupt!\n");
985 _rtl_pci_tx_isr(hw, BK_QUEUE);
986 }
987
988 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
989 rtlpriv->link_info.num_tx_inperiod++;
990
991 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
992 "BE TX OK interrupt!\n");
993 _rtl_pci_tx_isr(hw, BE_QUEUE);
994 }
995
996 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
997 rtlpriv->link_info.num_tx_inperiod++;
998
999 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1000 "VI TX OK interrupt!\n");
1001 _rtl_pci_tx_isr(hw, VI_QUEUE);
1002 }
1003
1004 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
1005 rtlpriv->link_info.num_tx_inperiod++;
1006
1007 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1008 "Vo TX OK interrupt!\n");
1009 _rtl_pci_tx_isr(hw, VO_QUEUE);
1010 }
1011
1012 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
1013 if (intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) {
1014 rtlpriv->link_info.num_tx_inperiod++;
1015
1016 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1017 "H2C TX OK interrupt!\n");
1018 _rtl_pci_tx_isr(hw, H2C_QUEUE);
1019 }
1020 }
1021
1022 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
1023 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
1024 rtlpriv->link_info.num_tx_inperiod++;
1025
1026 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1027 "CMD TX OK interrupt!\n");
1028 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
1029 }
1030 }
1031
1032 /*<3> Rx related */
1033 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
1034 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
1035 _rtl_pci_rx_interrupt(hw);
1036 }
1037
1038 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
1039 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1040 "rx descriptor unavailable!\n");
1041 _rtl_pci_rx_interrupt(hw);
1042 }
1043
1044 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
1045 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
1046 _rtl_pci_rx_interrupt(hw);
1047 }
1048
1049 /*<4> fw related*/
1050 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
1051 if (inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
1052 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1053 "firmware interrupt!\n");
1054 queue_delayed_work(rtlpriv->works.rtl_wq,
1055 &rtlpriv->works.fwevt_wq, 0);
1056 }
1057 }
1058
1059 /*<5> hsisr related*/
1060 /* Only 8188EE & 8723BE Supported.
1061 * If Other ICs Come in, System will corrupt,
1062 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR]
1063 * are not initialized
1064 */
1065 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
1066 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1067 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
1068 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1069 "hsisr interrupt!\n");
1070 _rtl_pci_hs_interrupt(hw);
1071 }
1072 }
1073
1074 if (rtlpriv->rtlhal.earlymode_enable)
1075 tasklet_schedule(&rtlpriv->works.irq_tasklet);
1076
1077 done:
1078 rtlpriv->cfg->ops->enable_interrupt(hw);
1079 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1080 return ret;
1081 }
1082
1083 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
1084 {
1085 _rtl_pci_tx_chk_waitq(hw);
1086 }
1087
1088 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
1089 {
1090 struct rtl_priv *rtlpriv = rtl_priv(hw);
1091 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1092 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1093 struct rtl8192_tx_ring *ring = NULL;
1094 struct ieee80211_hdr *hdr = NULL;
1095 struct ieee80211_tx_info *info = NULL;
1096 struct sk_buff *pskb = NULL;
1097 struct rtl_tx_desc *pdesc = NULL;
1098 struct rtl_tcb_desc tcb_desc;
1099 /*This is for new trx flow*/
1100 struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
1101 u8 temp_one = 1;
1102 u8 *entry;
1103
1104 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
1105 ring = &rtlpci->tx_ring[BEACON_QUEUE];
1106 pskb = __skb_dequeue(&ring->queue);
1107 if (rtlpriv->use_new_trx_flow)
1108 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1109 else
1110 entry = (u8 *)(&ring->desc[ring->idx]);
1111 if (pskb) {
1112 pci_unmap_single(rtlpci->pdev,
1113 rtlpriv->cfg->ops->get_desc(
1114 hw, (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
1115 pskb->len, PCI_DMA_TODEVICE);
1116 kfree_skb(pskb);
1117 }
1118
1119 /*NB: the beacon data buffer must be 32-bit aligned. */
1120 pskb = ieee80211_beacon_get(hw, mac->vif);
1121 if (!pskb)
1122 return;
1123 hdr = rtl_get_hdr(pskb);
1124 info = IEEE80211_SKB_CB(pskb);
1125 pdesc = &ring->desc[0];
1126 if (rtlpriv->use_new_trx_flow)
1127 pbuffer_desc = &ring->buffer_desc[0];
1128
1129 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1130 (u8 *)pbuffer_desc, info, NULL, pskb,
1131 BEACON_QUEUE, &tcb_desc);
1132
1133 __skb_queue_tail(&ring->queue, pskb);
1134
1135 if (rtlpriv->use_new_trx_flow) {
1136 temp_one = 4;
1137 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true,
1138 HW_DESC_OWN, (u8 *)&temp_one);
1139 } else {
1140 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1141 &temp_one);
1142 }
1143 }
1144
1145 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1146 {
1147 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1148 struct rtl_priv *rtlpriv = rtl_priv(hw);
1149 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1150 u8 i;
1151 u16 desc_num;
1152
1153 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1154 desc_num = TX_DESC_NUM_92E;
1155 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE)
1156 desc_num = TX_DESC_NUM_8822B;
1157 else
1158 desc_num = RT_TXDESC_NUM;
1159
1160 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1161 rtlpci->txringcount[i] = desc_num;
1162
1163 /*we just alloc 2 desc for beacon queue,
1164 *because we just need first desc in hw beacon.
1165 */
1166 rtlpci->txringcount[BEACON_QUEUE] = 2;
1167
1168 /*BE queue need more descriptor for performance
1169 *consideration or, No more tx desc will happen,
1170 *and may cause mac80211 mem leakage.
1171 */
1172 if (!rtl_priv(hw)->use_new_trx_flow)
1173 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1174
1175 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1176 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1177 }
1178
1179 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1180 struct pci_dev *pdev)
1181 {
1182 struct rtl_priv *rtlpriv = rtl_priv(hw);
1183 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1184 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1185 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1186
1187 rtlpci->up_first_time = true;
1188 rtlpci->being_init_adapter = false;
1189
1190 rtlhal->hw = hw;
1191 rtlpci->pdev = pdev;
1192
1193 /*Tx/Rx related var */
1194 _rtl_pci_init_trx_var(hw);
1195
1196 /*IBSS*/
1197 mac->beacon_interval = 100;
1198
1199 /*AMPDU*/
1200 mac->min_space_cfg = 0;
1201 mac->max_mss_density = 0;
1202 /*set sane AMPDU defaults */
1203 mac->current_ampdu_density = 7;
1204 mac->current_ampdu_factor = 3;
1205
1206 /*Retry Limit*/
1207 mac->retry_short = 7;
1208 mac->retry_long = 7;
1209
1210 /*QOS*/
1211 rtlpci->acm_method = EACMWAY2_SW;
1212
1213 /*task */
1214 tasklet_init(&rtlpriv->works.irq_tasklet,
1215 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1216 (unsigned long)hw);
1217 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1218 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1219 (unsigned long)hw);
1220 INIT_WORK(&rtlpriv->works.lps_change_work,
1221 rtl_lps_change_work_callback);
1222 }
1223
1224 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1225 unsigned int prio, unsigned int entries)
1226 {
1227 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1228 struct rtl_priv *rtlpriv = rtl_priv(hw);
1229 struct rtl_tx_buffer_desc *buffer_desc;
1230 struct rtl_tx_desc *desc;
1231 dma_addr_t buffer_desc_dma, desc_dma;
1232 u32 nextdescaddress;
1233 int i;
1234
1235 /* alloc tx buffer desc for new trx flow*/
1236 if (rtlpriv->use_new_trx_flow) {
1237 buffer_desc =
1238 pci_zalloc_consistent(rtlpci->pdev,
1239 sizeof(*buffer_desc) * entries,
1240 &buffer_desc_dma);
1241
1242 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
1243 pr_err("Cannot allocate TX ring (prio = %d)\n",
1244 prio);
1245 return -ENOMEM;
1246 }
1247
1248 rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1249 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1250
1251 rtlpci->tx_ring[prio].cur_tx_rp = 0;
1252 rtlpci->tx_ring[prio].cur_tx_wp = 0;
1253 rtlpci->tx_ring[prio].avl_desc = entries;
1254 }
1255
1256 /* alloc dma for this ring */
1257 desc = pci_zalloc_consistent(rtlpci->pdev,
1258 sizeof(*desc) * entries, &desc_dma);
1259
1260 if (!desc || (unsigned long)desc & 0xFF) {
1261 pr_err("Cannot allocate TX ring (prio = %d)\n", prio);
1262 return -ENOMEM;
1263 }
1264
1265 rtlpci->tx_ring[prio].desc = desc;
1266 rtlpci->tx_ring[prio].dma = desc_dma;
1267
1268 rtlpci->tx_ring[prio].idx = 0;
1269 rtlpci->tx_ring[prio].entries = entries;
1270 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1271
1272 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1273 prio, desc);
1274
1275 /* init every desc in this ring */
1276 if (!rtlpriv->use_new_trx_flow) {
1277 for (i = 0; i < entries; i++) {
1278 nextdescaddress = (u32)desc_dma +
1279 ((i + 1) % entries) *
1280 sizeof(*desc);
1281
1282 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i],
1283 true,
1284 HW_DESC_TX_NEXTDESC_ADDR,
1285 (u8 *)&nextdescaddress);
1286 }
1287 }
1288 return 0;
1289 }
1290
1291 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1292 {
1293 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1294 struct rtl_priv *rtlpriv = rtl_priv(hw);
1295 int i;
1296
1297 if (rtlpriv->use_new_trx_flow) {
1298 struct rtl_rx_buffer_desc *entry = NULL;
1299 /* alloc dma for this ring */
1300 rtlpci->rx_ring[rxring_idx].buffer_desc =
1301 pci_zalloc_consistent(rtlpci->pdev,
1302 sizeof(*rtlpci->rx_ring[rxring_idx].
1303 buffer_desc) *
1304 rtlpci->rxringcount,
1305 &rtlpci->rx_ring[rxring_idx].dma);
1306 if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1307 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
1308 pr_err("Cannot allocate RX ring\n");
1309 return -ENOMEM;
1310 }
1311
1312 /* init every desc in this ring */
1313 rtlpci->rx_ring[rxring_idx].idx = 0;
1314 for (i = 0; i < rtlpci->rxringcount; i++) {
1315 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
1316 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1317 rxring_idx, i))
1318 return -ENOMEM;
1319 }
1320 } else {
1321 struct rtl_rx_desc *entry = NULL;
1322 u8 tmp_one = 1;
1323 /* alloc dma for this ring */
1324 rtlpci->rx_ring[rxring_idx].desc =
1325 pci_zalloc_consistent(rtlpci->pdev,
1326 sizeof(*rtlpci->rx_ring[rxring_idx].
1327 desc) * rtlpci->rxringcount,
1328 &rtlpci->rx_ring[rxring_idx].dma);
1329 if (!rtlpci->rx_ring[rxring_idx].desc ||
1330 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
1331 pr_err("Cannot allocate RX ring\n");
1332 return -ENOMEM;
1333 }
1334
1335 /* init every desc in this ring */
1336 rtlpci->rx_ring[rxring_idx].idx = 0;
1337
1338 for (i = 0; i < rtlpci->rxringcount; i++) {
1339 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1340 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1341 rxring_idx, i))
1342 return -ENOMEM;
1343 }
1344
1345 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1346 HW_DESC_RXERO, &tmp_one);
1347 }
1348 return 0;
1349 }
1350
1351 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1352 unsigned int prio)
1353 {
1354 struct rtl_priv *rtlpriv = rtl_priv(hw);
1355 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1356 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1357
1358 /* free every desc in this ring */
1359 while (skb_queue_len(&ring->queue)) {
1360 u8 *entry;
1361 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1362
1363 if (rtlpriv->use_new_trx_flow)
1364 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1365 else
1366 entry = (u8 *)(&ring->desc[ring->idx]);
1367
1368 pci_unmap_single(rtlpci->pdev,
1369 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1370 true,
1371 HW_DESC_TXBUFF_ADDR),
1372 skb->len, PCI_DMA_TODEVICE);
1373 kfree_skb(skb);
1374 ring->idx = (ring->idx + 1) % ring->entries;
1375 }
1376
1377 /* free dma of this ring */
1378 pci_free_consistent(rtlpci->pdev,
1379 sizeof(*ring->desc) * ring->entries,
1380 ring->desc, ring->dma);
1381 ring->desc = NULL;
1382 if (rtlpriv->use_new_trx_flow) {
1383 pci_free_consistent(rtlpci->pdev,
1384 sizeof(*ring->buffer_desc) * ring->entries,
1385 ring->buffer_desc, ring->buffer_desc_dma);
1386 ring->buffer_desc = NULL;
1387 }
1388 }
1389
1390 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1391 {
1392 struct rtl_priv *rtlpriv = rtl_priv(hw);
1393 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1394 int i;
1395
1396 /* free every desc in this ring */
1397 for (i = 0; i < rtlpci->rxringcount; i++) {
1398 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
1399
1400 if (!skb)
1401 continue;
1402 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
1403 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
1404 kfree_skb(skb);
1405 }
1406
1407 /* free dma of this ring */
1408 if (rtlpriv->use_new_trx_flow) {
1409 pci_free_consistent(rtlpci->pdev,
1410 sizeof(*rtlpci->rx_ring[rxring_idx].
1411 buffer_desc) * rtlpci->rxringcount,
1412 rtlpci->rx_ring[rxring_idx].buffer_desc,
1413 rtlpci->rx_ring[rxring_idx].dma);
1414 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1415 } else {
1416 pci_free_consistent(rtlpci->pdev,
1417 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1418 rtlpci->rxringcount,
1419 rtlpci->rx_ring[rxring_idx].desc,
1420 rtlpci->rx_ring[rxring_idx].dma);
1421 rtlpci->rx_ring[rxring_idx].desc = NULL;
1422 }
1423 }
1424
1425 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1426 {
1427 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1428 int ret;
1429 int i, rxring_idx;
1430
1431 /* rxring_idx 0:RX_MPDU_QUEUE
1432 * rxring_idx 1:RX_CMD_QUEUE
1433 */
1434 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1435 ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1436 if (ret)
1437 return ret;
1438 }
1439
1440 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1441 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]);
1442 if (ret)
1443 goto err_free_rings;
1444 }
1445
1446 return 0;
1447
1448 err_free_rings:
1449 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1450 _rtl_pci_free_rx_ring(hw, rxring_idx);
1451
1452 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1453 if (rtlpci->tx_ring[i].desc ||
1454 rtlpci->tx_ring[i].buffer_desc)
1455 _rtl_pci_free_tx_ring(hw, i);
1456
1457 return 1;
1458 }
1459
1460 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1461 {
1462 u32 i, rxring_idx;
1463
1464 /*free rx rings */
1465 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1466 _rtl_pci_free_rx_ring(hw, rxring_idx);
1467
1468 /*free tx rings */
1469 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1470 _rtl_pci_free_tx_ring(hw, i);
1471
1472 return 0;
1473 }
1474
1475 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1476 {
1477 struct rtl_priv *rtlpriv = rtl_priv(hw);
1478 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1479 int i, rxring_idx;
1480 unsigned long flags;
1481 u8 tmp_one = 1;
1482 u32 bufferaddress;
1483 /* rxring_idx 0:RX_MPDU_QUEUE */
1484 /* rxring_idx 1:RX_CMD_QUEUE */
1485 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1486 /* force the rx_ring[RX_MPDU_QUEUE/
1487 * RX_CMD_QUEUE].idx to the first one
1488 *new trx flow, do nothing
1489 */
1490 if (!rtlpriv->use_new_trx_flow &&
1491 rtlpci->rx_ring[rxring_idx].desc) {
1492 struct rtl_rx_desc *entry = NULL;
1493
1494 rtlpci->rx_ring[rxring_idx].idx = 0;
1495 for (i = 0; i < rtlpci->rxringcount; i++) {
1496 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1497 bufferaddress =
1498 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1499 false, HW_DESC_RXBUFF_ADDR);
1500 memset((u8 *)entry, 0,
1501 sizeof(*rtlpci->rx_ring
1502 [rxring_idx].desc));/*clear one entry*/
1503 if (rtlpriv->use_new_trx_flow) {
1504 rtlpriv->cfg->ops->set_desc(hw,
1505 (u8 *)entry, false,
1506 HW_DESC_RX_PREPARE,
1507 (u8 *)&bufferaddress);
1508 } else {
1509 rtlpriv->cfg->ops->set_desc(hw,
1510 (u8 *)entry, false,
1511 HW_DESC_RXBUFF_ADDR,
1512 (u8 *)&bufferaddress);
1513 rtlpriv->cfg->ops->set_desc(hw,
1514 (u8 *)entry, false,
1515 HW_DESC_RXPKT_LEN,
1516 (u8 *)&rtlpci->rxbuffersize);
1517 rtlpriv->cfg->ops->set_desc(hw,
1518 (u8 *)entry, false,
1519 HW_DESC_RXOWN,
1520 (u8 *)&tmp_one);
1521 }
1522 }
1523 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1524 HW_DESC_RXERO, (u8 *)&tmp_one);
1525 }
1526 rtlpci->rx_ring[rxring_idx].idx = 0;
1527 }
1528
1529 /*after reset, release previous pending packet,
1530 *and force the tx idx to the first one
1531 */
1532 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1533 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1534 if (rtlpci->tx_ring[i].desc ||
1535 rtlpci->tx_ring[i].buffer_desc) {
1536 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1537
1538 while (skb_queue_len(&ring->queue)) {
1539 u8 *entry;
1540 struct sk_buff *skb =
1541 __skb_dequeue(&ring->queue);
1542 if (rtlpriv->use_new_trx_flow)
1543 entry = (u8 *)(&ring->buffer_desc
1544 [ring->idx]);
1545 else
1546 entry = (u8 *)(&ring->desc[ring->idx]);
1547
1548 pci_unmap_single(rtlpci->pdev,
1549 rtlpriv->cfg->ops->
1550 get_desc(hw, (u8 *)
1551 entry,
1552 true,
1553 HW_DESC_TXBUFF_ADDR),
1554 skb->len, PCI_DMA_TODEVICE);
1555 dev_kfree_skb_irq(skb);
1556 ring->idx = (ring->idx + 1) % ring->entries;
1557 }
1558
1559 if (rtlpriv->use_new_trx_flow) {
1560 rtlpci->tx_ring[i].cur_tx_rp = 0;
1561 rtlpci->tx_ring[i].cur_tx_wp = 0;
1562 }
1563
1564 ring->idx = 0;
1565 ring->entries = rtlpci->txringcount[i];
1566 }
1567 }
1568 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1569
1570 return 0;
1571 }
1572
1573 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1574 struct ieee80211_sta *sta,
1575 struct sk_buff *skb)
1576 {
1577 struct rtl_priv *rtlpriv = rtl_priv(hw);
1578 struct rtl_sta_info *sta_entry = NULL;
1579 u8 tid = rtl_get_tid(skb);
1580 __le16 fc = rtl_get_fc(skb);
1581
1582 if (!sta)
1583 return false;
1584 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1585
1586 if (!rtlpriv->rtlhal.earlymode_enable)
1587 return false;
1588 if (ieee80211_is_nullfunc(fc))
1589 return false;
1590 if (ieee80211_is_qos_nullfunc(fc))
1591 return false;
1592 if (ieee80211_is_pspoll(fc))
1593 return false;
1594 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1595 return false;
1596 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1597 return false;
1598 if (tid > 7)
1599 return false;
1600
1601 /* maybe every tid should be checked */
1602 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1603 return false;
1604
1605 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1606 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1607 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1608
1609 return true;
1610 }
1611
1612 static int rtl_pci_tx(struct ieee80211_hw *hw,
1613 struct ieee80211_sta *sta,
1614 struct sk_buff *skb,
1615 struct rtl_tcb_desc *ptcb_desc)
1616 {
1617 struct rtl_priv *rtlpriv = rtl_priv(hw);
1618 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1619 struct rtl8192_tx_ring *ring;
1620 struct rtl_tx_desc *pdesc;
1621 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
1622 u16 idx;
1623 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1624 unsigned long flags;
1625 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1626 __le16 fc = rtl_get_fc(skb);
1627 u8 *pda_addr = hdr->addr1;
1628 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1629 u8 own;
1630 u8 temp_one = 1;
1631
1632 if (ieee80211_is_mgmt(fc))
1633 rtl_tx_mgmt_proc(hw, skb);
1634
1635 if (rtlpriv->psc.sw_ps_enabled) {
1636 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1637 !ieee80211_has_pm(fc))
1638 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1639 }
1640
1641 rtl_action_proc(hw, skb, true);
1642
1643 if (is_multicast_ether_addr(pda_addr))
1644 rtlpriv->stats.txbytesmulticast += skb->len;
1645 else if (is_broadcast_ether_addr(pda_addr))
1646 rtlpriv->stats.txbytesbroadcast += skb->len;
1647 else
1648 rtlpriv->stats.txbytesunicast += skb->len;
1649
1650 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1651 ring = &rtlpci->tx_ring[hw_queue];
1652 if (hw_queue != BEACON_QUEUE) {
1653 if (rtlpriv->use_new_trx_flow)
1654 idx = ring->cur_tx_wp;
1655 else
1656 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1657 ring->entries;
1658 } else {
1659 idx = 0;
1660 }
1661
1662 pdesc = &ring->desc[idx];
1663 if (rtlpriv->use_new_trx_flow) {
1664 ptx_bd_desc = &ring->buffer_desc[idx];
1665 } else {
1666 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
1667 true, HW_DESC_OWN);
1668
1669 if (own == 1 && hw_queue != BEACON_QUEUE) {
1670 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1671 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1672 hw_queue, ring->idx, idx,
1673 skb_queue_len(&ring->queue));
1674
1675 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1676 flags);
1677 return skb->len;
1678 }
1679 }
1680
1681 if (rtlpriv->cfg->ops->get_available_desc &&
1682 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) {
1683 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1684 "get_available_desc fail\n");
1685 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1686 return skb->len;
1687 }
1688
1689 if (ieee80211_is_data(fc))
1690 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1691
1692 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1693 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc);
1694
1695 __skb_queue_tail(&ring->queue, skb);
1696
1697 if (rtlpriv->use_new_trx_flow) {
1698 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1699 HW_DESC_OWN, &hw_queue);
1700 } else {
1701 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1702 HW_DESC_OWN, &temp_one);
1703 }
1704
1705 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1706 hw_queue != BEACON_QUEUE) {
1707 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1708 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1709 hw_queue, ring->idx, idx,
1710 skb_queue_len(&ring->queue));
1711
1712 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1713 }
1714
1715 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1716
1717 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1718
1719 return 0;
1720 }
1721
1722 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1723 {
1724 struct rtl_priv *rtlpriv = rtl_priv(hw);
1725 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1726 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1727 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1728 u16 i = 0;
1729 int queue_id;
1730 struct rtl8192_tx_ring *ring;
1731
1732 if (mac->skip_scan)
1733 return;
1734
1735 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1736 u32 queue_len;
1737
1738 if (((queues >> queue_id) & 0x1) == 0) {
1739 queue_id--;
1740 continue;
1741 }
1742 ring = &pcipriv->dev.tx_ring[queue_id];
1743 queue_len = skb_queue_len(&ring->queue);
1744 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1745 queue_id == TXCMD_QUEUE) {
1746 queue_id--;
1747 continue;
1748 } else {
1749 msleep(20);
1750 i++;
1751 }
1752
1753 /* we just wait 1s for all queues */
1754 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1755 is_hal_stop(rtlhal) || i >= 200)
1756 return;
1757 }
1758 }
1759
1760 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1761 {
1762 struct rtl_priv *rtlpriv = rtl_priv(hw);
1763 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1764
1765 _rtl_pci_deinit_trx_ring(hw);
1766
1767 synchronize_irq(rtlpci->pdev->irq);
1768 tasklet_kill(&rtlpriv->works.irq_tasklet);
1769 cancel_work_sync(&rtlpriv->works.lps_change_work);
1770
1771 flush_workqueue(rtlpriv->works.rtl_wq);
1772 destroy_workqueue(rtlpriv->works.rtl_wq);
1773 }
1774
1775 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1776 {
1777 int err;
1778
1779 _rtl_pci_init_struct(hw, pdev);
1780
1781 err = _rtl_pci_init_trx_ring(hw);
1782 if (err) {
1783 pr_err("tx ring initialization failed\n");
1784 return err;
1785 }
1786
1787 return 0;
1788 }
1789
1790 static int rtl_pci_start(struct ieee80211_hw *hw)
1791 {
1792 struct rtl_priv *rtlpriv = rtl_priv(hw);
1793 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1794 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1795 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1796 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
1797
1798 int err;
1799
1800 rtl_pci_reset_trx_ring(hw);
1801
1802 rtlpci->driver_is_goingto_unload = false;
1803 if (rtlpriv->cfg->ops->get_btc_status &&
1804 rtlpriv->cfg->ops->get_btc_status()) {
1805 rtlpriv->btcoexist.btc_info.ap_num = 36;
1806 rtlpriv->btcoexist.btc_ops->btc_init_variables(rtlpriv);
1807 rtlpriv->btcoexist.btc_ops->btc_init_hal_vars(rtlpriv);
1808 }
1809 err = rtlpriv->cfg->ops->hw_init(hw);
1810 if (err) {
1811 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1812 "Failed to config hardware!\n");
1813 return err;
1814 }
1815 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
1816 &rtlmac->retry_long);
1817
1818 rtlpriv->cfg->ops->enable_interrupt(hw);
1819 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1820
1821 rtl_init_rx_config(hw);
1822
1823 /*should be after adapter start and interrupt enable. */
1824 set_hal_start(rtlhal);
1825
1826 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1827
1828 rtlpci->up_first_time = false;
1829
1830 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__);
1831 return 0;
1832 }
1833
1834 static void rtl_pci_stop(struct ieee80211_hw *hw)
1835 {
1836 struct rtl_priv *rtlpriv = rtl_priv(hw);
1837 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1838 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1839 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1840 unsigned long flags;
1841 u8 rf_timeout = 0;
1842
1843 if (rtlpriv->cfg->ops->get_btc_status())
1844 rtlpriv->btcoexist.btc_ops->btc_halt_notify();
1845
1846 /*should be before disable interrupt&adapter
1847 *and will do it immediately.
1848 */
1849 set_hal_stop(rtlhal);
1850
1851 rtlpci->driver_is_goingto_unload = true;
1852 rtlpriv->cfg->ops->disable_interrupt(hw);
1853 cancel_work_sync(&rtlpriv->works.lps_change_work);
1854
1855 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1856 while (ppsc->rfchange_inprogress) {
1857 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1858 if (rf_timeout > 100) {
1859 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1860 break;
1861 }
1862 mdelay(1);
1863 rf_timeout++;
1864 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1865 }
1866 ppsc->rfchange_inprogress = true;
1867 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1868
1869 rtlpriv->cfg->ops->hw_disable(hw);
1870 /* some things are not needed if firmware not available */
1871 if (!rtlpriv->max_fw_size)
1872 return;
1873 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1874
1875 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1876 ppsc->rfchange_inprogress = false;
1877 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1878
1879 rtl_pci_enable_aspm(hw);
1880 }
1881
1882 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1883 struct ieee80211_hw *hw)
1884 {
1885 struct rtl_priv *rtlpriv = rtl_priv(hw);
1886 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1887 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1888 struct pci_dev *bridge_pdev = pdev->bus->self;
1889 u16 venderid;
1890 u16 deviceid;
1891 u8 revisionid;
1892 u16 irqline;
1893 u8 tmp;
1894
1895 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1896 venderid = pdev->vendor;
1897 deviceid = pdev->device;
1898 pci_read_config_byte(pdev, 0x8, &revisionid);
1899 pci_read_config_word(pdev, 0x3C, &irqline);
1900
1901 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1902 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1903 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1904 * the correct driver is r8192e_pci, thus this routine should
1905 * return false.
1906 */
1907 if (deviceid == RTL_PCI_8192SE_DID &&
1908 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1909 return false;
1910
1911 if (deviceid == RTL_PCI_8192_DID ||
1912 deviceid == RTL_PCI_0044_DID ||
1913 deviceid == RTL_PCI_0047_DID ||
1914 deviceid == RTL_PCI_8192SE_DID ||
1915 deviceid == RTL_PCI_8174_DID ||
1916 deviceid == RTL_PCI_8173_DID ||
1917 deviceid == RTL_PCI_8172_DID ||
1918 deviceid == RTL_PCI_8171_DID) {
1919 switch (revisionid) {
1920 case RTL_PCI_REVISION_ID_8192PCIE:
1921 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1922 "8192 PCI-E is found - vid/did=%x/%x\n",
1923 venderid, deviceid);
1924 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1925 return false;
1926 case RTL_PCI_REVISION_ID_8192SE:
1927 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1928 "8192SE is found - vid/did=%x/%x\n",
1929 venderid, deviceid);
1930 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1931 break;
1932 default:
1933 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1934 "Err: Unknown device - vid/did=%x/%x\n",
1935 venderid, deviceid);
1936 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1937 break;
1938 }
1939 } else if (deviceid == RTL_PCI_8723AE_DID) {
1940 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1941 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1942 "8723AE PCI-E is found - vid/did=%x/%x\n",
1943 venderid, deviceid);
1944 } else if (deviceid == RTL_PCI_8192CET_DID ||
1945 deviceid == RTL_PCI_8192CE_DID ||
1946 deviceid == RTL_PCI_8191CE_DID ||
1947 deviceid == RTL_PCI_8188CE_DID) {
1948 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1949 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1950 "8192C PCI-E is found - vid/did=%x/%x\n",
1951 venderid, deviceid);
1952 } else if (deviceid == RTL_PCI_8192DE_DID ||
1953 deviceid == RTL_PCI_8192DE_DID2) {
1954 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1955 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1956 "8192D PCI-E is found - vid/did=%x/%x\n",
1957 venderid, deviceid);
1958 } else if (deviceid == RTL_PCI_8188EE_DID) {
1959 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
1960 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1961 "Find adapter, Hardware type is 8188EE\n");
1962 } else if (deviceid == RTL_PCI_8723BE_DID) {
1963 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
1964 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1965 "Find adapter, Hardware type is 8723BE\n");
1966 } else if (deviceid == RTL_PCI_8192EE_DID) {
1967 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
1968 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1969 "Find adapter, Hardware type is 8192EE\n");
1970 } else if (deviceid == RTL_PCI_8821AE_DID) {
1971 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
1972 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1973 "Find adapter, Hardware type is 8821AE\n");
1974 } else if (deviceid == RTL_PCI_8812AE_DID) {
1975 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
1976 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1977 "Find adapter, Hardware type is 8812AE\n");
1978 } else if (deviceid == RTL_PCI_8822BE_DID) {
1979 rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE;
1980 rtlhal->bandset = BAND_ON_BOTH;
1981 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1982 "Find adapter, Hardware type is 8822BE\n");
1983 } else {
1984 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1985 "Err: Unknown device - vid/did=%x/%x\n",
1986 venderid, deviceid);
1987
1988 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1989 }
1990
1991 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1992 if (revisionid == 0 || revisionid == 1) {
1993 if (revisionid == 0) {
1994 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1995 "Find 92DE MAC0\n");
1996 rtlhal->interfaceindex = 0;
1997 } else if (revisionid == 1) {
1998 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1999 "Find 92DE MAC1\n");
2000 rtlhal->interfaceindex = 1;
2001 }
2002 } else {
2003 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2004 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
2005 venderid, deviceid, revisionid);
2006 rtlhal->interfaceindex = 0;
2007 }
2008 }
2009
2010 switch (rtlhal->hw_type) {
2011 case HARDWARE_TYPE_RTL8192EE:
2012 case HARDWARE_TYPE_RTL8822BE:
2013 /* use new trx flow */
2014 rtlpriv->use_new_trx_flow = true;
2015 break;
2016
2017 default:
2018 rtlpriv->use_new_trx_flow = false;
2019 break;
2020 }
2021
2022 /*find bus info */
2023 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
2024 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
2025 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
2026
2027 /*find bridge info */
2028 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
2029 /* some ARM have no bridge_pdev and will crash here
2030 * so we should check if bridge_pdev is NULL
2031 */
2032 if (bridge_pdev) {
2033 /*find bridge info if available */
2034 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
2035 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
2036 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
2037 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
2038 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2039 "Pci Bridge Vendor is found index: %d\n",
2040 tmp);
2041 break;
2042 }
2043 }
2044 }
2045
2046 if (pcipriv->ndis_adapter.pcibridge_vendor !=
2047 PCI_BRIDGE_VENDOR_UNKNOWN) {
2048 pcipriv->ndis_adapter.pcibridge_busnum =
2049 bridge_pdev->bus->number;
2050 pcipriv->ndis_adapter.pcibridge_devnum =
2051 PCI_SLOT(bridge_pdev->devfn);
2052 pcipriv->ndis_adapter.pcibridge_funcnum =
2053 PCI_FUNC(bridge_pdev->devfn);
2054 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
2055 pci_pcie_cap(bridge_pdev);
2056 pcipriv->ndis_adapter.num4bytes =
2057 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
2058
2059 rtl_pci_get_linkcontrol_field(hw);
2060
2061 if (pcipriv->ndis_adapter.pcibridge_vendor ==
2062 PCI_BRIDGE_VENDOR_AMD) {
2063 pcipriv->ndis_adapter.amd_l1_patch =
2064 rtl_pci_get_amd_l1_patch(hw);
2065 }
2066 }
2067
2068 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2069 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
2070 pcipriv->ndis_adapter.busnumber,
2071 pcipriv->ndis_adapter.devnumber,
2072 pcipriv->ndis_adapter.funcnumber,
2073 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
2074
2075 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2076 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
2077 pcipriv->ndis_adapter.pcibridge_busnum,
2078 pcipriv->ndis_adapter.pcibridge_devnum,
2079 pcipriv->ndis_adapter.pcibridge_funcnum,
2080 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
2081 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
2082 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
2083 pcipriv->ndis_adapter.amd_l1_patch);
2084
2085 rtl_pci_parse_configuration(pdev, hw);
2086 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
2087
2088 return true;
2089 }
2090
2091 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
2092 {
2093 struct rtl_priv *rtlpriv = rtl_priv(hw);
2094 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2095 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2096 int ret;
2097
2098 ret = pci_enable_msi(rtlpci->pdev);
2099 if (ret < 0)
2100 return ret;
2101
2102 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2103 IRQF_SHARED, KBUILD_MODNAME, hw);
2104 if (ret < 0) {
2105 pci_disable_msi(rtlpci->pdev);
2106 return ret;
2107 }
2108
2109 rtlpci->using_msi = true;
2110
2111 RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2112 "MSI Interrupt Mode!\n");
2113 return 0;
2114 }
2115
2116 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2117 {
2118 struct rtl_priv *rtlpriv = rtl_priv(hw);
2119 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2120 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2121 int ret;
2122
2123 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2124 IRQF_SHARED, KBUILD_MODNAME, hw);
2125 if (ret < 0)
2126 return ret;
2127
2128 rtlpci->using_msi = false;
2129 RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2130 "Pin-based Interrupt Mode!\n");
2131 return 0;
2132 }
2133
2134 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2135 {
2136 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2137 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2138 int ret;
2139
2140 if (rtlpci->msi_support) {
2141 ret = rtl_pci_intr_mode_msi(hw);
2142 if (ret < 0)
2143 ret = rtl_pci_intr_mode_legacy(hw);
2144 } else {
2145 ret = rtl_pci_intr_mode_legacy(hw);
2146 }
2147 return ret;
2148 }
2149
2150 static void platform_enable_dma64(struct pci_dev *pdev, bool dma64)
2151 {
2152 u8 value;
2153
2154 pci_read_config_byte(pdev, 0x719, &value);
2155
2156 /* 0x719 Bit5 is DMA64 bit fetch. */
2157 if (dma64)
2158 value |= BIT(5);
2159 else
2160 value &= ~BIT(5);
2161
2162 pci_write_config_byte(pdev, 0x719, value);
2163 }
2164
2165 int rtl_pci_probe(struct pci_dev *pdev,
2166 const struct pci_device_id *id)
2167 {
2168 struct ieee80211_hw *hw = NULL;
2169
2170 struct rtl_priv *rtlpriv = NULL;
2171 struct rtl_pci_priv *pcipriv = NULL;
2172 struct rtl_pci *rtlpci;
2173 unsigned long pmem_start, pmem_len, pmem_flags;
2174 int err;
2175
2176 err = pci_enable_device(pdev);
2177 if (err) {
2178 WARN_ONCE(true, "%s : Cannot enable new PCI device\n",
2179 pci_name(pdev));
2180 return err;
2181 }
2182
2183 if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 &&
2184 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2185 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2186 WARN_ONCE(true,
2187 "Unable to obtain 64bit DMA for consistent allocations\n");
2188 err = -ENOMEM;
2189 goto fail1;
2190 }
2191
2192 platform_enable_dma64(pdev, true);
2193 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
2194 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
2195 WARN_ONCE(true,
2196 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n");
2197 err = -ENOMEM;
2198 goto fail1;
2199 }
2200
2201 platform_enable_dma64(pdev, false);
2202 }
2203
2204 pci_set_master(pdev);
2205
2206 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2207 sizeof(struct rtl_priv), &rtl_ops);
2208 if (!hw) {
2209 WARN_ONCE(true,
2210 "%s : ieee80211 alloc failed\n", pci_name(pdev));
2211 err = -ENOMEM;
2212 goto fail1;
2213 }
2214
2215 SET_IEEE80211_DEV(hw, &pdev->dev);
2216 pci_set_drvdata(pdev, hw);
2217
2218 rtlpriv = hw->priv;
2219 rtlpriv->hw = hw;
2220 pcipriv = (void *)rtlpriv->priv;
2221 pcipriv->dev.pdev = pdev;
2222 init_completion(&rtlpriv->firmware_loading_complete);
2223 /*proximity init here*/
2224 rtlpriv->proximity.proxim_on = false;
2225
2226 pcipriv = (void *)rtlpriv->priv;
2227 pcipriv->dev.pdev = pdev;
2228
2229 /* init cfg & intf_ops */
2230 rtlpriv->rtlhal.interface = INTF_PCI;
2231 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2232 rtlpriv->intf_ops = &rtl_pci_ops;
2233 rtlpriv->glb_var = &rtl_global_var;
2234
2235 /* MEM map */
2236 err = pci_request_regions(pdev, KBUILD_MODNAME);
2237 if (err) {
2238 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n");
2239 goto fail1;
2240 }
2241
2242 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2243 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2244 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
2245
2246 /*shared mem start */
2247 rtlpriv->io.pci_mem_start =
2248 (unsigned long)pci_iomap(pdev,
2249 rtlpriv->cfg->bar_id, pmem_len);
2250 if (rtlpriv->io.pci_mem_start == 0) {
2251 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n");
2252 err = -ENOMEM;
2253 goto fail2;
2254 }
2255
2256 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2257 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
2258 pmem_start, pmem_len, pmem_flags,
2259 rtlpriv->io.pci_mem_start);
2260
2261 /* Disable Clk Request */
2262 pci_write_config_byte(pdev, 0x81, 0);
2263 /* leave D3 mode */
2264 pci_write_config_byte(pdev, 0x44, 0);
2265 pci_write_config_byte(pdev, 0x04, 0x06);
2266 pci_write_config_byte(pdev, 0x04, 0x07);
2267
2268 /* find adapter */
2269 if (!_rtl_pci_find_adapter(pdev, hw)) {
2270 err = -ENODEV;
2271 goto fail2;
2272 }
2273
2274 /* Init IO handler */
2275 _rtl_pci_io_handler_init(&pdev->dev, hw);
2276
2277 /*like read eeprom and so on */
2278 rtlpriv->cfg->ops->read_eeprom_info(hw);
2279
2280 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
2281 pr_err("Can't init_sw_vars\n");
2282 err = -ENODEV;
2283 goto fail3;
2284 }
2285 rtlpriv->cfg->ops->init_sw_leds(hw);
2286
2287 /*aspm */
2288 rtl_pci_init_aspm(hw);
2289
2290 /* Init mac80211 sw */
2291 err = rtl_init_core(hw);
2292 if (err) {
2293 pr_err("Can't allocate sw for mac80211\n");
2294 goto fail3;
2295 }
2296
2297 /* Init PCI sw */
2298 err = rtl_pci_init(hw, pdev);
2299 if (err) {
2300 pr_err("Failed to init PCI\n");
2301 goto fail3;
2302 }
2303
2304 err = ieee80211_register_hw(hw);
2305 if (err) {
2306 pr_err("Can't register mac80211 hw.\n");
2307 err = -ENODEV;
2308 goto fail3;
2309 }
2310 rtlpriv->mac80211.mac80211_registered = 1;
2311
2312 /*init rfkill */
2313 rtl_init_rfkill(hw); /* Init PCI sw */
2314
2315 rtlpci = rtl_pcidev(pcipriv);
2316 err = rtl_pci_intr_mode_decide(hw);
2317 if (err) {
2318 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2319 "%s: failed to register IRQ handler\n",
2320 wiphy_name(hw->wiphy));
2321 goto fail3;
2322 }
2323 rtlpci->irq_alloc = 1;
2324
2325 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2326 return 0;
2327
2328 fail3:
2329 pci_set_drvdata(pdev, NULL);
2330 rtl_deinit_core(hw);
2331
2332 fail2:
2333 if (rtlpriv->io.pci_mem_start != 0)
2334 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2335
2336 pci_release_regions(pdev);
2337 complete(&rtlpriv->firmware_loading_complete);
2338
2339 fail1:
2340 if (hw)
2341 ieee80211_free_hw(hw);
2342 pci_disable_device(pdev);
2343
2344 return err;
2345 }
2346 EXPORT_SYMBOL(rtl_pci_probe);
2347
2348 void rtl_pci_disconnect(struct pci_dev *pdev)
2349 {
2350 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2351 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2352 struct rtl_priv *rtlpriv = rtl_priv(hw);
2353 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2354 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2355
2356 /* just in case driver is removed before firmware callback */
2357 wait_for_completion(&rtlpriv->firmware_loading_complete);
2358 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2359
2360 /*ieee80211_unregister_hw will call ops_stop */
2361 if (rtlmac->mac80211_registered == 1) {
2362 ieee80211_unregister_hw(hw);
2363 rtlmac->mac80211_registered = 0;
2364 } else {
2365 rtl_deinit_deferred_work(hw, false);
2366 rtlpriv->intf_ops->adapter_stop(hw);
2367 }
2368 rtlpriv->cfg->ops->disable_interrupt(hw);
2369
2370 /*deinit rfkill */
2371 rtl_deinit_rfkill(hw);
2372
2373 rtl_pci_deinit(hw);
2374 rtl_deinit_core(hw);
2375 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2376
2377 if (rtlpci->irq_alloc) {
2378 free_irq(rtlpci->pdev->irq, hw);
2379 rtlpci->irq_alloc = 0;
2380 }
2381
2382 if (rtlpci->using_msi)
2383 pci_disable_msi(rtlpci->pdev);
2384
2385 list_del(&rtlpriv->list);
2386 if (rtlpriv->io.pci_mem_start != 0) {
2387 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2388 pci_release_regions(pdev);
2389 }
2390
2391 pci_disable_device(pdev);
2392
2393 rtl_pci_disable_aspm(hw);
2394
2395 pci_set_drvdata(pdev, NULL);
2396
2397 ieee80211_free_hw(hw);
2398 }
2399 EXPORT_SYMBOL(rtl_pci_disconnect);
2400
2401 #ifdef CONFIG_PM_SLEEP
2402 /***************************************
2403 * kernel pci power state define:
2404 * PCI_D0 ((pci_power_t __force) 0)
2405 * PCI_D1 ((pci_power_t __force) 1)
2406 * PCI_D2 ((pci_power_t __force) 2)
2407 * PCI_D3hot ((pci_power_t __force) 3)
2408 * PCI_D3cold ((pci_power_t __force) 4)
2409 * PCI_UNKNOWN ((pci_power_t __force) 5)
2410
2411 * This function is called when system
2412 * goes into suspend state mac80211 will
2413 * call rtl_mac_stop() from the mac80211
2414 * suspend function first, So there is
2415 * no need to call hw_disable here.
2416 ****************************************/
2417 int rtl_pci_suspend(struct device *dev)
2418 {
2419 struct pci_dev *pdev = to_pci_dev(dev);
2420 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2421 struct rtl_priv *rtlpriv = rtl_priv(hw);
2422
2423 rtlpriv->cfg->ops->hw_suspend(hw);
2424 rtl_deinit_rfkill(hw);
2425
2426 return 0;
2427 }
2428 EXPORT_SYMBOL(rtl_pci_suspend);
2429
2430 int rtl_pci_resume(struct device *dev)
2431 {
2432 struct pci_dev *pdev = to_pci_dev(dev);
2433 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2434 struct rtl_priv *rtlpriv = rtl_priv(hw);
2435
2436 rtlpriv->cfg->ops->hw_resume(hw);
2437 rtl_init_rfkill(hw);
2438 return 0;
2439 }
2440 EXPORT_SYMBOL(rtl_pci_resume);
2441 #endif /* CONFIG_PM_SLEEP */
2442
2443 const struct rtl_intf_ops rtl_pci_ops = {
2444 .read_efuse_byte = read_efuse_byte,
2445 .adapter_start = rtl_pci_start,
2446 .adapter_stop = rtl_pci_stop,
2447 .check_buddy_priv = rtl_pci_check_buddy_priv,
2448 .adapter_tx = rtl_pci_tx,
2449 .flush = rtl_pci_flush,
2450 .reset_trx_ring = rtl_pci_reset_trx_ring,
2451 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2452
2453 .disable_aspm = rtl_pci_disable_aspm,
2454 .enable_aspm = rtl_pci_enable_aspm,
2455 };
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