1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
44 #include <linux/module.h>
46 static void rtl92s_init_aspm_vars(struct ieee80211_hw
*hw
)
48 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
50 /*close ASPM for AMD defaultly */
51 rtlpci
->const_amdpci_aspm
= 0;
55 * 1 - Enable ASPM without Clock Req,
56 * 2 - Enable ASPM with Clock Req,
57 * 3 - Alwyas Enable ASPM with Clock Req,
58 * 4 - Always Enable ASPM without Clock Req.
59 * set defult to RTL8192CE:3 RTL8192E:2
61 rtlpci
->const_pci_aspm
= 2;
63 /*Setting for PCI-E device */
64 rtlpci
->const_devicepci_aspm_setting
= 0x03;
66 /*Setting for PCI-E bridge */
67 rtlpci
->const_hostpci_aspm_setting
= 0x02;
69 /* In Hw/Sw Radio Off situation.
71 * 1 - From ASPM setting without low Mac Pwr,
72 * 2 - From ASPM setting with low Mac Pwr,
74 * set default to RTL8192CE:0 RTL8192SE:2
76 rtlpci
->const_hwsw_rfoff_d3
= 2;
78 /* This setting works for those device with
79 * backdoor ASPM setting such as EPHY setting.
80 * 0 - Not support ASPM,
82 * 2 - According to chipset.
84 rtlpci
->const_support_pciaspm
= 2;
87 static void rtl92se_fw_cb(const struct firmware
*firmware
, void *context
)
89 struct ieee80211_hw
*hw
= context
;
90 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
91 struct rt_firmware
*pfirmware
= NULL
;
92 char *fw_name
= "rtlwifi/rtl8192sefw.bin";
94 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_LOUD
,
95 "Firmware callback routine entered!\n");
96 complete(&rtlpriv
->firmware_loading_complete
);
98 pr_err("Firmware %s not available\n", fw_name
);
99 rtlpriv
->max_fw_size
= 0;
102 if (firmware
->size
> rtlpriv
->max_fw_size
) {
103 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
104 "Firmware is too big!\n");
105 rtlpriv
->max_fw_size
= 0;
106 release_firmware(firmware
);
109 pfirmware
= (struct rt_firmware
*)rtlpriv
->rtlhal
.pfirmware
;
110 memcpy(pfirmware
->sz_fw_tmpbuffer
, firmware
->data
, firmware
->size
);
111 pfirmware
->sz_fw_tmpbufferlen
= firmware
->size
;
112 release_firmware(firmware
);
115 static int rtl92s_init_sw_vars(struct ieee80211_hw
*hw
)
117 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
118 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
120 u16 earlyrxthreshold
= 7;
121 char *fw_name
= "rtlwifi/rtl8192sefw.bin";
123 rtlpriv
->dm
.dm_initialgain_enable
= true;
124 rtlpriv
->dm
.dm_flag
= 0;
125 rtlpriv
->dm
.disable_framebursting
= false;
126 rtlpriv
->dm
.thermalvalue
= 0;
127 rtlpriv
->dm
.useramask
= true;
129 /* compatible 5G band 91se just 2.4G band & smsp */
130 rtlpriv
->rtlhal
.current_bandtype
= BAND_ON_2_4G
;
131 rtlpriv
->rtlhal
.bandset
= BAND_ON_2_4G
;
132 rtlpriv
->rtlhal
.macphymode
= SINGLEMAC_SINGLEPHY
;
134 rtlpci
->transmit_config
= 0;
136 rtlpci
->receive_config
=
145 /* Accept ICV error, CRC32 Error */
148 /* Accept Broadcast, Multicast */
150 /* Accept Physical match */
152 /* Accept Destination Address packets */
154 RCR_APP_PHYST_STAFF
|
155 /* Accept PHY status */
157 (earlyrxthreshold
<< RCR_FIFO_OFFSET
);
159 rtlpci
->irq_mask
[0] = (u32
)
179 rtlpci
->irq_mask
[1] = (u32
) 0;
181 rtlpci
->shortretry_limit
= 0x30;
182 rtlpci
->longretry_limit
= 0x30;
184 rtlpci
->first_init
= true;
186 /* for debug level */
187 rtlpriv
->dbg
.global_debuglevel
= rtlpriv
->cfg
->mod_params
->debug
;
189 rtlpriv
->psc
.inactiveps
= rtlpriv
->cfg
->mod_params
->inactiveps
;
190 rtlpriv
->psc
.swctrl_lps
= rtlpriv
->cfg
->mod_params
->swctrl_lps
;
191 rtlpriv
->psc
.fwctrl_lps
= rtlpriv
->cfg
->mod_params
->fwctrl_lps
;
192 rtlpriv
->cfg
->mod_params
->sw_crypto
=
193 rtlpriv
->cfg
->mod_params
->sw_crypto
;
194 if (!rtlpriv
->psc
.inactiveps
)
195 pr_info("Power Save off (module option)\n");
196 if (!rtlpriv
->psc
.fwctrl_lps
)
197 pr_info("FW Power Save off (module option)\n");
198 rtlpriv
->psc
.reg_fwctrl_lps
= 3;
199 rtlpriv
->psc
.reg_max_lps_awakeintvl
= 5;
200 /* for ASPM, you can close aspm through
201 * set const_support_pciaspm = 0 */
202 rtl92s_init_aspm_vars(hw
);
204 if (rtlpriv
->psc
.reg_fwctrl_lps
== 1)
205 rtlpriv
->psc
.fwctrl_psmode
= FW_PS_MIN_MODE
;
206 else if (rtlpriv
->psc
.reg_fwctrl_lps
== 2)
207 rtlpriv
->psc
.fwctrl_psmode
= FW_PS_MAX_MODE
;
208 else if (rtlpriv
->psc
.reg_fwctrl_lps
== 3)
209 rtlpriv
->psc
.fwctrl_psmode
= FW_PS_DTIM_MODE
;
211 /* for firmware buf */
212 rtlpriv
->rtlhal
.pfirmware
= vzalloc(sizeof(struct rt_firmware
));
213 if (!rtlpriv
->rtlhal
.pfirmware
)
216 rtlpriv
->max_fw_size
= RTL8190_MAX_FIRMWARE_CODE_SIZE
*2 +
217 sizeof(struct fw_hdr
);
218 pr_info("Driver for Realtek RTL8192SE/RTL8191SE\n"
219 "Loading firmware %s\n", fw_name
);
221 err
= request_firmware_nowait(THIS_MODULE
, 1, fw_name
,
222 rtlpriv
->io
.dev
, GFP_KERNEL
, hw
,
225 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
226 "Failed to request firmware!\n");
233 static void rtl92s_deinit_sw_vars(struct ieee80211_hw
*hw
)
235 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
237 if (rtlpriv
->rtlhal
.pfirmware
) {
238 vfree(rtlpriv
->rtlhal
.pfirmware
);
239 rtlpriv
->rtlhal
.pfirmware
= NULL
;
243 static bool rtl92se_is_tx_desc_closed(struct ieee80211_hw
*hw
, u8 hw_queue
,
246 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
247 struct rtl8192_tx_ring
*ring
= &rtlpci
->tx_ring
[hw_queue
];
248 u8
*entry
= (u8
*)(&ring
->desc
[ring
->idx
]);
249 u8 own
= (u8
)rtl92se_get_desc(entry
, true, HW_DESC_OWN
);
256 static struct rtl_hal_ops rtl8192se_hal_ops
= {
257 .init_sw_vars
= rtl92s_init_sw_vars
,
258 .deinit_sw_vars
= rtl92s_deinit_sw_vars
,
259 .read_eeprom_info
= rtl92se_read_eeprom_info
,
260 .interrupt_recognized
= rtl92se_interrupt_recognized
,
261 .hw_init
= rtl92se_hw_init
,
262 .hw_disable
= rtl92se_card_disable
,
263 .hw_suspend
= rtl92se_suspend
,
264 .hw_resume
= rtl92se_resume
,
265 .enable_interrupt
= rtl92se_enable_interrupt
,
266 .disable_interrupt
= rtl92se_disable_interrupt
,
267 .set_network_type
= rtl92se_set_network_type
,
268 .set_chk_bssid
= rtl92se_set_check_bssid
,
269 .set_qos
= rtl92se_set_qos
,
270 .set_bcn_reg
= rtl92se_set_beacon_related_registers
,
271 .set_bcn_intv
= rtl92se_set_beacon_interval
,
272 .update_interrupt_mask
= rtl92se_update_interrupt_mask
,
273 .get_hw_reg
= rtl92se_get_hw_reg
,
274 .set_hw_reg
= rtl92se_set_hw_reg
,
275 .update_rate_tbl
= rtl92se_update_hal_rate_tbl
,
276 .fill_tx_desc
= rtl92se_tx_fill_desc
,
277 .fill_tx_cmddesc
= rtl92se_tx_fill_cmddesc
,
278 .query_rx_desc
= rtl92se_rx_query_desc
,
279 .set_channel_access
= rtl92se_update_channel_access_setting
,
280 .radio_onoff_checking
= rtl92se_gpio_radio_on_off_checking
,
281 .set_bw_mode
= rtl92s_phy_set_bw_mode
,
282 .switch_channel
= rtl92s_phy_sw_chnl
,
283 .dm_watchdog
= rtl92s_dm_watchdog
,
284 .scan_operation_backup
= rtl92s_phy_scan_operation_backup
,
285 .set_rf_power_state
= rtl92s_phy_set_rf_power_state
,
286 .led_control
= rtl92se_led_control
,
287 .set_desc
= rtl92se_set_desc
,
288 .get_desc
= rtl92se_get_desc
,
289 .is_tx_desc_closed
= rtl92se_is_tx_desc_closed
,
290 .tx_polling
= rtl92se_tx_polling
,
291 .enable_hw_sec
= rtl92se_enable_hw_security_config
,
292 .set_key
= rtl92se_set_key
,
293 .init_sw_leds
= rtl92se_init_sw_leds
,
294 .get_bbreg
= rtl92s_phy_query_bb_reg
,
295 .set_bbreg
= rtl92s_phy_set_bb_reg
,
296 .get_rfreg
= rtl92s_phy_query_rf_reg
,
297 .set_rfreg
= rtl92s_phy_set_rf_reg
,
298 .get_btc_status
= rtl_btc_status_false
,
301 static struct rtl_mod_params rtl92se_mod_params
= {
309 /* Because memory R/W bursting will cause system hang/crash
310 * for 92se, so we don't read back after every write action */
311 static const struct rtl_hal_cfg rtl92se_hal_cfg
= {
313 .write_readback
= false,
314 .name
= "rtl92s_pci",
315 .ops
= &rtl8192se_hal_ops
,
316 .mod_params
= &rtl92se_mod_params
,
318 .maps
[SYS_ISO_CTRL
] = REG_SYS_ISO_CTRL
,
319 .maps
[SYS_FUNC_EN
] = REG_SYS_FUNC_EN
,
320 .maps
[SYS_CLK
] = SYS_CLKR
,
321 .maps
[MAC_RCR_AM
] = RCR_AM
,
322 .maps
[MAC_RCR_AB
] = RCR_AB
,
323 .maps
[MAC_RCR_ACRC32
] = RCR_ACRC32
,
324 .maps
[MAC_RCR_ACF
] = RCR_ACF
,
325 .maps
[MAC_RCR_AAP
] = RCR_AAP
,
326 .maps
[MAC_HIMR
] = INTA_MASK
,
327 .maps
[MAC_HIMRE
] = INTA_MASK
+ 4,
329 .maps
[EFUSE_TEST
] = REG_EFUSE_TEST
,
330 .maps
[EFUSE_CTRL
] = REG_EFUSE_CTRL
,
331 .maps
[EFUSE_CLK
] = REG_EFUSE_CLK
,
332 .maps
[EFUSE_CLK_CTRL
] = REG_EFUSE_CTRL
,
333 .maps
[EFUSE_PWC_EV12V
] = 0, /* nouse for 8192se */
334 .maps
[EFUSE_FEN_ELDR
] = 0, /* nouse for 8192se */
335 .maps
[EFUSE_LOADER_CLK_EN
] = 0,/* nouse for 8192se */
336 .maps
[EFUSE_ANA8M
] = EFUSE_ANA8M
,
337 .maps
[EFUSE_HWSET_MAX_SIZE
] = HWSET_MAX_SIZE_92S
,
338 .maps
[EFUSE_MAX_SECTION_MAP
] = EFUSE_MAX_SECTION
,
339 .maps
[EFUSE_REAL_CONTENT_SIZE
] = EFUSE_REAL_CONTENT_LEN
,
340 .maps
[EFUSE_OOB_PROTECT_BYTES_LEN
] = EFUSE_OOB_PROTECT_BYTES
,
342 .maps
[RWCAM
] = REG_RWCAM
,
343 .maps
[WCAMI
] = REG_WCAMI
,
344 .maps
[RCAMO
] = REG_RCAMO
,
345 .maps
[CAMDBG
] = REG_CAMDBG
,
346 .maps
[SECR
] = REG_SECR
,
347 .maps
[SEC_CAM_NONE
] = CAM_NONE
,
348 .maps
[SEC_CAM_WEP40
] = CAM_WEP40
,
349 .maps
[SEC_CAM_TKIP
] = CAM_TKIP
,
350 .maps
[SEC_CAM_AES
] = CAM_AES
,
351 .maps
[SEC_CAM_WEP104
] = CAM_WEP104
,
353 .maps
[RTL_IMR_BCNDMAINT6
] = IMR_BCNDMAINT6
,
354 .maps
[RTL_IMR_BCNDMAINT5
] = IMR_BCNDMAINT5
,
355 .maps
[RTL_IMR_BCNDMAINT4
] = IMR_BCNDMAINT4
,
356 .maps
[RTL_IMR_BCNDMAINT3
] = IMR_BCNDMAINT3
,
357 .maps
[RTL_IMR_BCNDMAINT2
] = IMR_BCNDMAINT2
,
358 .maps
[RTL_IMR_BCNDMAINT1
] = IMR_BCNDMAINT1
,
359 .maps
[RTL_IMR_BCNDOK8
] = IMR_BCNDOK8
,
360 .maps
[RTL_IMR_BCNDOK7
] = IMR_BCNDOK7
,
361 .maps
[RTL_IMR_BCNDOK6
] = IMR_BCNDOK6
,
362 .maps
[RTL_IMR_BCNDOK5
] = IMR_BCNDOK5
,
363 .maps
[RTL_IMR_BCNDOK4
] = IMR_BCNDOK4
,
364 .maps
[RTL_IMR_BCNDOK3
] = IMR_BCNDOK3
,
365 .maps
[RTL_IMR_BCNDOK2
] = IMR_BCNDOK2
,
366 .maps
[RTL_IMR_BCNDOK1
] = IMR_BCNDOK1
,
367 .maps
[RTL_IMR_TIMEOUT2
] = IMR_TIMEOUT2
,
368 .maps
[RTL_IMR_TIMEOUT1
] = IMR_TIMEOUT1
,
370 .maps
[RTL_IMR_TXFOVW
] = IMR_TXFOVW
,
371 .maps
[RTL_IMR_PSTIMEOUT
] = IMR_PSTIMEOUT
,
372 .maps
[RTL_IMR_BCNINT
] = IMR_BCNINT
,
373 .maps
[RTL_IMR_RXFOVW
] = IMR_RXFOVW
,
374 .maps
[RTL_IMR_RDU
] = IMR_RDU
,
375 .maps
[RTL_IMR_ATIMEND
] = IMR_ATIMEND
,
376 .maps
[RTL_IMR_BDOK
] = IMR_BDOK
,
377 .maps
[RTL_IMR_MGNTDOK
] = IMR_MGNTDOK
,
378 .maps
[RTL_IMR_TBDER
] = IMR_TBDER
,
379 .maps
[RTL_IMR_HIGHDOK
] = IMR_HIGHDOK
,
380 .maps
[RTL_IMR_COMDOK
] = IMR_COMDOK
,
381 .maps
[RTL_IMR_TBDOK
] = IMR_TBDOK
,
382 .maps
[RTL_IMR_BKDOK
] = IMR_BKDOK
,
383 .maps
[RTL_IMR_BEDOK
] = IMR_BEDOK
,
384 .maps
[RTL_IMR_VIDOK
] = IMR_VIDOK
,
385 .maps
[RTL_IMR_VODOK
] = IMR_VODOK
,
386 .maps
[RTL_IMR_ROK
] = IMR_ROK
,
387 .maps
[RTL_IBSS_INT_MASKS
] = (IMR_BCNINT
| IMR_TBDOK
| IMR_TBDER
),
389 .maps
[RTL_RC_CCK_RATE1M
] = DESC_RATE1M
,
390 .maps
[RTL_RC_CCK_RATE2M
] = DESC_RATE2M
,
391 .maps
[RTL_RC_CCK_RATE5_5M
] = DESC_RATE5_5M
,
392 .maps
[RTL_RC_CCK_RATE11M
] = DESC_RATE11M
,
393 .maps
[RTL_RC_OFDM_RATE6M
] = DESC_RATE6M
,
394 .maps
[RTL_RC_OFDM_RATE9M
] = DESC_RATE9M
,
395 .maps
[RTL_RC_OFDM_RATE12M
] = DESC_RATE12M
,
396 .maps
[RTL_RC_OFDM_RATE18M
] = DESC_RATE18M
,
397 .maps
[RTL_RC_OFDM_RATE24M
] = DESC_RATE24M
,
398 .maps
[RTL_RC_OFDM_RATE36M
] = DESC_RATE36M
,
399 .maps
[RTL_RC_OFDM_RATE48M
] = DESC_RATE48M
,
400 .maps
[RTL_RC_OFDM_RATE54M
] = DESC_RATE54M
,
402 .maps
[RTL_RC_HT_RATEMCS7
] = DESC_RATEMCS7
,
403 .maps
[RTL_RC_HT_RATEMCS15
] = DESC_RATEMCS15
,
406 static struct pci_device_id rtl92se_pci_ids
[] = {
407 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8192, rtl92se_hal_cfg
)},
408 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8171, rtl92se_hal_cfg
)},
409 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8172, rtl92se_hal_cfg
)},
410 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8173, rtl92se_hal_cfg
)},
411 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8174, rtl92se_hal_cfg
)},
415 MODULE_DEVICE_TABLE(pci
, rtl92se_pci_ids
);
417 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
418 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
419 MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
420 MODULE_LICENSE("GPL");
421 MODULE_DESCRIPTION("Realtek 8192S/8191S 802.11n PCI wireless");
422 MODULE_FIRMWARE("rtlwifi/rtl8192sefw.bin");
424 module_param_named(swenc
, rtl92se_mod_params
.sw_crypto
, bool, 0444);
425 module_param_named(debug
, rtl92se_mod_params
.debug
, int, 0444);
426 module_param_named(ips
, rtl92se_mod_params
.inactiveps
, bool, 0444);
427 module_param_named(swlps
, rtl92se_mod_params
.swctrl_lps
, bool, 0444);
428 module_param_named(fwlps
, rtl92se_mod_params
.fwctrl_lps
, bool, 0444);
429 MODULE_PARM_DESC(swenc
, "Set to 1 for software crypto (default 0)\n");
430 MODULE_PARM_DESC(ips
, "Set to 0 to not use link power save (default 1)\n");
431 MODULE_PARM_DESC(swlps
, "Set to 1 to use SW control power save (default 1)\n");
432 MODULE_PARM_DESC(fwlps
, "Set to 1 to use FW control power save (default 0)\n");
433 MODULE_PARM_DESC(debug
, "Set debug level (0-5) (default 0)");
435 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops
, rtl_pci_suspend
, rtl_pci_resume
);
437 static struct pci_driver rtl92se_driver
= {
438 .name
= KBUILD_MODNAME
,
439 .id_table
= rtl92se_pci_ids
,
440 .probe
= rtl_pci_probe
,
441 .remove
= rtl_pci_disconnect
,
442 .driver
.pm
= &rtlwifi_pm_ops
,
445 module_pci_driver(rtl92se_driver
);