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[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / realtek / rtlwifi / wifi.h
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #ifndef __RTL_WIFI_H__
27 #define __RTL_WIFI_H__
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sched.h>
32 #include <linux/firmware.h>
33 #include <linux/etherdevice.h>
34 #include <linux/vmalloc.h>
35 #include <linux/usb.h>
36 #include <net/mac80211.h>
37 #include <linux/completion.h>
38 #include "debug.h"
39
40 #define MASKBYTE0 0xff
41 #define MASKBYTE1 0xff00
42 #define MASKBYTE2 0xff0000
43 #define MASKBYTE3 0xff000000
44 #define MASKHWORD 0xffff0000
45 #define MASKLWORD 0x0000ffff
46 #define MASKDWORD 0xffffffff
47 #define MASK12BITS 0xfff
48 #define MASKH4BITS 0xf0000000
49 #define MASKOFDM_D 0xffc00000
50 #define MASKCCK 0x3f3f3f3f
51
52 #define MASK4BITS 0x0f
53 #define MASK20BITS 0xfffff
54 #define RFREG_OFFSET_MASK 0xfffff
55
56 #define MASKBYTE0 0xff
57 #define MASKBYTE1 0xff00
58 #define MASKBYTE2 0xff0000
59 #define MASKBYTE3 0xff000000
60 #define MASKHWORD 0xffff0000
61 #define MASKLWORD 0x0000ffff
62 #define MASKDWORD 0xffffffff
63 #define MASK12BITS 0xfff
64 #define MASKH4BITS 0xf0000000
65 #define MASKOFDM_D 0xffc00000
66 #define MASKCCK 0x3f3f3f3f
67
68 #define MASK4BITS 0x0f
69 #define MASK20BITS 0xfffff
70 #define RFREG_OFFSET_MASK 0xfffff
71
72 #define RF_CHANGE_BY_INIT 0
73 #define RF_CHANGE_BY_IPS BIT(28)
74 #define RF_CHANGE_BY_PS BIT(29)
75 #define RF_CHANGE_BY_HW BIT(30)
76 #define RF_CHANGE_BY_SW BIT(31)
77
78 #define IQK_ADDA_REG_NUM 16
79 #define IQK_MAC_REG_NUM 4
80 #define IQK_THRESHOLD 8
81
82 #define MAX_KEY_LEN 61
83 #define KEY_BUF_SIZE 5
84
85 /* QoS related. */
86 /*aci: 0x00 Best Effort*/
87 /*aci: 0x01 Background*/
88 /*aci: 0x10 Video*/
89 /*aci: 0x11 Voice*/
90 /*Max: define total number.*/
91 #define AC0_BE 0
92 #define AC1_BK 1
93 #define AC2_VI 2
94 #define AC3_VO 3
95 #define AC_MAX 4
96 #define QOS_QUEUE_NUM 4
97 #define RTL_MAC80211_NUM_QUEUE 5
98 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
99 #define RTL_USB_MAX_RX_COUNT 100
100 #define QBSS_LOAD_SIZE 5
101 #define MAX_WMMELE_LENGTH 64
102
103 #define TOTAL_CAM_ENTRY 32
104
105 /*slot time for 11g. */
106 #define RTL_SLOT_TIME_9 9
107 #define RTL_SLOT_TIME_20 20
108
109 /*related to tcp/ip. */
110 #define SNAP_SIZE 6
111 #define PROTOC_TYPE_SIZE 2
112
113 /*related with 802.11 frame*/
114 #define MAC80211_3ADDR_LEN 24
115 #define MAC80211_4ADDR_LEN 30
116
117 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
118 #define CHANNEL_MAX_NUMBER_2G 14
119 #define CHANNEL_MAX_NUMBER_5G 49 /* Please refer to
120 *"phy_GetChnlGroup8812A" and
121 * "Hal_ReadTxPowerInfo8812A"
122 */
123 #define CHANNEL_MAX_NUMBER_5G_80M 7
124 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
125 #define MAX_PG_GROUP 13
126 #define CHANNEL_GROUP_MAX_2G 3
127 #define CHANNEL_GROUP_IDX_5GL 3
128 #define CHANNEL_GROUP_IDX_5GM 6
129 #define CHANNEL_GROUP_IDX_5GH 9
130 #define CHANNEL_GROUP_MAX_5G 9
131 #define CHANNEL_MAX_NUMBER_2G 14
132 #define AVG_THERMAL_NUM 8
133 #define AVG_THERMAL_NUM_88E 4
134 #define AVG_THERMAL_NUM_8723BE 4
135 #define MAX_TID_COUNT 9
136
137 /* for early mode */
138 #define FCS_LEN 4
139 #define EM_HDR_LEN 8
140
141 enum rtl8192c_h2c_cmd {
142 H2C_AP_OFFLOAD = 0,
143 H2C_SETPWRMODE = 1,
144 H2C_JOINBSSRPT = 2,
145 H2C_RSVDPAGE = 3,
146 H2C_RSSI_REPORT = 5,
147 H2C_RA_MASK = 6,
148 H2C_MACID_PS_MODE = 7,
149 H2C_P2P_PS_OFFLOAD = 8,
150 H2C_MAC_MODE_SEL = 9,
151 H2C_PWRM = 15,
152 H2C_P2P_PS_CTW_CMD = 24,
153 MAX_H2CCMD
154 };
155
156 #define MAX_TX_COUNT 4
157 #define MAX_REGULATION_NUM 4
158 #define MAX_RF_PATH_NUM 4
159 #define MAX_RATE_SECTION_NUM 6
160 #define MAX_2_4G_BANDWITH_NUM 4
161 #define MAX_5G_BANDWITH_NUM 4
162 #define MAX_RF_PATH 4
163 #define MAX_CHNL_GROUP_24G 6
164 #define MAX_CHNL_GROUP_5G 14
165
166 #define TX_PWR_BY_RATE_NUM_BAND 2
167 #define TX_PWR_BY_RATE_NUM_RF 4
168 #define TX_PWR_BY_RATE_NUM_SECTION 12
169 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6
170 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5
171
172 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
173
174 #define DEL_SW_IDX_SZ 30
175 #define BAND_NUM 3
176
177 /* For now, it's just for 8192ee
178 * but not OK yet, keep it 0
179 */
180 #define DMA_IS_64BIT 0
181 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
182
183 enum rf_tx_num {
184 RF_1TX = 0,
185 RF_2TX,
186 RF_MAX_TX_NUM,
187 RF_TX_NUM_NONIMPLEMENT,
188 };
189
190 #define PACKET_NORMAL 0
191 #define PACKET_DHCP 1
192 #define PACKET_ARP 2
193 #define PACKET_EAPOL 3
194
195 #define MAX_SUPPORT_WOL_PATTERN_NUM 16
196 #define RSVD_WOL_PATTERN_NUM 1
197 #define WKFMCAM_ADDR_NUM 6
198 #define WKFMCAM_SIZE 24
199
200 #define MAX_WOL_BIT_MASK_SIZE 16
201 /* MIN LEN keeps 13 here */
202 #define MIN_WOL_PATTERN_SIZE 13
203 #define MAX_WOL_PATTERN_SIZE 128
204
205 #define WAKE_ON_MAGIC_PACKET BIT(0)
206 #define WAKE_ON_PATTERN_MATCH BIT(1)
207
208 #define WOL_REASON_PTK_UPDATE BIT(0)
209 #define WOL_REASON_GTK_UPDATE BIT(1)
210 #define WOL_REASON_DISASSOC BIT(2)
211 #define WOL_REASON_DEAUTH BIT(3)
212 #define WOL_REASON_AP_LOST BIT(4)
213 #define WOL_REASON_MAGIC_PKT BIT(5)
214 #define WOL_REASON_UNICAST_PKT BIT(6)
215 #define WOL_REASON_PATTERN_PKT BIT(7)
216 #define WOL_REASON_RTD3_SSID_MATCH BIT(8)
217 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9)
218 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10)
219
220 struct rtlwifi_firmware_header {
221 __le16 signature;
222 u8 category;
223 u8 function;
224 __le16 version;
225 u8 subversion;
226 u8 rsvd1;
227 u8 month;
228 u8 date;
229 u8 hour;
230 u8 minute;
231 __le16 ramcodeSize;
232 __le16 rsvd2;
233 __le32 svnindex;
234 __le32 rsvd3;
235 __le32 rsvd4;
236 __le32 rsvd5;
237 };
238
239 struct txpower_info_2g {
240 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
241 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
242 /*If only one tx, only BW20 and OFDM are used.*/
243 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
244 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
245 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
246 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
247 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
248 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
249 };
250
251 struct txpower_info_5g {
252 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
253 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
254 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
255 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
256 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
257 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
258 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
259 };
260
261 enum rate_section {
262 CCK = 0,
263 OFDM,
264 HT_MCS0_MCS7,
265 HT_MCS8_MCS15,
266 VHT_1SSMCS0_1SSMCS9,
267 VHT_2SSMCS0_2SSMCS9,
268 };
269
270 enum intf_type {
271 INTF_PCI = 0,
272 INTF_USB = 1,
273 };
274
275 enum radio_path {
276 RF90_PATH_A = 0,
277 RF90_PATH_B = 1,
278 RF90_PATH_C = 2,
279 RF90_PATH_D = 3,
280 };
281
282 enum regulation_txpwr_lmt {
283 TXPWR_LMT_FCC = 0,
284 TXPWR_LMT_MKK = 1,
285 TXPWR_LMT_ETSI = 2,
286 TXPWR_LMT_WW = 3,
287
288 TXPWR_LMT_MAX_REGULATION_NUM = 4
289 };
290
291 enum rt_eeprom_type {
292 EEPROM_93C46,
293 EEPROM_93C56,
294 EEPROM_BOOT_EFUSE,
295 };
296
297 enum ttl_status {
298 RTL_STATUS_INTERFACE_START = 0,
299 };
300
301 enum hardware_type {
302 HARDWARE_TYPE_RTL8192E,
303 HARDWARE_TYPE_RTL8192U,
304 HARDWARE_TYPE_RTL8192SE,
305 HARDWARE_TYPE_RTL8192SU,
306 HARDWARE_TYPE_RTL8192CE,
307 HARDWARE_TYPE_RTL8192CU,
308 HARDWARE_TYPE_RTL8192DE,
309 HARDWARE_TYPE_RTL8192DU,
310 HARDWARE_TYPE_RTL8723AE,
311 HARDWARE_TYPE_RTL8723U,
312 HARDWARE_TYPE_RTL8188EE,
313 HARDWARE_TYPE_RTL8723BE,
314 HARDWARE_TYPE_RTL8192EE,
315 HARDWARE_TYPE_RTL8821AE,
316 HARDWARE_TYPE_RTL8812AE,
317
318 /* keep it last */
319 HARDWARE_TYPE_NUM
320 };
321
322 #define IS_HARDWARE_TYPE_8192SU(rtlhal) \
323 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
324 #define IS_HARDWARE_TYPE_8192SE(rtlhal) \
325 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
326 #define IS_HARDWARE_TYPE_8192CE(rtlhal) \
327 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
328 #define IS_HARDWARE_TYPE_8192CU(rtlhal) \
329 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
330 #define IS_HARDWARE_TYPE_8192DE(rtlhal) \
331 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
332 #define IS_HARDWARE_TYPE_8192DU(rtlhal) \
333 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
334 #define IS_HARDWARE_TYPE_8723E(rtlhal) \
335 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
336 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
337 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
338 #define IS_HARDWARE_TYPE_8192S(rtlhal) \
339 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
340 #define IS_HARDWARE_TYPE_8192C(rtlhal) \
341 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
342 #define IS_HARDWARE_TYPE_8192D(rtlhal) \
343 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
344 #define IS_HARDWARE_TYPE_8723(rtlhal) \
345 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
346
347 #define RX_HAL_IS_CCK_RATE(rxmcs) \
348 ((rxmcs) == DESC_RATE1M || \
349 (rxmcs) == DESC_RATE2M || \
350 (rxmcs) == DESC_RATE5_5M || \
351 (rxmcs) == DESC_RATE11M)
352
353 enum scan_operation_backup_opt {
354 SCAN_OPT_BACKUP = 0,
355 SCAN_OPT_BACKUP_BAND0 = 0,
356 SCAN_OPT_BACKUP_BAND1,
357 SCAN_OPT_RESTORE,
358 SCAN_OPT_MAX
359 };
360
361 /*RF state.*/
362 enum rf_pwrstate {
363 ERFON,
364 ERFSLEEP,
365 ERFOFF
366 };
367
368 struct bb_reg_def {
369 u32 rfintfs;
370 u32 rfintfi;
371 u32 rfintfo;
372 u32 rfintfe;
373 u32 rf3wire_offset;
374 u32 rflssi_select;
375 u32 rftxgain_stage;
376 u32 rfhssi_para1;
377 u32 rfhssi_para2;
378 u32 rfsw_ctrl;
379 u32 rfagc_control1;
380 u32 rfagc_control2;
381 u32 rfrxiq_imbal;
382 u32 rfrx_afe;
383 u32 rftxiq_imbal;
384 u32 rftx_afe;
385 u32 rf_rb; /* rflssi_readback */
386 u32 rf_rbpi; /* rflssi_readbackpi */
387 };
388
389 enum io_type {
390 IO_CMD_PAUSE_DM_BY_SCAN = 0,
391 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
392 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
393 IO_CMD_RESUME_DM_BY_SCAN = 2,
394 };
395
396 enum hw_variables {
397 HW_VAR_ETHER_ADDR = 0x0,
398 HW_VAR_MULTICAST_REG = 0x1,
399 HW_VAR_BASIC_RATE = 0x2,
400 HW_VAR_BSSID = 0x3,
401 HW_VAR_MEDIA_STATUS= 0x4,
402 HW_VAR_SECURITY_CONF= 0x5,
403 HW_VAR_BEACON_INTERVAL = 0x6,
404 HW_VAR_ATIM_WINDOW = 0x7,
405 HW_VAR_LISTEN_INTERVAL = 0x8,
406 HW_VAR_CS_COUNTER = 0x9,
407 HW_VAR_DEFAULTKEY0 = 0xa,
408 HW_VAR_DEFAULTKEY1 = 0xb,
409 HW_VAR_DEFAULTKEY2 = 0xc,
410 HW_VAR_DEFAULTKEY3 = 0xd,
411 HW_VAR_SIFS = 0xe,
412 HW_VAR_R2T_SIFS = 0xf,
413 HW_VAR_DIFS = 0x10,
414 HW_VAR_EIFS = 0x11,
415 HW_VAR_SLOT_TIME = 0x12,
416 HW_VAR_ACK_PREAMBLE = 0x13,
417 HW_VAR_CW_CONFIG = 0x14,
418 HW_VAR_CW_VALUES = 0x15,
419 HW_VAR_RATE_FALLBACK_CONTROL= 0x16,
420 HW_VAR_CONTENTION_WINDOW = 0x17,
421 HW_VAR_RETRY_COUNT = 0x18,
422 HW_VAR_TR_SWITCH = 0x19,
423 HW_VAR_COMMAND = 0x1a,
424 HW_VAR_WPA_CONFIG = 0x1b,
425 HW_VAR_AMPDU_MIN_SPACE = 0x1c,
426 HW_VAR_SHORTGI_DENSITY = 0x1d,
427 HW_VAR_AMPDU_FACTOR = 0x1e,
428 HW_VAR_MCS_RATE_AVAILABLE = 0x1f,
429 HW_VAR_AC_PARAM = 0x20,
430 HW_VAR_ACM_CTRL = 0x21,
431 HW_VAR_DIS_Req_Qsize = 0x22,
432 HW_VAR_CCX_CHNL_LOAD = 0x23,
433 HW_VAR_CCX_NOISE_HISTOGRAM = 0x24,
434 HW_VAR_CCX_CLM_NHM = 0x25,
435 HW_VAR_TxOPLimit = 0x26,
436 HW_VAR_TURBO_MODE = 0x27,
437 HW_VAR_RF_STATE = 0x28,
438 HW_VAR_RF_OFF_BY_HW = 0x29,
439 HW_VAR_BUS_SPEED = 0x2a,
440 HW_VAR_SET_DEV_POWER = 0x2b,
441
442 HW_VAR_RCR = 0x2c,
443 HW_VAR_RATR_0 = 0x2d,
444 HW_VAR_RRSR = 0x2e,
445 HW_VAR_CPU_RST = 0x2f,
446 HW_VAR_CHECK_BSSID = 0x30,
447 HW_VAR_LBK_MODE = 0x31,
448 HW_VAR_AES_11N_FIX = 0x32,
449 HW_VAR_USB_RX_AGGR = 0x33,
450 HW_VAR_USER_CONTROL_TURBO_MODE = 0x34,
451 HW_VAR_RETRY_LIMIT = 0x35,
452 HW_VAR_INIT_TX_RATE = 0x36,
453 HW_VAR_TX_RATE_REG = 0x37,
454 HW_VAR_EFUSE_USAGE = 0x38,
455 HW_VAR_EFUSE_BYTES = 0x39,
456 HW_VAR_AUTOLOAD_STATUS = 0x3a,
457 HW_VAR_RF_2R_DISABLE = 0x3b,
458 HW_VAR_SET_RPWM = 0x3c,
459 HW_VAR_H2C_FW_PWRMODE = 0x3d,
460 HW_VAR_H2C_FW_JOINBSSRPT = 0x3e,
461 HW_VAR_H2C_FW_MEDIASTATUSRPT = 0x3f,
462 HW_VAR_H2C_FW_P2P_PS_OFFLOAD = 0x40,
463 HW_VAR_FW_PSMODE_STATUS = 0x41,
464 HW_VAR_INIT_RTS_RATE = 0x42,
465 HW_VAR_RESUME_CLK_ON = 0x43,
466 HW_VAR_FW_LPS_ACTION = 0x44,
467 HW_VAR_1X1_RECV_COMBINE = 0x45,
468 HW_VAR_STOP_SEND_BEACON = 0x46,
469 HW_VAR_TSF_TIMER = 0x47,
470 HW_VAR_IO_CMD = 0x48,
471
472 HW_VAR_RF_RECOVERY = 0x49,
473 HW_VAR_H2C_FW_UPDATE_GTK = 0x4a,
474 HW_VAR_WF_MASK = 0x4b,
475 HW_VAR_WF_CRC = 0x4c,
476 HW_VAR_WF_IS_MAC_ADDR = 0x4d,
477 HW_VAR_H2C_FW_OFFLOAD = 0x4e,
478 HW_VAR_RESET_WFCRC = 0x4f,
479
480 HW_VAR_HANDLE_FW_C2H = 0x50,
481 HW_VAR_DL_FW_RSVD_PAGE = 0x51,
482 HW_VAR_AID = 0x52,
483 HW_VAR_HW_SEQ_ENABLE = 0x53,
484 HW_VAR_CORRECT_TSF = 0x54,
485 HW_VAR_BCN_VALID = 0x55,
486 HW_VAR_FWLPS_RF_ON = 0x56,
487 HW_VAR_DUAL_TSF_RST = 0x57,
488 HW_VAR_SWITCH_EPHY_WoWLAN = 0x58,
489 HW_VAR_INT_MIGRATION = 0x59,
490 HW_VAR_INT_AC = 0x5a,
491 HW_VAR_RF_TIMING = 0x5b,
492
493 HAL_DEF_WOWLAN = 0x5c,
494 HW_VAR_MRC = 0x5d,
495 HW_VAR_KEEP_ALIVE = 0x5e,
496 HW_VAR_NAV_UPPER = 0x5f,
497
498 HW_VAR_MGT_FILTER = 0x60,
499 HW_VAR_CTRL_FILTER = 0x61,
500 HW_VAR_DATA_FILTER = 0x62,
501 };
502
503 enum rt_media_status {
504 RT_MEDIA_DISCONNECT = 0,
505 RT_MEDIA_CONNECT = 1
506 };
507
508 enum rt_oem_id {
509 RT_CID_DEFAULT = 0,
510 RT_CID_8187_ALPHA0 = 1,
511 RT_CID_8187_SERCOMM_PS = 2,
512 RT_CID_8187_HW_LED = 3,
513 RT_CID_8187_NETGEAR = 4,
514 RT_CID_WHQL = 5,
515 RT_CID_819X_CAMEO = 6,
516 RT_CID_819X_RUNTOP = 7,
517 RT_CID_819X_SENAO = 8,
518 RT_CID_TOSHIBA = 9,
519 RT_CID_819X_NETCORE = 10,
520 RT_CID_NETTRONIX = 11,
521 RT_CID_DLINK = 12,
522 RT_CID_PRONET = 13,
523 RT_CID_COREGA = 14,
524 RT_CID_819X_ALPHA = 15,
525 RT_CID_819X_SITECOM = 16,
526 RT_CID_CCX = 17,
527 RT_CID_819X_LENOVO = 18,
528 RT_CID_819X_QMI = 19,
529 RT_CID_819X_EDIMAX_BELKIN = 20,
530 RT_CID_819X_SERCOMM_BELKIN = 21,
531 RT_CID_819X_CAMEO1 = 22,
532 RT_CID_819X_MSI = 23,
533 RT_CID_819X_ACER = 24,
534 RT_CID_819X_HP = 27,
535 RT_CID_819X_CLEVO = 28,
536 RT_CID_819X_ARCADYAN_BELKIN = 29,
537 RT_CID_819X_SAMSUNG = 30,
538 RT_CID_819X_WNC_COREGA = 31,
539 RT_CID_819X_FOXCOON = 32,
540 RT_CID_819X_DELL = 33,
541 RT_CID_819X_PRONETS = 34,
542 RT_CID_819X_EDIMAX_ASUS = 35,
543 RT_CID_NETGEAR = 36,
544 RT_CID_PLANEX = 37,
545 RT_CID_CC_C = 38,
546 };
547
548 enum hw_descs {
549 HW_DESC_OWN,
550 HW_DESC_RXOWN,
551 HW_DESC_TX_NEXTDESC_ADDR,
552 HW_DESC_TXBUFF_ADDR,
553 HW_DESC_RXBUFF_ADDR,
554 HW_DESC_RXPKT_LEN,
555 HW_DESC_RXERO,
556 HW_DESC_RX_PREPARE,
557 };
558
559 enum prime_sc {
560 PRIME_CHNL_OFFSET_DONT_CARE = 0,
561 PRIME_CHNL_OFFSET_LOWER = 1,
562 PRIME_CHNL_OFFSET_UPPER = 2,
563 };
564
565 enum rf_type {
566 RF_1T1R = 0,
567 RF_1T2R = 1,
568 RF_2T2R = 2,
569 RF_2T2R_GREEN = 3,
570 };
571
572 enum ht_channel_width {
573 HT_CHANNEL_WIDTH_20 = 0,
574 HT_CHANNEL_WIDTH_20_40 = 1,
575 HT_CHANNEL_WIDTH_80 = 2,
576 };
577
578 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
579 Cipher Suites Encryption Algorithms */
580 enum rt_enc_alg {
581 NO_ENCRYPTION = 0,
582 WEP40_ENCRYPTION = 1,
583 TKIP_ENCRYPTION = 2,
584 RSERVED_ENCRYPTION = 3,
585 AESCCMP_ENCRYPTION = 4,
586 WEP104_ENCRYPTION = 5,
587 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
588 };
589
590 enum rtl_hal_state {
591 _HAL_STATE_STOP = 0,
592 _HAL_STATE_START = 1,
593 };
594
595 enum rtl_desc92_rate {
596 DESC_RATE1M = 0x00,
597 DESC_RATE2M = 0x01,
598 DESC_RATE5_5M = 0x02,
599 DESC_RATE11M = 0x03,
600
601 DESC_RATE6M = 0x04,
602 DESC_RATE9M = 0x05,
603 DESC_RATE12M = 0x06,
604 DESC_RATE18M = 0x07,
605 DESC_RATE24M = 0x08,
606 DESC_RATE36M = 0x09,
607 DESC_RATE48M = 0x0a,
608 DESC_RATE54M = 0x0b,
609
610 DESC_RATEMCS0 = 0x0c,
611 DESC_RATEMCS1 = 0x0d,
612 DESC_RATEMCS2 = 0x0e,
613 DESC_RATEMCS3 = 0x0f,
614 DESC_RATEMCS4 = 0x10,
615 DESC_RATEMCS5 = 0x11,
616 DESC_RATEMCS6 = 0x12,
617 DESC_RATEMCS7 = 0x13,
618 DESC_RATEMCS8 = 0x14,
619 DESC_RATEMCS9 = 0x15,
620 DESC_RATEMCS10 = 0x16,
621 DESC_RATEMCS11 = 0x17,
622 DESC_RATEMCS12 = 0x18,
623 DESC_RATEMCS13 = 0x19,
624 DESC_RATEMCS14 = 0x1a,
625 DESC_RATEMCS15 = 0x1b,
626 DESC_RATEMCS15_SG = 0x1c,
627 DESC_RATEMCS32 = 0x20,
628
629 DESC_RATEVHT1SS_MCS0 = 0x2c,
630 DESC_RATEVHT1SS_MCS1 = 0x2d,
631 DESC_RATEVHT1SS_MCS2 = 0x2e,
632 DESC_RATEVHT1SS_MCS3 = 0x2f,
633 DESC_RATEVHT1SS_MCS4 = 0x30,
634 DESC_RATEVHT1SS_MCS5 = 0x31,
635 DESC_RATEVHT1SS_MCS6 = 0x32,
636 DESC_RATEVHT1SS_MCS7 = 0x33,
637 DESC_RATEVHT1SS_MCS8 = 0x34,
638 DESC_RATEVHT1SS_MCS9 = 0x35,
639 DESC_RATEVHT2SS_MCS0 = 0x36,
640 DESC_RATEVHT2SS_MCS1 = 0x37,
641 DESC_RATEVHT2SS_MCS2 = 0x38,
642 DESC_RATEVHT2SS_MCS3 = 0x39,
643 DESC_RATEVHT2SS_MCS4 = 0x3a,
644 DESC_RATEVHT2SS_MCS5 = 0x3b,
645 DESC_RATEVHT2SS_MCS6 = 0x3c,
646 DESC_RATEVHT2SS_MCS7 = 0x3d,
647 DESC_RATEVHT2SS_MCS8 = 0x3e,
648 DESC_RATEVHT2SS_MCS9 = 0x3f,
649 };
650
651 enum rtl_var_map {
652 /*reg map */
653 SYS_ISO_CTRL = 0,
654 SYS_FUNC_EN,
655 SYS_CLK,
656 MAC_RCR_AM,
657 MAC_RCR_AB,
658 MAC_RCR_ACRC32,
659 MAC_RCR_ACF,
660 MAC_RCR_AAP,
661 MAC_HIMR,
662 MAC_HIMRE,
663 MAC_HSISR,
664
665 /*efuse map */
666 EFUSE_TEST,
667 EFUSE_CTRL,
668 EFUSE_CLK,
669 EFUSE_CLK_CTRL,
670 EFUSE_PWC_EV12V,
671 EFUSE_FEN_ELDR,
672 EFUSE_LOADER_CLK_EN,
673 EFUSE_ANA8M,
674 EFUSE_HWSET_MAX_SIZE,
675 EFUSE_MAX_SECTION_MAP,
676 EFUSE_REAL_CONTENT_SIZE,
677 EFUSE_OOB_PROTECT_BYTES_LEN,
678 EFUSE_ACCESS,
679
680 /*CAM map */
681 RWCAM,
682 WCAMI,
683 RCAMO,
684 CAMDBG,
685 SECR,
686 SEC_CAM_NONE,
687 SEC_CAM_WEP40,
688 SEC_CAM_TKIP,
689 SEC_CAM_AES,
690 SEC_CAM_WEP104,
691
692 /*IMR map */
693 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
694 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
695 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
696 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
697 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
698 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
699 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
700 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
701 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
702 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
703 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
704 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
705 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
706 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
707 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
708 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
709 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
710 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
711 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */
712 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
713 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
714 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
715 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
716 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
717 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
718 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
719 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
720 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
721 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
722 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
723 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
724 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
725 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
726 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/
727 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
728 * RTL_IMR_TBDER) */
729 RTL_IMR_C2HCMD, /*fw interrupt*/
730
731 /*CCK Rates, TxHT = 0 */
732 RTL_RC_CCK_RATE1M,
733 RTL_RC_CCK_RATE2M,
734 RTL_RC_CCK_RATE5_5M,
735 RTL_RC_CCK_RATE11M,
736
737 /*OFDM Rates, TxHT = 0 */
738 RTL_RC_OFDM_RATE6M,
739 RTL_RC_OFDM_RATE9M,
740 RTL_RC_OFDM_RATE12M,
741 RTL_RC_OFDM_RATE18M,
742 RTL_RC_OFDM_RATE24M,
743 RTL_RC_OFDM_RATE36M,
744 RTL_RC_OFDM_RATE48M,
745 RTL_RC_OFDM_RATE54M,
746
747 RTL_RC_HT_RATEMCS7,
748 RTL_RC_HT_RATEMCS15,
749
750 RTL_RC_VHT_RATE_1SS_MCS7,
751 RTL_RC_VHT_RATE_1SS_MCS8,
752 RTL_RC_VHT_RATE_1SS_MCS9,
753 RTL_RC_VHT_RATE_2SS_MCS7,
754 RTL_RC_VHT_RATE_2SS_MCS8,
755 RTL_RC_VHT_RATE_2SS_MCS9,
756
757 /*keep it last */
758 RTL_VAR_MAP_MAX,
759 };
760
761 /*Firmware PS mode for control LPS.*/
762 enum _fw_ps_mode {
763 FW_PS_ACTIVE_MODE = 0,
764 FW_PS_MIN_MODE = 1,
765 FW_PS_MAX_MODE = 2,
766 FW_PS_DTIM_MODE = 3,
767 FW_PS_VOIP_MODE = 4,
768 FW_PS_UAPSD_WMM_MODE = 5,
769 FW_PS_UAPSD_MODE = 6,
770 FW_PS_IBSS_MODE = 7,
771 FW_PS_WWLAN_MODE = 8,
772 FW_PS_PM_Radio_Off = 9,
773 FW_PS_PM_Card_Disable = 10,
774 };
775
776 enum rt_psmode {
777 EACTIVE, /*Active/Continuous access. */
778 EMAXPS, /*Max power save mode. */
779 EFASTPS, /*Fast power save mode. */
780 EAUTOPS, /*Auto power save mode. */
781 };
782
783 /*LED related.*/
784 enum led_ctl_mode {
785 LED_CTL_POWER_ON = 1,
786 LED_CTL_LINK = 2,
787 LED_CTL_NO_LINK = 3,
788 LED_CTL_TX = 4,
789 LED_CTL_RX = 5,
790 LED_CTL_SITE_SURVEY = 6,
791 LED_CTL_POWER_OFF = 7,
792 LED_CTL_START_TO_LINK = 8,
793 LED_CTL_START_WPS = 9,
794 LED_CTL_STOP_WPS = 10,
795 };
796
797 enum rtl_led_pin {
798 LED_PIN_GPIO0,
799 LED_PIN_LED0,
800 LED_PIN_LED1,
801 LED_PIN_LED2
802 };
803
804 /*QoS related.*/
805 /*acm implementation method.*/
806 enum acm_method {
807 eAcmWay0_SwAndHw = 0,
808 eAcmWay1_HW = 1,
809 EACMWAY2_SW = 2,
810 };
811
812 enum macphy_mode {
813 SINGLEMAC_SINGLEPHY = 0,
814 DUALMAC_DUALPHY,
815 DUALMAC_SINGLEPHY,
816 };
817
818 enum band_type {
819 BAND_ON_2_4G = 0,
820 BAND_ON_5G,
821 BAND_ON_BOTH,
822 BANDMAX
823 };
824
825 /*aci/aifsn Field.
826 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
827 union aci_aifsn {
828 u8 char_data;
829
830 struct {
831 u8 aifsn:4;
832 u8 acm:1;
833 u8 aci:2;
834 u8 reserved:1;
835 } f; /* Field */
836 };
837
838 /*mlme related.*/
839 enum wireless_mode {
840 WIRELESS_MODE_UNKNOWN = 0x00,
841 WIRELESS_MODE_A = 0x01,
842 WIRELESS_MODE_B = 0x02,
843 WIRELESS_MODE_G = 0x04,
844 WIRELESS_MODE_AUTO = 0x08,
845 WIRELESS_MODE_N_24G = 0x10,
846 WIRELESS_MODE_N_5G = 0x20,
847 WIRELESS_MODE_AC_5G = 0x40,
848 WIRELESS_MODE_AC_24G = 0x80,
849 WIRELESS_MODE_AC_ONLY = 0x100,
850 WIRELESS_MODE_MAX = 0x800
851 };
852
853 #define IS_WIRELESS_MODE_A(wirelessmode) \
854 (wirelessmode == WIRELESS_MODE_A)
855 #define IS_WIRELESS_MODE_B(wirelessmode) \
856 (wirelessmode == WIRELESS_MODE_B)
857 #define IS_WIRELESS_MODE_G(wirelessmode) \
858 (wirelessmode == WIRELESS_MODE_G)
859 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
860 (wirelessmode == WIRELESS_MODE_N_24G)
861 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
862 (wirelessmode == WIRELESS_MODE_N_5G)
863
864 enum ratr_table_mode {
865 RATR_INX_WIRELESS_NGB = 0,
866 RATR_INX_WIRELESS_NG = 1,
867 RATR_INX_WIRELESS_NB = 2,
868 RATR_INX_WIRELESS_N = 3,
869 RATR_INX_WIRELESS_GB = 4,
870 RATR_INX_WIRELESS_G = 5,
871 RATR_INX_WIRELESS_B = 6,
872 RATR_INX_WIRELESS_MC = 7,
873 RATR_INX_WIRELESS_A = 8,
874 RATR_INX_WIRELESS_AC_5N = 8,
875 RATR_INX_WIRELESS_AC_24N = 9,
876 };
877
878 enum rtl_link_state {
879 MAC80211_NOLINK = 0,
880 MAC80211_LINKING = 1,
881 MAC80211_LINKED = 2,
882 MAC80211_LINKED_SCANNING = 3,
883 };
884
885 enum act_category {
886 ACT_CAT_QOS = 1,
887 ACT_CAT_DLS = 2,
888 ACT_CAT_BA = 3,
889 ACT_CAT_HT = 7,
890 ACT_CAT_WMM = 17,
891 };
892
893 enum ba_action {
894 ACT_ADDBAREQ = 0,
895 ACT_ADDBARSP = 1,
896 ACT_DELBA = 2,
897 };
898
899 enum rt_polarity_ctl {
900 RT_POLARITY_LOW_ACT = 0,
901 RT_POLARITY_HIGH_ACT = 1,
902 };
903
904 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */
905 enum fw_wow_reason_v2 {
906 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01,
907 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02,
908 FW_WOW_V2_DISASSOC_EVENT = 0x04,
909 FW_WOW_V2_DEAUTH_EVENT = 0x08,
910 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10,
911 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21,
912 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22,
913 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23,
914 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24,
915 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30,
916 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31,
917 FW_WOW_V2_REASON_MAX = 0xff,
918 };
919
920 enum wolpattern_type {
921 UNICAST_PATTERN = 0,
922 MULTICAST_PATTERN = 1,
923 BROADCAST_PATTERN = 2,
924 DONT_CARE_DA = 3,
925 UNKNOWN_TYPE = 4,
926 };
927
928 struct octet_string {
929 u8 *octet;
930 u16 length;
931 };
932
933 struct rtl_hdr_3addr {
934 __le16 frame_ctl;
935 __le16 duration_id;
936 u8 addr1[ETH_ALEN];
937 u8 addr2[ETH_ALEN];
938 u8 addr3[ETH_ALEN];
939 __le16 seq_ctl;
940 u8 payload[0];
941 } __packed;
942
943 struct rtl_info_element {
944 u8 id;
945 u8 len;
946 u8 data[0];
947 } __packed;
948
949 struct rtl_probe_rsp {
950 struct rtl_hdr_3addr header;
951 u32 time_stamp[2];
952 __le16 beacon_interval;
953 __le16 capability;
954 /*SSID, supported rates, FH params, DS params,
955 CF params, IBSS params, TIM (if beacon), RSN */
956 struct rtl_info_element info_element[0];
957 } __packed;
958
959 /*LED related.*/
960 /*ledpin Identify how to implement this SW led.*/
961 struct rtl_led {
962 void *hw;
963 enum rtl_led_pin ledpin;
964 bool ledon;
965 };
966
967 struct rtl_led_ctl {
968 bool led_opendrain;
969 struct rtl_led sw_led0;
970 struct rtl_led sw_led1;
971 };
972
973 struct rtl_qos_parameters {
974 __le16 cw_min;
975 __le16 cw_max;
976 u8 aifs;
977 u8 flag;
978 __le16 tx_op;
979 } __packed;
980
981 struct rt_smooth_data {
982 u32 elements[100]; /*array to store values */
983 u32 index; /*index to current array to store */
984 u32 total_num; /*num of valid elements */
985 u32 total_val; /*sum of valid elements */
986 };
987
988 struct false_alarm_statistics {
989 u32 cnt_parity_fail;
990 u32 cnt_rate_illegal;
991 u32 cnt_crc8_fail;
992 u32 cnt_mcs_fail;
993 u32 cnt_fast_fsync_fail;
994 u32 cnt_sb_search_fail;
995 u32 cnt_ofdm_fail;
996 u32 cnt_cck_fail;
997 u32 cnt_all;
998 u32 cnt_ofdm_cca;
999 u32 cnt_cck_cca;
1000 u32 cnt_cca_all;
1001 u32 cnt_bw_usc;
1002 u32 cnt_bw_lsc;
1003 };
1004
1005 struct init_gain {
1006 u8 xaagccore1;
1007 u8 xbagccore1;
1008 u8 xcagccore1;
1009 u8 xdagccore1;
1010 u8 cca;
1011
1012 };
1013
1014 struct wireless_stats {
1015 unsigned long txbytesunicast;
1016 unsigned long txbytesmulticast;
1017 unsigned long txbytesbroadcast;
1018 unsigned long rxbytesunicast;
1019
1020 long rx_snr_db[4];
1021 /*Correct smoothed ss in Dbm, only used
1022 in driver to report real power now. */
1023 long recv_signal_power;
1024 long signal_quality;
1025 long last_sigstrength_inpercent;
1026
1027 u32 rssi_calculate_cnt;
1028 u32 pwdb_all_cnt;
1029
1030 /*Transformed, in dbm. Beautified signal
1031 strength for UI, not correct. */
1032 long signal_strength;
1033
1034 u8 rx_rssi_percentage[4];
1035 u8 rx_evm_dbm[4];
1036 u8 rx_evm_percentage[2];
1037
1038 u16 rx_cfo_short[4];
1039 u16 rx_cfo_tail[4];
1040
1041 struct rt_smooth_data ui_rssi;
1042 struct rt_smooth_data ui_link_quality;
1043 };
1044
1045 struct rate_adaptive {
1046 u8 rate_adaptive_disabled;
1047 u8 ratr_state;
1048 u16 reserve;
1049
1050 u32 high_rssi_thresh_for_ra;
1051 u32 high2low_rssi_thresh_for_ra;
1052 u8 low2high_rssi_thresh_for_ra40m;
1053 u32 low_rssi_thresh_for_ra40m;
1054 u8 low2high_rssi_thresh_for_ra20m;
1055 u32 low_rssi_thresh_for_ra20m;
1056 u32 upper_rssi_threshold_ratr;
1057 u32 middleupper_rssi_threshold_ratr;
1058 u32 middle_rssi_threshold_ratr;
1059 u32 middlelow_rssi_threshold_ratr;
1060 u32 low_rssi_threshold_ratr;
1061 u32 ultralow_rssi_threshold_ratr;
1062 u32 low_rssi_threshold_ratr_40m;
1063 u32 low_rssi_threshold_ratr_20m;
1064 u8 ping_rssi_enable;
1065 u32 ping_rssi_ratr;
1066 u32 ping_rssi_thresh_for_ra;
1067 u32 last_ratr;
1068 u8 pre_ratr_state;
1069 u8 ldpc_thres;
1070 bool use_ldpc;
1071 bool lower_rts_rate;
1072 bool is_special_data;
1073 };
1074
1075 struct regd_pair_mapping {
1076 u16 reg_dmnenum;
1077 u16 reg_5ghz_ctl;
1078 u16 reg_2ghz_ctl;
1079 };
1080
1081 struct dynamic_primary_cca {
1082 u8 pricca_flag;
1083 u8 intf_flag;
1084 u8 intf_type;
1085 u8 dup_rts_flag;
1086 u8 monitor_flag;
1087 u8 ch_offset;
1088 u8 mf_state;
1089 };
1090
1091 struct rtl_regulatory {
1092 s8 alpha2[2];
1093 u16 country_code;
1094 u16 max_power_level;
1095 u32 tp_scale;
1096 u16 current_rd;
1097 u16 current_rd_ext;
1098 int16_t power_limit;
1099 struct regd_pair_mapping *regpair;
1100 };
1101
1102 struct rtl_rfkill {
1103 bool rfkill_state; /*0 is off, 1 is on */
1104 };
1105
1106 /*for P2P PS**/
1107 #define P2P_MAX_NOA_NUM 2
1108
1109 enum p2p_role {
1110 P2P_ROLE_DISABLE = 0,
1111 P2P_ROLE_DEVICE = 1,
1112 P2P_ROLE_CLIENT = 2,
1113 P2P_ROLE_GO = 3
1114 };
1115
1116 enum p2p_ps_state {
1117 P2P_PS_DISABLE = 0,
1118 P2P_PS_ENABLE = 1,
1119 P2P_PS_SCAN = 2,
1120 P2P_PS_SCAN_DONE = 3,
1121 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
1122 };
1123
1124 enum p2p_ps_mode {
1125 P2P_PS_NONE = 0,
1126 P2P_PS_CTWINDOW = 1,
1127 P2P_PS_NOA = 2,
1128 P2P_PS_MIX = 3, /* CTWindow and NoA */
1129 };
1130
1131 struct rtl_p2p_ps_info {
1132 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
1133 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
1134 u8 noa_index; /* Identifies instance of Notice of Absence timing. */
1135 /* Client traffic window. A period of time in TU after TBTT. */
1136 u8 ctwindow;
1137 u8 opp_ps; /* opportunistic power save. */
1138 u8 noa_num; /* number of NoA descriptor in P2P IE. */
1139 /* Count for owner, Type of client. */
1140 u8 noa_count_type[P2P_MAX_NOA_NUM];
1141 /* Max duration for owner, preferred or min acceptable duration
1142 * for client.
1143 */
1144 u32 noa_duration[P2P_MAX_NOA_NUM];
1145 /* Length of interval for owner, preferred or max acceptable intervali
1146 * of client.
1147 */
1148 u32 noa_interval[P2P_MAX_NOA_NUM];
1149 /* schedule in terms of the lower 4 bytes of the TSF timer. */
1150 u32 noa_start_time[P2P_MAX_NOA_NUM];
1151 };
1152
1153 struct p2p_ps_offload_t {
1154 u8 offload_en:1;
1155 u8 role:1; /* 1: Owner, 0: Client */
1156 u8 ctwindow_en:1;
1157 u8 noa0_en:1;
1158 u8 noa1_en:1;
1159 u8 allstasleep:1;
1160 u8 discovery:1;
1161 u8 reserved:1;
1162 };
1163
1164 #define IQK_MATRIX_REG_NUM 8
1165 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
1166
1167 struct iqk_matrix_regs {
1168 bool iqk_done;
1169 long value[1][IQK_MATRIX_REG_NUM];
1170 };
1171
1172 struct phy_parameters {
1173 u16 length;
1174 u32 *pdata;
1175 };
1176
1177 enum hw_param_tab_index {
1178 PHY_REG_2T,
1179 PHY_REG_1T,
1180 PHY_REG_PG,
1181 RADIOA_2T,
1182 RADIOB_2T,
1183 RADIOA_1T,
1184 RADIOB_1T,
1185 MAC_REG,
1186 AGCTAB_2T,
1187 AGCTAB_1T,
1188 MAX_TAB
1189 };
1190
1191 struct rtl_phy {
1192 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
1193 struct init_gain initgain_backup;
1194 enum io_type current_io_type;
1195
1196 u8 rf_mode;
1197 u8 rf_type;
1198 u8 current_chan_bw;
1199 u8 set_bwmode_inprogress;
1200 u8 sw_chnl_inprogress;
1201 u8 sw_chnl_stage;
1202 u8 sw_chnl_step;
1203 u8 current_channel;
1204 u8 h2c_box_num;
1205 u8 set_io_inprogress;
1206 u8 lck_inprogress;
1207
1208 /* record for power tracking */
1209 s32 reg_e94;
1210 s32 reg_e9c;
1211 s32 reg_ea4;
1212 s32 reg_eac;
1213 s32 reg_eb4;
1214 s32 reg_ebc;
1215 s32 reg_ec4;
1216 s32 reg_ecc;
1217 u8 rfpienable;
1218 u8 reserve_0;
1219 u16 reserve_1;
1220 u32 reg_c04, reg_c08, reg_874;
1221 u32 adda_backup[16];
1222 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1223 u32 iqk_bb_backup[10];
1224 bool iqk_initialized;
1225
1226 bool rfpath_rx_enable[MAX_RF_PATH];
1227 u8 reg_837;
1228 /* Dual mac */
1229 bool need_iqk;
1230 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1231
1232 bool rfpi_enable;
1233 bool iqk_in_progress;
1234
1235 u8 pwrgroup_cnt;
1236 u8 cck_high_power;
1237 /* this is for 88E & 8723A */
1238 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1239 /* MAX_PG_GROUP groups of pwr diff by rates */
1240 u32 mcs_offset[MAX_PG_GROUP][16];
1241 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1242 [TX_PWR_BY_RATE_NUM_RF]
1243 [TX_PWR_BY_RATE_NUM_RF]
1244 [TX_PWR_BY_RATE_NUM_SECTION];
1245 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1246 [TX_PWR_BY_RATE_NUM_RF]
1247 [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
1248 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1249 [TX_PWR_BY_RATE_NUM_RF]
1250 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
1251 u8 default_initialgain[4];
1252
1253 /* the current Tx power level */
1254 u8 cur_cck_txpwridx;
1255 u8 cur_ofdm24g_txpwridx;
1256 u8 cur_bw20_txpwridx;
1257 u8 cur_bw40_txpwridx;
1258
1259 s8 txpwr_limit_2_4g[MAX_REGULATION_NUM]
1260 [MAX_2_4G_BANDWITH_NUM]
1261 [MAX_RATE_SECTION_NUM]
1262 [CHANNEL_MAX_NUMBER_2G]
1263 [MAX_RF_PATH_NUM];
1264 s8 txpwr_limit_5g[MAX_REGULATION_NUM]
1265 [MAX_5G_BANDWITH_NUM]
1266 [MAX_RATE_SECTION_NUM]
1267 [CHANNEL_MAX_NUMBER_5G]
1268 [MAX_RF_PATH_NUM];
1269
1270 u32 rfreg_chnlval[2];
1271 bool apk_done;
1272 u32 reg_rf3c[2]; /* pathA / pathB */
1273
1274 u32 backup_rf_0x1a;/*92ee*/
1275 /* bfsync */
1276 u8 framesync;
1277 u32 framesync_c34;
1278
1279 u8 num_total_rfpath;
1280 struct phy_parameters hwparam_tables[MAX_TAB];
1281 u16 rf_pathmap;
1282
1283 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1284 enum rt_polarity_ctl polarity_ctl;
1285 };
1286
1287 #define MAX_TID_COUNT 9
1288 #define RTL_AGG_STOP 0
1289 #define RTL_AGG_PROGRESS 1
1290 #define RTL_AGG_START 2
1291 #define RTL_AGG_OPERATIONAL 3
1292 #define RTL_AGG_OFF 0
1293 #define RTL_AGG_ON 1
1294 #define RTL_RX_AGG_START 1
1295 #define RTL_RX_AGG_STOP 0
1296 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
1297 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
1298
1299 struct rtl_ht_agg {
1300 u16 txq_id;
1301 u16 wait_for_ba;
1302 u16 start_idx;
1303 u64 bitmap;
1304 u32 rate_n_flags;
1305 u8 agg_state;
1306 u8 rx_agg_state;
1307 };
1308
1309 struct rssi_sta {
1310 long undec_sm_pwdb;
1311 long undec_sm_cck;
1312 };
1313
1314 struct rtl_tid_data {
1315 u16 seq_number;
1316 struct rtl_ht_agg agg;
1317 };
1318
1319 struct rtl_sta_info {
1320 struct list_head list;
1321 struct rtl_tid_data tids[MAX_TID_COUNT];
1322 /* just used for ap adhoc or mesh*/
1323 struct rssi_sta rssi_stat;
1324 u16 wireless_mode;
1325 u8 ratr_index;
1326 u8 mimo_ps;
1327 u8 mac_addr[ETH_ALEN];
1328 } __packed;
1329
1330 struct rtl_priv;
1331 struct rtl_io {
1332 struct device *dev;
1333 struct mutex bb_mutex;
1334
1335 /*PCI MEM map */
1336 unsigned long pci_mem_end; /*shared mem end */
1337 unsigned long pci_mem_start; /*shared mem start */
1338
1339 /*PCI IO map */
1340 unsigned long pci_base_addr; /*device I/O address */
1341
1342 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
1343 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
1344 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
1345 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf,
1346 u16 len);
1347
1348 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
1349 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
1350 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
1351
1352 };
1353
1354 struct rtl_mac {
1355 u8 mac_addr[ETH_ALEN];
1356 u8 mac80211_registered;
1357 u8 beacon_enabled;
1358
1359 u32 tx_ss_num;
1360 u32 rx_ss_num;
1361
1362 struct ieee80211_supported_band bands[NUM_NL80211_BANDS];
1363 struct ieee80211_hw *hw;
1364 struct ieee80211_vif *vif;
1365 enum nl80211_iftype opmode;
1366
1367 /*Probe Beacon management */
1368 struct rtl_tid_data tids[MAX_TID_COUNT];
1369 enum rtl_link_state link_state;
1370
1371 int n_channels;
1372 int n_bitrates;
1373
1374 bool offchan_delay;
1375 u8 p2p; /*using p2p role*/
1376 bool p2p_in_use;
1377
1378 /*filters */
1379 u32 rx_conf;
1380 u16 rx_mgt_filter;
1381 u16 rx_ctrl_filter;
1382 u16 rx_data_filter;
1383
1384 bool act_scanning;
1385 u8 cnt_after_linked;
1386 bool skip_scan;
1387
1388 /* early mode */
1389 /* skb wait queue */
1390 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1391
1392 u8 ht_stbc_cap;
1393 u8 ht_cur_stbc;
1394
1395 /*vht support*/
1396 u8 vht_enable;
1397 u8 bw_80;
1398 u8 vht_cur_ldpc;
1399 u8 vht_cur_stbc;
1400 u8 vht_stbc_cap;
1401 u8 vht_ldpc_cap;
1402
1403 /*RDG*/
1404 bool rdg_en;
1405
1406 /*AP*/
1407 u8 bssid[ETH_ALEN] __aligned(2);
1408 u32 vendor;
1409 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1410 u32 basic_rates; /* b/g rates */
1411 u8 ht_enable;
1412 u8 sgi_40;
1413 u8 sgi_20;
1414 u8 bw_40;
1415 u16 mode; /* wireless mode */
1416 u8 slot_time;
1417 u8 short_preamble;
1418 u8 use_cts_protect;
1419 u8 cur_40_prime_sc;
1420 u8 cur_40_prime_sc_bk;
1421 u8 cur_80_prime_sc;
1422 u64 tsf;
1423 u8 retry_short;
1424 u8 retry_long;
1425 u16 assoc_id;
1426 bool hiddenssid;
1427
1428 /*IBSS*/
1429 int beacon_interval;
1430
1431 /*AMPDU*/
1432 u8 min_space_cfg; /*For Min spacing configurations */
1433 u8 max_mss_density;
1434 u8 current_ampdu_factor;
1435 u8 current_ampdu_density;
1436
1437 /*QOS & EDCA */
1438 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1439 struct rtl_qos_parameters ac[AC_MAX];
1440
1441 /* counters */
1442 u64 last_txok_cnt;
1443 u64 last_rxok_cnt;
1444 u32 last_bt_edca_ul;
1445 u32 last_bt_edca_dl;
1446 };
1447
1448 struct btdm_8723 {
1449 bool all_off;
1450 bool agc_table_en;
1451 bool adc_back_off_on;
1452 bool b2_ant_hid_en;
1453 bool low_penalty_rate_adaptive;
1454 bool rf_rx_lpf_shrink;
1455 bool reject_aggre_pkt;
1456 bool tra_tdma_on;
1457 u8 tra_tdma_nav;
1458 u8 tra_tdma_ant;
1459 bool tdma_on;
1460 u8 tdma_ant;
1461 u8 tdma_nav;
1462 u8 tdma_dac_swing;
1463 u8 fw_dac_swing_lvl;
1464 bool ps_tdma_on;
1465 u8 ps_tdma_byte[5];
1466 bool pta_on;
1467 u32 val_0x6c0;
1468 u32 val_0x6c8;
1469 u32 val_0x6cc;
1470 bool sw_dac_swing_on;
1471 u32 sw_dac_swing_lvl;
1472 u32 wlan_act_hi;
1473 u32 wlan_act_lo;
1474 u32 bt_retry_index;
1475 bool dec_bt_pwr;
1476 bool ignore_wlan_act;
1477 };
1478
1479 struct bt_coexist_8723 {
1480 u32 high_priority_tx;
1481 u32 high_priority_rx;
1482 u32 low_priority_tx;
1483 u32 low_priority_rx;
1484 u8 c2h_bt_info;
1485 bool c2h_bt_info_req_sent;
1486 bool c2h_bt_inquiry_page;
1487 u32 bt_inq_page_start_time;
1488 u8 bt_retry_cnt;
1489 u8 c2h_bt_info_original;
1490 u8 bt_inquiry_page_cnt;
1491 struct btdm_8723 btdm;
1492 };
1493
1494 struct rtl_hal {
1495 struct ieee80211_hw *hw;
1496 bool driver_is_goingto_unload;
1497 bool up_first_time;
1498 bool first_init;
1499 bool being_init_adapter;
1500 bool bbrf_ready;
1501 bool mac_func_enable;
1502 bool pre_edcca_enable;
1503 struct bt_coexist_8723 hal_coex_8723;
1504
1505 enum intf_type interface;
1506 u16 hw_type; /*92c or 92d or 92s and so on */
1507 u8 ic_class;
1508 u8 oem_id;
1509 u32 version; /*version of chip */
1510 u8 state; /*stop 0, start 1 */
1511 u8 board_type;
1512 u8 external_pa;
1513
1514 u8 pa_mode;
1515 u8 pa_type_2g;
1516 u8 pa_type_5g;
1517 u8 lna_type_2g;
1518 u8 lna_type_5g;
1519 u8 external_pa_2g;
1520 u8 external_lna_2g;
1521 u8 external_pa_5g;
1522 u8 external_lna_5g;
1523 u8 rfe_type;
1524
1525 /*firmware */
1526 u32 fwsize;
1527 u8 *pfirmware;
1528 u16 fw_version;
1529 u16 fw_subversion;
1530 bool h2c_setinprogress;
1531 u8 last_hmeboxnum;
1532 bool fw_ready;
1533 /*Reserve page start offset except beacon in TxQ. */
1534 u8 fw_rsvdpage_startoffset;
1535 u8 h2c_txcmd_seq;
1536 u8 current_ra_rate;
1537
1538 /* FW Cmd IO related */
1539 u16 fwcmd_iomap;
1540 u32 fwcmd_ioparam;
1541 bool set_fwcmd_inprogress;
1542 u8 current_fwcmd_io;
1543
1544 struct p2p_ps_offload_t p2p_ps_offload;
1545 bool fw_clk_change_in_progress;
1546 bool allow_sw_to_change_hwclc;
1547 u8 fw_ps_state;
1548 /**/
1549 bool driver_going2unload;
1550
1551 /*AMPDU init min space*/
1552 u8 minspace_cfg; /*For Min spacing configurations */
1553
1554 /* Dual mac */
1555 enum macphy_mode macphymode;
1556 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1557 enum band_type current_bandtypebackup;
1558 enum band_type bandset;
1559 /* dual MAC 0--Mac0 1--Mac1 */
1560 u32 interfaceindex;
1561 /* just for DualMac S3S4 */
1562 u8 macphyctl_reg;
1563 bool earlymode_enable;
1564 u8 max_earlymode_num;
1565 /* Dual mac*/
1566 bool during_mac0init_radiob;
1567 bool during_mac1init_radioa;
1568 bool reloadtxpowerindex;
1569 /* True if IMR or IQK have done
1570 for 2.4G in scan progress */
1571 bool load_imrandiqk_setting_for2g;
1572
1573 bool disable_amsdu_8k;
1574 bool master_of_dmsp;
1575 bool slave_of_dmsp;
1576
1577 u16 rx_tag;/*for 92ee*/
1578 u8 rts_en;
1579
1580 /*for wowlan*/
1581 bool wow_enable;
1582 bool enter_pnp_sleep;
1583 bool wake_from_pnp_sleep;
1584 bool wow_enabled;
1585 __kernel_time_t last_suspend_sec;
1586 u32 wowlan_fwsize;
1587 u8 *wowlan_firmware;
1588
1589 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1590
1591 bool real_wow_v2_enable;
1592 bool re_init_llt_table;
1593 };
1594
1595 struct rtl_security {
1596 /*default 0 */
1597 bool use_sw_sec;
1598
1599 bool being_setkey;
1600 bool use_defaultkey;
1601 /*Encryption Algorithm for Unicast Packet */
1602 enum rt_enc_alg pairwise_enc_algorithm;
1603 /*Encryption Algorithm for Brocast/Multicast */
1604 enum rt_enc_alg group_enc_algorithm;
1605 /*Cam Entry Bitmap */
1606 u32 hwsec_cam_bitmap;
1607 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1608 /*local Key buffer, indx 0 is for
1609 pairwise key 1-4 is for agoup key. */
1610 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1611 u8 key_len[KEY_BUF_SIZE];
1612
1613 /*The pointer of Pairwise Key,
1614 it always points to KeyBuf[4] */
1615 u8 *pairwise_key;
1616 };
1617
1618 #define ASSOCIATE_ENTRY_NUM 33
1619
1620 struct fast_ant_training {
1621 u8 bssid[6];
1622 u8 antsel_rx_keep_0;
1623 u8 antsel_rx_keep_1;
1624 u8 antsel_rx_keep_2;
1625 u32 ant_sum[7];
1626 u32 ant_cnt[7];
1627 u32 ant_ave[7];
1628 u8 fat_state;
1629 u32 train_idx;
1630 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1631 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1632 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1633 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1634 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1635 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1636 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1637 u8 rx_idle_ant;
1638 bool becomelinked;
1639 };
1640
1641 struct dm_phy_dbg_info {
1642 s8 rx_snrdb[4];
1643 u64 num_qry_phy_status;
1644 u64 num_qry_phy_status_cck;
1645 u64 num_qry_phy_status_ofdm;
1646 u16 num_qry_beacon_pkt;
1647 u16 num_non_be_pkt;
1648 s32 rx_evm[4];
1649 };
1650
1651 struct rtl_dm {
1652 /*PHY status for Dynamic Management */
1653 long entry_min_undec_sm_pwdb;
1654 long undec_sm_cck;
1655 long undec_sm_pwdb; /*out dm */
1656 long entry_max_undec_sm_pwdb;
1657 s32 ofdm_pkt_cnt;
1658 bool dm_initialgain_enable;
1659 bool dynamic_txpower_enable;
1660 bool current_turbo_edca;
1661 bool is_any_nonbepkts; /*out dm */
1662 bool is_cur_rdlstate;
1663 bool txpower_trackinginit;
1664 bool disable_framebursting;
1665 bool cck_inch14;
1666 bool txpower_tracking;
1667 bool useramask;
1668 bool rfpath_rxenable[4];
1669 bool inform_fw_driverctrldm;
1670 bool current_mrc_switch;
1671 u8 txpowercount;
1672 u8 powerindex_backup[6];
1673
1674 u8 thermalvalue_rxgain;
1675 u8 thermalvalue_iqk;
1676 u8 thermalvalue_lck;
1677 u8 thermalvalue;
1678 u8 last_dtp_lvl;
1679 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1680 u8 thermalvalue_avg_index;
1681 u8 tm_trigger;
1682 bool done_txpower;
1683 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1684 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1685 u8 dm_flag_tmp;
1686 u8 dm_type;
1687 u8 dm_rssi_sel;
1688 u8 txpower_track_control;
1689 bool interrupt_migration;
1690 bool disable_tx_int;
1691 s8 ofdm_index[MAX_RF_PATH];
1692 u8 default_ofdm_index;
1693 u8 default_cck_index;
1694 s8 cck_index;
1695 s8 delta_power_index[MAX_RF_PATH];
1696 s8 delta_power_index_last[MAX_RF_PATH];
1697 s8 power_index_offset[MAX_RF_PATH];
1698 s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
1699 s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
1700 s8 remnant_cck_idx;
1701 bool modify_txagc_flag_path_a;
1702 bool modify_txagc_flag_path_b;
1703
1704 bool one_entry_only;
1705 struct dm_phy_dbg_info dbginfo;
1706
1707 /* Dynamic ATC switch */
1708 bool atc_status;
1709 bool large_cfo_hit;
1710 bool is_freeze;
1711 int cfo_tail[2];
1712 int cfo_ave_pre;
1713 int crystal_cap;
1714 u8 cfo_threshold;
1715 u32 packet_count;
1716 u32 packet_count_pre;
1717 u8 tx_rate;
1718
1719 /*88e tx power tracking*/
1720 u8 swing_idx_ofdm[MAX_RF_PATH];
1721 u8 swing_idx_ofdm_cur;
1722 u8 swing_idx_ofdm_base[MAX_RF_PATH];
1723 bool swing_flag_ofdm;
1724 u8 swing_idx_cck;
1725 u8 swing_idx_cck_cur;
1726 u8 swing_idx_cck_base;
1727 bool swing_flag_cck;
1728
1729 s8 swing_diff_2g;
1730 s8 swing_diff_5g;
1731
1732 u8 delta_swing_table_idx_24gccka_p[DEL_SW_IDX_SZ];
1733 u8 delta_swing_table_idx_24gccka_n[DEL_SW_IDX_SZ];
1734 u8 delta_swing_table_idx_24gcckb_p[DEL_SW_IDX_SZ];
1735 u8 delta_swing_table_idx_24gcckb_n[DEL_SW_IDX_SZ];
1736 u8 delta_swing_table_idx_24ga_p[DEL_SW_IDX_SZ];
1737 u8 delta_swing_table_idx_24ga_n[DEL_SW_IDX_SZ];
1738 u8 delta_swing_table_idx_24gb_p[DEL_SW_IDX_SZ];
1739 u8 delta_swing_table_idx_24gb_n[DEL_SW_IDX_SZ];
1740 u8 delta_swing_table_idx_5ga_p[BAND_NUM][DEL_SW_IDX_SZ];
1741 u8 delta_swing_table_idx_5ga_n[BAND_NUM][DEL_SW_IDX_SZ];
1742 u8 delta_swing_table_idx_5gb_p[BAND_NUM][DEL_SW_IDX_SZ];
1743 u8 delta_swing_table_idx_5gb_n[BAND_NUM][DEL_SW_IDX_SZ];
1744 u8 delta_swing_table_idx_24ga_p_8188e[DEL_SW_IDX_SZ];
1745 u8 delta_swing_table_idx_24ga_n_8188e[DEL_SW_IDX_SZ];
1746
1747 /* DMSP */
1748 bool supp_phymode_switch;
1749
1750 /* DulMac */
1751 struct fast_ant_training fat_table;
1752
1753 u8 resp_tx_path;
1754 u8 path_sel;
1755 u32 patha_sum;
1756 u32 pathb_sum;
1757 u32 patha_cnt;
1758 u32 pathb_cnt;
1759
1760 u8 pre_channel;
1761 u8 *p_channel;
1762 u8 linked_interval;
1763
1764 u64 last_tx_ok_cnt;
1765 u64 last_rx_ok_cnt;
1766 };
1767
1768 #define EFUSE_MAX_LOGICAL_SIZE 512
1769
1770 struct rtl_efuse {
1771 bool autoLoad_ok;
1772 bool bootfromefuse;
1773 u16 max_physical_size;
1774
1775 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1776 u16 efuse_usedbytes;
1777 u8 efuse_usedpercentage;
1778 #ifdef EFUSE_REPG_WORKAROUND
1779 bool efuse_re_pg_sec1flag;
1780 u8 efuse_re_pg_data[8];
1781 #endif
1782
1783 u8 autoload_failflag;
1784 u8 autoload_status;
1785
1786 short epromtype;
1787 u16 eeprom_vid;
1788 u16 eeprom_did;
1789 u16 eeprom_svid;
1790 u16 eeprom_smid;
1791 u8 eeprom_oemid;
1792 u16 eeprom_channelplan;
1793 u8 eeprom_version;
1794 u8 board_type;
1795 u8 external_pa;
1796
1797 u8 dev_addr[6];
1798 u8 wowlan_enable;
1799 u8 antenna_div_cfg;
1800 u8 antenna_div_type;
1801
1802 bool txpwr_fromeprom;
1803 u8 eeprom_crystalcap;
1804 u8 eeprom_tssi[2];
1805 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1806 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1807 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1808 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
1809 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1810 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1811
1812 u8 internal_pa_5g[2]; /* pathA / pathB */
1813 u8 eeprom_c9;
1814 u8 eeprom_cc;
1815
1816 /*For power group */
1817 u8 eeprom_pwrgroup[2][3];
1818 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1819 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1820
1821 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
1822 /*For HT 40MHZ pwr */
1823 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1824 /*For HT 40MHZ pwr */
1825 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1826
1827 /*--------------------------------------------------------*
1828 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays,
1829 * other ICs (8188EE\8723BE\8192EE\8812AE...)
1830 * define new arrays in Windows code.
1831 * BUT, in linux code, we use the same array for all ICs.
1832 *
1833 * The Correspondance relation between two arrays is:
1834 * txpwr_cckdiff[][] == CCK_24G_Diff[][]
1835 * txpwr_ht20diff[][] == BW20_24G_Diff[][]
1836 * txpwr_ht40diff[][] == BW40_24G_Diff[][]
1837 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][]
1838 *
1839 * Sizes of these arrays are decided by the larger ones.
1840 */
1841 s8 txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1842 s8 txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1843 s8 txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1844 s8 txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1845
1846 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1847 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
1848 s8 txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
1849 s8 txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
1850 s8 txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
1851 s8 txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
1852
1853 u8 txpwr_safetyflag; /* Band edge enable flag */
1854 u16 eeprom_txpowerdiff;
1855 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1856 u8 antenna_txpwdiff[3];
1857
1858 u8 eeprom_regulatory;
1859 u8 eeprom_thermalmeter;
1860 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1861 u16 tssi_13dbm;
1862 u8 crystalcap; /* CrystalCap. */
1863 u8 delta_iqk;
1864 u8 delta_lck;
1865
1866 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1867 bool apk_thermalmeterignore;
1868
1869 bool b1x1_recvcombine;
1870 bool b1ss_support;
1871
1872 /*channel plan */
1873 u8 channel_plan;
1874 };
1875
1876 struct rtl_ps_ctl {
1877 bool pwrdomain_protect;
1878 bool in_powersavemode;
1879 bool rfchange_inprogress;
1880 bool swrf_processing;
1881 bool hwradiooff;
1882 /*
1883 * just for PCIE ASPM
1884 * If it supports ASPM, Offset[560h] = 0x40,
1885 * otherwise Offset[560h] = 0x00.
1886 * */
1887 bool support_aspm;
1888 bool support_backdoor;
1889
1890 /*for LPS */
1891 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1892 bool swctrl_lps;
1893 bool leisure_ps;
1894 bool fwctrl_lps;
1895 u8 fwctrl_psmode;
1896 /*For Fw control LPS mode */
1897 u8 reg_fwctrl_lps;
1898 /*Record Fw PS mode status. */
1899 bool fw_current_inpsmode;
1900 u8 reg_max_lps_awakeintvl;
1901 bool report_linked;
1902 bool low_power_enable;/*for 32k*/
1903
1904 /*for IPS */
1905 bool inactiveps;
1906
1907 u32 rfoff_reason;
1908
1909 /*RF OFF Level */
1910 u32 cur_ps_level;
1911 u32 reg_rfps_level;
1912
1913 /*just for PCIE ASPM */
1914 u8 const_amdpci_aspm;
1915 bool pwrdown_mode;
1916
1917 enum rf_pwrstate inactive_pwrstate;
1918 enum rf_pwrstate rfpwr_state; /*cur power state */
1919
1920 /* for SW LPS*/
1921 bool sw_ps_enabled;
1922 bool state;
1923 bool state_inap;
1924 bool multi_buffered;
1925 u16 nullfunc_seq;
1926 unsigned int dtim_counter;
1927 unsigned int sleep_ms;
1928 unsigned long last_sleep_jiffies;
1929 unsigned long last_awake_jiffies;
1930 unsigned long last_delaylps_stamp_jiffies;
1931 unsigned long last_dtim;
1932 unsigned long last_beacon;
1933 unsigned long last_action;
1934 unsigned long last_slept;
1935
1936 /*For P2P PS */
1937 struct rtl_p2p_ps_info p2p_ps_info;
1938 u8 pwr_mode;
1939 u8 smart_ps;
1940
1941 /* wake up on line */
1942 u8 wo_wlan_mode;
1943 u8 arp_offload_enable;
1944 u8 gtk_offload_enable;
1945 /* Used for WOL, indicates the reason for waking event.*/
1946 u32 wakeup_reason;
1947 /* Record the last waking time for comparison with setting key. */
1948 u64 last_wakeup_time;
1949 };
1950
1951 struct rtl_stats {
1952 u8 psaddr[ETH_ALEN];
1953 u32 mac_time[2];
1954 s8 rssi;
1955 u8 signal;
1956 u8 noise;
1957 u8 rate; /* hw desc rate */
1958 u8 received_channel;
1959 u8 control;
1960 u8 mask;
1961 u8 freq;
1962 u16 len;
1963 u64 tsf;
1964 u32 beacon_time;
1965 u8 nic_type;
1966 u16 length;
1967 u8 signalquality; /*in 0-100 index. */
1968 /*
1969 * Real power in dBm for this packet,
1970 * no beautification and aggregation.
1971 * */
1972 s32 recvsignalpower;
1973 s8 rxpower; /*in dBm Translate from PWdB */
1974 u8 signalstrength; /*in 0-100 index. */
1975 u16 hwerror:1;
1976 u16 crc:1;
1977 u16 icv:1;
1978 u16 shortpreamble:1;
1979 u16 antenna:1;
1980 u16 decrypted:1;
1981 u16 wakeup:1;
1982 u32 timestamp_low;
1983 u32 timestamp_high;
1984 bool shift;
1985
1986 u8 rx_drvinfo_size;
1987 u8 rx_bufshift;
1988 bool isampdu;
1989 bool isfirst_ampdu;
1990 bool rx_is40Mhzpacket;
1991 u8 rx_packet_bw;
1992 u32 rx_pwdb_all;
1993 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1994 s8 rx_mimo_signalquality[4];
1995 u8 rx_mimo_evm_dbm[4];
1996 u16 cfo_short[4]; /* per-path's Cfo_short */
1997 u16 cfo_tail[4];
1998
1999 s8 rx_mimo_sig_qual[4];
2000 u8 rx_pwr[4]; /* per-path's pwdb */
2001 u8 rx_snr[4]; /* per-path's SNR */
2002 u8 bandwidth;
2003 u8 bt_coex_pwr_adjust;
2004 bool packet_matchbssid;
2005 bool is_cck;
2006 bool is_ht;
2007 bool packet_toself;
2008 bool packet_beacon; /*for rssi */
2009 s8 cck_adc_pwdb[4]; /*for rx path selection */
2010
2011 bool is_vht;
2012 bool is_short_gi;
2013 u8 vht_nss;
2014
2015 u8 packet_report_type;
2016
2017 u32 macid;
2018 u8 wake_match;
2019 u32 bt_rx_rssi_percentage;
2020 u32 macid_valid_entry[2];
2021 };
2022
2023
2024 struct rt_link_detect {
2025 /* count for roaming */
2026 u32 bcn_rx_inperiod;
2027 u32 roam_times;
2028
2029 u32 num_tx_in4period[4];
2030 u32 num_rx_in4period[4];
2031
2032 u32 num_tx_inperiod;
2033 u32 num_rx_inperiod;
2034
2035 bool busytraffic;
2036 bool tx_busy_traffic;
2037 bool rx_busy_traffic;
2038 bool higher_busytraffic;
2039 bool higher_busyrxtraffic;
2040
2041 u32 tidtx_in4period[MAX_TID_COUNT][4];
2042 u32 tidtx_inperiod[MAX_TID_COUNT];
2043 bool higher_busytxtraffic[MAX_TID_COUNT];
2044 };
2045
2046 struct rtl_tcb_desc {
2047 u8 packet_bw:2;
2048 u8 multicast:1;
2049 u8 broadcast:1;
2050
2051 u8 rts_stbc:1;
2052 u8 rts_enable:1;
2053 u8 cts_enable:1;
2054 u8 rts_use_shortpreamble:1;
2055 u8 rts_use_shortgi:1;
2056 u8 rts_sc:1;
2057 u8 rts_bw:1;
2058 u8 rts_rate;
2059
2060 u8 use_shortgi:1;
2061 u8 use_shortpreamble:1;
2062 u8 use_driver_rate:1;
2063 u8 disable_ratefallback:1;
2064
2065 u8 ratr_index;
2066 u8 mac_id;
2067 u8 hw_rate;
2068
2069 u8 last_inipkt:1;
2070 u8 cmd_or_init:1;
2071 u8 queue_index;
2072
2073 /* early mode */
2074 u8 empkt_num;
2075 /* The max value by HW */
2076 u32 empkt_len[10];
2077 bool tx_enable_sw_calc_duration;
2078 };
2079
2080 struct rtl_wow_pattern {
2081 u8 type;
2082 u16 crc;
2083 u32 mask[4];
2084 };
2085
2086 struct rtl_hal_ops {
2087 int (*init_sw_vars) (struct ieee80211_hw *hw);
2088 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
2089 void (*read_chip_version)(struct ieee80211_hw *hw);
2090 void (*read_eeprom_info) (struct ieee80211_hw *hw);
2091 void (*interrupt_recognized) (struct ieee80211_hw *hw,
2092 u32 *p_inta, u32 *p_intb);
2093 int (*hw_init) (struct ieee80211_hw *hw);
2094 void (*hw_disable) (struct ieee80211_hw *hw);
2095 void (*hw_suspend) (struct ieee80211_hw *hw);
2096 void (*hw_resume) (struct ieee80211_hw *hw);
2097 void (*enable_interrupt) (struct ieee80211_hw *hw);
2098 void (*disable_interrupt) (struct ieee80211_hw *hw);
2099 int (*set_network_type) (struct ieee80211_hw *hw,
2100 enum nl80211_iftype type);
2101 void (*set_chk_bssid)(struct ieee80211_hw *hw,
2102 bool check_bssid);
2103 void (*set_bw_mode) (struct ieee80211_hw *hw,
2104 enum nl80211_channel_type ch_type);
2105 u8(*switch_channel) (struct ieee80211_hw *hw);
2106 void (*set_qos) (struct ieee80211_hw *hw, int aci);
2107 void (*set_bcn_reg) (struct ieee80211_hw *hw);
2108 void (*set_bcn_intv) (struct ieee80211_hw *hw);
2109 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
2110 u32 add_msr, u32 rm_msr);
2111 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
2112 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
2113 void (*update_rate_tbl) (struct ieee80211_hw *hw,
2114 struct ieee80211_sta *sta, u8 rssi_level);
2115 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc,
2116 u8 *desc, u8 queue_index,
2117 struct sk_buff *skb, dma_addr_t addr);
2118 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
2119 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw,
2120 u8 queue_index);
2121 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc,
2122 u8 queue_index);
2123 void (*fill_tx_desc) (struct ieee80211_hw *hw,
2124 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
2125 u8 *pbd_desc_tx,
2126 struct ieee80211_tx_info *info,
2127 struct ieee80211_sta *sta,
2128 struct sk_buff *skb, u8 hw_queue,
2129 struct rtl_tcb_desc *ptcb_desc);
2130 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
2131 u32 buffer_len, bool bIsPsPoll);
2132 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
2133 bool firstseg, bool lastseg,
2134 struct sk_buff *skb);
2135 bool (*query_rx_desc) (struct ieee80211_hw *hw,
2136 struct rtl_stats *stats,
2137 struct ieee80211_rx_status *rx_status,
2138 u8 *pdesc, struct sk_buff *skb);
2139 void (*set_channel_access) (struct ieee80211_hw *hw);
2140 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
2141 void (*dm_watchdog) (struct ieee80211_hw *hw);
2142 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
2143 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
2144 enum rf_pwrstate rfpwr_state);
2145 void (*led_control) (struct ieee80211_hw *hw,
2146 enum led_ctl_mode ledaction);
2147 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2148 u8 desc_name, u8 *val);
2149 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
2150 bool (*is_tx_desc_closed) (struct ieee80211_hw *hw,
2151 u8 hw_queue, u16 index);
2152 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
2153 void (*enable_hw_sec) (struct ieee80211_hw *hw);
2154 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
2155 u8 *macaddr, bool is_group, u8 enc_algo,
2156 bool is_wepkey, bool clear_all);
2157 void (*init_sw_leds) (struct ieee80211_hw *hw);
2158 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
2159 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
2160 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
2161 u32 data);
2162 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
2163 u32 regaddr, u32 bitmask);
2164 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
2165 u32 regaddr, u32 bitmask, u32 data);
2166 void (*linked_set_reg) (struct ieee80211_hw *hw);
2167 void (*chk_switch_dmdp) (struct ieee80211_hw *hw);
2168 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw);
2169 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw);
2170 bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
2171 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
2172 u8 *powerlevel);
2173 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
2174 u8 *ppowerlevel, u8 channel);
2175 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
2176 u8 configtype);
2177 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
2178 u8 configtype);
2179 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
2180 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
2181 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
2182 void (*c2h_command_handle) (struct ieee80211_hw *hw);
2183 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw,
2184 bool mstate);
2185 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
2186 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
2187 u32 cmd_len, u8 *p_cmdbuffer);
2188 bool (*get_btc_status) (void);
2189 bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr);
2190 u32 (*rx_command_packet)(struct ieee80211_hw *hw,
2191 const struct rtl_stats *status, struct sk_buff *skb);
2192 void (*add_wowlan_pattern)(struct ieee80211_hw *hw,
2193 struct rtl_wow_pattern *rtl_pattern,
2194 u8 index);
2195 u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx);
2196 };
2197
2198 struct rtl_intf_ops {
2199 /*com */
2200 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
2201 int (*adapter_start) (struct ieee80211_hw *hw);
2202 void (*adapter_stop) (struct ieee80211_hw *hw);
2203 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
2204 struct rtl_priv **buddy_priv);
2205
2206 int (*adapter_tx) (struct ieee80211_hw *hw,
2207 struct ieee80211_sta *sta,
2208 struct sk_buff *skb,
2209 struct rtl_tcb_desc *ptcb_desc);
2210 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop);
2211 int (*reset_trx_ring) (struct ieee80211_hw *hw);
2212 bool (*waitq_insert) (struct ieee80211_hw *hw,
2213 struct ieee80211_sta *sta,
2214 struct sk_buff *skb);
2215
2216 /*pci */
2217 void (*disable_aspm) (struct ieee80211_hw *hw);
2218 void (*enable_aspm) (struct ieee80211_hw *hw);
2219
2220 /*usb */
2221 };
2222
2223 struct rtl_mod_params {
2224 /* default: 0 = using hardware encryption */
2225 bool sw_crypto;
2226
2227 /* default: 0 = DBG_EMERG (0)*/
2228 int debug;
2229
2230 /* default: 1 = using no linked power save */
2231 bool inactiveps;
2232
2233 /* default: 1 = using linked sw power save */
2234 bool swctrl_lps;
2235
2236 /* default: 1 = using linked fw power save */
2237 bool fwctrl_lps;
2238
2239 /* default: 0 = not using MSI interrupts mode
2240 * submodules should set their own default value
2241 */
2242 bool msi_support;
2243
2244 /* default 0: 1 means disable */
2245 bool disable_watchdog;
2246
2247 /* default 0: 1 means do not disable interrupts */
2248 bool int_clear;
2249
2250 /* select antenna */
2251 int ant_sel;
2252 };
2253
2254 struct rtl_hal_usbint_cfg {
2255 /* data - rx */
2256 u32 in_ep_num;
2257 u32 rx_urb_num;
2258 u32 rx_max_size;
2259
2260 /* op - rx */
2261 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
2262 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
2263 struct sk_buff_head *);
2264
2265 /* tx */
2266 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
2267 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
2268 struct sk_buff *);
2269 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
2270 struct sk_buff_head *);
2271
2272 /* endpoint mapping */
2273 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
2274 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
2275 };
2276
2277 struct rtl_hal_cfg {
2278 u8 bar_id;
2279 bool write_readback;
2280 char *name;
2281 char *alt_fw_name;
2282 struct rtl_hal_ops *ops;
2283 struct rtl_mod_params *mod_params;
2284 struct rtl_hal_usbint_cfg *usb_interface_cfg;
2285
2286 /*this map used for some registers or vars
2287 defined int HAL but used in MAIN */
2288 u32 maps[RTL_VAR_MAP_MAX];
2289
2290 };
2291
2292 struct rtl_locks {
2293 /* mutex */
2294 struct mutex conf_mutex;
2295 struct mutex ps_mutex;
2296
2297 /*spin lock */
2298 spinlock_t ips_lock;
2299 spinlock_t irq_th_lock;
2300 spinlock_t irq_pci_lock;
2301 spinlock_t tx_lock;
2302 spinlock_t h2c_lock;
2303 spinlock_t rf_ps_lock;
2304 spinlock_t rf_lock;
2305 spinlock_t lps_lock;
2306 spinlock_t waitq_lock;
2307 spinlock_t entry_list_lock;
2308 spinlock_t usb_lock;
2309
2310 /*FW clock change */
2311 spinlock_t fw_ps_lock;
2312
2313 /*Dual mac*/
2314 spinlock_t cck_and_rw_pagea_lock;
2315
2316 /*Easy concurrent*/
2317 spinlock_t check_sendpkt_lock;
2318
2319 spinlock_t iqk_lock;
2320 };
2321
2322 struct rtl_works {
2323 struct ieee80211_hw *hw;
2324
2325 /*timer */
2326 struct timer_list watchdog_timer;
2327 struct timer_list dualmac_easyconcurrent_retrytimer;
2328 struct timer_list fw_clockoff_timer;
2329 struct timer_list fast_antenna_training_timer;
2330 /*task */
2331 struct tasklet_struct irq_tasklet;
2332 struct tasklet_struct irq_prepare_bcn_tasklet;
2333
2334 /*work queue */
2335 struct workqueue_struct *rtl_wq;
2336 struct delayed_work watchdog_wq;
2337 struct delayed_work ips_nic_off_wq;
2338
2339 /* For SW LPS */
2340 struct delayed_work ps_work;
2341 struct delayed_work ps_rfon_wq;
2342 struct delayed_work fwevt_wq;
2343
2344 struct work_struct lps_change_work;
2345 struct work_struct fill_h2c_cmd;
2346 };
2347
2348 struct rtl_debug {
2349 u32 dbgp_type[DBGP_TYPE_MAX];
2350 int global_debuglevel;
2351 u64 global_debugcomponents;
2352
2353 /* add for proc debug */
2354 struct proc_dir_entry *proc_dir;
2355 char proc_name[20];
2356 };
2357
2358 #define MIMO_PS_STATIC 0
2359 #define MIMO_PS_DYNAMIC 1
2360 #define MIMO_PS_NOLIMIT 3
2361
2362 struct rtl_dualmac_easy_concurrent_ctl {
2363 enum band_type currentbandtype_backfordmdp;
2364 bool close_bbandrf_for_dmsp;
2365 bool change_to_dmdp;
2366 bool change_to_dmsp;
2367 bool switch_in_process;
2368 };
2369
2370 struct rtl_dmsp_ctl {
2371 bool activescan_for_slaveofdmsp;
2372 bool scan_for_anothermac_fordmsp;
2373 bool scan_for_itself_fordmsp;
2374 bool writedig_for_anothermacofdmsp;
2375 u32 curdigvalue_for_anothermacofdmsp;
2376 bool changecckpdstate_for_anothermacofdmsp;
2377 u8 curcckpdstate_for_anothermacofdmsp;
2378 bool changetxhighpowerlvl_for_anothermacofdmsp;
2379 u8 curtxhighlvl_for_anothermacofdmsp;
2380 long rssivalmin_for_anothermacofdmsp;
2381 };
2382
2383 struct ps_t {
2384 u8 pre_ccastate;
2385 u8 cur_ccasate;
2386 u8 pre_rfstate;
2387 u8 cur_rfstate;
2388 u8 initialize;
2389 long rssi_val_min;
2390 };
2391
2392 struct dig_t {
2393 u32 rssi_lowthresh;
2394 u32 rssi_highthresh;
2395 u32 fa_lowthresh;
2396 u32 fa_highthresh;
2397 long last_min_undec_pwdb_for_dm;
2398 long rssi_highpower_lowthresh;
2399 long rssi_highpower_highthresh;
2400 u32 recover_cnt;
2401 u32 pre_igvalue;
2402 u32 cur_igvalue;
2403 long rssi_val;
2404 u8 dig_enable_flag;
2405 u8 dig_ext_port_stage;
2406 u8 dig_algorithm;
2407 u8 dig_twoport_algorithm;
2408 u8 dig_dbgmode;
2409 u8 dig_slgorithm_switch;
2410 u8 cursta_cstate;
2411 u8 presta_cstate;
2412 u8 curmultista_cstate;
2413 u8 stop_dig;
2414 s8 back_val;
2415 s8 back_range_max;
2416 s8 back_range_min;
2417 u8 rx_gain_max;
2418 u8 rx_gain_min;
2419 u8 min_undec_pwdb_for_dm;
2420 u8 rssi_val_min;
2421 u8 pre_cck_cca_thres;
2422 u8 cur_cck_cca_thres;
2423 u8 pre_cck_pd_state;
2424 u8 cur_cck_pd_state;
2425 u8 pre_cck_fa_state;
2426 u8 cur_cck_fa_state;
2427 u8 pre_ccastate;
2428 u8 cur_ccasate;
2429 u8 large_fa_hit;
2430 u8 forbidden_igi;
2431 u8 dig_state;
2432 u8 dig_highpwrstate;
2433 u8 cur_sta_cstate;
2434 u8 pre_sta_cstate;
2435 u8 cur_ap_cstate;
2436 u8 pre_ap_cstate;
2437 u8 cur_pd_thstate;
2438 u8 pre_pd_thstate;
2439 u8 cur_cs_ratiostate;
2440 u8 pre_cs_ratiostate;
2441 u8 backoff_enable_flag;
2442 s8 backoffval_range_max;
2443 s8 backoffval_range_min;
2444 u8 dig_min_0;
2445 u8 dig_min_1;
2446 u8 bt30_cur_igi;
2447 bool media_connect_0;
2448 bool media_connect_1;
2449
2450 u32 antdiv_rssi_max;
2451 u32 rssi_max;
2452 };
2453
2454 struct rtl_global_var {
2455 /* from this list we can get
2456 * other adapter's rtl_priv */
2457 struct list_head glb_priv_list;
2458 spinlock_t glb_list_lock;
2459 };
2460
2461 struct rtl_btc_info {
2462 u8 bt_type;
2463 u8 btcoexist;
2464 u8 ant_num;
2465 };
2466
2467 struct bt_coexist_info {
2468 struct rtl_btc_ops *btc_ops;
2469 struct rtl_btc_info btc_info;
2470 /* EEPROM BT info. */
2471 u8 eeprom_bt_coexist;
2472 u8 eeprom_bt_type;
2473 u8 eeprom_bt_ant_num;
2474 u8 eeprom_bt_ant_isol;
2475 u8 eeprom_bt_radio_shared;
2476
2477 u8 bt_coexistence;
2478 u8 bt_ant_num;
2479 u8 bt_coexist_type;
2480 u8 bt_state;
2481 u8 bt_cur_state; /* 0:on, 1:off */
2482 u8 bt_ant_isolation; /* 0:good, 1:bad */
2483 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2484 u8 bt_service;
2485 u8 bt_radio_shared_type;
2486 u8 bt_rfreg_origin_1e;
2487 u8 bt_rfreg_origin_1f;
2488 u8 bt_rssi_state;
2489 u32 ratio_tx;
2490 u32 ratio_pri;
2491 u32 bt_edca_ul;
2492 u32 bt_edca_dl;
2493
2494 bool init_set;
2495 bool bt_busy_traffic;
2496 bool bt_traffic_mode_set;
2497 bool bt_non_traffic_mode_set;
2498
2499 bool fw_coexist_all_off;
2500 bool sw_coexist_all_off;
2501 bool hw_coexist_all_off;
2502 u32 cstate;
2503 u32 previous_state;
2504 u32 cstate_h;
2505 u32 previous_state_h;
2506
2507 u8 bt_pre_rssi_state;
2508 u8 bt_pre_rssi_state1;
2509
2510 u8 reg_bt_iso;
2511 u8 reg_bt_sco;
2512 bool balance_on;
2513 u8 bt_active_zero_cnt;
2514 bool cur_bt_disabled;
2515 bool pre_bt_disabled;
2516
2517 u8 bt_profile_case;
2518 u8 bt_profile_action;
2519 bool bt_busy;
2520 bool hold_for_bt_operation;
2521 u8 lps_counter;
2522 };
2523
2524 struct rtl_btc_ops {
2525 void (*btc_init_variables) (struct rtl_priv *rtlpriv);
2526 void (*btc_init_hal_vars) (struct rtl_priv *rtlpriv);
2527 void (*btc_init_hw_config) (struct rtl_priv *rtlpriv);
2528 void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type);
2529 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type);
2530 void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype);
2531 void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action);
2532 void (*btc_mediastatus_notify) (struct rtl_priv *rtlpriv,
2533 enum rt_media_status mstatus);
2534 void (*btc_periodical) (struct rtl_priv *rtlpriv);
2535 void (*btc_halt_notify) (void);
2536 void (*btc_btinfo_notify) (struct rtl_priv *rtlpriv,
2537 u8 *tmp_buf, u8 length);
2538 bool (*btc_is_limited_dig) (struct rtl_priv *rtlpriv);
2539 bool (*btc_is_disable_edca_turbo) (struct rtl_priv *rtlpriv);
2540 bool (*btc_is_bt_disabled) (struct rtl_priv *rtlpriv);
2541 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv,
2542 u8 pkt_type);
2543 };
2544
2545 struct proxim {
2546 bool proxim_on;
2547
2548 void *proximity_priv;
2549 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status,
2550 struct sk_buff *skb);
2551 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
2552 };
2553
2554 struct rtl_priv {
2555 struct ieee80211_hw *hw;
2556 struct completion firmware_loading_complete;
2557 struct list_head list;
2558 struct rtl_priv *buddy_priv;
2559 struct rtl_global_var *glb_var;
2560 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
2561 struct rtl_dmsp_ctl dmsp_ctl;
2562 struct rtl_locks locks;
2563 struct rtl_works works;
2564 struct rtl_mac mac80211;
2565 struct rtl_hal rtlhal;
2566 struct rtl_regulatory regd;
2567 struct rtl_rfkill rfkill;
2568 struct rtl_io io;
2569 struct rtl_phy phy;
2570 struct rtl_dm dm;
2571 struct rtl_security sec;
2572 struct rtl_efuse efuse;
2573
2574 struct rtl_ps_ctl psc;
2575 struct rate_adaptive ra;
2576 struct dynamic_primary_cca primarycca;
2577 struct wireless_stats stats;
2578 struct rt_link_detect link_info;
2579 struct false_alarm_statistics falsealm_cnt;
2580
2581 struct rtl_rate_priv *rate_priv;
2582
2583 /* sta entry list for ap adhoc or mesh */
2584 struct list_head entry_list;
2585
2586 struct rtl_debug dbg;
2587 int max_fw_size;
2588
2589 /*
2590 *hal_cfg : for diff cards
2591 *intf_ops : for diff interrface usb/pcie
2592 */
2593 struct rtl_hal_cfg *cfg;
2594 const struct rtl_intf_ops *intf_ops;
2595
2596 /*this var will be set by set_bit,
2597 and was used to indicate status of
2598 interface or hardware */
2599 unsigned long status;
2600
2601 /* tables for dm */
2602 struct dig_t dm_digtable;
2603 struct ps_t dm_pstable;
2604
2605 u32 reg_874;
2606 u32 reg_c70;
2607 u32 reg_85c;
2608 u32 reg_a74;
2609 bool reg_init; /* true if regs saved */
2610 bool bt_operation_on;
2611 __le32 *usb_data;
2612 int usb_data_index;
2613 bool initialized;
2614 bool enter_ps; /* true when entering PS */
2615 u8 rate_mask[5];
2616
2617 /* intel Proximity, should be alloc mem
2618 * in intel Proximity module and can only
2619 * be used in intel Proximity mode
2620 */
2621 struct proxim proximity;
2622
2623 /*for bt coexist use*/
2624 struct bt_coexist_info btcoexist;
2625
2626 /* separate 92ee from other ICs,
2627 * 92ee use new trx flow.
2628 */
2629 bool use_new_trx_flow;
2630
2631 #ifdef CONFIG_PM
2632 struct wiphy_wowlan_support wowlan;
2633 #endif
2634 /*This must be the last item so
2635 that it points to the data allocated
2636 beyond this structure like:
2637 rtl_pci_priv or rtl_usb_priv */
2638 u8 priv[0] __aligned(sizeof(void *));
2639 };
2640
2641 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2642 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2643 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2644 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2645 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2646
2647
2648 /***************************************
2649 Bluetooth Co-existence Related
2650 ****************************************/
2651
2652 enum bt_ant_num {
2653 ANT_X2 = 0,
2654 ANT_X1 = 1,
2655 };
2656
2657 enum bt_co_type {
2658 BT_2WIRE = 0,
2659 BT_ISSC_3WIRE = 1,
2660 BT_ACCEL = 2,
2661 BT_CSR_BC4 = 3,
2662 BT_CSR_BC8 = 4,
2663 BT_RTL8756 = 5,
2664 BT_RTL8723A = 6,
2665 BT_RTL8821A = 7,
2666 BT_RTL8723B = 8,
2667 BT_RTL8192E = 9,
2668 BT_RTL8812A = 11,
2669 };
2670
2671 enum bt_total_ant_num {
2672 ANT_TOTAL_X2 = 0,
2673 ANT_TOTAL_X1 = 1
2674 };
2675
2676 enum bt_cur_state {
2677 BT_OFF = 0,
2678 BT_ON = 1,
2679 };
2680
2681 enum bt_service_type {
2682 BT_SCO = 0,
2683 BT_A2DP = 1,
2684 BT_HID = 2,
2685 BT_HID_IDLE = 3,
2686 BT_SCAN = 4,
2687 BT_IDLE = 5,
2688 BT_OTHER_ACTION = 6,
2689 BT_BUSY = 7,
2690 BT_OTHERBUSY = 8,
2691 BT_PAN = 9,
2692 };
2693
2694 enum bt_radio_shared {
2695 BT_RADIO_SHARED = 0,
2696 BT_RADIO_INDIVIDUAL = 1,
2697 };
2698
2699
2700 /****************************************
2701 mem access macro define start
2702 Call endian free function when
2703 1. Read/write packet content.
2704 2. Before write integer to IO.
2705 3. After read integer from IO.
2706 ****************************************/
2707 /* Convert little data endian to host ordering */
2708 #define EF1BYTE(_val) \
2709 ((u8)(_val))
2710 #define EF2BYTE(_val) \
2711 (le16_to_cpu(_val))
2712 #define EF4BYTE(_val) \
2713 (le32_to_cpu(_val))
2714
2715 /* Read data from memory */
2716 #define READEF1BYTE(_ptr) \
2717 EF1BYTE(*((u8 *)(_ptr)))
2718 /* Read le16 data from memory and convert to host ordering */
2719 #define READEF2BYTE(_ptr) \
2720 EF2BYTE(*(_ptr))
2721 #define READEF4BYTE(_ptr) \
2722 EF4BYTE(*(_ptr))
2723
2724 /* Write data to memory */
2725 #define WRITEEF1BYTE(_ptr, _val) \
2726 (*((u8 *)(_ptr))) = EF1BYTE(_val)
2727 /* Write le16 data to memory in host ordering */
2728 #define WRITEEF2BYTE(_ptr, _val) \
2729 (*((u16 *)(_ptr))) = EF2BYTE(_val)
2730 #define WRITEEF4BYTE(_ptr, _val) \
2731 (*((u32 *)(_ptr))) = EF2BYTE(_val)
2732
2733 /* Create a bit mask
2734 * Examples:
2735 * BIT_LEN_MASK_32(0) => 0x00000000
2736 * BIT_LEN_MASK_32(1) => 0x00000001
2737 * BIT_LEN_MASK_32(2) => 0x00000003
2738 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
2739 */
2740 #define BIT_LEN_MASK_32(__bitlen) \
2741 (0xFFFFFFFF >> (32 - (__bitlen)))
2742 #define BIT_LEN_MASK_16(__bitlen) \
2743 (0xFFFF >> (16 - (__bitlen)))
2744 #define BIT_LEN_MASK_8(__bitlen) \
2745 (0xFF >> (8 - (__bitlen)))
2746
2747 /* Create an offset bit mask
2748 * Examples:
2749 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
2750 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
2751 */
2752 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
2753 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
2754 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
2755 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
2756 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
2757 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
2758
2759 /*Description:
2760 * Return 4-byte value in host byte ordering from
2761 * 4-byte pointer in little-endian system.
2762 */
2763 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
2764 (EF4BYTE(*((__le32 *)(__pstart))))
2765 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
2766 (EF2BYTE(*((__le16 *)(__pstart))))
2767 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
2768 (EF1BYTE(*((u8 *)(__pstart))))
2769
2770 /*Description:
2771 Translate subfield (continuous bits in little-endian) of 4-byte
2772 value to host byte ordering.*/
2773 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2774 ( \
2775 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
2776 BIT_LEN_MASK_32(__bitlen) \
2777 )
2778 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2779 ( \
2780 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
2781 BIT_LEN_MASK_16(__bitlen) \
2782 )
2783 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2784 ( \
2785 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
2786 BIT_LEN_MASK_8(__bitlen) \
2787 )
2788
2789 /* Description:
2790 * Mask subfield (continuous bits in little-endian) of 4-byte value
2791 * and return the result in 4-byte value in host byte ordering.
2792 */
2793 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2794 ( \
2795 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
2796 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
2797 )
2798 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2799 ( \
2800 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
2801 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
2802 )
2803 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2804 ( \
2805 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
2806 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
2807 )
2808
2809 /* Description:
2810 * Set subfield of little-endian 4-byte value to specified value.
2811 */
2812 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
2813 *((u32 *)(__pstart)) = \
2814 ( \
2815 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
2816 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
2817 );
2818 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
2819 *((u16 *)(__pstart)) = \
2820 ( \
2821 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
2822 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
2823 );
2824 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
2825 *((u8 *)(__pstart)) = EF1BYTE \
2826 ( \
2827 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
2828 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
2829 );
2830
2831 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2832 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2833
2834 /****************************************
2835 mem access macro define end
2836 ****************************************/
2837
2838 #define byte(x, n) ((x >> (8 * n)) & 0xff)
2839
2840 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2841 #define RTL_WATCH_DOG_TIME 2000
2842 #define MSECS(t) msecs_to_jiffies(t)
2843 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
2844 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
2845 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
2846 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
2847 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
2848
2849 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
2850 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
2851 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
2852 /*NIC halt, re-initialize hw parameters*/
2853 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
2854 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
2855 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
2856 /*Always enable ASPM and Clock Req in initialization.*/
2857 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
2858 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2859 #define RT_PS_LEVEL_ASPM BIT(7)
2860 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
2861 #define RT_RF_LPS_DISALBE_2R BIT(30)
2862 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
2863 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
2864 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2865 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
2866 (ppsc->cur_ps_level &= (~(_ps_flg)))
2867 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
2868 (ppsc->cur_ps_level |= _ps_flg)
2869
2870 #define container_of_dwork_rtl(x, y, z) \
2871 container_of(to_delayed_work(x), y, z)
2872
2873 #define FILL_OCTET_STRING(_os, _octet, _len) \
2874 (_os).octet = (u8 *)(_octet); \
2875 (_os).length = (_len);
2876
2877 #define CP_MACADDR(des, src) \
2878 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
2879 (des)[2] = (src)[2], (des)[3] = (src)[3],\
2880 (des)[4] = (src)[4], (des)[5] = (src)[5])
2881
2882 #define LDPC_HT_ENABLE_RX BIT(0)
2883 #define LDPC_HT_ENABLE_TX BIT(1)
2884 #define LDPC_HT_TEST_TX_ENABLE BIT(2)
2885 #define LDPC_HT_CAP_TX BIT(3)
2886
2887 #define STBC_HT_ENABLE_RX BIT(0)
2888 #define STBC_HT_ENABLE_TX BIT(1)
2889 #define STBC_HT_TEST_TX_ENABLE BIT(2)
2890 #define STBC_HT_CAP_TX BIT(3)
2891
2892 #define LDPC_VHT_ENABLE_RX BIT(0)
2893 #define LDPC_VHT_ENABLE_TX BIT(1)
2894 #define LDPC_VHT_TEST_TX_ENABLE BIT(2)
2895 #define LDPC_VHT_CAP_TX BIT(3)
2896
2897 #define STBC_VHT_ENABLE_RX BIT(0)
2898 #define STBC_VHT_ENABLE_TX BIT(1)
2899 #define STBC_VHT_TEST_TX_ENABLE BIT(2)
2900 #define STBC_VHT_CAP_TX BIT(3)
2901
2902 extern u8 channel5g[CHANNEL_MAX_NUMBER_5G];
2903
2904 extern u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M];
2905
2906 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2907 {
2908 return rtlpriv->io.read8_sync(rtlpriv, addr);
2909 }
2910
2911 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2912 {
2913 return rtlpriv->io.read16_sync(rtlpriv, addr);
2914 }
2915
2916 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2917 {
2918 return rtlpriv->io.read32_sync(rtlpriv, addr);
2919 }
2920
2921 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2922 {
2923 rtlpriv->io.write8_async(rtlpriv, addr, val8);
2924
2925 if (rtlpriv->cfg->write_readback)
2926 rtlpriv->io.read8_sync(rtlpriv, addr);
2927 }
2928
2929 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2930 {
2931 rtlpriv->io.write16_async(rtlpriv, addr, val16);
2932
2933 if (rtlpriv->cfg->write_readback)
2934 rtlpriv->io.read16_sync(rtlpriv, addr);
2935 }
2936
2937 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2938 u32 addr, u32 val32)
2939 {
2940 rtlpriv->io.write32_async(rtlpriv, addr, val32);
2941
2942 if (rtlpriv->cfg->write_readback)
2943 rtlpriv->io.read32_sync(rtlpriv, addr);
2944 }
2945
2946 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
2947 u32 regaddr, u32 bitmask)
2948 {
2949 struct rtl_priv *rtlpriv = hw->priv;
2950
2951 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
2952 }
2953
2954 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
2955 u32 bitmask, u32 data)
2956 {
2957 struct rtl_priv *rtlpriv = hw->priv;
2958
2959 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
2960 }
2961
2962 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
2963 enum radio_path rfpath, u32 regaddr,
2964 u32 bitmask)
2965 {
2966 struct rtl_priv *rtlpriv = hw->priv;
2967
2968 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
2969 }
2970
2971 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
2972 enum radio_path rfpath, u32 regaddr,
2973 u32 bitmask, u32 data)
2974 {
2975 struct rtl_priv *rtlpriv = hw->priv;
2976
2977 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
2978 }
2979
2980 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
2981 {
2982 return (_HAL_STATE_STOP == rtlhal->state);
2983 }
2984
2985 static inline void set_hal_start(struct rtl_hal *rtlhal)
2986 {
2987 rtlhal->state = _HAL_STATE_START;
2988 }
2989
2990 static inline void set_hal_stop(struct rtl_hal *rtlhal)
2991 {
2992 rtlhal->state = _HAL_STATE_STOP;
2993 }
2994
2995 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
2996 {
2997 return rtlphy->rf_type;
2998 }
2999
3000 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
3001 {
3002 return (struct ieee80211_hdr *)(skb->data);
3003 }
3004
3005 static inline __le16 rtl_get_fc(struct sk_buff *skb)
3006 {
3007 return rtl_get_hdr(skb)->frame_control;
3008 }
3009
3010 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
3011 {
3012 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
3013 }
3014
3015 static inline u16 rtl_get_tid(struct sk_buff *skb)
3016 {
3017 return rtl_get_tid_h(rtl_get_hdr(skb));
3018 }
3019
3020 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
3021 struct ieee80211_vif *vif,
3022 const u8 *bssid)
3023 {
3024 return ieee80211_find_sta(vif, bssid);
3025 }
3026
3027 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
3028 u8 *mac_addr)
3029 {
3030 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3031 return ieee80211_find_sta(mac->vif, mac_addr);
3032 }
3033
3034 #endif
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