1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
18 union phy_table_tile
{
19 struct rtw_phy_cond cond
;
20 struct phy_cfg_pair cfg
;
23 static const u32 db_invert_table
[12][8] = {
29 1007, 1268, 1596, 2010},
31 794, 1000, 1259, 1585},
32 {1995, 2512, 3162, 3981,
33 5012, 6310, 7943, 10000},
34 {12589, 15849, 19953, 25119,
35 31623, 39811, 50119, 63098},
36 {79433, 100000, 125893, 158489,
37 199526, 251189, 316228, 398107},
38 {501187, 630957, 794328, 1000000,
39 1258925, 1584893, 1995262, 2511886},
40 {3162278, 3981072, 5011872, 6309573,
41 7943282, 1000000, 12589254, 15848932},
42 {19952623, 25118864, 31622777, 39810717,
43 50118723, 63095734, 79432823, 100000000},
44 {125892541, 158489319, 199526232, 251188643,
45 316227766, 398107171, 501187234, 630957345},
46 {794328235, 1000000000, 1258925412, 1584893192,
47 1995262315, 2511886432U, 3162277660U, 3981071706U}
50 u8 rtw_cck_rates
[] = { DESC_RATE1M
, DESC_RATE2M
, DESC_RATE5_5M
, DESC_RATE11M
};
51 u8 rtw_ofdm_rates
[] = {
52 DESC_RATE6M
, DESC_RATE9M
, DESC_RATE12M
,
53 DESC_RATE18M
, DESC_RATE24M
, DESC_RATE36M
,
54 DESC_RATE48M
, DESC_RATE54M
56 u8 rtw_ht_1s_rates
[] = {
57 DESC_RATEMCS0
, DESC_RATEMCS1
, DESC_RATEMCS2
,
58 DESC_RATEMCS3
, DESC_RATEMCS4
, DESC_RATEMCS5
,
59 DESC_RATEMCS6
, DESC_RATEMCS7
61 u8 rtw_ht_2s_rates
[] = {
62 DESC_RATEMCS8
, DESC_RATEMCS9
, DESC_RATEMCS10
,
63 DESC_RATEMCS11
, DESC_RATEMCS12
, DESC_RATEMCS13
,
64 DESC_RATEMCS14
, DESC_RATEMCS15
66 u8 rtw_vht_1s_rates
[] = {
67 DESC_RATEVHT1SS_MCS0
, DESC_RATEVHT1SS_MCS1
,
68 DESC_RATEVHT1SS_MCS2
, DESC_RATEVHT1SS_MCS3
,
69 DESC_RATEVHT1SS_MCS4
, DESC_RATEVHT1SS_MCS5
,
70 DESC_RATEVHT1SS_MCS6
, DESC_RATEVHT1SS_MCS7
,
71 DESC_RATEVHT1SS_MCS8
, DESC_RATEVHT1SS_MCS9
73 u8 rtw_vht_2s_rates
[] = {
74 DESC_RATEVHT2SS_MCS0
, DESC_RATEVHT2SS_MCS1
,
75 DESC_RATEVHT2SS_MCS2
, DESC_RATEVHT2SS_MCS3
,
76 DESC_RATEVHT2SS_MCS4
, DESC_RATEVHT2SS_MCS5
,
77 DESC_RATEVHT2SS_MCS6
, DESC_RATEVHT2SS_MCS7
,
78 DESC_RATEVHT2SS_MCS8
, DESC_RATEVHT2SS_MCS9
80 u8
*rtw_rate_section
[RTW_RATE_SECTION_MAX
] = {
81 rtw_cck_rates
, rtw_ofdm_rates
,
82 rtw_ht_1s_rates
, rtw_ht_2s_rates
,
83 rtw_vht_1s_rates
, rtw_vht_2s_rates
85 u8 rtw_rate_size
[RTW_RATE_SECTION_MAX
] = {
86 ARRAY_SIZE(rtw_cck_rates
),
87 ARRAY_SIZE(rtw_ofdm_rates
),
88 ARRAY_SIZE(rtw_ht_1s_rates
),
89 ARRAY_SIZE(rtw_ht_2s_rates
),
90 ARRAY_SIZE(rtw_vht_1s_rates
),
91 ARRAY_SIZE(rtw_vht_2s_rates
)
93 static const u8 rtw_cck_size
= ARRAY_SIZE(rtw_cck_rates
);
94 static const u8 rtw_ofdm_size
= ARRAY_SIZE(rtw_ofdm_rates
);
95 static const u8 rtw_ht_1s_size
= ARRAY_SIZE(rtw_ht_1s_rates
);
96 static const u8 rtw_ht_2s_size
= ARRAY_SIZE(rtw_ht_2s_rates
);
97 static const u8 rtw_vht_1s_size
= ARRAY_SIZE(rtw_vht_1s_rates
);
98 static const u8 rtw_vht_2s_size
= ARRAY_SIZE(rtw_vht_2s_rates
);
100 enum rtw_phy_band_type
{
105 static void rtw_phy_cck_pd_init(struct rtw_dev
*rtwdev
)
107 struct rtw_dm_info
*dm_info
= &rtwdev
->dm_info
;
110 for (i
= 0; i
<= RTW_CHANNEL_WIDTH_40
; i
++) {
111 for (j
= 0; j
< RTW_RF_PATH_MAX
; j
++)
112 dm_info
->cck_pd_lv
[i
][j
] = CCK_PD_LV0
;
115 dm_info
->cck_fa_avg
= CCK_FA_AVG_RESET
;
118 void rtw_phy_init(struct rtw_dev
*rtwdev
)
120 struct rtw_chip_info
*chip
= rtwdev
->chip
;
121 struct rtw_dm_info
*dm_info
= &rtwdev
->dm_info
;
124 dm_info
->fa_history
[3] = 0;
125 dm_info
->fa_history
[2] = 0;
126 dm_info
->fa_history
[1] = 0;
127 dm_info
->fa_history
[0] = 0;
128 dm_info
->igi_bitmap
= 0;
129 dm_info
->igi_history
[3] = 0;
130 dm_info
->igi_history
[2] = 0;
131 dm_info
->igi_history
[1] = 0;
133 addr
= chip
->dig
[0].addr
;
134 mask
= chip
->dig
[0].mask
;
135 dm_info
->igi_history
[0] = rtw_read32_mask(rtwdev
, addr
, mask
);
136 rtw_phy_cck_pd_init(rtwdev
);
139 void rtw_phy_dig_write(struct rtw_dev
*rtwdev
, u8 igi
)
141 struct rtw_chip_info
*chip
= rtwdev
->chip
;
142 struct rtw_hal
*hal
= &rtwdev
->hal
;
146 for (path
= 0; path
< hal
->rf_path_num
; path
++) {
147 addr
= chip
->dig
[path
].addr
;
148 mask
= chip
->dig
[path
].mask
;
149 rtw_write32_mask(rtwdev
, addr
, mask
, igi
);
153 static void rtw_phy_stat_false_alarm(struct rtw_dev
*rtwdev
)
155 struct rtw_chip_info
*chip
= rtwdev
->chip
;
157 chip
->ops
->false_alarm_statistics(rtwdev
);
160 #define RA_FLOOR_TABLE_SIZE 7
161 #define RA_FLOOR_UP_GAP 3
163 static u8
rtw_phy_get_rssi_level(u8 old_level
, u8 rssi
)
165 u8 table
[RA_FLOOR_TABLE_SIZE
] = {20, 34, 38, 42, 46, 50, 100};
169 for (i
= 0; i
< RA_FLOOR_TABLE_SIZE
; i
++)
171 table
[i
] += RA_FLOOR_UP_GAP
;
173 for (i
= 0; i
< RA_FLOOR_TABLE_SIZE
; i
++) {
174 if (rssi
< table
[i
]) {
183 struct rtw_phy_stat_iter_data
{
184 struct rtw_dev
*rtwdev
;
188 static void rtw_phy_stat_rssi_iter(void *data
, struct ieee80211_sta
*sta
)
190 struct rtw_phy_stat_iter_data
*iter_data
= data
;
191 struct rtw_dev
*rtwdev
= iter_data
->rtwdev
;
192 struct rtw_sta_info
*si
= (struct rtw_sta_info
*)sta
->drv_priv
;
195 rssi
= ewma_rssi_read(&si
->avg_rssi
);
196 si
->rssi_level
= rtw_phy_get_rssi_level(si
->rssi_level
, rssi
);
198 rtw_fw_send_rssi_info(rtwdev
, si
);
200 iter_data
->min_rssi
= min_t(u8
, rssi
, iter_data
->min_rssi
);
203 static void rtw_phy_stat_rssi(struct rtw_dev
*rtwdev
)
205 struct rtw_dm_info
*dm_info
= &rtwdev
->dm_info
;
206 struct rtw_phy_stat_iter_data data
= {};
208 data
.rtwdev
= rtwdev
;
209 data
.min_rssi
= U8_MAX
;
210 rtw_iterate_stas_atomic(rtwdev
, rtw_phy_stat_rssi_iter
, &data
);
212 dm_info
->pre_min_rssi
= dm_info
->min_rssi
;
213 dm_info
->min_rssi
= data
.min_rssi
;
216 static void rtw_phy_stat_rate_cnt(struct rtw_dev
*rtwdev
)
218 struct rtw_dm_info
*dm_info
= &rtwdev
->dm_info
;
220 dm_info
->last_pkt_count
= dm_info
->cur_pkt_count
;
221 memset(&dm_info
->cur_pkt_count
, 0, sizeof(dm_info
->cur_pkt_count
));
224 static void rtw_phy_statistics(struct rtw_dev
*rtwdev
)
226 rtw_phy_stat_rssi(rtwdev
);
227 rtw_phy_stat_false_alarm(rtwdev
);
228 rtw_phy_stat_rate_cnt(rtwdev
);
231 #define DIG_PERF_FA_TH_LOW 250
232 #define DIG_PERF_FA_TH_HIGH 500
233 #define DIG_PERF_FA_TH_EXTRA_HIGH 750
234 #define DIG_PERF_MAX 0x5a
235 #define DIG_PERF_MID 0x40
236 #define DIG_CVRG_FA_TH_LOW 2000
237 #define DIG_CVRG_FA_TH_HIGH 4000
238 #define DIG_CVRG_FA_TH_EXTRA_HIGH 5000
239 #define DIG_CVRG_MAX 0x2a
240 #define DIG_CVRG_MID 0x26
241 #define DIG_CVRG_MIN 0x1c
242 #define DIG_RSSI_GAIN_OFFSET 15
245 rtw_phy_dig_check_damping(struct rtw_dm_info
*dm_info
)
247 u16 fa_lo
= DIG_PERF_FA_TH_LOW
;
248 u16 fa_hi
= DIG_PERF_FA_TH_HIGH
;
255 bool damping
= false;
257 min_rssi
= dm_info
->min_rssi
;
258 if (dm_info
->damping
) {
259 damping_rssi
= dm_info
->damping_rssi
;
260 diff
= min_rssi
> damping_rssi
? min_rssi
- damping_rssi
:
261 damping_rssi
- min_rssi
;
262 if (diff
> 3 || dm_info
->damping_cnt
++ > 20) {
263 dm_info
->damping
= false;
270 igi_history
= dm_info
->igi_history
;
271 fa_history
= dm_info
->fa_history
;
272 igi_bitmap
= dm_info
->igi_bitmap
& 0xf;
273 switch (igi_bitmap
) {
275 /* down -> up -> down -> up */
276 if (igi_history
[0] > igi_history
[1] &&
277 igi_history
[2] > igi_history
[3] &&
278 igi_history
[0] - igi_history
[1] >= 2 &&
279 igi_history
[2] - igi_history
[3] >= 2 &&
280 fa_history
[0] > fa_hi
&& fa_history
[1] < fa_lo
&&
281 fa_history
[2] > fa_hi
&& fa_history
[3] < fa_lo
)
285 /* up -> down -> down -> up */
286 if (igi_history
[0] > igi_history
[1] &&
287 igi_history
[3] > igi_history
[2] &&
288 igi_history
[0] - igi_history
[1] >= 4 &&
289 igi_history
[3] - igi_history
[2] >= 2 &&
290 fa_history
[0] > fa_hi
&& fa_history
[1] < fa_lo
&&
291 fa_history
[2] < fa_lo
&& fa_history
[3] > fa_hi
)
299 dm_info
->damping
= true;
300 dm_info
->damping_cnt
= 0;
301 dm_info
->damping_rssi
= min_rssi
;
307 static void rtw_phy_dig_get_boundary(struct rtw_dm_info
*dm_info
,
308 u8
*upper
, u8
*lower
, bool linked
)
310 u8 dig_max
, dig_min
, dig_mid
;
314 dig_max
= DIG_PERF_MAX
;
315 dig_mid
= DIG_PERF_MID
;
316 /* 22B=0x1c, 22C=0x20 */
318 min_rssi
= max_t(u8
, dm_info
->min_rssi
, dig_min
);
320 dig_max
= DIG_CVRG_MAX
;
321 dig_mid
= DIG_CVRG_MID
;
322 dig_min
= DIG_CVRG_MIN
;
326 /* DIG MAX should be bounded by minimum RSSI with offset +15 */
327 dig_max
= min_t(u8
, dig_max
, min_rssi
+ DIG_RSSI_GAIN_OFFSET
);
329 *lower
= clamp_t(u8
, min_rssi
, dig_min
, dig_mid
);
330 *upper
= clamp_t(u8
, *lower
+ DIG_RSSI_GAIN_OFFSET
, dig_min
, dig_max
);
333 static void rtw_phy_dig_get_threshold(struct rtw_dm_info
*dm_info
,
334 u16
*fa_th
, u8
*step
, bool linked
)
336 u8 min_rssi
, pre_min_rssi
;
338 min_rssi
= dm_info
->min_rssi
;
339 pre_min_rssi
= dm_info
->pre_min_rssi
;
345 fa_th
[0] = DIG_PERF_FA_TH_EXTRA_HIGH
;
346 fa_th
[1] = DIG_PERF_FA_TH_HIGH
;
347 fa_th
[2] = DIG_PERF_FA_TH_LOW
;
348 if (pre_min_rssi
> min_rssi
) {
354 fa_th
[0] = DIG_CVRG_FA_TH_EXTRA_HIGH
;
355 fa_th
[1] = DIG_CVRG_FA_TH_HIGH
;
356 fa_th
[2] = DIG_CVRG_FA_TH_LOW
;
360 static void rtw_phy_dig_recorder(struct rtw_dm_info
*dm_info
, u8 igi
, u16 fa
)
367 igi_bitmap
= dm_info
->igi_bitmap
<< 1 & 0xfe;
368 igi_history
= dm_info
->igi_history
;
369 fa_history
= dm_info
->fa_history
;
371 up
= igi
> igi_history
[0];
374 igi_history
[3] = igi_history
[2];
375 igi_history
[2] = igi_history
[1];
376 igi_history
[1] = igi_history
[0];
377 igi_history
[0] = igi
;
379 fa_history
[3] = fa_history
[2];
380 fa_history
[2] = fa_history
[1];
381 fa_history
[1] = fa_history
[0];
384 dm_info
->igi_bitmap
= igi_bitmap
;
387 static void rtw_phy_dig(struct rtw_dev
*rtwdev
)
389 struct rtw_dm_info
*dm_info
= &rtwdev
->dm_info
;
390 u8 upper_bound
, lower_bound
;
392 u16 fa_th
[3], fa_cnt
;
397 if (test_bit(RTW_FLAG_DIG_DISABLE
, rtwdev
->flags
))
400 if (rtw_phy_dig_check_damping(dm_info
))
403 linked
= !!rtwdev
->sta_cnt
;
405 fa_cnt
= dm_info
->total_fa_cnt
;
406 pre_igi
= dm_info
->igi_history
[0];
408 rtw_phy_dig_get_threshold(dm_info
, fa_th
, step
, linked
);
410 /* test the false alarm count from the highest threshold level first,
411 * and increase it by corresponding step size
413 * note that the step size is offset by -2, compensate it afterall
416 for (level
= 0; level
< 3; level
++) {
417 if (fa_cnt
> fa_th
[level
]) {
418 cur_igi
+= step
[level
];
424 /* calculate the upper/lower bound by the minimum rssi we have among
425 * the peers connected with us, meanwhile make sure the igi value does
426 * not beyond the hardware limitation
428 rtw_phy_dig_get_boundary(dm_info
, &upper_bound
, &lower_bound
, linked
);
429 cur_igi
= clamp_t(u8
, cur_igi
, lower_bound
, upper_bound
);
431 /* record current igi value and false alarm statistics for further
432 * damping checks, and record the trend of igi values
434 rtw_phy_dig_recorder(dm_info
, cur_igi
, fa_cnt
);
436 if (cur_igi
!= pre_igi
)
437 rtw_phy_dig_write(rtwdev
, cur_igi
);
440 static void rtw_phy_ra_info_update_iter(void *data
, struct ieee80211_sta
*sta
)
442 struct rtw_dev
*rtwdev
= data
;
443 struct rtw_sta_info
*si
= (struct rtw_sta_info
*)sta
->drv_priv
;
445 rtw_update_sta_info(rtwdev
, si
);
448 static void rtw_phy_ra_info_update(struct rtw_dev
*rtwdev
)
450 if (rtwdev
->watch_dog_cnt
& 0x3)
453 rtw_iterate_stas_atomic(rtwdev
, rtw_phy_ra_info_update_iter
, rtwdev
);
456 static void rtw_phy_dpk_track(struct rtw_dev
*rtwdev
)
458 struct rtw_chip_info
*chip
= rtwdev
->chip
;
460 if (chip
->ops
->dpk_track
)
461 chip
->ops
->dpk_track(rtwdev
);
464 #define CCK_PD_FA_LV1_MIN 1000
465 #define CCK_PD_FA_LV0_MAX 500
467 static u8
rtw_phy_cck_pd_lv_unlink(struct rtw_dev
*rtwdev
)
469 struct rtw_dm_info
*dm_info
= &rtwdev
->dm_info
;
470 u32 cck_fa_avg
= dm_info
->cck_fa_avg
;
472 if (cck_fa_avg
> CCK_PD_FA_LV1_MIN
)
475 if (cck_fa_avg
< CCK_PD_FA_LV0_MAX
)
478 return CCK_PD_LV_MAX
;
481 #define CCK_PD_IGI_LV4_VAL 0x38
482 #define CCK_PD_IGI_LV3_VAL 0x2a
483 #define CCK_PD_IGI_LV2_VAL 0x24
484 #define CCK_PD_RSSI_LV4_VAL 32
485 #define CCK_PD_RSSI_LV3_VAL 32
486 #define CCK_PD_RSSI_LV2_VAL 24
488 static u8
rtw_phy_cck_pd_lv_link(struct rtw_dev
*rtwdev
)
490 struct rtw_dm_info
*dm_info
= &rtwdev
->dm_info
;
491 u8 igi
= dm_info
->igi_history
[0];
492 u8 rssi
= dm_info
->min_rssi
;
493 u32 cck_fa_avg
= dm_info
->cck_fa_avg
;
495 if (igi
> CCK_PD_IGI_LV4_VAL
&& rssi
> CCK_PD_RSSI_LV4_VAL
)
497 if (igi
> CCK_PD_IGI_LV3_VAL
&& rssi
> CCK_PD_RSSI_LV3_VAL
)
499 if (igi
> CCK_PD_IGI_LV2_VAL
|| rssi
> CCK_PD_RSSI_LV2_VAL
)
501 if (cck_fa_avg
> CCK_PD_FA_LV1_MIN
)
503 if (cck_fa_avg
< CCK_PD_FA_LV0_MAX
)
506 return CCK_PD_LV_MAX
;
509 static u8
rtw_phy_cck_pd_lv(struct rtw_dev
*rtwdev
)
511 if (!rtw_is_assoc(rtwdev
))
512 return rtw_phy_cck_pd_lv_unlink(rtwdev
);
514 return rtw_phy_cck_pd_lv_link(rtwdev
);
517 static void rtw_phy_cck_pd(struct rtw_dev
*rtwdev
)
519 struct rtw_dm_info
*dm_info
= &rtwdev
->dm_info
;
520 struct rtw_chip_info
*chip
= rtwdev
->chip
;
521 u32 cck_fa
= dm_info
->cck_fa_cnt
;
524 if (rtwdev
->hal
.current_band_type
!= RTW_BAND_2G
)
527 if (dm_info
->cck_fa_avg
== CCK_FA_AVG_RESET
)
528 dm_info
->cck_fa_avg
= cck_fa
;
530 dm_info
->cck_fa_avg
= (dm_info
->cck_fa_avg
* 3 + cck_fa
) >> 2;
532 level
= rtw_phy_cck_pd_lv(rtwdev
);
534 if (level
>= CCK_PD_LV_MAX
)
537 if (chip
->ops
->cck_pd_set
)
538 chip
->ops
->cck_pd_set(rtwdev
, level
);
541 static void rtw_phy_pwr_track(struct rtw_dev
*rtwdev
)
543 rtwdev
->chip
->ops
->pwr_track(rtwdev
);
546 void rtw_phy_dynamic_mechanism(struct rtw_dev
*rtwdev
)
548 /* for further calculation */
549 rtw_phy_statistics(rtwdev
);
551 rtw_phy_cck_pd(rtwdev
);
552 rtw_phy_ra_info_update(rtwdev
);
553 rtw_phy_dpk_track(rtwdev
);
554 rtw_phy_pwr_track(rtwdev
);
559 static u8
rtw_phy_power_2_db(s8 power
)
561 if (power
<= -100 || power
>= 20)
569 static u64
rtw_phy_db_2_linear(u8 power_db
)
576 else if (power_db
< 1)
580 i
= (power_db
- 1) >> 3;
581 j
= (power_db
- 1) - (i
<< 3);
583 linear
= db_invert_table
[i
][j
];
584 linear
= i
> 2 ? linear
<< FRAC_BITS
: linear
;
589 static u8
rtw_phy_linear_2_db(u64 linear
)
595 if (linear
>= db_invert_table
[11][7])
596 return 96; /* maximum 96 dB */
598 for (i
= 0; i
< 12; i
++) {
599 if (i
<= 2 && (linear
<< FRAC_BITS
) <= db_invert_table
[i
][7])
601 else if (i
> 2 && linear
<= db_invert_table
[i
][7])
605 for (j
= 0; j
< 8; j
++) {
606 if (i
<= 2 && (linear
<< FRAC_BITS
) <= db_invert_table
[i
][j
])
608 else if (i
> 2 && linear
<= db_invert_table
[i
][j
])
612 if (j
== 0 && i
== 0)
617 if (db_invert_table
[i
][0] - linear
>
618 linear
- db_invert_table
[i
- 1][7]) {
623 if (db_invert_table
[3][0] - linear
>
624 linear
- db_invert_table
[2][7]) {
630 if (db_invert_table
[i
][j
] - linear
>
631 linear
- db_invert_table
[i
][j
- 1]) {
636 dB
= (i
<< 3) + j
+ 1;
641 u8
rtw_phy_rf_power_2_rssi(s8
*rf_power
, u8 path_num
)
649 for (path
= 0; path
< path_num
; path
++) {
650 power
= rf_power
[path
];
651 power_db
= rtw_phy_power_2_db(power
);
652 linear
= rtw_phy_db_2_linear(power_db
);
656 sum
= (sum
+ (1 << (FRAC_BITS
- 1))) >> FRAC_BITS
;
662 sum
= ((sum
) + ((sum
) << 1) + ((sum
) << 3)) >> 5;
671 return rtw_phy_linear_2_db(sum
);
674 u32
rtw_phy_read_rf(struct rtw_dev
*rtwdev
, enum rtw_rf_path rf_path
,
677 struct rtw_hal
*hal
= &rtwdev
->hal
;
678 struct rtw_chip_info
*chip
= rtwdev
->chip
;
679 const u32
*base_addr
= chip
->rf_base_addr
;
680 u32 val
, direct_addr
;
682 if (rf_path
>= hal
->rf_path_num
) {
683 rtw_err(rtwdev
, "unsupported rf path (%d)\n", rf_path
);
688 direct_addr
= base_addr
[rf_path
] + (addr
<< 2);
691 val
= rtw_read32_mask(rtwdev
, direct_addr
, mask
);
696 bool rtw_phy_write_rf_reg_sipi(struct rtw_dev
*rtwdev
, enum rtw_rf_path rf_path
,
697 u32 addr
, u32 mask
, u32 data
)
699 struct rtw_hal
*hal
= &rtwdev
->hal
;
700 struct rtw_chip_info
*chip
= rtwdev
->chip
;
701 u32
*sipi_addr
= chip
->rf_sipi_addr
;
706 if (rf_path
>= hal
->rf_path_num
) {
707 rtw_err(rtwdev
, "unsupported rf path (%d)\n", rf_path
);
714 if (mask
!= RFREG_MASK
) {
715 old_data
= rtw_phy_read_rf(rtwdev
, rf_path
, addr
, RFREG_MASK
);
717 if (old_data
== INV_RF_DATA
) {
718 rtw_err(rtwdev
, "Write fail, rf is disabled\n");
723 data
= ((old_data
) & (~mask
)) | (data
<< shift
);
726 data_and_addr
= ((addr
<< 20) | (data
& 0x000fffff)) & 0x0fffffff;
728 rtw_write32(rtwdev
, sipi_addr
[rf_path
], data_and_addr
);
735 bool rtw_phy_write_rf_reg(struct rtw_dev
*rtwdev
, enum rtw_rf_path rf_path
,
736 u32 addr
, u32 mask
, u32 data
)
738 struct rtw_hal
*hal
= &rtwdev
->hal
;
739 struct rtw_chip_info
*chip
= rtwdev
->chip
;
740 const u32
*base_addr
= chip
->rf_base_addr
;
743 if (rf_path
>= hal
->rf_path_num
) {
744 rtw_err(rtwdev
, "unsupported rf path (%d)\n", rf_path
);
749 direct_addr
= base_addr
[rf_path
] + (addr
<< 2);
752 if (addr
== RF_CFGCH
) {
753 rtw_write32_mask(rtwdev
, REG_RSV_CTRL
, BITS_RFC_DIRECT
, DISABLE_PI
);
754 rtw_write32_mask(rtwdev
, REG_WLRF1
, BITS_RFC_DIRECT
, DISABLE_PI
);
757 rtw_write32_mask(rtwdev
, direct_addr
, mask
, data
);
761 if (addr
== RF_CFGCH
) {
762 rtw_write32_mask(rtwdev
, REG_RSV_CTRL
, BITS_RFC_DIRECT
, ENABLE_PI
);
763 rtw_write32_mask(rtwdev
, REG_WLRF1
, BITS_RFC_DIRECT
, ENABLE_PI
);
769 bool rtw_phy_write_rf_reg_mix(struct rtw_dev
*rtwdev
, enum rtw_rf_path rf_path
,
770 u32 addr
, u32 mask
, u32 data
)
773 return rtw_phy_write_rf_reg(rtwdev
, rf_path
, addr
, mask
, data
);
775 return rtw_phy_write_rf_reg_sipi(rtwdev
, rf_path
, addr
, mask
, data
);
778 void rtw_phy_setup_phy_cond(struct rtw_dev
*rtwdev
, u32 pkg
)
780 struct rtw_hal
*hal
= &rtwdev
->hal
;
781 struct rtw_efuse
*efuse
= &rtwdev
->efuse
;
782 struct rtw_phy_cond cond
= {0};
784 cond
.cut
= hal
->cut_version
? hal
->cut_version
: 15;
785 cond
.pkg
= pkg
? pkg
: 15;
787 cond
.rfe
= efuse
->rfe_option
;
789 switch (rtw_hci_type(rtwdev
)) {
790 case RTW_HCI_TYPE_USB
:
791 cond
.intf
= INTF_USB
;
793 case RTW_HCI_TYPE_SDIO
:
794 cond
.intf
= INTF_SDIO
;
796 case RTW_HCI_TYPE_PCIE
:
798 cond
.intf
= INTF_PCIE
;
802 hal
->phy_cond
= cond
;
804 rtw_dbg(rtwdev
, RTW_DBG_PHY
, "phy cond=0x%08x\n", *((u32
*)&hal
->phy_cond
));
807 static bool check_positive(struct rtw_dev
*rtwdev
, struct rtw_phy_cond cond
)
809 struct rtw_hal
*hal
= &rtwdev
->hal
;
810 struct rtw_phy_cond drv_cond
= hal
->phy_cond
;
812 if (cond
.cut
&& cond
.cut
!= drv_cond
.cut
)
815 if (cond
.pkg
&& cond
.pkg
!= drv_cond
.pkg
)
818 if (cond
.intf
&& cond
.intf
!= drv_cond
.intf
)
821 if (cond
.rfe
!= drv_cond
.rfe
)
827 void rtw_parse_tbl_phy_cond(struct rtw_dev
*rtwdev
, const struct rtw_table
*tbl
)
829 const union phy_table_tile
*p
= tbl
->data
;
830 const union phy_table_tile
*end
= p
+ tbl
->size
/ 2;
831 struct rtw_phy_cond pos_cond
= {0};
832 bool is_matched
= true, is_skipped
= false;
834 BUILD_BUG_ON(sizeof(union phy_table_tile
) != sizeof(struct phy_cfg_pair
));
836 for (; p
< end
; p
++) {
838 switch (p
->cond
.branch
) {
844 is_matched
= is_skipped
? false : true;
852 } else if (p
->cond
.neg
) {
854 if (check_positive(rtwdev
, pos_cond
)) {
864 } else if (is_matched
) {
865 (*tbl
->do_cfg
)(rtwdev
, tbl
, p
->cfg
.addr
, p
->cfg
.data
);
870 #define bcd_to_dec_pwr_by_rate(val, i) bcd2bin(val >> (i * 8))
872 static u8
tbl_to_dec_pwr_by_rate(struct rtw_dev
*rtwdev
, u32 hex
, u8 i
)
874 if (rtwdev
->chip
->is_pwr_by_rate_dec
)
875 return bcd_to_dec_pwr_by_rate(hex
, i
);
877 return (hex
>> (i
* 8)) & 0xFF;
881 rtw_phy_get_rate_values_of_txpwr_by_rate(struct rtw_dev
*rtwdev
,
882 u32 addr
, u32 mask
, u32 val
, u8
*rate
,
883 u8
*pwr_by_rate
, u8
*rate_num
)
890 rate
[0] = DESC_RATE6M
;
891 rate
[1] = DESC_RATE9M
;
892 rate
[2] = DESC_RATE12M
;
893 rate
[3] = DESC_RATE18M
;
894 for (i
= 0; i
< 4; ++i
)
895 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
900 rate
[0] = DESC_RATE24M
;
901 rate
[1] = DESC_RATE36M
;
902 rate
[2] = DESC_RATE48M
;
903 rate
[3] = DESC_RATE54M
;
904 for (i
= 0; i
< 4; ++i
)
905 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
909 rate
[0] = DESC_RATE1M
;
910 pwr_by_rate
[0] = bcd_to_dec_pwr_by_rate(val
, 1);
914 if (mask
== 0xffffff00) {
915 rate
[0] = DESC_RATE2M
;
916 rate
[1] = DESC_RATE5_5M
;
917 rate
[2] = DESC_RATE11M
;
918 for (i
= 1; i
< 4; ++i
)
920 tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
922 } else if (mask
== 0x000000ff) {
923 rate
[0] = DESC_RATE11M
;
924 pwr_by_rate
[0] = bcd_to_dec_pwr_by_rate(val
, 0);
930 rate
[0] = DESC_RATEMCS0
;
931 rate
[1] = DESC_RATEMCS1
;
932 rate
[2] = DESC_RATEMCS2
;
933 rate
[3] = DESC_RATEMCS3
;
934 for (i
= 0; i
< 4; ++i
)
935 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
940 rate
[0] = DESC_RATEMCS4
;
941 rate
[1] = DESC_RATEMCS5
;
942 rate
[2] = DESC_RATEMCS6
;
943 rate
[3] = DESC_RATEMCS7
;
944 for (i
= 0; i
< 4; ++i
)
945 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
950 rate
[0] = DESC_RATEMCS8
;
951 rate
[1] = DESC_RATEMCS9
;
952 rate
[2] = DESC_RATEMCS10
;
953 rate
[3] = DESC_RATEMCS11
;
954 for (i
= 0; i
< 4; ++i
)
955 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
960 rate
[0] = DESC_RATEMCS12
;
961 rate
[1] = DESC_RATEMCS13
;
962 rate
[2] = DESC_RATEMCS14
;
963 rate
[3] = DESC_RATEMCS15
;
964 for (i
= 0; i
< 4; ++i
)
965 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
969 rate
[0] = DESC_RATE1M
;
970 rate
[1] = DESC_RATE2M
;
971 rate
[2] = DESC_RATE5_5M
;
972 for (i
= 1; i
< 4; ++i
)
973 pwr_by_rate
[i
- 1] = tbl_to_dec_pwr_by_rate(rtwdev
,
981 rate
[0] = DESC_RATE1M
;
982 rate
[1] = DESC_RATE2M
;
983 rate
[2] = DESC_RATE5_5M
;
984 rate
[3] = DESC_RATE11M
;
985 for (i
= 0; i
< 4; ++i
)
986 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
993 rate
[0] = DESC_RATE6M
;
994 rate
[1] = DESC_RATE9M
;
995 rate
[2] = DESC_RATE12M
;
996 rate
[3] = DESC_RATE18M
;
997 for (i
= 0; i
< 4; ++i
)
998 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
1005 rate
[0] = DESC_RATE24M
;
1006 rate
[1] = DESC_RATE36M
;
1007 rate
[2] = DESC_RATE48M
;
1008 rate
[3] = DESC_RATE54M
;
1009 for (i
= 0; i
< 4; ++i
)
1010 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
1017 rate
[0] = DESC_RATEMCS0
;
1018 rate
[1] = DESC_RATEMCS1
;
1019 rate
[2] = DESC_RATEMCS2
;
1020 rate
[3] = DESC_RATEMCS3
;
1021 for (i
= 0; i
< 4; ++i
)
1022 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
1029 rate
[0] = DESC_RATEMCS4
;
1030 rate
[1] = DESC_RATEMCS5
;
1031 rate
[2] = DESC_RATEMCS6
;
1032 rate
[3] = DESC_RATEMCS7
;
1033 for (i
= 0; i
< 4; ++i
)
1034 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
1041 rate
[0] = DESC_RATEMCS8
;
1042 rate
[1] = DESC_RATEMCS9
;
1043 rate
[2] = DESC_RATEMCS10
;
1044 rate
[3] = DESC_RATEMCS11
;
1045 for (i
= 0; i
< 4; ++i
)
1046 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
1053 rate
[0] = DESC_RATEMCS12
;
1054 rate
[1] = DESC_RATEMCS13
;
1055 rate
[2] = DESC_RATEMCS14
;
1056 rate
[3] = DESC_RATEMCS15
;
1057 for (i
= 0; i
< 4; ++i
)
1058 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
1065 rate
[0] = DESC_RATEVHT1SS_MCS0
;
1066 rate
[1] = DESC_RATEVHT1SS_MCS1
;
1067 rate
[2] = DESC_RATEVHT1SS_MCS2
;
1068 rate
[3] = DESC_RATEVHT1SS_MCS3
;
1069 for (i
= 0; i
< 4; ++i
)
1070 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
1077 rate
[0] = DESC_RATEVHT1SS_MCS4
;
1078 rate
[1] = DESC_RATEVHT1SS_MCS5
;
1079 rate
[2] = DESC_RATEVHT1SS_MCS6
;
1080 rate
[3] = DESC_RATEVHT1SS_MCS7
;
1081 for (i
= 0; i
< 4; ++i
)
1082 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
1089 rate
[0] = DESC_RATEVHT1SS_MCS8
;
1090 rate
[1] = DESC_RATEVHT1SS_MCS9
;
1091 rate
[2] = DESC_RATEVHT2SS_MCS0
;
1092 rate
[3] = DESC_RATEVHT2SS_MCS1
;
1093 for (i
= 0; i
< 4; ++i
)
1094 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
1101 rate
[0] = DESC_RATEVHT2SS_MCS2
;
1102 rate
[1] = DESC_RATEVHT2SS_MCS3
;
1103 rate
[2] = DESC_RATEVHT2SS_MCS4
;
1104 rate
[3] = DESC_RATEVHT2SS_MCS5
;
1105 for (i
= 0; i
< 4; ++i
)
1106 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
1113 rate
[0] = DESC_RATEVHT2SS_MCS6
;
1114 rate
[1] = DESC_RATEVHT2SS_MCS7
;
1115 rate
[2] = DESC_RATEVHT2SS_MCS8
;
1116 rate
[3] = DESC_RATEVHT2SS_MCS9
;
1117 for (i
= 0; i
< 4; ++i
)
1118 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
1125 rate
[0] = DESC_RATEMCS16
;
1126 rate
[1] = DESC_RATEMCS17
;
1127 rate
[2] = DESC_RATEMCS18
;
1128 rate
[3] = DESC_RATEMCS19
;
1129 for (i
= 0; i
< 4; ++i
)
1130 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
1137 rate
[0] = DESC_RATEMCS20
;
1138 rate
[1] = DESC_RATEMCS21
;
1139 rate
[2] = DESC_RATEMCS22
;
1140 rate
[3] = DESC_RATEMCS23
;
1141 for (i
= 0; i
< 4; ++i
)
1142 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
1149 rate
[0] = DESC_RATEVHT3SS_MCS0
;
1150 rate
[1] = DESC_RATEVHT3SS_MCS1
;
1151 rate
[2] = DESC_RATEVHT3SS_MCS2
;
1152 rate
[3] = DESC_RATEVHT3SS_MCS3
;
1153 for (i
= 0; i
< 4; ++i
)
1154 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
1161 rate
[0] = DESC_RATEVHT3SS_MCS4
;
1162 rate
[1] = DESC_RATEVHT3SS_MCS5
;
1163 rate
[2] = DESC_RATEVHT3SS_MCS6
;
1164 rate
[3] = DESC_RATEVHT3SS_MCS7
;
1165 for (i
= 0; i
< 4; ++i
)
1166 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
1173 rate
[0] = DESC_RATEVHT3SS_MCS8
;
1174 rate
[1] = DESC_RATEVHT3SS_MCS9
;
1175 for (i
= 0; i
< 2; ++i
)
1176 pwr_by_rate
[i
] = tbl_to_dec_pwr_by_rate(rtwdev
, val
, i
);
1180 rtw_warn(rtwdev
, "invalid tx power index addr 0x%08x\n", addr
);
1185 static void rtw_phy_store_tx_power_by_rate(struct rtw_dev
*rtwdev
,
1186 u32 band
, u32 rfpath
, u32 txnum
,
1187 u32 regaddr
, u32 bitmask
, u32 data
)
1189 struct rtw_hal
*hal
= &rtwdev
->hal
;
1192 u8 rates
[RTW_RF_PATH_MAX
] = {0};
1194 s8 pwr_by_rate
[RTW_RF_PATH_MAX
] = {0};
1197 rtw_phy_get_rate_values_of_txpwr_by_rate(rtwdev
, regaddr
, bitmask
, data
,
1198 rates
, pwr_by_rate
, &rate_num
);
1200 if (WARN_ON(rfpath
>= RTW_RF_PATH_MAX
||
1201 (band
!= PHY_BAND_2G
&& band
!= PHY_BAND_5G
) ||
1202 rate_num
> RTW_RF_PATH_MAX
))
1205 for (i
= 0; i
< rate_num
; i
++) {
1206 offset
= pwr_by_rate
[i
];
1208 if (band
== PHY_BAND_2G
)
1209 hal
->tx_pwr_by_rate_offset_2g
[rfpath
][rate
] = offset
;
1210 else if (band
== PHY_BAND_5G
)
1211 hal
->tx_pwr_by_rate_offset_5g
[rfpath
][rate
] = offset
;
1217 void rtw_parse_tbl_bb_pg(struct rtw_dev
*rtwdev
, const struct rtw_table
*tbl
)
1219 const struct rtw_phy_pg_cfg_pair
*p
= tbl
->data
;
1220 const struct rtw_phy_pg_cfg_pair
*end
= p
+ tbl
->size
;
1222 for (; p
< end
; p
++) {
1223 if (p
->addr
== 0xfe || p
->addr
== 0xffe) {
1227 rtw_phy_store_tx_power_by_rate(rtwdev
, p
->band
, p
->rf_path
,
1228 p
->tx_num
, p
->addr
, p
->bitmask
,
1233 static const u8 rtw_channel_idx_5g
[RTW_MAX_CHANNEL_NUM_5G
] = {
1234 36, 38, 40, 42, 44, 46, 48, /* Band 1 */
1235 52, 54, 56, 58, 60, 62, 64, /* Band 2 */
1236 100, 102, 104, 106, 108, 110, 112, /* Band 3 */
1237 116, 118, 120, 122, 124, 126, 128, /* Band 3 */
1238 132, 134, 136, 138, 140, 142, 144, /* Band 3 */
1239 149, 151, 153, 155, 157, 159, 161, /* Band 4 */
1240 165, 167, 169, 171, 173, 175, 177}; /* Band 4 */
1242 static int rtw_channel_to_idx(u8 band
, u8 channel
)
1247 if (band
== PHY_BAND_2G
) {
1248 ch_idx
= channel
- 1;
1249 n_channel
= RTW_MAX_CHANNEL_NUM_2G
;
1250 } else if (band
== PHY_BAND_5G
) {
1251 n_channel
= RTW_MAX_CHANNEL_NUM_5G
;
1252 for (ch_idx
= 0; ch_idx
< n_channel
; ch_idx
++)
1253 if (rtw_channel_idx_5g
[ch_idx
] == channel
)
1259 if (ch_idx
>= n_channel
)
1265 static void rtw_phy_set_tx_power_limit(struct rtw_dev
*rtwdev
, u8 regd
, u8 band
,
1266 u8 bw
, u8 rs
, u8 ch
, s8 pwr_limit
)
1268 struct rtw_hal
*hal
= &rtwdev
->hal
;
1269 u8 max_power_index
= rtwdev
->chip
->max_power_index
;
1273 pwr_limit
= clamp_t(s8
, pwr_limit
,
1274 -max_power_index
, max_power_index
);
1275 ch_idx
= rtw_channel_to_idx(band
, ch
);
1277 if (regd
>= RTW_REGD_MAX
|| bw
>= RTW_CHANNEL_WIDTH_MAX
||
1278 rs
>= RTW_RATE_SECTION_MAX
|| ch_idx
< 0) {
1280 "wrong txpwr_lmt regd=%u, band=%u bw=%u, rs=%u, ch_idx=%u, pwr_limit=%d\n",
1281 regd
, band
, bw
, rs
, ch_idx
, pwr_limit
);
1285 if (band
== PHY_BAND_2G
) {
1286 hal
->tx_pwr_limit_2g
[regd
][bw
][rs
][ch_idx
] = pwr_limit
;
1287 ww
= hal
->tx_pwr_limit_2g
[RTW_REGD_WW
][bw
][rs
][ch_idx
];
1288 ww
= min_t(s8
, ww
, pwr_limit
);
1289 hal
->tx_pwr_limit_2g
[RTW_REGD_WW
][bw
][rs
][ch_idx
] = ww
;
1290 } else if (band
== PHY_BAND_5G
) {
1291 hal
->tx_pwr_limit_5g
[regd
][bw
][rs
][ch_idx
] = pwr_limit
;
1292 ww
= hal
->tx_pwr_limit_5g
[RTW_REGD_WW
][bw
][rs
][ch_idx
];
1293 ww
= min_t(s8
, ww
, pwr_limit
);
1294 hal
->tx_pwr_limit_5g
[RTW_REGD_WW
][bw
][rs
][ch_idx
] = ww
;
1298 /* cross-reference 5G power limits if values are not assigned */
1300 rtw_xref_5g_txpwr_lmt(struct rtw_dev
*rtwdev
, u8 regd
,
1301 u8 bw
, u8 ch_idx
, u8 rs_ht
, u8 rs_vht
)
1303 struct rtw_hal
*hal
= &rtwdev
->hal
;
1304 u8 max_power_index
= rtwdev
->chip
->max_power_index
;
1305 s8 lmt_ht
= hal
->tx_pwr_limit_5g
[regd
][bw
][rs_ht
][ch_idx
];
1306 s8 lmt_vht
= hal
->tx_pwr_limit_5g
[regd
][bw
][rs_vht
][ch_idx
];
1308 if (lmt_ht
== lmt_vht
)
1311 if (lmt_ht
== max_power_index
)
1312 hal
->tx_pwr_limit_5g
[regd
][bw
][rs_ht
][ch_idx
] = lmt_vht
;
1314 else if (lmt_vht
== max_power_index
)
1315 hal
->tx_pwr_limit_5g
[regd
][bw
][rs_vht
][ch_idx
] = lmt_ht
;
1318 /* cross-reference power limits for ht and vht */
1320 rtw_xref_txpwr_lmt_by_rs(struct rtw_dev
*rtwdev
, u8 regd
, u8 bw
, u8 ch_idx
)
1322 u8 rs_idx
, rs_ht
, rs_vht
;
1323 u8 rs_cmp
[2][2] = {{RTW_RATE_SECTION_HT_1S
, RTW_RATE_SECTION_VHT_1S
},
1324 {RTW_RATE_SECTION_HT_2S
, RTW_RATE_SECTION_VHT_2S
} };
1326 for (rs_idx
= 0; rs_idx
< 2; rs_idx
++) {
1327 rs_ht
= rs_cmp
[rs_idx
][0];
1328 rs_vht
= rs_cmp
[rs_idx
][1];
1330 rtw_xref_5g_txpwr_lmt(rtwdev
, regd
, bw
, ch_idx
, rs_ht
, rs_vht
);
1334 /* cross-reference power limits for 5G channels */
1336 rtw_xref_5g_txpwr_lmt_by_ch(struct rtw_dev
*rtwdev
, u8 regd
, u8 bw
)
1340 for (ch_idx
= 0; ch_idx
< RTW_MAX_CHANNEL_NUM_5G
; ch_idx
++)
1341 rtw_xref_txpwr_lmt_by_rs(rtwdev
, regd
, bw
, ch_idx
);
1344 /* cross-reference power limits for 20/40M bandwidth */
1346 rtw_xref_txpwr_lmt_by_bw(struct rtw_dev
*rtwdev
, u8 regd
)
1350 for (bw
= RTW_CHANNEL_WIDTH_20
; bw
<= RTW_CHANNEL_WIDTH_40
; bw
++)
1351 rtw_xref_5g_txpwr_lmt_by_ch(rtwdev
, regd
, bw
);
1354 /* cross-reference power limits */
1355 static void rtw_xref_txpwr_lmt(struct rtw_dev
*rtwdev
)
1359 for (regd
= 0; regd
< RTW_REGD_MAX
; regd
++)
1360 rtw_xref_txpwr_lmt_by_bw(rtwdev
, regd
);
1363 void rtw_parse_tbl_txpwr_lmt(struct rtw_dev
*rtwdev
,
1364 const struct rtw_table
*tbl
)
1366 const struct rtw_txpwr_lmt_cfg_pair
*p
= tbl
->data
;
1367 const struct rtw_txpwr_lmt_cfg_pair
*end
= p
+ tbl
->size
;
1369 for (; p
< end
; p
++) {
1370 rtw_phy_set_tx_power_limit(rtwdev
, p
->regd
, p
->band
,
1371 p
->bw
, p
->rs
, p
->ch
, p
->txpwr_lmt
);
1374 rtw_xref_txpwr_lmt(rtwdev
);
1377 void rtw_phy_cfg_mac(struct rtw_dev
*rtwdev
, const struct rtw_table
*tbl
,
1380 rtw_write8(rtwdev
, addr
, data
);
1383 void rtw_phy_cfg_agc(struct rtw_dev
*rtwdev
, const struct rtw_table
*tbl
,
1386 rtw_write32(rtwdev
, addr
, data
);
1389 void rtw_phy_cfg_bb(struct rtw_dev
*rtwdev
, const struct rtw_table
*tbl
,
1394 else if (addr
== 0xfd)
1396 else if (addr
== 0xfc)
1398 else if (addr
== 0xfb)
1399 usleep_range(50, 60);
1400 else if (addr
== 0xfa)
1402 else if (addr
== 0xf9)
1405 rtw_write32(rtwdev
, addr
, data
);
1408 void rtw_phy_cfg_rf(struct rtw_dev
*rtwdev
, const struct rtw_table
*tbl
,
1411 if (addr
== 0xffe) {
1413 } else if (addr
== 0xfe) {
1414 usleep_range(100, 110);
1416 rtw_write_rf(rtwdev
, tbl
->rf_path
, addr
, RFREG_MASK
, data
);
1421 static void rtw_load_rfk_table(struct rtw_dev
*rtwdev
)
1423 struct rtw_chip_info
*chip
= rtwdev
->chip
;
1424 struct rtw_dpk_info
*dpk_info
= &rtwdev
->dm_info
.dpk_info
;
1426 if (!chip
->rfk_init_tbl
)
1429 rtw_write32_mask(rtwdev
, 0x1e24, BIT(17), 0x1);
1430 rtw_write32_mask(rtwdev
, 0x1cd0, BIT(28), 0x1);
1431 rtw_write32_mask(rtwdev
, 0x1cd0, BIT(29), 0x1);
1432 rtw_write32_mask(rtwdev
, 0x1cd0, BIT(30), 0x1);
1433 rtw_write32_mask(rtwdev
, 0x1cd0, BIT(31), 0x0);
1435 rtw_load_table(rtwdev
, chip
->rfk_init_tbl
);
1437 dpk_info
->is_dpk_pwr_on
= 1;
1440 void rtw_phy_load_tables(struct rtw_dev
*rtwdev
)
1442 struct rtw_chip_info
*chip
= rtwdev
->chip
;
1445 rtw_load_table(rtwdev
, chip
->mac_tbl
);
1446 rtw_load_table(rtwdev
, chip
->bb_tbl
);
1447 rtw_load_table(rtwdev
, chip
->agc_tbl
);
1448 rtw_load_rfk_table(rtwdev
);
1450 for (rf_path
= 0; rf_path
< rtwdev
->hal
.rf_path_num
; rf_path
++) {
1451 const struct rtw_table
*tbl
;
1453 tbl
= chip
->rf_tbl
[rf_path
];
1454 rtw_load_table(rtwdev
, tbl
);
1458 static u8
rtw_get_channel_group(u8 channel
)
1547 static s8
rtw_phy_get_dis_dpd_by_rate_diff(struct rtw_dev
*rtwdev
, u16 rate
)
1549 struct rtw_chip_info
*chip
= rtwdev
->chip
;
1552 if (!chip
->en_dis_dpd
)
1555 #define RTW_DPD_RATE_CHECK(_rate) \
1556 case DESC_RATE ## _rate: \
1557 if (DIS_DPD_RATE ## _rate & chip->dpd_ratemask) \
1558 dpd_diff = -6 * chip->txgi_factor; \
1562 RTW_DPD_RATE_CHECK(6M
);
1563 RTW_DPD_RATE_CHECK(9M
);
1564 RTW_DPD_RATE_CHECK(MCS0
);
1565 RTW_DPD_RATE_CHECK(MCS1
);
1566 RTW_DPD_RATE_CHECK(MCS8
);
1567 RTW_DPD_RATE_CHECK(MCS9
);
1568 RTW_DPD_RATE_CHECK(VHT1SS_MCS0
);
1569 RTW_DPD_RATE_CHECK(VHT1SS_MCS1
);
1570 RTW_DPD_RATE_CHECK(VHT2SS_MCS0
);
1571 RTW_DPD_RATE_CHECK(VHT2SS_MCS1
);
1573 #undef RTW_DPD_RATE_CHECK
1578 static u8
rtw_phy_get_2g_tx_power_index(struct rtw_dev
*rtwdev
,
1579 struct rtw_2g_txpwr_idx
*pwr_idx_2g
,
1580 enum rtw_bandwidth bandwidth
,
1583 struct rtw_chip_info
*chip
= rtwdev
->chip
;
1587 u8 factor
= chip
->txgi_factor
;
1589 if (rate
<= DESC_RATE11M
)
1590 tx_power
= pwr_idx_2g
->cck_base
[group
];
1592 tx_power
= pwr_idx_2g
->bw40_base
[group
];
1594 if (rate
>= DESC_RATE6M
&& rate
<= DESC_RATE54M
)
1595 tx_power
+= pwr_idx_2g
->ht_1s_diff
.ofdm
* factor
;
1597 mcs_rate
= (rate
>= DESC_RATEMCS0
&& rate
<= DESC_RATEMCS15
) ||
1598 (rate
>= DESC_RATEVHT1SS_MCS0
&&
1599 rate
<= DESC_RATEVHT2SS_MCS9
);
1600 above_2ss
= (rate
>= DESC_RATEMCS8
&& rate
<= DESC_RATEMCS15
) ||
1601 (rate
>= DESC_RATEVHT2SS_MCS0
);
1606 switch (bandwidth
) {
1610 case RTW_CHANNEL_WIDTH_20
:
1611 tx_power
+= pwr_idx_2g
->ht_1s_diff
.bw20
* factor
;
1613 tx_power
+= pwr_idx_2g
->ht_2s_diff
.bw20
* factor
;
1615 case RTW_CHANNEL_WIDTH_40
:
1616 /* bw40 is the base power */
1618 tx_power
+= pwr_idx_2g
->ht_2s_diff
.bw40
* factor
;
1625 static u8
rtw_phy_get_5g_tx_power_index(struct rtw_dev
*rtwdev
,
1626 struct rtw_5g_txpwr_idx
*pwr_idx_5g
,
1627 enum rtw_bandwidth bandwidth
,
1630 struct rtw_chip_info
*chip
= rtwdev
->chip
;
1635 u8 factor
= chip
->txgi_factor
;
1637 tx_power
= pwr_idx_5g
->bw40_base
[group
];
1639 mcs_rate
= (rate
>= DESC_RATEMCS0
&& rate
<= DESC_RATEMCS15
) ||
1640 (rate
>= DESC_RATEVHT1SS_MCS0
&&
1641 rate
<= DESC_RATEVHT2SS_MCS9
);
1642 above_2ss
= (rate
>= DESC_RATEMCS8
&& rate
<= DESC_RATEMCS15
) ||
1643 (rate
>= DESC_RATEVHT2SS_MCS0
);
1646 tx_power
+= pwr_idx_5g
->ht_1s_diff
.ofdm
* factor
;
1650 switch (bandwidth
) {
1654 case RTW_CHANNEL_WIDTH_20
:
1655 tx_power
+= pwr_idx_5g
->ht_1s_diff
.bw20
* factor
;
1657 tx_power
+= pwr_idx_5g
->ht_2s_diff
.bw20
* factor
;
1659 case RTW_CHANNEL_WIDTH_40
:
1660 /* bw40 is the base power */
1662 tx_power
+= pwr_idx_5g
->ht_2s_diff
.bw40
* factor
;
1664 case RTW_CHANNEL_WIDTH_80
:
1665 /* the base idx of bw80 is the average of bw40+/bw40- */
1666 lower
= pwr_idx_5g
->bw40_base
[group
];
1667 upper
= pwr_idx_5g
->bw40_base
[group
+ 1];
1669 tx_power
= (lower
+ upper
) / 2;
1670 tx_power
+= pwr_idx_5g
->vht_1s_diff
.bw80
* factor
;
1672 tx_power
+= pwr_idx_5g
->vht_2s_diff
.bw80
* factor
;
1679 static s8
rtw_phy_get_tx_power_limit(struct rtw_dev
*rtwdev
, u8 band
,
1680 enum rtw_bandwidth bw
, u8 rf_path
,
1681 u8 rate
, u8 channel
, u8 regd
)
1683 struct rtw_hal
*hal
= &rtwdev
->hal
;
1684 u8
*cch_by_bw
= hal
->cch_by_bw
;
1685 s8 power_limit
= (s8
)rtwdev
->chip
->max_power_index
;
1691 if (regd
> RTW_REGD_WW
)
1694 if (rate
>= DESC_RATE1M
&& rate
<= DESC_RATE11M
)
1695 rs
= RTW_RATE_SECTION_CCK
;
1696 else if (rate
>= DESC_RATE6M
&& rate
<= DESC_RATE54M
)
1697 rs
= RTW_RATE_SECTION_OFDM
;
1698 else if (rate
>= DESC_RATEMCS0
&& rate
<= DESC_RATEMCS7
)
1699 rs
= RTW_RATE_SECTION_HT_1S
;
1700 else if (rate
>= DESC_RATEMCS8
&& rate
<= DESC_RATEMCS15
)
1701 rs
= RTW_RATE_SECTION_HT_2S
;
1702 else if (rate
>= DESC_RATEVHT1SS_MCS0
&& rate
<= DESC_RATEVHT1SS_MCS9
)
1703 rs
= RTW_RATE_SECTION_VHT_1S
;
1704 else if (rate
>= DESC_RATEVHT2SS_MCS0
&& rate
<= DESC_RATEVHT2SS_MCS9
)
1705 rs
= RTW_RATE_SECTION_VHT_2S
;
1709 /* only 20M BW with cck and ofdm */
1710 if (rs
== RTW_RATE_SECTION_CCK
|| rs
== RTW_RATE_SECTION_OFDM
)
1711 bw
= RTW_CHANNEL_WIDTH_20
;
1713 /* only 20/40M BW with ht */
1714 if (rs
== RTW_RATE_SECTION_HT_1S
|| rs
== RTW_RATE_SECTION_HT_2S
)
1715 bw
= min_t(u8
, bw
, RTW_CHANNEL_WIDTH_40
);
1717 /* select min power limit among [20M BW ~ current BW] */
1718 for (cur_bw
= RTW_CHANNEL_WIDTH_20
; cur_bw
<= bw
; cur_bw
++) {
1719 cur_ch
= cch_by_bw
[cur_bw
];
1721 ch_idx
= rtw_channel_to_idx(band
, cur_ch
);
1725 cur_lmt
= cur_ch
<= RTW_MAX_CHANNEL_NUM_2G
?
1726 hal
->tx_pwr_limit_2g
[regd
][cur_bw
][rs
][ch_idx
] :
1727 hal
->tx_pwr_limit_5g
[regd
][cur_bw
][rs
][ch_idx
];
1729 power_limit
= min_t(s8
, cur_lmt
, power_limit
);
1735 WARN(1, "invalid arguments, band=%d, bw=%d, path=%d, rate=%d, ch=%d\n",
1736 band
, bw
, rf_path
, rate
, channel
);
1737 return (s8
)rtwdev
->chip
->max_power_index
;
1740 void rtw_get_tx_power_params(struct rtw_dev
*rtwdev
, u8 path
, u8 rate
, u8 bw
,
1741 u8 ch
, u8 regd
, struct rtw_power_params
*pwr_param
)
1743 struct rtw_hal
*hal
= &rtwdev
->hal
;
1744 struct rtw_txpwr_idx
*pwr_idx
;
1746 u8
*base
= &pwr_param
->pwr_base
;
1747 s8
*offset
= &pwr_param
->pwr_offset
;
1748 s8
*limit
= &pwr_param
->pwr_limit
;
1750 pwr_idx
= &rtwdev
->efuse
.txpwr_idx_table
[path
];
1751 group
= rtw_get_channel_group(ch
);
1753 /* base power index for 2.4G/5G */
1754 if (IS_CH_2G_BAND(ch
)) {
1756 *base
= rtw_phy_get_2g_tx_power_index(rtwdev
,
1757 &pwr_idx
->pwr_idx_2g
,
1759 *offset
= hal
->tx_pwr_by_rate_offset_2g
[path
][rate
];
1762 *base
= rtw_phy_get_5g_tx_power_index(rtwdev
,
1763 &pwr_idx
->pwr_idx_5g
,
1765 *offset
= hal
->tx_pwr_by_rate_offset_5g
[path
][rate
];
1768 *limit
= rtw_phy_get_tx_power_limit(rtwdev
, band
, bw
, path
,
1773 rtw_phy_get_tx_power_index(struct rtw_dev
*rtwdev
, u8 rf_path
, u8 rate
,
1774 enum rtw_bandwidth bandwidth
, u8 channel
, u8 regd
)
1776 struct rtw_power_params pwr_param
= {0};
1780 rtw_get_tx_power_params(rtwdev
, rf_path
, rate
, bandwidth
,
1781 channel
, regd
, &pwr_param
);
1783 tx_power
= pwr_param
.pwr_base
;
1784 offset
= min_t(s8
, pwr_param
.pwr_offset
, pwr_param
.pwr_limit
);
1786 if (rtwdev
->chip
->en_dis_dpd
)
1787 offset
+= rtw_phy_get_dis_dpd_by_rate_diff(rtwdev
, rate
);
1791 if (tx_power
> rtwdev
->chip
->max_power_index
)
1792 tx_power
= rtwdev
->chip
->max_power_index
;
1797 static void rtw_phy_set_tx_power_index_by_rs(struct rtw_dev
*rtwdev
,
1798 u8 ch
, u8 path
, u8 rs
)
1800 struct rtw_hal
*hal
= &rtwdev
->hal
;
1801 u8 regd
= rtwdev
->regd
.txpwr_regd
;
1809 if (rs
>= RTW_RATE_SECTION_MAX
)
1812 rates
= rtw_rate_section
[rs
];
1813 size
= rtw_rate_size
[rs
];
1814 bw
= hal
->current_band_width
;
1815 for (i
= 0; i
< size
; i
++) {
1817 pwr_idx
= rtw_phy_get_tx_power_index(rtwdev
, path
, rate
,
1819 hal
->tx_pwr_tbl
[path
][rate
] = pwr_idx
;
1823 /* set tx power level by path for each rates, note that the order of the rates
1824 * are *very* important, bacause 8822B/8821C combines every four bytes of tx
1825 * power index into a four-byte power index register, and calls set_tx_agc to
1826 * write these values into hardware
1828 static void rtw_phy_set_tx_power_level_by_path(struct rtw_dev
*rtwdev
,
1831 struct rtw_hal
*hal
= &rtwdev
->hal
;
1834 /* do not need cck rates if we are not in 2.4G */
1835 if (hal
->current_band_type
== RTW_BAND_2G
)
1836 rs
= RTW_RATE_SECTION_CCK
;
1838 rs
= RTW_RATE_SECTION_OFDM
;
1840 for (; rs
< RTW_RATE_SECTION_MAX
; rs
++)
1841 rtw_phy_set_tx_power_index_by_rs(rtwdev
, ch
, path
, rs
);
1844 void rtw_phy_set_tx_power_level(struct rtw_dev
*rtwdev
, u8 channel
)
1846 struct rtw_chip_info
*chip
= rtwdev
->chip
;
1847 struct rtw_hal
*hal
= &rtwdev
->hal
;
1850 mutex_lock(&hal
->tx_power_mutex
);
1852 for (path
= 0; path
< hal
->rf_path_num
; path
++)
1853 rtw_phy_set_tx_power_level_by_path(rtwdev
, channel
, path
);
1855 chip
->ops
->set_tx_power_index(rtwdev
);
1856 mutex_unlock(&hal
->tx_power_mutex
);
1860 rtw_phy_tx_power_by_rate_config_by_path(struct rtw_hal
*hal
, u8 path
,
1861 u8 rs
, u8 size
, u8
*rates
)
1864 u8 base_idx
, rate_idx
;
1865 s8 base_2g
, base_5g
;
1867 if (rs
>= RTW_RATE_SECTION_VHT_1S
)
1868 base_idx
= rates
[size
- 3];
1870 base_idx
= rates
[size
- 1];
1871 base_2g
= hal
->tx_pwr_by_rate_offset_2g
[path
][base_idx
];
1872 base_5g
= hal
->tx_pwr_by_rate_offset_5g
[path
][base_idx
];
1873 hal
->tx_pwr_by_rate_base_2g
[path
][rs
] = base_2g
;
1874 hal
->tx_pwr_by_rate_base_5g
[path
][rs
] = base_5g
;
1875 for (rate
= 0; rate
< size
; rate
++) {
1876 rate_idx
= rates
[rate
];
1877 hal
->tx_pwr_by_rate_offset_2g
[path
][rate_idx
] -= base_2g
;
1878 hal
->tx_pwr_by_rate_offset_5g
[path
][rate_idx
] -= base_5g
;
1882 void rtw_phy_tx_power_by_rate_config(struct rtw_hal
*hal
)
1886 for (path
= 0; path
< RTW_RF_PATH_MAX
; path
++) {
1887 rtw_phy_tx_power_by_rate_config_by_path(hal
, path
,
1888 RTW_RATE_SECTION_CCK
,
1889 rtw_cck_size
, rtw_cck_rates
);
1890 rtw_phy_tx_power_by_rate_config_by_path(hal
, path
,
1891 RTW_RATE_SECTION_OFDM
,
1892 rtw_ofdm_size
, rtw_ofdm_rates
);
1893 rtw_phy_tx_power_by_rate_config_by_path(hal
, path
,
1894 RTW_RATE_SECTION_HT_1S
,
1895 rtw_ht_1s_size
, rtw_ht_1s_rates
);
1896 rtw_phy_tx_power_by_rate_config_by_path(hal
, path
,
1897 RTW_RATE_SECTION_HT_2S
,
1898 rtw_ht_2s_size
, rtw_ht_2s_rates
);
1899 rtw_phy_tx_power_by_rate_config_by_path(hal
, path
,
1900 RTW_RATE_SECTION_VHT_1S
,
1901 rtw_vht_1s_size
, rtw_vht_1s_rates
);
1902 rtw_phy_tx_power_by_rate_config_by_path(hal
, path
,
1903 RTW_RATE_SECTION_VHT_2S
,
1904 rtw_vht_2s_size
, rtw_vht_2s_rates
);
1909 __rtw_phy_tx_power_limit_config(struct rtw_hal
*hal
, u8 regd
, u8 bw
, u8 rs
)
1914 for (ch
= 0; ch
< RTW_MAX_CHANNEL_NUM_2G
; ch
++) {
1915 base
= hal
->tx_pwr_by_rate_base_2g
[0][rs
];
1916 hal
->tx_pwr_limit_2g
[regd
][bw
][rs
][ch
] -= base
;
1919 for (ch
= 0; ch
< RTW_MAX_CHANNEL_NUM_5G
; ch
++) {
1920 base
= hal
->tx_pwr_by_rate_base_5g
[0][rs
];
1921 hal
->tx_pwr_limit_5g
[regd
][bw
][rs
][ch
] -= base
;
1925 void rtw_phy_tx_power_limit_config(struct rtw_hal
*hal
)
1929 /* default at channel 1 */
1930 hal
->cch_by_bw
[RTW_CHANNEL_WIDTH_20
] = 1;
1932 for (regd
= 0; regd
< RTW_REGD_MAX
; regd
++)
1933 for (bw
= 0; bw
< RTW_CHANNEL_WIDTH_MAX
; bw
++)
1934 for (rs
= 0; rs
< RTW_RATE_SECTION_MAX
; rs
++)
1935 __rtw_phy_tx_power_limit_config(hal
, regd
, bw
, rs
);
1938 static void rtw_phy_init_tx_power_limit(struct rtw_dev
*rtwdev
,
1939 u8 regd
, u8 bw
, u8 rs
)
1941 struct rtw_hal
*hal
= &rtwdev
->hal
;
1942 s8 max_power_index
= (s8
)rtwdev
->chip
->max_power_index
;
1946 for (ch
= 0; ch
< RTW_MAX_CHANNEL_NUM_2G
; ch
++)
1947 hal
->tx_pwr_limit_2g
[regd
][bw
][rs
][ch
] = max_power_index
;
1950 for (ch
= 0; ch
< RTW_MAX_CHANNEL_NUM_5G
; ch
++)
1951 hal
->tx_pwr_limit_5g
[regd
][bw
][rs
][ch
] = max_power_index
;
1954 void rtw_phy_init_tx_power(struct rtw_dev
*rtwdev
)
1956 struct rtw_hal
*hal
= &rtwdev
->hal
;
1957 u8 regd
, path
, rate
, rs
, bw
;
1959 /* init tx power by rate offset */
1960 for (path
= 0; path
< RTW_RF_PATH_MAX
; path
++) {
1961 for (rate
= 0; rate
< DESC_RATE_MAX
; rate
++) {
1962 hal
->tx_pwr_by_rate_offset_2g
[path
][rate
] = 0;
1963 hal
->tx_pwr_by_rate_offset_5g
[path
][rate
] = 0;
1967 /* init tx power limit */
1968 for (regd
= 0; regd
< RTW_REGD_MAX
; regd
++)
1969 for (bw
= 0; bw
< RTW_CHANNEL_WIDTH_MAX
; bw
++)
1970 for (rs
= 0; rs
< RTW_RATE_SECTION_MAX
; rs
++)
1971 rtw_phy_init_tx_power_limit(rtwdev
, regd
, bw
,
1975 void rtw_phy_config_swing_table(struct rtw_dev
*rtwdev
,
1976 struct rtw_swing_table
*swing_table
)
1978 const struct rtw_pwr_track_tbl
*tbl
= rtwdev
->chip
->pwr_track_tbl
;
1979 u8 channel
= rtwdev
->hal
.current_channel
;
1981 if (IS_CH_2G_BAND(channel
)) {
1982 if (rtwdev
->dm_info
.tx_rate
<= DESC_RATE11M
) {
1983 swing_table
->p
[RF_PATH_A
] = tbl
->pwrtrk_2g_ccka_p
;
1984 swing_table
->n
[RF_PATH_A
] = tbl
->pwrtrk_2g_ccka_n
;
1985 swing_table
->p
[RF_PATH_B
] = tbl
->pwrtrk_2g_cckb_p
;
1986 swing_table
->n
[RF_PATH_B
] = tbl
->pwrtrk_2g_cckb_n
;
1988 swing_table
->p
[RF_PATH_A
] = tbl
->pwrtrk_2ga_p
;
1989 swing_table
->n
[RF_PATH_A
] = tbl
->pwrtrk_2ga_n
;
1990 swing_table
->p
[RF_PATH_B
] = tbl
->pwrtrk_2gb_p
;
1991 swing_table
->n
[RF_PATH_B
] = tbl
->pwrtrk_2gb_n
;
1993 } else if (IS_CH_5G_BAND_1(channel
) || IS_CH_5G_BAND_2(channel
)) {
1994 swing_table
->p
[RF_PATH_A
] = tbl
->pwrtrk_5ga_p
[RTW_PWR_TRK_5G_1
];
1995 swing_table
->n
[RF_PATH_A
] = tbl
->pwrtrk_5ga_n
[RTW_PWR_TRK_5G_1
];
1996 swing_table
->p
[RF_PATH_B
] = tbl
->pwrtrk_5gb_p
[RTW_PWR_TRK_5G_1
];
1997 swing_table
->n
[RF_PATH_B
] = tbl
->pwrtrk_5gb_n
[RTW_PWR_TRK_5G_1
];
1998 } else if (IS_CH_5G_BAND_3(channel
)) {
1999 swing_table
->p
[RF_PATH_A
] = tbl
->pwrtrk_5ga_p
[RTW_PWR_TRK_5G_2
];
2000 swing_table
->n
[RF_PATH_A
] = tbl
->pwrtrk_5ga_n
[RTW_PWR_TRK_5G_2
];
2001 swing_table
->p
[RF_PATH_B
] = tbl
->pwrtrk_5gb_p
[RTW_PWR_TRK_5G_2
];
2002 swing_table
->n
[RF_PATH_B
] = tbl
->pwrtrk_5gb_n
[RTW_PWR_TRK_5G_2
];
2003 } else if (IS_CH_5G_BAND_4(channel
)) {
2004 swing_table
->p
[RF_PATH_A
] = tbl
->pwrtrk_5ga_p
[RTW_PWR_TRK_5G_3
];
2005 swing_table
->n
[RF_PATH_A
] = tbl
->pwrtrk_5ga_n
[RTW_PWR_TRK_5G_3
];
2006 swing_table
->p
[RF_PATH_B
] = tbl
->pwrtrk_5gb_p
[RTW_PWR_TRK_5G_3
];
2007 swing_table
->n
[RF_PATH_B
] = tbl
->pwrtrk_5gb_n
[RTW_PWR_TRK_5G_3
];
2009 swing_table
->p
[RF_PATH_A
] = tbl
->pwrtrk_2ga_p
;
2010 swing_table
->n
[RF_PATH_A
] = tbl
->pwrtrk_2ga_n
;
2011 swing_table
->p
[RF_PATH_B
] = tbl
->pwrtrk_2gb_p
;
2012 swing_table
->n
[RF_PATH_B
] = tbl
->pwrtrk_2gb_n
;
2016 void rtw_phy_pwrtrack_avg(struct rtw_dev
*rtwdev
, u8 thermal
, u8 path
)
2018 struct rtw_dm_info
*dm_info
= &rtwdev
->dm_info
;
2020 ewma_thermal_add(&dm_info
->avg_thermal
[path
], thermal
);
2021 dm_info
->thermal_avg
[path
] =
2022 ewma_thermal_read(&dm_info
->avg_thermal
[path
]);
2025 bool rtw_phy_pwrtrack_thermal_changed(struct rtw_dev
*rtwdev
, u8 thermal
,
2028 struct rtw_dm_info
*dm_info
= &rtwdev
->dm_info
;
2029 u8 avg
= ewma_thermal_read(&dm_info
->avg_thermal
[path
]);
2037 u8
rtw_phy_pwrtrack_get_delta(struct rtw_dev
*rtwdev
, u8 path
)
2039 struct rtw_dm_info
*dm_info
= &rtwdev
->dm_info
;
2040 u8 therm_avg
, therm_efuse
, therm_delta
;
2042 therm_avg
= dm_info
->thermal_avg
[path
];
2043 therm_efuse
= rtwdev
->efuse
.thermal_meter
[path
];
2044 therm_delta
= abs(therm_avg
- therm_efuse
);
2046 return min_t(u8
, therm_delta
, RTW_PWR_TRK_TBL_SZ
- 1);
2049 s8
rtw_phy_pwrtrack_get_pwridx(struct rtw_dev
*rtwdev
,
2050 struct rtw_swing_table
*swing_table
,
2051 u8 tbl_path
, u8 therm_path
, u8 delta
)
2053 struct rtw_dm_info
*dm_info
= &rtwdev
->dm_info
;
2054 const u8
*delta_swing_table_idx_pos
;
2055 const u8
*delta_swing_table_idx_neg
;
2057 if (delta
>= RTW_PWR_TRK_TBL_SZ
) {
2058 rtw_warn(rtwdev
, "power track table overflow\n");
2063 rtw_warn(rtwdev
, "swing table not configured\n");
2067 delta_swing_table_idx_pos
= swing_table
->p
[tbl_path
];
2068 delta_swing_table_idx_neg
= swing_table
->n
[tbl_path
];
2070 if (!delta_swing_table_idx_pos
|| !delta_swing_table_idx_neg
) {
2071 rtw_warn(rtwdev
, "invalid swing table index\n");
2075 if (dm_info
->thermal_avg
[therm_path
] >
2076 rtwdev
->efuse
.thermal_meter
[therm_path
])
2077 return delta_swing_table_idx_pos
[delta
];
2079 return -delta_swing_table_idx_neg
[delta
];
2082 bool rtw_phy_pwrtrack_need_iqk(struct rtw_dev
*rtwdev
)
2084 struct rtw_dm_info
*dm_info
= &rtwdev
->dm_info
;
2087 delta_iqk
= abs(dm_info
->thermal_avg
[0] - dm_info
->thermal_meter_k
);
2088 if (delta_iqk
>= rtwdev
->chip
->iqk_threshold
) {
2089 dm_info
->thermal_meter_k
= dm_info
->thermal_avg
[0];