drivers/net/wireless/realtek/rtw88/rtw8822c.h

   1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2 /* Copyright(c) 2018-2019  Realtek Corporation
   3  */
   4
   5 #ifndef __RTW8822C_H__
   6 #define __RTW8822C_H__
   7
   8 #include <asm/byteorder.h>
   9
  10 struct rtw8822cu_efuse {
  11         u8 res0[0x30];                  /* 0x120 */
  12         u8 vid[2];                      /* 0x150 */
  13         u8 pid[2];
  14         u8 res1[3];
  15         u8 mac_addr[ETH_ALEN];          /* 0x157 */
  16         u8 res2[0x3d];
  17 };
  18
  19 struct rtw8822ce_efuse {
  20         u8 mac_addr[ETH_ALEN];          /* 0x120 */
  21         u8 vender_id[2];
  22         u8 device_id[2];
  23         u8 sub_vender_id[2];
  24         u8 sub_device_id[2];
  25         u8 pmc[2];
  26         u8 exp_device_cap[2];
  27         u8 msi_cap;
  28         u8 ltr_cap;                     /* 0x133 */
  29         u8 exp_link_control[2];
  30         u8 link_cap[4];
  31         u8 link_control[2];
  32         u8 serial_number[8];
  33         u8 res0:2;                      /* 0x144 */
  34         u8 ltr_en:1;
  35         u8 res1:2;
  36         u8 obff:2;
  37         u8 res2:3;
  38         u8 obff_cap:2;
  39         u8 res3:4;
  40         u8 class_code[3];
  41         u8 res4;
  42         u8 pci_pm_L1_2_supp:1;
  43         u8 pci_pm_L1_1_supp:1;
  44         u8 aspm_pm_L1_2_supp:1;
  45         u8 aspm_pm_L1_1_supp:1;
  46         u8 L1_pm_substates_supp:1;
  47         u8 res5:3;
  48         u8 port_common_mode_restore_time;
  49         u8 port_t_power_on_scale:2;
  50         u8 res6:1;
  51         u8 port_t_power_on_value:5;
  52         u8 res7;
  53 };
  54
  55 struct rtw8822c_efuse {
  56         __le16 rtl_id;
  57         u8 res0[0x0e];
  58
  59         /* power index for four RF paths */
  60         struct rtw_txpwr_idx txpwr_idx_table[4];
  61
  62         u8 channel_plan;                /* 0xb8 */
  63         u8 xtal_k;
  64         u8 res1;
  65         u8 iqk_lck;
  66         u8 res2[5];                     /* 0xbc */
  67         u8 rf_board_option;
  68         u8 rf_feature_option;
  69         u8 rf_bt_setting;
  70         u8 eeprom_version;
  71         u8 eeprom_customer_id;
  72         u8 tx_bb_swing_setting_2g;
  73         u8 tx_bb_swing_setting_5g;
  74         u8 tx_pwr_calibrate_rate;
  75         u8 rf_antenna_option;           /* 0xc9 */
  76         u8 rfe_option;
  77         u8 country_code[2];
  78         u8 res3[3];
  79         u8 path_a_thermal;              /* 0xd0 */
  80         u8 path_b_thermal;
  81         u8 res4[2];
  82         u8 rx_gain_gap_2g_ofdm;
  83         u8 res5;
  84         u8 rx_gain_gap_2g_cck;
  85         u8 res6;
  86         u8 rx_gain_gap_5gl;
  87         u8 res7;
  88         u8 rx_gain_gap_5gm;
  89         u8 res8;
  90         u8 rx_gain_gap_5gh;
  91         u8 res9;
  92         u8 res10[0x42];
  93         union {
  94                 struct rtw8822cu_efuse u;
  95                 struct rtw8822ce_efuse e;
  96         };
  97 };
  98
  99 enum rtw8822c_dpk_agc_phase {
 100         RTW_DPK_GAIN_CHECK,
 101         RTW_DPK_GAIN_LARGE,
 102         RTW_DPK_GAIN_LESS,
 103         RTW_DPK_GL_LARGE,
 104         RTW_DPK_GL_LESS,
 105         RTW_DPK_LOSS_CHECK,
 106         RTW_DPK_AGC_OUT,
 107 };
 108
 109 enum rtw8822c_dpk_one_shot_action {
 110         RTW_DPK_CAL_PWR,
 111         RTW_DPK_GAIN_LOSS,
 112         RTW_DPK_DO_DPK,
 113         RTW_DPK_DPK_ON,
 114         RTW_DPK_DAGC,
 115         RTW_DPK_ACTION_MAX
 116 };
 117
 118 void rtw8822c_parse_tbl_dpk(struct rtw_dev *rtwdev,
 119                             const struct rtw_table *tbl);
 120
 121 #define RTW_DECL_TABLE_DPK(name)                        \
 122 const struct rtw_table name ## _tbl = {                 \
 123         .data = name,                                   \
 124         .size = ARRAY_SIZE(name),                       \
 125         .parse = rtw8822c_parse_tbl_dpk,                \
 126 }
 127
 128 #define DACK_PATH_8822C         2
 129 #define DACK_REG_8822C          16
 130 #define DACK_RF_8822C           1
 131 #define DACK_SN_8822C           100
 132
 133 /* phy status page0 */
 134 #define GET_PHY_STAT_P0_PWDB_A(phy_stat)                                       \
 135         le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
 136 #define GET_PHY_STAT_P0_PWDB_B(phy_stat)                                       \
 137         le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
 138 #define GET_PHY_STAT_P0_GAIN_A(phy_stat)                                       \
 139         le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(21, 16))
 140 #define GET_PHY_STAT_P0_GAIN_B(phy_stat)                                       \
 141         le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(29, 24))
 142
 143 /* phy status page1 */
 144 #define GET_PHY_STAT_P1_PWDB_A(phy_stat)                                       \
 145         le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
 146 #define GET_PHY_STAT_P1_PWDB_B(phy_stat)                                       \
 147         le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
 148 #define GET_PHY_STAT_P1_L_RXSC(phy_stat)                                       \
 149         le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
 150 #define GET_PHY_STAT_P1_HT_RXSC(phy_stat)                                      \
 151         le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
 152
 153 #define REG_ANAPARLDO_POW_MAC   0x0029
 154 #define BIT_LDOE25_PON          BIT(0)
 155 #define REG_RRSR                0x0440
 156 #define BITS_RRSR_RSC           (BIT(21) | BIT(22))
 157
 158 #define REG_TXDFIR0     0x808
 159 #define REG_DFIRBW      0x810
 160 #define REG_ANTMAP0     0x820
 161 #define REG_ANTMAP      0x824
 162 #define REG_DYMPRITH    0x86c
 163 #define REG_DYMENTH0    0x870
 164 #define REG_DYMENTH     0x874
 165 #define REG_SBD         0x88c
 166 #define BITS_SUBTUNE            GENMASK(15, 12)
 167 #define REG_DYMTHMIN    0x8a4
 168 #define REG_TXBWCTL     0x9b0
 169 #define REG_TXCLK       0x9b4
 170 #define REG_SCOTRK      0xc30
 171 #define REG_MRCM        0xc38
 172 #define REG_AGCSWSH     0xc44
 173 #define REG_ANTWTPD     0xc54
 174 #define REG_PT_CHSMO    0xcbc
 175 #define BIT_PT_OPT              BIT(21)
 176 #define REG_ORITXCODE   0x1800
 177 #define REG_3WIRE       0x180c
 178 #define BIT_3WIRE_TX_EN         BIT(0)
 179 #define BIT_3WIRE_RX_EN         BIT(1)
 180 #define BIT_3WIRE_PI_ON         BIT(28)
 181 #define REG_RXAGCCTL0   0x18ac
 182 #define BITS_RXAGC_CCK          GENMASK(15, 12)
 183 #define BITS_RXAGC_OFDM         GENMASK(8, 4)
 184 #define REG_DCKA_I_0    0x18bc
 185 #define REG_DCKA_I_1    0x18c0
 186 #define REG_DCKA_Q_0    0x18d8
 187 #define REG_DCKA_Q_1    0x18dc
 188 #define REG_CCKSB       0x1a00
 189 #define REG_RXCCKSEL    0x1a04
 190 #define REG_BGCTRL      0x1a14
 191 #define BITS_RX_IQ_WEIGHT       (BIT(8) | BIT(9))
 192 #define REG_TXF0        0x1a20
 193 #define REG_TXF1        0x1a24
 194 #define REG_TXF2        0x1a28
 195 #define REG_CCANRX      0x1a2c
 196 #define BIT_CCK_FA_RST          (BIT(14) | BIT(15))
 197 #define BIT_OFDM_FA_RST         (BIT(12) | BIT(13))
 198 #define REG_CCK_FACNT   0x1a5c
 199 #define REG_CCKTXONLY   0x1a80
 200 #define BIT_BB_CCK_CHECK_EN     BIT(18)
 201 #define REG_TXF3        0x1a98
 202 #define REG_TXF4        0x1a9c
 203 #define REG_TXF5        0x1aa0
 204 #define REG_TXF6        0x1aac
 205 #define REG_TXF7        0x1ab0
 206 #define REG_CCK_SOURCE  0x1abc
 207 #define BIT_NBI_EN              BIT(30)
 208 #define REG_IQKSTAT     0x1b10
 209 #define REG_TXANT       0x1c28
 210 #define REG_ENCCK       0x1c3c
 211 #define BIT_CCK_BLK_EN          BIT(1)
 212 #define BIT_CCK_OFDM_BLK_EN     (BIT(0) | BIT(1))
 213 #define REG_CCAMSK      0x1c80
 214 #define REG_RX_BREAK    0x1d2c
 215 #define BIT_COM_RX_GCK_EN       BIT(31)
 216 #define REG_RXFNCTL     0x1d30
 217 #define REG_RXIGI       0x1d70
 218 #define REG_ENFN        0x1e24
 219 #define REG_TXANTSEG    0x1e28
 220 #define REG_TXLGMAP     0x1e2c
 221 #define REG_CCKPATH     0x1e5c
 222 #define REG_CNT_CTRL    0x1eb4
 223 #define BIT_ALL_CNT_RST         BIT(25)
 224 #define REG_OFDM_FACNT  0x2d00
 225 #define REG_OFDM_FACNT1 0x2d04
 226 #define REG_OFDM_FACNT2 0x2d08
 227 #define REG_OFDM_FACNT3 0x2d0c
 228 #define REG_OFDM_FACNT4 0x2d10
 229 #define REG_OFDM_FACNT5 0x2d20
 230 #define REG_RPT_CIP     0x2d9c
 231 #define REG_OFDM_TXCNT  0x2de0
 232 #define REG_ORITXCODE2  0x4100
 233 #define REG_3WIRE2      0x410c
 234 #define REG_RXAGCCTL    0x41ac
 235 #define REG_DCKB_I_0    0x41bc
 236 #define REG_DCKB_I_1    0x41c0
 237 #define REG_DCKB_Q_0    0x41d8
 238 #define REG_DCKB_Q_1    0x41dc
 239
 240 #define RF_MODE_TRXAGC          0x00
 241 #define RF_RXAGC_OFFSET         0x19
 242 #define RF_BW_TRXBB             0x1a
 243 #define RF_TX_GAIN_OFFSET       0x55
 244 #define RF_TX_GAIN              0x56
 245 #define RF_TXA_LB_SW            0x63
 246 #define RF_RXG_GAIN             0x87
 247 #define RF_RXA_MIX_GAIN         0x8a
 248 #define RF_EXT_TIA_BW           0x8f
 249 #define RF_DEBUG                0xde
 250
 251 #define REG_NCTL0               0x1b00
 252 #define REG_DPD_CTL0_S0         0x1b04
 253 #define REG_DPD_CTL1_S0         0x1b08
 254 #define REG_IQK_CTL1            0x1b20
 255 #define REG_DPD_LUT0            0x1b44
 256 #define REG_DPD_CTL0_S1         0x1b5c
 257 #define REG_DPD_LUT3            0x1b60
 258 #define REG_DPD_CTL1_S1         0x1b60
 259 #define REG_DPD_AGC             0x1b67
 260 #define REG_DPD_CTL0            0x1bb4
 261 #define REG_R_CONFIG            0x1bcc
 262 #define REG_RXSRAM_CTL          0x1bd4
 263 #define REG_DPD_CTL11           0x1be4
 264 #define REG_DPD_CTL12           0x1be8
 265 #define REG_DPD_CTL15           0x1bf4
 266 #define REG_DPD_CTL16           0x1bf8
 267 #define REG_STAT_RPT            0x1bfc
 268
 269 #define BIT_EXT_TIA_BW          BIT(1)
 270 #define BIT_DE_TRXBW            BIT(2)
 271 #define BIT_DE_TX_GAIN          BIT(16)
 272 #define BIT_RXG_GAIN            BIT(18)
 273 #define BIT_DE_PWR_TRIM         BIT(19)
 274 #define BIT_INNER_LB            BIT(21)
 275 #define BIT_BYPASS_DPD          BIT(25)
 276 #define BIT_DPD_EN              BIT(31)
 277 #define BIT_SUBPAGE             GENMASK(3, 0)
 278 #define BIT_TXAGC               GENMASK(4, 0)
 279 #define BIT_GAIN_TXBB           GENMASK(4, 0)
 280 #define BIT_LB_ATT              GENMASK(4, 2)
 281 #define BIT_RXA_MIX_GAIN        GENMASK(4, 3)
 282 #define BIT_IQ_SWITCH           GENMASK(5, 0)
 283 #define BIT_DPD_CLK             GENMASK(7, 4)
 284 #define BIT_RXAGC               GENMASK(9, 5)
 285 #define BIT_BW_RXBB             GENMASK(11, 10)
 286 #define BIT_LB_SW               GENMASK(13, 12)
 287 #define BIT_BW_TXBB             GENMASK(14, 12)
 288 #define BIT_GLOSS_DB            GENMASK(14, 12)
 289 #define BIT_TXA_LB_ATT          GENMASK(15, 14)
 290 #define BIT_TX_OFFSET_VAL       GENMASK(18, 14)
 291 #define BIT_RPT_SEL             GENMASK(20, 16)
 292 #define BIT_GS_PWSF             GENMASK(27, 0)
 293 #define BIT_RPT_DGAIN           GENMASK(27, 16)
 294 #define BIT_TX_CFIR             GENMASK(31, 30)
 295 #endif