2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
36 #include "rt2x00pci.h"
37 #include "rt2400pci.h"
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
52 static u32
rt2400pci_bbp_check(struct rt2x00_dev
*rt2x00dev
)
57 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
58 rt2x00pci_register_read(rt2x00dev
, BBPCSR
, ®
);
59 if (!rt2x00_get_field32(reg
, BBPCSR_BUSY
))
61 udelay(REGISTER_BUSY_DELAY
);
67 static void rt2400pci_bbp_write(struct rt2x00_dev
*rt2x00dev
,
68 const unsigned int word
, const u8 value
)
73 * Wait until the BBP becomes ready.
75 reg
= rt2400pci_bbp_check(rt2x00dev
);
76 if (rt2x00_get_field32(reg
, BBPCSR_BUSY
)) {
77 ERROR(rt2x00dev
, "BBPCSR register busy. Write failed.\n");
82 * Write the data into the BBP.
85 rt2x00_set_field32(®
, BBPCSR_VALUE
, value
);
86 rt2x00_set_field32(®
, BBPCSR_REGNUM
, word
);
87 rt2x00_set_field32(®
, BBPCSR_BUSY
, 1);
88 rt2x00_set_field32(®
, BBPCSR_WRITE_CONTROL
, 1);
90 rt2x00pci_register_write(rt2x00dev
, BBPCSR
, reg
);
93 static void rt2400pci_bbp_read(struct rt2x00_dev
*rt2x00dev
,
94 const unsigned int word
, u8
*value
)
99 * Wait until the BBP becomes ready.
101 reg
= rt2400pci_bbp_check(rt2x00dev
);
102 if (rt2x00_get_field32(reg
, BBPCSR_BUSY
)) {
103 ERROR(rt2x00dev
, "BBPCSR register busy. Read failed.\n");
108 * Write the request into the BBP.
111 rt2x00_set_field32(®
, BBPCSR_REGNUM
, word
);
112 rt2x00_set_field32(®
, BBPCSR_BUSY
, 1);
113 rt2x00_set_field32(®
, BBPCSR_WRITE_CONTROL
, 0);
115 rt2x00pci_register_write(rt2x00dev
, BBPCSR
, reg
);
118 * Wait until the BBP becomes ready.
120 reg
= rt2400pci_bbp_check(rt2x00dev
);
121 if (rt2x00_get_field32(reg
, BBPCSR_BUSY
)) {
122 ERROR(rt2x00dev
, "BBPCSR register busy. Read failed.\n");
127 *value
= rt2x00_get_field32(reg
, BBPCSR_VALUE
);
130 static void rt2400pci_rf_write(struct rt2x00_dev
*rt2x00dev
,
131 const unsigned int word
, const u32 value
)
139 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
140 rt2x00pci_register_read(rt2x00dev
, RFCSR
, ®
);
141 if (!rt2x00_get_field32(reg
, RFCSR_BUSY
))
143 udelay(REGISTER_BUSY_DELAY
);
146 ERROR(rt2x00dev
, "RFCSR register busy. Write failed.\n");
151 rt2x00_set_field32(®
, RFCSR_VALUE
, value
);
152 rt2x00_set_field32(®
, RFCSR_NUMBER_OF_BITS
, 20);
153 rt2x00_set_field32(®
, RFCSR_IF_SELECT
, 0);
154 rt2x00_set_field32(®
, RFCSR_BUSY
, 1);
156 rt2x00pci_register_write(rt2x00dev
, RFCSR
, reg
);
157 rt2x00_rf_write(rt2x00dev
, word
, value
);
160 static void rt2400pci_eepromregister_read(struct eeprom_93cx6
*eeprom
)
162 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
165 rt2x00pci_register_read(rt2x00dev
, CSR21
, ®
);
167 eeprom
->reg_data_in
= !!rt2x00_get_field32(reg
, CSR21_EEPROM_DATA_IN
);
168 eeprom
->reg_data_out
= !!rt2x00_get_field32(reg
, CSR21_EEPROM_DATA_OUT
);
169 eeprom
->reg_data_clock
=
170 !!rt2x00_get_field32(reg
, CSR21_EEPROM_DATA_CLOCK
);
171 eeprom
->reg_chip_select
=
172 !!rt2x00_get_field32(reg
, CSR21_EEPROM_CHIP_SELECT
);
175 static void rt2400pci_eepromregister_write(struct eeprom_93cx6
*eeprom
)
177 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
180 rt2x00_set_field32(®
, CSR21_EEPROM_DATA_IN
, !!eeprom
->reg_data_in
);
181 rt2x00_set_field32(®
, CSR21_EEPROM_DATA_OUT
, !!eeprom
->reg_data_out
);
182 rt2x00_set_field32(®
, CSR21_EEPROM_DATA_CLOCK
,
183 !!eeprom
->reg_data_clock
);
184 rt2x00_set_field32(®
, CSR21_EEPROM_CHIP_SELECT
,
185 !!eeprom
->reg_chip_select
);
187 rt2x00pci_register_write(rt2x00dev
, CSR21
, reg
);
190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
191 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
193 static void rt2400pci_read_csr(struct rt2x00_dev
*rt2x00dev
,
194 const unsigned int word
, u32
*data
)
196 rt2x00pci_register_read(rt2x00dev
, CSR_OFFSET(word
), data
);
199 static void rt2400pci_write_csr(struct rt2x00_dev
*rt2x00dev
,
200 const unsigned int word
, u32 data
)
202 rt2x00pci_register_write(rt2x00dev
, CSR_OFFSET(word
), data
);
205 static const struct rt2x00debug rt2400pci_rt2x00debug
= {
206 .owner
= THIS_MODULE
,
208 .read
= rt2400pci_read_csr
,
209 .write
= rt2400pci_write_csr
,
210 .word_size
= sizeof(u32
),
211 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
214 .read
= rt2x00_eeprom_read
,
215 .write
= rt2x00_eeprom_write
,
216 .word_size
= sizeof(u16
),
217 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
220 .read
= rt2400pci_bbp_read
,
221 .write
= rt2400pci_bbp_write
,
222 .word_size
= sizeof(u8
),
223 .word_count
= BBP_SIZE
/ sizeof(u8
),
226 .read
= rt2x00_rf_read
,
227 .write
= rt2400pci_rf_write
,
228 .word_size
= sizeof(u32
),
229 .word_count
= RF_SIZE
/ sizeof(u32
),
232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
234 #ifdef CONFIG_RT2400PCI_RFKILL
235 static int rt2400pci_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
239 rt2x00pci_register_read(rt2x00dev
, GPIOCSR
, ®
);
240 return rt2x00_get_field32(reg
, GPIOCSR_BIT0
);
243 #define rt2400pci_rfkill_poll NULL
244 #endif /* CONFIG_RT2400PCI_RFKILL */
246 #ifdef CONFIG_RT2400PCI_LEDS
247 static void rt2400pci_led_brightness(struct led_classdev
*led_cdev
,
248 enum led_brightness brightness
)
250 struct rt2x00_led
*led
=
251 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
252 unsigned int enabled
= brightness
!= LED_OFF
;
253 unsigned int activity
=
254 led
->rt2x00dev
->led_flags
& LED_SUPPORT_ACTIVITY
;
257 rt2x00pci_register_read(led
->rt2x00dev
, LEDCSR
, ®
);
259 if (led
->type
== LED_TYPE_RADIO
|| led
->type
== LED_TYPE_ASSOC
) {
260 rt2x00_set_field32(®
, LEDCSR_LINK
, enabled
);
261 rt2x00_set_field32(®
, LEDCSR_ACTIVITY
, enabled
&& activity
);
264 rt2x00pci_register_write(led
->rt2x00dev
, LEDCSR
, reg
);
267 #define rt2400pci_led_brightness NULL
268 #endif /* CONFIG_RT2400PCI_LEDS */
271 * Configuration handlers.
273 static void rt2400pci_config_intf(struct rt2x00_dev
*rt2x00dev
,
274 struct rt2x00_intf
*intf
,
275 struct rt2x00intf_conf
*conf
,
276 const unsigned int flags
)
278 unsigned int bcn_preload
;
281 if (flags
& CONFIG_UPDATE_TYPE
) {
283 * Enable beacon config
285 bcn_preload
= PREAMBLE
+ get_duration(IEEE80211_HEADER
, 20);
286 rt2x00pci_register_read(rt2x00dev
, BCNCSR1
, ®
);
287 rt2x00_set_field32(®
, BCNCSR1_PRELOAD
, bcn_preload
);
288 rt2x00pci_register_write(rt2x00dev
, BCNCSR1
, reg
);
291 * Enable synchronisation.
293 rt2x00pci_register_read(rt2x00dev
, CSR14
, ®
);
294 rt2x00_set_field32(®
, CSR14_TSF_COUNT
, 1);
295 rt2x00_set_field32(®
, CSR14_TSF_SYNC
, conf
->sync
);
296 rt2x00_set_field32(®
, CSR14_TBCN
, 1);
297 rt2x00pci_register_write(rt2x00dev
, CSR14
, reg
);
300 if (flags
& CONFIG_UPDATE_MAC
)
301 rt2x00pci_register_multiwrite(rt2x00dev
, CSR3
,
302 conf
->mac
, sizeof(conf
->mac
));
304 if (flags
& CONFIG_UPDATE_BSSID
)
305 rt2x00pci_register_multiwrite(rt2x00dev
, CSR5
,
306 conf
->bssid
, sizeof(conf
->bssid
));
309 static int rt2400pci_config_erp(struct rt2x00_dev
*rt2x00dev
,
310 struct rt2x00lib_erp
*erp
)
316 * When short preamble is enabled, we should set bit 0x08
318 preamble_mask
= erp
->short_preamble
<< 3;
320 rt2x00pci_register_read(rt2x00dev
, TXCSR1
, ®
);
321 rt2x00_set_field32(®
, TXCSR1_ACK_TIMEOUT
,
323 rt2x00_set_field32(®
, TXCSR1_ACK_CONSUME_TIME
,
324 erp
->ack_consume_time
);
325 rt2x00pci_register_write(rt2x00dev
, TXCSR1
, reg
);
327 rt2x00pci_register_read(rt2x00dev
, ARCSR2
, ®
);
328 rt2x00_set_field32(®
, ARCSR2_SIGNAL
, 0x00 | preamble_mask
);
329 rt2x00_set_field32(®
, ARCSR2_SERVICE
, 0x04);
330 rt2x00_set_field32(®
, ARCSR2_LENGTH
, get_duration(ACK_SIZE
, 10));
331 rt2x00pci_register_write(rt2x00dev
, ARCSR2
, reg
);
333 rt2x00pci_register_read(rt2x00dev
, ARCSR3
, ®
);
334 rt2x00_set_field32(®
, ARCSR3_SIGNAL
, 0x01 | preamble_mask
);
335 rt2x00_set_field32(®
, ARCSR3_SERVICE
, 0x04);
336 rt2x00_set_field32(®
, ARCSR2_LENGTH
, get_duration(ACK_SIZE
, 20));
337 rt2x00pci_register_write(rt2x00dev
, ARCSR3
, reg
);
339 rt2x00pci_register_read(rt2x00dev
, ARCSR4
, ®
);
340 rt2x00_set_field32(®
, ARCSR4_SIGNAL
, 0x02 | preamble_mask
);
341 rt2x00_set_field32(®
, ARCSR4_SERVICE
, 0x04);
342 rt2x00_set_field32(®
, ARCSR2_LENGTH
, get_duration(ACK_SIZE
, 55));
343 rt2x00pci_register_write(rt2x00dev
, ARCSR4
, reg
);
345 rt2x00pci_register_read(rt2x00dev
, ARCSR5
, ®
);
346 rt2x00_set_field32(®
, ARCSR5_SIGNAL
, 0x03 | preamble_mask
);
347 rt2x00_set_field32(®
, ARCSR5_SERVICE
, 0x84);
348 rt2x00_set_field32(®
, ARCSR2_LENGTH
, get_duration(ACK_SIZE
, 110));
349 rt2x00pci_register_write(rt2x00dev
, ARCSR5
, reg
);
354 static void rt2400pci_config_phymode(struct rt2x00_dev
*rt2x00dev
,
355 const int basic_rate_mask
)
357 rt2x00pci_register_write(rt2x00dev
, ARCSR1
, basic_rate_mask
);
360 static void rt2400pci_config_channel(struct rt2x00_dev
*rt2x00dev
,
361 struct rf_channel
*rf
)
364 * Switch on tuning bits.
366 rt2x00_set_field32(&rf
->rf1
, RF1_TUNER
, 1);
367 rt2x00_set_field32(&rf
->rf3
, RF3_TUNER
, 1);
369 rt2400pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
370 rt2400pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
371 rt2400pci_rf_write(rt2x00dev
, 3, rf
->rf3
);
374 * RF2420 chipset don't need any additional actions.
376 if (rt2x00_rf(&rt2x00dev
->chip
, RF2420
))
380 * For the RT2421 chipsets we need to write an invalid
381 * reference clock rate to activate auto_tune.
382 * After that we set the value back to the correct channel.
384 rt2400pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
385 rt2400pci_rf_write(rt2x00dev
, 2, 0x000c2a32);
386 rt2400pci_rf_write(rt2x00dev
, 3, rf
->rf3
);
390 rt2400pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
391 rt2400pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
392 rt2400pci_rf_write(rt2x00dev
, 3, rf
->rf3
);
397 * Switch off tuning bits.
399 rt2x00_set_field32(&rf
->rf1
, RF1_TUNER
, 0);
400 rt2x00_set_field32(&rf
->rf3
, RF3_TUNER
, 0);
402 rt2400pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
403 rt2400pci_rf_write(rt2x00dev
, 3, rf
->rf3
);
406 * Clear false CRC during channel switch.
408 rt2x00pci_register_read(rt2x00dev
, CNT0
, &rf
->rf1
);
411 static void rt2400pci_config_txpower(struct rt2x00_dev
*rt2x00dev
, int txpower
)
413 rt2400pci_bbp_write(rt2x00dev
, 3, TXPOWER_TO_DEV(txpower
));
416 static void rt2400pci_config_antenna(struct rt2x00_dev
*rt2x00dev
,
417 struct antenna_setup
*ant
)
423 * We should never come here because rt2x00lib is supposed
424 * to catch this and send us the correct antenna explicitely.
426 BUG_ON(ant
->rx
== ANTENNA_SW_DIVERSITY
||
427 ant
->tx
== ANTENNA_SW_DIVERSITY
);
429 rt2400pci_bbp_read(rt2x00dev
, 4, &r4
);
430 rt2400pci_bbp_read(rt2x00dev
, 1, &r1
);
433 * Configure the TX antenna.
436 case ANTENNA_HW_DIVERSITY
:
437 rt2x00_set_field8(&r1
, BBP_R1_TX_ANTENNA
, 1);
440 rt2x00_set_field8(&r1
, BBP_R1_TX_ANTENNA
, 0);
444 rt2x00_set_field8(&r1
, BBP_R1_TX_ANTENNA
, 2);
449 * Configure the RX antenna.
452 case ANTENNA_HW_DIVERSITY
:
453 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA
, 1);
456 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA
, 0);
460 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA
, 2);
464 rt2400pci_bbp_write(rt2x00dev
, 4, r4
);
465 rt2400pci_bbp_write(rt2x00dev
, 1, r1
);
468 static void rt2400pci_config_duration(struct rt2x00_dev
*rt2x00dev
,
469 struct rt2x00lib_conf
*libconf
)
473 rt2x00pci_register_read(rt2x00dev
, CSR11
, ®
);
474 rt2x00_set_field32(®
, CSR11_SLOT_TIME
, libconf
->slot_time
);
475 rt2x00pci_register_write(rt2x00dev
, CSR11
, reg
);
477 rt2x00pci_register_read(rt2x00dev
, CSR18
, ®
);
478 rt2x00_set_field32(®
, CSR18_SIFS
, libconf
->sifs
);
479 rt2x00_set_field32(®
, CSR18_PIFS
, libconf
->pifs
);
480 rt2x00pci_register_write(rt2x00dev
, CSR18
, reg
);
482 rt2x00pci_register_read(rt2x00dev
, CSR19
, ®
);
483 rt2x00_set_field32(®
, CSR19_DIFS
, libconf
->difs
);
484 rt2x00_set_field32(®
, CSR19_EIFS
, libconf
->eifs
);
485 rt2x00pci_register_write(rt2x00dev
, CSR19
, reg
);
487 rt2x00pci_register_read(rt2x00dev
, TXCSR1
, ®
);
488 rt2x00_set_field32(®
, TXCSR1_TSF_OFFSET
, IEEE80211_HEADER
);
489 rt2x00_set_field32(®
, TXCSR1_AUTORESPONDER
, 1);
490 rt2x00pci_register_write(rt2x00dev
, TXCSR1
, reg
);
492 rt2x00pci_register_read(rt2x00dev
, CSR12
, ®
);
493 rt2x00_set_field32(®
, CSR12_BEACON_INTERVAL
,
494 libconf
->conf
->beacon_int
* 16);
495 rt2x00_set_field32(®
, CSR12_CFP_MAX_DURATION
,
496 libconf
->conf
->beacon_int
* 16);
497 rt2x00pci_register_write(rt2x00dev
, CSR12
, reg
);
500 static void rt2400pci_config(struct rt2x00_dev
*rt2x00dev
,
501 struct rt2x00lib_conf
*libconf
,
502 const unsigned int flags
)
504 if (flags
& CONFIG_UPDATE_PHYMODE
)
505 rt2400pci_config_phymode(rt2x00dev
, libconf
->basic_rates
);
506 if (flags
& CONFIG_UPDATE_CHANNEL
)
507 rt2400pci_config_channel(rt2x00dev
, &libconf
->rf
);
508 if (flags
& CONFIG_UPDATE_TXPOWER
)
509 rt2400pci_config_txpower(rt2x00dev
,
510 libconf
->conf
->power_level
);
511 if (flags
& CONFIG_UPDATE_ANTENNA
)
512 rt2400pci_config_antenna(rt2x00dev
, &libconf
->ant
);
513 if (flags
& (CONFIG_UPDATE_SLOT_TIME
| CONFIG_UPDATE_BEACON_INT
))
514 rt2400pci_config_duration(rt2x00dev
, libconf
);
517 static void rt2400pci_config_cw(struct rt2x00_dev
*rt2x00dev
,
518 const int cw_min
, const int cw_max
)
522 rt2x00pci_register_read(rt2x00dev
, CSR11
, ®
);
523 rt2x00_set_field32(®
, CSR11_CWMIN
, cw_min
);
524 rt2x00_set_field32(®
, CSR11_CWMAX
, cw_max
);
525 rt2x00pci_register_write(rt2x00dev
, CSR11
, reg
);
531 static void rt2400pci_link_stats(struct rt2x00_dev
*rt2x00dev
,
532 struct link_qual
*qual
)
538 * Update FCS error count from register.
540 rt2x00pci_register_read(rt2x00dev
, CNT0
, ®
);
541 qual
->rx_failed
= rt2x00_get_field32(reg
, CNT0_FCS_ERROR
);
544 * Update False CCA count from register.
546 rt2400pci_bbp_read(rt2x00dev
, 39, &bbp
);
547 qual
->false_cca
= bbp
;
550 static void rt2400pci_reset_tuner(struct rt2x00_dev
*rt2x00dev
)
552 rt2400pci_bbp_write(rt2x00dev
, 13, 0x08);
553 rt2x00dev
->link
.vgc_level
= 0x08;
556 static void rt2400pci_link_tuner(struct rt2x00_dev
*rt2x00dev
)
561 * The link tuner should not run longer then 60 seconds,
562 * and should run once every 2 seconds.
564 if (rt2x00dev
->link
.count
> 60 || !(rt2x00dev
->link
.count
& 1))
568 * Base r13 link tuning on the false cca count.
570 rt2400pci_bbp_read(rt2x00dev
, 13, ®
);
572 if (rt2x00dev
->link
.qual
.false_cca
> 512 && reg
< 0x20) {
573 rt2400pci_bbp_write(rt2x00dev
, 13, ++reg
);
574 rt2x00dev
->link
.vgc_level
= reg
;
575 } else if (rt2x00dev
->link
.qual
.false_cca
< 100 && reg
> 0x08) {
576 rt2400pci_bbp_write(rt2x00dev
, 13, --reg
);
577 rt2x00dev
->link
.vgc_level
= reg
;
582 * Initialization functions.
584 static void rt2400pci_init_rxentry(struct rt2x00_dev
*rt2x00dev
,
585 struct queue_entry
*entry
)
587 struct queue_entry_priv_pci_rx
*priv_rx
= entry
->priv_data
;
590 rt2x00_desc_read(priv_rx
->desc
, 2, &word
);
591 rt2x00_set_field32(&word
, RXD_W2_BUFFER_LENGTH
,
592 entry
->queue
->data_size
);
593 rt2x00_desc_write(priv_rx
->desc
, 2, word
);
595 rt2x00_desc_read(priv_rx
->desc
, 1, &word
);
596 rt2x00_set_field32(&word
, RXD_W1_BUFFER_ADDRESS
, priv_rx
->data_dma
);
597 rt2x00_desc_write(priv_rx
->desc
, 1, word
);
599 rt2x00_desc_read(priv_rx
->desc
, 0, &word
);
600 rt2x00_set_field32(&word
, RXD_W0_OWNER_NIC
, 1);
601 rt2x00_desc_write(priv_rx
->desc
, 0, word
);
604 static void rt2400pci_init_txentry(struct rt2x00_dev
*rt2x00dev
,
605 struct queue_entry
*entry
)
607 struct queue_entry_priv_pci_tx
*priv_tx
= entry
->priv_data
;
610 rt2x00_desc_read(priv_tx
->desc
, 1, &word
);
611 rt2x00_set_field32(&word
, TXD_W1_BUFFER_ADDRESS
, priv_tx
->data_dma
);
612 rt2x00_desc_write(priv_tx
->desc
, 1, word
);
614 rt2x00_desc_read(priv_tx
->desc
, 2, &word
);
615 rt2x00_set_field32(&word
, TXD_W2_BUFFER_LENGTH
,
616 entry
->queue
->data_size
);
617 rt2x00_desc_write(priv_tx
->desc
, 2, word
);
619 rt2x00_desc_read(priv_tx
->desc
, 0, &word
);
620 rt2x00_set_field32(&word
, TXD_W0_VALID
, 0);
621 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 0);
622 rt2x00_desc_write(priv_tx
->desc
, 0, word
);
625 static int rt2400pci_init_queues(struct rt2x00_dev
*rt2x00dev
)
627 struct queue_entry_priv_pci_rx
*priv_rx
;
628 struct queue_entry_priv_pci_tx
*priv_tx
;
632 * Initialize registers.
634 rt2x00pci_register_read(rt2x00dev
, TXCSR2
, ®
);
635 rt2x00_set_field32(®
, TXCSR2_TXD_SIZE
, rt2x00dev
->tx
[0].desc_size
);
636 rt2x00_set_field32(®
, TXCSR2_NUM_TXD
, rt2x00dev
->tx
[1].limit
);
637 rt2x00_set_field32(®
, TXCSR2_NUM_ATIM
, rt2x00dev
->bcn
[1].limit
);
638 rt2x00_set_field32(®
, TXCSR2_NUM_PRIO
, rt2x00dev
->tx
[0].limit
);
639 rt2x00pci_register_write(rt2x00dev
, TXCSR2
, reg
);
641 priv_tx
= rt2x00dev
->tx
[1].entries
[0].priv_data
;
642 rt2x00pci_register_read(rt2x00dev
, TXCSR3
, ®
);
643 rt2x00_set_field32(®
, TXCSR3_TX_RING_REGISTER
,
645 rt2x00pci_register_write(rt2x00dev
, TXCSR3
, reg
);
647 priv_tx
= rt2x00dev
->tx
[0].entries
[0].priv_data
;
648 rt2x00pci_register_read(rt2x00dev
, TXCSR5
, ®
);
649 rt2x00_set_field32(®
, TXCSR5_PRIO_RING_REGISTER
,
651 rt2x00pci_register_write(rt2x00dev
, TXCSR5
, reg
);
653 priv_tx
= rt2x00dev
->bcn
[1].entries
[0].priv_data
;
654 rt2x00pci_register_read(rt2x00dev
, TXCSR4
, ®
);
655 rt2x00_set_field32(®
, TXCSR4_ATIM_RING_REGISTER
,
657 rt2x00pci_register_write(rt2x00dev
, TXCSR4
, reg
);
659 priv_tx
= rt2x00dev
->bcn
[0].entries
[0].priv_data
;
660 rt2x00pci_register_read(rt2x00dev
, TXCSR6
, ®
);
661 rt2x00_set_field32(®
, TXCSR6_BEACON_RING_REGISTER
,
663 rt2x00pci_register_write(rt2x00dev
, TXCSR6
, reg
);
665 rt2x00pci_register_read(rt2x00dev
, RXCSR1
, ®
);
666 rt2x00_set_field32(®
, RXCSR1_RXD_SIZE
, rt2x00dev
->rx
->desc_size
);
667 rt2x00_set_field32(®
, RXCSR1_NUM_RXD
, rt2x00dev
->rx
->limit
);
668 rt2x00pci_register_write(rt2x00dev
, RXCSR1
, reg
);
670 priv_rx
= rt2x00dev
->rx
->entries
[0].priv_data
;
671 rt2x00pci_register_read(rt2x00dev
, RXCSR2
, ®
);
672 rt2x00_set_field32(®
, RXCSR2_RX_RING_REGISTER
, priv_rx
->desc_dma
);
673 rt2x00pci_register_write(rt2x00dev
, RXCSR2
, reg
);
678 static int rt2400pci_init_registers(struct rt2x00_dev
*rt2x00dev
)
682 rt2x00pci_register_write(rt2x00dev
, PSCSR0
, 0x00020002);
683 rt2x00pci_register_write(rt2x00dev
, PSCSR1
, 0x00000002);
684 rt2x00pci_register_write(rt2x00dev
, PSCSR2
, 0x00023f20);
685 rt2x00pci_register_write(rt2x00dev
, PSCSR3
, 0x00000002);
687 rt2x00pci_register_read(rt2x00dev
, TIMECSR
, ®
);
688 rt2x00_set_field32(®
, TIMECSR_US_COUNT
, 33);
689 rt2x00_set_field32(®
, TIMECSR_US_64_COUNT
, 63);
690 rt2x00_set_field32(®
, TIMECSR_BEACON_EXPECT
, 0);
691 rt2x00pci_register_write(rt2x00dev
, TIMECSR
, reg
);
693 rt2x00pci_register_read(rt2x00dev
, CSR9
, ®
);
694 rt2x00_set_field32(®
, CSR9_MAX_FRAME_UNIT
,
695 (rt2x00dev
->rx
->data_size
/ 128));
696 rt2x00pci_register_write(rt2x00dev
, CSR9
, reg
);
698 rt2x00pci_register_read(rt2x00dev
, LEDCSR
, ®
);
699 rt2x00_set_field32(®
, LEDCSR_ON_PERIOD
, 70);
700 rt2x00_set_field32(®
, LEDCSR_OFF_PERIOD
, 30);
701 rt2x00pci_register_write(rt2x00dev
, LEDCSR
, reg
);
703 rt2x00pci_register_write(rt2x00dev
, CNT3
, 0x3f080000);
705 rt2x00pci_register_read(rt2x00dev
, ARCSR0
, ®
);
706 rt2x00_set_field32(®
, ARCSR0_AR_BBP_DATA0
, 133);
707 rt2x00_set_field32(®
, ARCSR0_AR_BBP_ID0
, 134);
708 rt2x00_set_field32(®
, ARCSR0_AR_BBP_DATA1
, 136);
709 rt2x00_set_field32(®
, ARCSR0_AR_BBP_ID1
, 135);
710 rt2x00pci_register_write(rt2x00dev
, ARCSR0
, reg
);
712 rt2x00pci_register_read(rt2x00dev
, RXCSR3
, ®
);
713 rt2x00_set_field32(®
, RXCSR3_BBP_ID0
, 3); /* Tx power.*/
714 rt2x00_set_field32(®
, RXCSR3_BBP_ID0_VALID
, 1);
715 rt2x00_set_field32(®
, RXCSR3_BBP_ID1
, 32); /* Signal */
716 rt2x00_set_field32(®
, RXCSR3_BBP_ID1_VALID
, 1);
717 rt2x00_set_field32(®
, RXCSR3_BBP_ID2
, 36); /* Rssi */
718 rt2x00_set_field32(®
, RXCSR3_BBP_ID2_VALID
, 1);
719 rt2x00pci_register_write(rt2x00dev
, RXCSR3
, reg
);
721 rt2x00pci_register_write(rt2x00dev
, PWRCSR0
, 0x3f3b3100);
723 if (rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, STATE_AWAKE
))
726 rt2x00pci_register_write(rt2x00dev
, MACCSR0
, 0x00217223);
727 rt2x00pci_register_write(rt2x00dev
, MACCSR1
, 0x00235518);
729 rt2x00pci_register_read(rt2x00dev
, MACCSR2
, ®
);
730 rt2x00_set_field32(®
, MACCSR2_DELAY
, 64);
731 rt2x00pci_register_write(rt2x00dev
, MACCSR2
, reg
);
733 rt2x00pci_register_read(rt2x00dev
, RALINKCSR
, ®
);
734 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_DATA0
, 17);
735 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_ID0
, 154);
736 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_DATA1
, 0);
737 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_ID1
, 154);
738 rt2x00pci_register_write(rt2x00dev
, RALINKCSR
, reg
);
740 rt2x00pci_register_read(rt2x00dev
, CSR1
, ®
);
741 rt2x00_set_field32(®
, CSR1_SOFT_RESET
, 1);
742 rt2x00_set_field32(®
, CSR1_BBP_RESET
, 0);
743 rt2x00_set_field32(®
, CSR1_HOST_READY
, 0);
744 rt2x00pci_register_write(rt2x00dev
, CSR1
, reg
);
746 rt2x00pci_register_read(rt2x00dev
, CSR1
, ®
);
747 rt2x00_set_field32(®
, CSR1_SOFT_RESET
, 0);
748 rt2x00_set_field32(®
, CSR1_HOST_READY
, 1);
749 rt2x00pci_register_write(rt2x00dev
, CSR1
, reg
);
752 * We must clear the FCS and FIFO error count.
753 * These registers are cleared on read,
754 * so we may pass a useless variable to store the value.
756 rt2x00pci_register_read(rt2x00dev
, CNT0
, ®
);
757 rt2x00pci_register_read(rt2x00dev
, CNT4
, ®
);
762 static int rt2400pci_init_bbp(struct rt2x00_dev
*rt2x00dev
)
769 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
770 rt2400pci_bbp_read(rt2x00dev
, 0, &value
);
771 if ((value
!= 0xff) && (value
!= 0x00))
772 goto continue_csr_init
;
773 NOTICE(rt2x00dev
, "Waiting for BBP register.\n");
774 udelay(REGISTER_BUSY_DELAY
);
777 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
781 rt2400pci_bbp_write(rt2x00dev
, 1, 0x00);
782 rt2400pci_bbp_write(rt2x00dev
, 3, 0x27);
783 rt2400pci_bbp_write(rt2x00dev
, 4, 0x08);
784 rt2400pci_bbp_write(rt2x00dev
, 10, 0x0f);
785 rt2400pci_bbp_write(rt2x00dev
, 15, 0x72);
786 rt2400pci_bbp_write(rt2x00dev
, 16, 0x74);
787 rt2400pci_bbp_write(rt2x00dev
, 17, 0x20);
788 rt2400pci_bbp_write(rt2x00dev
, 18, 0x72);
789 rt2400pci_bbp_write(rt2x00dev
, 19, 0x0b);
790 rt2400pci_bbp_write(rt2x00dev
, 20, 0x00);
791 rt2400pci_bbp_write(rt2x00dev
, 28, 0x11);
792 rt2400pci_bbp_write(rt2x00dev
, 29, 0x04);
793 rt2400pci_bbp_write(rt2x00dev
, 30, 0x21);
794 rt2400pci_bbp_write(rt2x00dev
, 31, 0x00);
796 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
797 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
799 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
800 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
801 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
802 rt2400pci_bbp_write(rt2x00dev
, reg_id
, value
);
810 * Device state switch handlers.
812 static void rt2400pci_toggle_rx(struct rt2x00_dev
*rt2x00dev
,
813 enum dev_state state
)
817 rt2x00pci_register_read(rt2x00dev
, RXCSR0
, ®
);
818 rt2x00_set_field32(®
, RXCSR0_DISABLE_RX
,
819 state
== STATE_RADIO_RX_OFF
);
820 rt2x00pci_register_write(rt2x00dev
, RXCSR0
, reg
);
823 static void rt2400pci_toggle_irq(struct rt2x00_dev
*rt2x00dev
,
824 enum dev_state state
)
826 int mask
= (state
== STATE_RADIO_IRQ_OFF
);
830 * When interrupts are being enabled, the interrupt registers
831 * should clear the register to assure a clean state.
833 if (state
== STATE_RADIO_IRQ_ON
) {
834 rt2x00pci_register_read(rt2x00dev
, CSR7
, ®
);
835 rt2x00pci_register_write(rt2x00dev
, CSR7
, reg
);
839 * Only toggle the interrupts bits we are going to use.
840 * Non-checked interrupt bits are disabled by default.
842 rt2x00pci_register_read(rt2x00dev
, CSR8
, ®
);
843 rt2x00_set_field32(®
, CSR8_TBCN_EXPIRE
, mask
);
844 rt2x00_set_field32(®
, CSR8_TXDONE_TXRING
, mask
);
845 rt2x00_set_field32(®
, CSR8_TXDONE_ATIMRING
, mask
);
846 rt2x00_set_field32(®
, CSR8_TXDONE_PRIORING
, mask
);
847 rt2x00_set_field32(®
, CSR8_RXDONE
, mask
);
848 rt2x00pci_register_write(rt2x00dev
, CSR8
, reg
);
851 static int rt2400pci_enable_radio(struct rt2x00_dev
*rt2x00dev
)
854 * Initialize all registers.
856 if (rt2400pci_init_queues(rt2x00dev
) ||
857 rt2400pci_init_registers(rt2x00dev
) ||
858 rt2400pci_init_bbp(rt2x00dev
)) {
859 ERROR(rt2x00dev
, "Register initialization failed.\n");
866 rt2400pci_toggle_irq(rt2x00dev
, STATE_RADIO_IRQ_ON
);
871 static void rt2400pci_disable_radio(struct rt2x00_dev
*rt2x00dev
)
875 rt2x00pci_register_write(rt2x00dev
, PWRCSR0
, 0);
878 * Disable synchronisation.
880 rt2x00pci_register_write(rt2x00dev
, CSR14
, 0);
885 rt2x00pci_register_read(rt2x00dev
, TXCSR0
, ®
);
886 rt2x00_set_field32(®
, TXCSR0_ABORT
, 1);
887 rt2x00pci_register_write(rt2x00dev
, TXCSR0
, reg
);
890 * Disable interrupts.
892 rt2400pci_toggle_irq(rt2x00dev
, STATE_RADIO_IRQ_OFF
);
895 static int rt2400pci_set_state(struct rt2x00_dev
*rt2x00dev
,
896 enum dev_state state
)
904 put_to_sleep
= (state
!= STATE_AWAKE
);
906 rt2x00pci_register_read(rt2x00dev
, PWRCSR1
, ®
);
907 rt2x00_set_field32(®
, PWRCSR1_SET_STATE
, 1);
908 rt2x00_set_field32(®
, PWRCSR1_BBP_DESIRE_STATE
, state
);
909 rt2x00_set_field32(®
, PWRCSR1_RF_DESIRE_STATE
, state
);
910 rt2x00_set_field32(®
, PWRCSR1_PUT_TO_SLEEP
, put_to_sleep
);
911 rt2x00pci_register_write(rt2x00dev
, PWRCSR1
, reg
);
914 * Device is not guaranteed to be in the requested state yet.
915 * We must wait until the register indicates that the
916 * device has entered the correct state.
918 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
919 rt2x00pci_register_read(rt2x00dev
, PWRCSR1
, ®
);
920 bbp_state
= rt2x00_get_field32(reg
, PWRCSR1_BBP_CURR_STATE
);
921 rf_state
= rt2x00_get_field32(reg
, PWRCSR1_RF_CURR_STATE
);
922 if (bbp_state
== state
&& rf_state
== state
)
927 NOTICE(rt2x00dev
, "Device failed to enter state %d, "
928 "current device state: bbp %d and rf %d.\n",
929 state
, bbp_state
, rf_state
);
934 static int rt2400pci_set_device_state(struct rt2x00_dev
*rt2x00dev
,
935 enum dev_state state
)
941 retval
= rt2400pci_enable_radio(rt2x00dev
);
943 case STATE_RADIO_OFF
:
944 rt2400pci_disable_radio(rt2x00dev
);
946 case STATE_RADIO_RX_ON
:
947 case STATE_RADIO_RX_ON_LINK
:
948 rt2400pci_toggle_rx(rt2x00dev
, STATE_RADIO_RX_ON
);
950 case STATE_RADIO_RX_OFF
:
951 case STATE_RADIO_RX_OFF_LINK
:
952 rt2400pci_toggle_rx(rt2x00dev
, STATE_RADIO_RX_OFF
);
954 case STATE_DEEP_SLEEP
:
958 retval
= rt2400pci_set_state(rt2x00dev
, state
);
969 * TX descriptor initialization
971 static void rt2400pci_write_tx_desc(struct rt2x00_dev
*rt2x00dev
,
973 struct txentry_desc
*txdesc
,
974 struct ieee80211_tx_control
*control
)
976 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(skb
);
977 __le32
*txd
= skbdesc
->desc
;
981 * Start writing the descriptor words.
983 rt2x00_desc_read(txd
, 2, &word
);
984 rt2x00_set_field32(&word
, TXD_W2_DATABYTE_COUNT
, skbdesc
->data_len
);
985 rt2x00_desc_write(txd
, 2, word
);
987 rt2x00_desc_read(txd
, 3, &word
);
988 rt2x00_set_field32(&word
, TXD_W3_PLCP_SIGNAL
, txdesc
->signal
);
989 rt2x00_set_field32(&word
, TXD_W3_PLCP_SIGNAL_REGNUM
, 5);
990 rt2x00_set_field32(&word
, TXD_W3_PLCP_SIGNAL_BUSY
, 1);
991 rt2x00_set_field32(&word
, TXD_W3_PLCP_SERVICE
, txdesc
->service
);
992 rt2x00_set_field32(&word
, TXD_W3_PLCP_SERVICE_REGNUM
, 6);
993 rt2x00_set_field32(&word
, TXD_W3_PLCP_SERVICE_BUSY
, 1);
994 rt2x00_desc_write(txd
, 3, word
);
996 rt2x00_desc_read(txd
, 4, &word
);
997 rt2x00_set_field32(&word
, TXD_W4_PLCP_LENGTH_LOW
, txdesc
->length_low
);
998 rt2x00_set_field32(&word
, TXD_W3_PLCP_LENGTH_LOW_REGNUM
, 8);
999 rt2x00_set_field32(&word
, TXD_W3_PLCP_LENGTH_LOW_BUSY
, 1);
1000 rt2x00_set_field32(&word
, TXD_W4_PLCP_LENGTH_HIGH
, txdesc
->length_high
);
1001 rt2x00_set_field32(&word
, TXD_W3_PLCP_LENGTH_HIGH_REGNUM
, 7);
1002 rt2x00_set_field32(&word
, TXD_W3_PLCP_LENGTH_HIGH_BUSY
, 1);
1003 rt2x00_desc_write(txd
, 4, word
);
1005 rt2x00_desc_read(txd
, 0, &word
);
1006 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 1);
1007 rt2x00_set_field32(&word
, TXD_W0_VALID
, 1);
1008 rt2x00_set_field32(&word
, TXD_W0_MORE_FRAG
,
1009 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
1010 rt2x00_set_field32(&word
, TXD_W0_ACK
,
1011 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
1012 rt2x00_set_field32(&word
, TXD_W0_TIMESTAMP
,
1013 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
1014 rt2x00_set_field32(&word
, TXD_W0_RTS
,
1015 test_bit(ENTRY_TXD_RTS_FRAME
, &txdesc
->flags
));
1016 rt2x00_set_field32(&word
, TXD_W0_IFS
, txdesc
->ifs
);
1017 rt2x00_set_field32(&word
, TXD_W0_RETRY_MODE
,
1019 IEEE80211_TXCTL_LONG_RETRY_LIMIT
));
1020 rt2x00_desc_write(txd
, 0, word
);
1024 * TX data initialization
1026 static void rt2400pci_kick_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1027 const unsigned int queue
)
1031 if (queue
== RT2X00_BCN_QUEUE_BEACON
) {
1032 rt2x00pci_register_read(rt2x00dev
, CSR14
, ®
);
1033 if (!rt2x00_get_field32(reg
, CSR14_BEACON_GEN
)) {
1034 rt2x00_set_field32(®
, CSR14_TSF_COUNT
, 1);
1035 rt2x00_set_field32(®
, CSR14_TBCN
, 1);
1036 rt2x00_set_field32(®
, CSR14_BEACON_GEN
, 1);
1037 rt2x00pci_register_write(rt2x00dev
, CSR14
, reg
);
1042 rt2x00pci_register_read(rt2x00dev
, TXCSR0
, ®
);
1043 rt2x00_set_field32(®
, TXCSR0_KICK_PRIO
,
1044 (queue
== IEEE80211_TX_QUEUE_DATA0
));
1045 rt2x00_set_field32(®
, TXCSR0_KICK_TX
,
1046 (queue
== IEEE80211_TX_QUEUE_DATA1
));
1047 rt2x00_set_field32(®
, TXCSR0_KICK_ATIM
,
1048 (queue
== RT2X00_BCN_QUEUE_ATIM
));
1049 rt2x00pci_register_write(rt2x00dev
, TXCSR0
, reg
);
1053 * RX control handlers
1055 static void rt2400pci_fill_rxdone(struct queue_entry
*entry
,
1056 struct rxdone_entry_desc
*rxdesc
)
1058 struct queue_entry_priv_pci_rx
*priv_rx
= entry
->priv_data
;
1063 rt2x00_desc_read(priv_rx
->desc
, 0, &word0
);
1064 rt2x00_desc_read(priv_rx
->desc
, 2, &word2
);
1065 rt2x00_desc_read(priv_rx
->desc
, 3, &word3
);
1068 if (rt2x00_get_field32(word0
, RXD_W0_CRC_ERROR
))
1069 rxdesc
->flags
|= RX_FLAG_FAILED_FCS_CRC
;
1070 if (rt2x00_get_field32(word0
, RXD_W0_PHYSICAL_ERROR
))
1071 rxdesc
->flags
|= RX_FLAG_FAILED_PLCP_CRC
;
1074 * Obtain the status about this packet.
1075 * The signal is the PLCP value, and needs to be stripped
1076 * of the preamble bit (0x08).
1078 rxdesc
->signal
= rt2x00_get_field32(word2
, RXD_W2_SIGNAL
) & ~0x08;
1079 rxdesc
->rssi
= rt2x00_get_field32(word2
, RXD_W3_RSSI
) -
1080 entry
->queue
->rt2x00dev
->rssi_offset
;
1081 rxdesc
->size
= rt2x00_get_field32(word0
, RXD_W0_DATABYTE_COUNT
);
1083 rxdesc
->dev_flags
= RXDONE_SIGNAL_PLCP
;
1084 if (rt2x00_get_field32(word0
, RXD_W0_MY_BSS
))
1085 rxdesc
->dev_flags
|= RXDONE_MY_BSS
;
1089 * Interrupt functions.
1091 static void rt2400pci_txdone(struct rt2x00_dev
*rt2x00dev
,
1092 const enum ieee80211_tx_queue queue_idx
)
1094 struct data_queue
*queue
= rt2x00queue_get_queue(rt2x00dev
, queue_idx
);
1095 struct queue_entry_priv_pci_tx
*priv_tx
;
1096 struct queue_entry
*entry
;
1097 struct txdone_entry_desc txdesc
;
1100 while (!rt2x00queue_empty(queue
)) {
1101 entry
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
1102 priv_tx
= entry
->priv_data
;
1103 rt2x00_desc_read(priv_tx
->desc
, 0, &word
);
1105 if (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
1106 !rt2x00_get_field32(word
, TXD_W0_VALID
))
1110 * Obtain the status about this packet.
1112 txdesc
.status
= rt2x00_get_field32(word
, TXD_W0_RESULT
);
1113 txdesc
.retry
= rt2x00_get_field32(word
, TXD_W0_RETRY_COUNT
);
1115 rt2x00pci_txdone(rt2x00dev
, entry
, &txdesc
);
1119 static irqreturn_t
rt2400pci_interrupt(int irq
, void *dev_instance
)
1121 struct rt2x00_dev
*rt2x00dev
= dev_instance
;
1125 * Get the interrupt sources & saved to local variable.
1126 * Write register value back to clear pending interrupts.
1128 rt2x00pci_register_read(rt2x00dev
, CSR7
, ®
);
1129 rt2x00pci_register_write(rt2x00dev
, CSR7
, reg
);
1134 if (!test_bit(DEVICE_ENABLED_RADIO
, &rt2x00dev
->flags
))
1138 * Handle interrupts, walk through all bits
1139 * and run the tasks, the bits are checked in order of
1144 * 1 - Beacon timer expired interrupt.
1146 if (rt2x00_get_field32(reg
, CSR7_TBCN_EXPIRE
))
1147 rt2x00lib_beacondone(rt2x00dev
);
1150 * 2 - Rx ring done interrupt.
1152 if (rt2x00_get_field32(reg
, CSR7_RXDONE
))
1153 rt2x00pci_rxdone(rt2x00dev
);
1156 * 3 - Atim ring transmit done interrupt.
1158 if (rt2x00_get_field32(reg
, CSR7_TXDONE_ATIMRING
))
1159 rt2400pci_txdone(rt2x00dev
, RT2X00_BCN_QUEUE_ATIM
);
1162 * 4 - Priority ring transmit done interrupt.
1164 if (rt2x00_get_field32(reg
, CSR7_TXDONE_PRIORING
))
1165 rt2400pci_txdone(rt2x00dev
, IEEE80211_TX_QUEUE_DATA0
);
1168 * 5 - Tx ring transmit done interrupt.
1170 if (rt2x00_get_field32(reg
, CSR7_TXDONE_TXRING
))
1171 rt2400pci_txdone(rt2x00dev
, IEEE80211_TX_QUEUE_DATA1
);
1177 * Device probe functions.
1179 static int rt2400pci_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
1181 struct eeprom_93cx6 eeprom
;
1186 rt2x00pci_register_read(rt2x00dev
, CSR21
, ®
);
1188 eeprom
.data
= rt2x00dev
;
1189 eeprom
.register_read
= rt2400pci_eepromregister_read
;
1190 eeprom
.register_write
= rt2400pci_eepromregister_write
;
1191 eeprom
.width
= rt2x00_get_field32(reg
, CSR21_TYPE_93C46
) ?
1192 PCI_EEPROM_WIDTH_93C46
: PCI_EEPROM_WIDTH_93C66
;
1193 eeprom
.reg_data_in
= 0;
1194 eeprom
.reg_data_out
= 0;
1195 eeprom
.reg_data_clock
= 0;
1196 eeprom
.reg_chip_select
= 0;
1198 eeprom_93cx6_multiread(&eeprom
, EEPROM_BASE
, rt2x00dev
->eeprom
,
1199 EEPROM_SIZE
/ sizeof(u16
));
1202 * Start validation of the data that has been read.
1204 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
1205 if (!is_valid_ether_addr(mac
)) {
1206 DECLARE_MAC_BUF(macbuf
);
1208 random_ether_addr(mac
);
1209 EEPROM(rt2x00dev
, "MAC: %s\n", print_mac(macbuf
, mac
));
1212 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
1213 if (word
== 0xffff) {
1214 ERROR(rt2x00dev
, "Invalid EEPROM data detected.\n");
1221 static int rt2400pci_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
1228 * Read EEPROM word for configuration.
1230 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
1233 * Identify RF chipset.
1235 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
1236 rt2x00pci_register_read(rt2x00dev
, CSR0
, ®
);
1237 rt2x00_set_chip(rt2x00dev
, RT2460
, value
, reg
);
1239 if (!rt2x00_rf(&rt2x00dev
->chip
, RF2420
) &&
1240 !rt2x00_rf(&rt2x00dev
->chip
, RF2421
)) {
1241 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
1246 * Identify default antenna configuration.
1248 rt2x00dev
->default_ant
.tx
=
1249 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TX_DEFAULT
);
1250 rt2x00dev
->default_ant
.rx
=
1251 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RX_DEFAULT
);
1254 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1255 * I am not 100% sure about this, but the legacy drivers do not
1256 * indicate antenna swapping in software is required when
1257 * diversity is enabled.
1259 if (rt2x00dev
->default_ant
.tx
== ANTENNA_SW_DIVERSITY
)
1260 rt2x00dev
->default_ant
.tx
= ANTENNA_HW_DIVERSITY
;
1261 if (rt2x00dev
->default_ant
.rx
== ANTENNA_SW_DIVERSITY
)
1262 rt2x00dev
->default_ant
.rx
= ANTENNA_HW_DIVERSITY
;
1265 * Store led mode, for correct led behaviour.
1267 #ifdef CONFIG_RT2400PCI_LEDS
1268 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_LED_MODE
);
1272 case LED_MODE_ALPHA
:
1273 case LED_MODE_DEFAULT
:
1274 rt2x00dev
->led_flags
= LED_SUPPORT_RADIO
;
1276 case LED_MODE_TXRX_ACTIVITY
:
1277 rt2x00dev
->led_flags
=
1278 LED_SUPPORT_RADIO
| LED_SUPPORT_ACTIVITY
;
1280 case LED_MODE_SIGNAL_STRENGTH
:
1281 rt2x00dev
->led_flags
= LED_SUPPORT_RADIO
;
1284 #endif /* CONFIG_RT2400PCI_LEDS */
1287 * Detect if this device has an hardware controlled radio.
1289 #ifdef CONFIG_RT2400PCI_RFKILL
1290 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_HARDWARE_RADIO
))
1291 __set_bit(CONFIG_SUPPORT_HW_BUTTON
, &rt2x00dev
->flags
);
1292 #endif /* CONFIG_RT2400PCI_RFKILL */
1295 * Check if the BBP tuning should be enabled.
1297 if (!rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RX_AGCVGC_TUNING
))
1298 __set_bit(CONFIG_DISABLE_LINK_TUNING
, &rt2x00dev
->flags
);
1304 * RF value list for RF2420 & RF2421
1307 static const struct rf_channel rf_vals_bg
[] = {
1308 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1309 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1310 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1311 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1312 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1313 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1314 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1315 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1316 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1317 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1318 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1319 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1320 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1321 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1324 static void rt2400pci_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
1326 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
1331 * Initialize all hw fields.
1333 rt2x00dev
->hw
->flags
= IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
;
1334 rt2x00dev
->hw
->extra_tx_headroom
= 0;
1335 rt2x00dev
->hw
->max_signal
= MAX_SIGNAL
;
1336 rt2x00dev
->hw
->max_rssi
= MAX_RX_SSI
;
1337 rt2x00dev
->hw
->queues
= 2;
1339 SET_IEEE80211_DEV(rt2x00dev
->hw
, &rt2x00dev_pci(rt2x00dev
)->dev
);
1340 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
1341 rt2x00_eeprom_addr(rt2x00dev
,
1342 EEPROM_MAC_ADDR_0
));
1345 * Convert tx_power array in eeprom.
1347 txpower
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_START
);
1348 for (i
= 0; i
< 14; i
++)
1349 txpower
[i
] = TXPOWER_FROM_DEV(txpower
[i
]);
1352 * Initialize hw_mode information.
1354 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
1355 spec
->supported_rates
= SUPPORT_RATE_CCK
;
1356 spec
->tx_power_a
= NULL
;
1357 spec
->tx_power_bg
= txpower
;
1358 spec
->tx_power_default
= DEFAULT_TXPOWER
;
1360 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg
);
1361 spec
->channels
= rf_vals_bg
;
1364 static int rt2400pci_probe_hw(struct rt2x00_dev
*rt2x00dev
)
1369 * Allocate eeprom data.
1371 retval
= rt2400pci_validate_eeprom(rt2x00dev
);
1375 retval
= rt2400pci_init_eeprom(rt2x00dev
);
1380 * Initialize hw specifications.
1382 rt2400pci_probe_hw_mode(rt2x00dev
);
1385 * This device requires the atim queue
1387 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE
, &rt2x00dev
->flags
);
1390 * Set the rssi offset.
1392 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
1398 * IEEE80211 stack callback functions.
1400 static void rt2400pci_configure_filter(struct ieee80211_hw
*hw
,
1401 unsigned int changed_flags
,
1402 unsigned int *total_flags
,
1404 struct dev_addr_list
*mc_list
)
1406 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1410 * Mask off any flags we are going to ignore from
1411 * the total_flags field.
1422 * Apply some rules to the filters:
1423 * - Some filters imply different filters to be set.
1424 * - Some things we can't filter out at all.
1426 *total_flags
|= FIF_ALLMULTI
;
1427 if (*total_flags
& FIF_OTHER_BSS
||
1428 *total_flags
& FIF_PROMISC_IN_BSS
)
1429 *total_flags
|= FIF_PROMISC_IN_BSS
| FIF_OTHER_BSS
;
1432 * Check if there is any work left for us.
1434 if (rt2x00dev
->packet_filter
== *total_flags
)
1436 rt2x00dev
->packet_filter
= *total_flags
;
1439 * Start configuration steps.
1440 * Note that the version error will always be dropped
1441 * since there is no filter for it at this time.
1443 rt2x00pci_register_read(rt2x00dev
, RXCSR0
, ®
);
1444 rt2x00_set_field32(®
, RXCSR0_DROP_CRC
,
1445 !(*total_flags
& FIF_FCSFAIL
));
1446 rt2x00_set_field32(®
, RXCSR0_DROP_PHYSICAL
,
1447 !(*total_flags
& FIF_PLCPFAIL
));
1448 rt2x00_set_field32(®
, RXCSR0_DROP_CONTROL
,
1449 !(*total_flags
& FIF_CONTROL
));
1450 rt2x00_set_field32(®
, RXCSR0_DROP_NOT_TO_ME
,
1451 !(*total_flags
& FIF_PROMISC_IN_BSS
));
1452 rt2x00_set_field32(®
, RXCSR0_DROP_TODS
,
1453 !(*total_flags
& FIF_PROMISC_IN_BSS
));
1454 rt2x00_set_field32(®
, RXCSR0_DROP_VERSION_ERROR
, 1);
1455 rt2x00pci_register_write(rt2x00dev
, RXCSR0
, reg
);
1458 static int rt2400pci_set_retry_limit(struct ieee80211_hw
*hw
,
1459 u32 short_retry
, u32 long_retry
)
1461 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1464 rt2x00pci_register_read(rt2x00dev
, CSR11
, ®
);
1465 rt2x00_set_field32(®
, CSR11_LONG_RETRY
, long_retry
);
1466 rt2x00_set_field32(®
, CSR11_SHORT_RETRY
, short_retry
);
1467 rt2x00pci_register_write(rt2x00dev
, CSR11
, reg
);
1472 static int rt2400pci_conf_tx(struct ieee80211_hw
*hw
,
1474 const struct ieee80211_tx_queue_params
*params
)
1476 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1479 * We don't support variating cw_min and cw_max variables
1480 * per queue. So by default we only configure the TX queue,
1481 * and ignore all other configurations.
1483 if (queue
!= IEEE80211_TX_QUEUE_DATA0
)
1486 if (rt2x00mac_conf_tx(hw
, queue
, params
))
1490 * Write configuration to register.
1492 rt2400pci_config_cw(rt2x00dev
,
1493 rt2x00dev
->tx
->cw_min
, rt2x00dev
->tx
->cw_max
);
1498 static u64
rt2400pci_get_tsf(struct ieee80211_hw
*hw
)
1500 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1504 rt2x00pci_register_read(rt2x00dev
, CSR17
, ®
);
1505 tsf
= (u64
) rt2x00_get_field32(reg
, CSR17_HIGH_TSFTIMER
) << 32;
1506 rt2x00pci_register_read(rt2x00dev
, CSR16
, ®
);
1507 tsf
|= rt2x00_get_field32(reg
, CSR16_LOW_TSFTIMER
);
1512 static int rt2400pci_beacon_update(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
1513 struct ieee80211_tx_control
*control
)
1515 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1516 struct rt2x00_intf
*intf
= vif_to_intf(control
->vif
);
1517 struct queue_entry_priv_pci_tx
*priv_tx
;
1518 struct skb_frame_desc
*skbdesc
;
1521 if (unlikely(!intf
->beacon
))
1523 priv_tx
= intf
->beacon
->priv_data
;
1526 * Fill in skb descriptor
1528 skbdesc
= get_skb_frame_desc(skb
);
1529 memset(skbdesc
, 0, sizeof(*skbdesc
));
1530 skbdesc
->flags
|= FRAME_DESC_DRIVER_GENERATED
;
1531 skbdesc
->data
= skb
->data
;
1532 skbdesc
->data_len
= skb
->len
;
1533 skbdesc
->desc
= priv_tx
->desc
;
1534 skbdesc
->desc_len
= intf
->beacon
->queue
->desc_size
;
1535 skbdesc
->entry
= intf
->beacon
;
1538 * Disable beaconing while we are reloading the beacon data,
1539 * otherwise we might be sending out invalid data.
1541 rt2x00pci_register_read(rt2x00dev
, CSR14
, ®
);
1542 rt2x00_set_field32(®
, CSR14_TSF_COUNT
, 0);
1543 rt2x00_set_field32(®
, CSR14_TBCN
, 0);
1544 rt2x00_set_field32(®
, CSR14_BEACON_GEN
, 0);
1545 rt2x00pci_register_write(rt2x00dev
, CSR14
, reg
);
1548 * mac80211 doesn't provide the control->queue variable
1549 * for beacons. Set our own queue identification so
1550 * it can be used during descriptor initialization.
1552 control
->queue
= RT2X00_BCN_QUEUE_BEACON
;
1553 rt2x00lib_write_tx_desc(rt2x00dev
, skb
, control
);
1556 * Enable beacon generation.
1557 * Write entire beacon with descriptor to register,
1558 * and kick the beacon generator.
1560 memcpy(priv_tx
->data
, skb
->data
, skb
->len
);
1561 rt2x00dev
->ops
->lib
->kick_tx_queue(rt2x00dev
, control
->queue
);
1566 static int rt2400pci_tx_last_beacon(struct ieee80211_hw
*hw
)
1568 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1571 rt2x00pci_register_read(rt2x00dev
, CSR15
, ®
);
1572 return rt2x00_get_field32(reg
, CSR15_BEACON_SENT
);
1575 static const struct ieee80211_ops rt2400pci_mac80211_ops
= {
1577 .start
= rt2x00mac_start
,
1578 .stop
= rt2x00mac_stop
,
1579 .add_interface
= rt2x00mac_add_interface
,
1580 .remove_interface
= rt2x00mac_remove_interface
,
1581 .config
= rt2x00mac_config
,
1582 .config_interface
= rt2x00mac_config_interface
,
1583 .configure_filter
= rt2400pci_configure_filter
,
1584 .get_stats
= rt2x00mac_get_stats
,
1585 .set_retry_limit
= rt2400pci_set_retry_limit
,
1586 .bss_info_changed
= rt2x00mac_bss_info_changed
,
1587 .conf_tx
= rt2400pci_conf_tx
,
1588 .get_tx_stats
= rt2x00mac_get_tx_stats
,
1589 .get_tsf
= rt2400pci_get_tsf
,
1590 .beacon_update
= rt2400pci_beacon_update
,
1591 .tx_last_beacon
= rt2400pci_tx_last_beacon
,
1594 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops
= {
1595 .irq_handler
= rt2400pci_interrupt
,
1596 .probe_hw
= rt2400pci_probe_hw
,
1597 .initialize
= rt2x00pci_initialize
,
1598 .uninitialize
= rt2x00pci_uninitialize
,
1599 .init_rxentry
= rt2400pci_init_rxentry
,
1600 .init_txentry
= rt2400pci_init_txentry
,
1601 .set_device_state
= rt2400pci_set_device_state
,
1602 .rfkill_poll
= rt2400pci_rfkill_poll
,
1603 .link_stats
= rt2400pci_link_stats
,
1604 .reset_tuner
= rt2400pci_reset_tuner
,
1605 .link_tuner
= rt2400pci_link_tuner
,
1606 .led_brightness
= rt2400pci_led_brightness
,
1607 .write_tx_desc
= rt2400pci_write_tx_desc
,
1608 .write_tx_data
= rt2x00pci_write_tx_data
,
1609 .kick_tx_queue
= rt2400pci_kick_tx_queue
,
1610 .fill_rxdone
= rt2400pci_fill_rxdone
,
1611 .config_intf
= rt2400pci_config_intf
,
1612 .config_erp
= rt2400pci_config_erp
,
1613 .config
= rt2400pci_config
,
1616 static const struct data_queue_desc rt2400pci_queue_rx
= {
1617 .entry_num
= RX_ENTRIES
,
1618 .data_size
= DATA_FRAME_SIZE
,
1619 .desc_size
= RXD_DESC_SIZE
,
1620 .priv_size
= sizeof(struct queue_entry_priv_pci_rx
),
1623 static const struct data_queue_desc rt2400pci_queue_tx
= {
1624 .entry_num
= TX_ENTRIES
,
1625 .data_size
= DATA_FRAME_SIZE
,
1626 .desc_size
= TXD_DESC_SIZE
,
1627 .priv_size
= sizeof(struct queue_entry_priv_pci_tx
),
1630 static const struct data_queue_desc rt2400pci_queue_bcn
= {
1631 .entry_num
= BEACON_ENTRIES
,
1632 .data_size
= MGMT_FRAME_SIZE
,
1633 .desc_size
= TXD_DESC_SIZE
,
1634 .priv_size
= sizeof(struct queue_entry_priv_pci_tx
),
1637 static const struct data_queue_desc rt2400pci_queue_atim
= {
1638 .entry_num
= ATIM_ENTRIES
,
1639 .data_size
= DATA_FRAME_SIZE
,
1640 .desc_size
= TXD_DESC_SIZE
,
1641 .priv_size
= sizeof(struct queue_entry_priv_pci_tx
),
1644 static const struct rt2x00_ops rt2400pci_ops
= {
1645 .name
= KBUILD_MODNAME
,
1648 .eeprom_size
= EEPROM_SIZE
,
1650 .rx
= &rt2400pci_queue_rx
,
1651 .tx
= &rt2400pci_queue_tx
,
1652 .bcn
= &rt2400pci_queue_bcn
,
1653 .atim
= &rt2400pci_queue_atim
,
1654 .lib
= &rt2400pci_rt2x00_ops
,
1655 .hw
= &rt2400pci_mac80211_ops
,
1656 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1657 .debugfs
= &rt2400pci_rt2x00debug
,
1658 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1662 * RT2400pci module information.
1664 static struct pci_device_id rt2400pci_device_table
[] = {
1665 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops
) },
1669 MODULE_AUTHOR(DRV_PROJECT
);
1670 MODULE_VERSION(DRV_VERSION
);
1671 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1672 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1673 MODULE_DEVICE_TABLE(pci
, rt2400pci_device_table
);
1674 MODULE_LICENSE("GPL");
1676 static struct pci_driver rt2400pci_driver
= {
1677 .name
= KBUILD_MODNAME
,
1678 .id_table
= rt2400pci_device_table
,
1679 .probe
= rt2x00pci_probe
,
1680 .remove
= __devexit_p(rt2x00pci_remove
),
1681 .suspend
= rt2x00pci_suspend
,
1682 .resume
= rt2x00pci_resume
,
1685 static int __init
rt2400pci_init(void)
1687 return pci_register_driver(&rt2400pci_driver
);
1690 static void __exit
rt2400pci_exit(void)
1692 pci_unregister_driver(&rt2400pci_driver
);
1695 module_init(rt2400pci_init
);
1696 module_exit(rt2400pci_exit
);