2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
36 #include "rt2x00pci.h"
37 #include "rt2400pci.h"
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
52 static u32
rt2400pci_bbp_check(struct rt2x00_dev
*rt2x00dev
)
57 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
58 rt2x00pci_register_read(rt2x00dev
, BBPCSR
, ®
);
59 if (!rt2x00_get_field32(reg
, BBPCSR_BUSY
))
61 udelay(REGISTER_BUSY_DELAY
);
67 static void rt2400pci_bbp_write(struct rt2x00_dev
*rt2x00dev
,
68 const unsigned int word
, const u8 value
)
73 * Wait until the BBP becomes ready.
75 reg
= rt2400pci_bbp_check(rt2x00dev
);
76 if (rt2x00_get_field32(reg
, BBPCSR_BUSY
)) {
77 ERROR(rt2x00dev
, "BBPCSR register busy. Write failed.\n");
82 * Write the data into the BBP.
85 rt2x00_set_field32(®
, BBPCSR_VALUE
, value
);
86 rt2x00_set_field32(®
, BBPCSR_REGNUM
, word
);
87 rt2x00_set_field32(®
, BBPCSR_BUSY
, 1);
88 rt2x00_set_field32(®
, BBPCSR_WRITE_CONTROL
, 1);
90 rt2x00pci_register_write(rt2x00dev
, BBPCSR
, reg
);
93 static void rt2400pci_bbp_read(struct rt2x00_dev
*rt2x00dev
,
94 const unsigned int word
, u8
*value
)
99 * Wait until the BBP becomes ready.
101 reg
= rt2400pci_bbp_check(rt2x00dev
);
102 if (rt2x00_get_field32(reg
, BBPCSR_BUSY
)) {
103 ERROR(rt2x00dev
, "BBPCSR register busy. Read failed.\n");
108 * Write the request into the BBP.
111 rt2x00_set_field32(®
, BBPCSR_REGNUM
, word
);
112 rt2x00_set_field32(®
, BBPCSR_BUSY
, 1);
113 rt2x00_set_field32(®
, BBPCSR_WRITE_CONTROL
, 0);
115 rt2x00pci_register_write(rt2x00dev
, BBPCSR
, reg
);
118 * Wait until the BBP becomes ready.
120 reg
= rt2400pci_bbp_check(rt2x00dev
);
121 if (rt2x00_get_field32(reg
, BBPCSR_BUSY
)) {
122 ERROR(rt2x00dev
, "BBPCSR register busy. Read failed.\n");
127 *value
= rt2x00_get_field32(reg
, BBPCSR_VALUE
);
130 static void rt2400pci_rf_write(struct rt2x00_dev
*rt2x00dev
,
131 const unsigned int word
, const u32 value
)
139 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
140 rt2x00pci_register_read(rt2x00dev
, RFCSR
, ®
);
141 if (!rt2x00_get_field32(reg
, RFCSR_BUSY
))
143 udelay(REGISTER_BUSY_DELAY
);
146 ERROR(rt2x00dev
, "RFCSR register busy. Write failed.\n");
151 rt2x00_set_field32(®
, RFCSR_VALUE
, value
);
152 rt2x00_set_field32(®
, RFCSR_NUMBER_OF_BITS
, 20);
153 rt2x00_set_field32(®
, RFCSR_IF_SELECT
, 0);
154 rt2x00_set_field32(®
, RFCSR_BUSY
, 1);
156 rt2x00pci_register_write(rt2x00dev
, RFCSR
, reg
);
157 rt2x00_rf_write(rt2x00dev
, word
, value
);
160 static void rt2400pci_eepromregister_read(struct eeprom_93cx6
*eeprom
)
162 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
165 rt2x00pci_register_read(rt2x00dev
, CSR21
, ®
);
167 eeprom
->reg_data_in
= !!rt2x00_get_field32(reg
, CSR21_EEPROM_DATA_IN
);
168 eeprom
->reg_data_out
= !!rt2x00_get_field32(reg
, CSR21_EEPROM_DATA_OUT
);
169 eeprom
->reg_data_clock
=
170 !!rt2x00_get_field32(reg
, CSR21_EEPROM_DATA_CLOCK
);
171 eeprom
->reg_chip_select
=
172 !!rt2x00_get_field32(reg
, CSR21_EEPROM_CHIP_SELECT
);
175 static void rt2400pci_eepromregister_write(struct eeprom_93cx6
*eeprom
)
177 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
180 rt2x00_set_field32(®
, CSR21_EEPROM_DATA_IN
, !!eeprom
->reg_data_in
);
181 rt2x00_set_field32(®
, CSR21_EEPROM_DATA_OUT
, !!eeprom
->reg_data_out
);
182 rt2x00_set_field32(®
, CSR21_EEPROM_DATA_CLOCK
,
183 !!eeprom
->reg_data_clock
);
184 rt2x00_set_field32(®
, CSR21_EEPROM_CHIP_SELECT
,
185 !!eeprom
->reg_chip_select
);
187 rt2x00pci_register_write(rt2x00dev
, CSR21
, reg
);
190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
191 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
193 static void rt2400pci_read_csr(struct rt2x00_dev
*rt2x00dev
,
194 const unsigned int word
, u32
*data
)
196 rt2x00pci_register_read(rt2x00dev
, CSR_OFFSET(word
), data
);
199 static void rt2400pci_write_csr(struct rt2x00_dev
*rt2x00dev
,
200 const unsigned int word
, u32 data
)
202 rt2x00pci_register_write(rt2x00dev
, CSR_OFFSET(word
), data
);
205 static const struct rt2x00debug rt2400pci_rt2x00debug
= {
206 .owner
= THIS_MODULE
,
208 .read
= rt2400pci_read_csr
,
209 .write
= rt2400pci_write_csr
,
210 .word_size
= sizeof(u32
),
211 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
214 .read
= rt2x00_eeprom_read
,
215 .write
= rt2x00_eeprom_write
,
216 .word_size
= sizeof(u16
),
217 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
220 .read
= rt2400pci_bbp_read
,
221 .write
= rt2400pci_bbp_write
,
222 .word_size
= sizeof(u8
),
223 .word_count
= BBP_SIZE
/ sizeof(u8
),
226 .read
= rt2x00_rf_read
,
227 .write
= rt2400pci_rf_write
,
228 .word_size
= sizeof(u32
),
229 .word_count
= RF_SIZE
/ sizeof(u32
),
232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
234 #ifdef CONFIG_RT2400PCI_RFKILL
235 static int rt2400pci_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
239 rt2x00pci_register_read(rt2x00dev
, GPIOCSR
, ®
);
240 return rt2x00_get_field32(reg
, GPIOCSR_BIT0
);
243 #define rt2400pci_rfkill_poll NULL
244 #endif /* CONFIG_RT2400PCI_RFKILL */
247 * Configuration handlers.
249 static void rt2400pci_config_intf(struct rt2x00_dev
*rt2x00dev
,
250 struct rt2x00_intf
*intf
,
251 struct rt2x00intf_conf
*conf
,
252 const unsigned int flags
)
254 unsigned int bcn_preload
;
257 if (flags
& CONFIG_UPDATE_TYPE
) {
258 rt2x00pci_register_write(rt2x00dev
, CSR14
, 0);
261 * Enable beacon config
263 bcn_preload
= PREAMBLE
+ get_duration(IEEE80211_HEADER
, 20);
264 rt2x00pci_register_read(rt2x00dev
, BCNCSR1
, ®
);
265 rt2x00_set_field32(®
, BCNCSR1_PRELOAD
, bcn_preload
);
266 rt2x00pci_register_write(rt2x00dev
, BCNCSR1
, reg
);
269 * Enable synchronisation.
271 rt2x00pci_register_read(rt2x00dev
, CSR14
, ®
);
272 rt2x00_set_field32(®
, CSR14_TSF_COUNT
, 1);
273 rt2x00_set_field32(®
, CSR14_TBCN
,
274 (conf
->sync
== TSF_SYNC_BEACON
));
275 rt2x00_set_field32(®
, CSR14_BEACON_GEN
, 0);
276 rt2x00_set_field32(®
, CSR14_TSF_SYNC
, conf
->sync
);
277 rt2x00pci_register_write(rt2x00dev
, CSR14
, reg
);
280 if (flags
& CONFIG_UPDATE_MAC
)
281 rt2x00pci_register_multiwrite(rt2x00dev
, CSR3
,
282 conf
->mac
, sizeof(conf
->mac
));
284 if (flags
& CONFIG_UPDATE_BSSID
)
285 rt2x00pci_register_multiwrite(rt2x00dev
, CSR5
,
286 conf
->bssid
, sizeof(conf
->bssid
));
289 static int rt2400pci_config_preamble(struct rt2x00_dev
*rt2x00dev
,
290 const int short_preamble
,
291 const int ack_timeout
,
292 const int ack_consume_time
)
298 * When short preamble is enabled, we should set bit 0x08
300 preamble_mask
= short_preamble
<< 3;
302 rt2x00pci_register_read(rt2x00dev
, TXCSR1
, ®
);
303 rt2x00_set_field32(®
, TXCSR1_ACK_TIMEOUT
, ack_timeout
);
304 rt2x00_set_field32(®
, TXCSR1_ACK_CONSUME_TIME
, ack_consume_time
);
305 rt2x00pci_register_write(rt2x00dev
, TXCSR1
, reg
);
307 rt2x00pci_register_read(rt2x00dev
, ARCSR2
, ®
);
308 rt2x00_set_field32(®
, ARCSR2_SIGNAL
, 0x00 | preamble_mask
);
309 rt2x00_set_field32(®
, ARCSR2_SERVICE
, 0x04);
310 rt2x00_set_field32(®
, ARCSR2_LENGTH
, get_duration(ACK_SIZE
, 10));
311 rt2x00pci_register_write(rt2x00dev
, ARCSR2
, reg
);
313 rt2x00pci_register_read(rt2x00dev
, ARCSR3
, ®
);
314 rt2x00_set_field32(®
, ARCSR3_SIGNAL
, 0x01 | preamble_mask
);
315 rt2x00_set_field32(®
, ARCSR3_SERVICE
, 0x04);
316 rt2x00_set_field32(®
, ARCSR2_LENGTH
, get_duration(ACK_SIZE
, 20));
317 rt2x00pci_register_write(rt2x00dev
, ARCSR3
, reg
);
319 rt2x00pci_register_read(rt2x00dev
, ARCSR4
, ®
);
320 rt2x00_set_field32(®
, ARCSR4_SIGNAL
, 0x02 | preamble_mask
);
321 rt2x00_set_field32(®
, ARCSR4_SERVICE
, 0x04);
322 rt2x00_set_field32(®
, ARCSR2_LENGTH
, get_duration(ACK_SIZE
, 55));
323 rt2x00pci_register_write(rt2x00dev
, ARCSR4
, reg
);
325 rt2x00pci_register_read(rt2x00dev
, ARCSR5
, ®
);
326 rt2x00_set_field32(®
, ARCSR5_SIGNAL
, 0x03 | preamble_mask
);
327 rt2x00_set_field32(®
, ARCSR5_SERVICE
, 0x84);
328 rt2x00_set_field32(®
, ARCSR2_LENGTH
, get_duration(ACK_SIZE
, 110));
329 rt2x00pci_register_write(rt2x00dev
, ARCSR5
, reg
);
334 static void rt2400pci_config_phymode(struct rt2x00_dev
*rt2x00dev
,
335 const int basic_rate_mask
)
337 rt2x00pci_register_write(rt2x00dev
, ARCSR1
, basic_rate_mask
);
340 static void rt2400pci_config_channel(struct rt2x00_dev
*rt2x00dev
,
341 struct rf_channel
*rf
)
344 * Switch on tuning bits.
346 rt2x00_set_field32(&rf
->rf1
, RF1_TUNER
, 1);
347 rt2x00_set_field32(&rf
->rf3
, RF3_TUNER
, 1);
349 rt2400pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
350 rt2400pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
351 rt2400pci_rf_write(rt2x00dev
, 3, rf
->rf3
);
354 * RF2420 chipset don't need any additional actions.
356 if (rt2x00_rf(&rt2x00dev
->chip
, RF2420
))
360 * For the RT2421 chipsets we need to write an invalid
361 * reference clock rate to activate auto_tune.
362 * After that we set the value back to the correct channel.
364 rt2400pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
365 rt2400pci_rf_write(rt2x00dev
, 2, 0x000c2a32);
366 rt2400pci_rf_write(rt2x00dev
, 3, rf
->rf3
);
370 rt2400pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
371 rt2400pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
372 rt2400pci_rf_write(rt2x00dev
, 3, rf
->rf3
);
377 * Switch off tuning bits.
379 rt2x00_set_field32(&rf
->rf1
, RF1_TUNER
, 0);
380 rt2x00_set_field32(&rf
->rf3
, RF3_TUNER
, 0);
382 rt2400pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
383 rt2400pci_rf_write(rt2x00dev
, 3, rf
->rf3
);
386 * Clear false CRC during channel switch.
388 rt2x00pci_register_read(rt2x00dev
, CNT0
, &rf
->rf1
);
391 static void rt2400pci_config_txpower(struct rt2x00_dev
*rt2x00dev
, int txpower
)
393 rt2400pci_bbp_write(rt2x00dev
, 3, TXPOWER_TO_DEV(txpower
));
396 static void rt2400pci_config_antenna(struct rt2x00_dev
*rt2x00dev
,
397 struct antenna_setup
*ant
)
402 rt2400pci_bbp_read(rt2x00dev
, 4, &r4
);
403 rt2400pci_bbp_read(rt2x00dev
, 1, &r1
);
406 * Configure the TX antenna.
409 case ANTENNA_HW_DIVERSITY
:
410 rt2x00_set_field8(&r1
, BBP_R1_TX_ANTENNA
, 1);
413 rt2x00_set_field8(&r1
, BBP_R1_TX_ANTENNA
, 0);
415 case ANTENNA_SW_DIVERSITY
:
417 * NOTE: We should never come here because rt2x00lib is
418 * supposed to catch this and send us the correct antenna
419 * explicitely. However we are nog going to bug about this.
420 * Instead, just default to antenna B.
423 rt2x00_set_field8(&r1
, BBP_R1_TX_ANTENNA
, 2);
428 * Configure the RX antenna.
431 case ANTENNA_HW_DIVERSITY
:
432 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA
, 1);
435 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA
, 0);
437 case ANTENNA_SW_DIVERSITY
:
439 * NOTE: We should never come here because rt2x00lib is
440 * supposed to catch this and send us the correct antenna
441 * explicitely. However we are nog going to bug about this.
442 * Instead, just default to antenna B.
445 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA
, 2);
449 rt2400pci_bbp_write(rt2x00dev
, 4, r4
);
450 rt2400pci_bbp_write(rt2x00dev
, 1, r1
);
453 static void rt2400pci_config_duration(struct rt2x00_dev
*rt2x00dev
,
454 struct rt2x00lib_conf
*libconf
)
458 rt2x00pci_register_read(rt2x00dev
, CSR11
, ®
);
459 rt2x00_set_field32(®
, CSR11_SLOT_TIME
, libconf
->slot_time
);
460 rt2x00pci_register_write(rt2x00dev
, CSR11
, reg
);
462 rt2x00pci_register_read(rt2x00dev
, CSR18
, ®
);
463 rt2x00_set_field32(®
, CSR18_SIFS
, libconf
->sifs
);
464 rt2x00_set_field32(®
, CSR18_PIFS
, libconf
->pifs
);
465 rt2x00pci_register_write(rt2x00dev
, CSR18
, reg
);
467 rt2x00pci_register_read(rt2x00dev
, CSR19
, ®
);
468 rt2x00_set_field32(®
, CSR19_DIFS
, libconf
->difs
);
469 rt2x00_set_field32(®
, CSR19_EIFS
, libconf
->eifs
);
470 rt2x00pci_register_write(rt2x00dev
, CSR19
, reg
);
472 rt2x00pci_register_read(rt2x00dev
, TXCSR1
, ®
);
473 rt2x00_set_field32(®
, TXCSR1_TSF_OFFSET
, IEEE80211_HEADER
);
474 rt2x00_set_field32(®
, TXCSR1_AUTORESPONDER
, 1);
475 rt2x00pci_register_write(rt2x00dev
, TXCSR1
, reg
);
477 rt2x00pci_register_read(rt2x00dev
, CSR12
, ®
);
478 rt2x00_set_field32(®
, CSR12_BEACON_INTERVAL
,
479 libconf
->conf
->beacon_int
* 16);
480 rt2x00_set_field32(®
, CSR12_CFP_MAX_DURATION
,
481 libconf
->conf
->beacon_int
* 16);
482 rt2x00pci_register_write(rt2x00dev
, CSR12
, reg
);
485 static void rt2400pci_config(struct rt2x00_dev
*rt2x00dev
,
486 struct rt2x00lib_conf
*libconf
,
487 const unsigned int flags
)
489 if (flags
& CONFIG_UPDATE_PHYMODE
)
490 rt2400pci_config_phymode(rt2x00dev
, libconf
->basic_rates
);
491 if (flags
& CONFIG_UPDATE_CHANNEL
)
492 rt2400pci_config_channel(rt2x00dev
, &libconf
->rf
);
493 if (flags
& CONFIG_UPDATE_TXPOWER
)
494 rt2400pci_config_txpower(rt2x00dev
,
495 libconf
->conf
->power_level
);
496 if (flags
& CONFIG_UPDATE_ANTENNA
)
497 rt2400pci_config_antenna(rt2x00dev
, &libconf
->ant
);
498 if (flags
& (CONFIG_UPDATE_SLOT_TIME
| CONFIG_UPDATE_BEACON_INT
))
499 rt2400pci_config_duration(rt2x00dev
, libconf
);
502 static void rt2400pci_config_cw(struct rt2x00_dev
*rt2x00dev
,
503 const int cw_min
, const int cw_max
)
507 rt2x00pci_register_read(rt2x00dev
, CSR11
, ®
);
508 rt2x00_set_field32(®
, CSR11_CWMIN
, cw_min
);
509 rt2x00_set_field32(®
, CSR11_CWMAX
, cw_max
);
510 rt2x00pci_register_write(rt2x00dev
, CSR11
, reg
);
516 static void rt2400pci_enable_led(struct rt2x00_dev
*rt2x00dev
)
520 rt2x00pci_register_read(rt2x00dev
, LEDCSR
, ®
);
522 rt2x00_set_field32(®
, LEDCSR_ON_PERIOD
, 70);
523 rt2x00_set_field32(®
, LEDCSR_OFF_PERIOD
, 30);
524 rt2x00_set_field32(®
, LEDCSR_LINK
,
525 (rt2x00dev
->led_mode
!= LED_MODE_ASUS
));
526 rt2x00_set_field32(®
, LEDCSR_ACTIVITY
,
527 (rt2x00dev
->led_mode
!= LED_MODE_TXRX_ACTIVITY
));
528 rt2x00pci_register_write(rt2x00dev
, LEDCSR
, reg
);
531 static void rt2400pci_disable_led(struct rt2x00_dev
*rt2x00dev
)
535 rt2x00pci_register_read(rt2x00dev
, LEDCSR
, ®
);
536 rt2x00_set_field32(®
, LEDCSR_LINK
, 0);
537 rt2x00_set_field32(®
, LEDCSR_ACTIVITY
, 0);
538 rt2x00pci_register_write(rt2x00dev
, LEDCSR
, reg
);
544 static void rt2400pci_link_stats(struct rt2x00_dev
*rt2x00dev
,
545 struct link_qual
*qual
)
551 * Update FCS error count from register.
553 rt2x00pci_register_read(rt2x00dev
, CNT0
, ®
);
554 qual
->rx_failed
= rt2x00_get_field32(reg
, CNT0_FCS_ERROR
);
557 * Update False CCA count from register.
559 rt2400pci_bbp_read(rt2x00dev
, 39, &bbp
);
560 qual
->false_cca
= bbp
;
563 static void rt2400pci_reset_tuner(struct rt2x00_dev
*rt2x00dev
)
565 rt2400pci_bbp_write(rt2x00dev
, 13, 0x08);
566 rt2x00dev
->link
.vgc_level
= 0x08;
569 static void rt2400pci_link_tuner(struct rt2x00_dev
*rt2x00dev
)
574 * The link tuner should not run longer then 60 seconds,
575 * and should run once every 2 seconds.
577 if (rt2x00dev
->link
.count
> 60 || !(rt2x00dev
->link
.count
& 1))
581 * Base r13 link tuning on the false cca count.
583 rt2400pci_bbp_read(rt2x00dev
, 13, ®
);
585 if (rt2x00dev
->link
.qual
.false_cca
> 512 && reg
< 0x20) {
586 rt2400pci_bbp_write(rt2x00dev
, 13, ++reg
);
587 rt2x00dev
->link
.vgc_level
= reg
;
588 } else if (rt2x00dev
->link
.qual
.false_cca
< 100 && reg
> 0x08) {
589 rt2400pci_bbp_write(rt2x00dev
, 13, --reg
);
590 rt2x00dev
->link
.vgc_level
= reg
;
595 * Initialization functions.
597 static void rt2400pci_init_rxentry(struct rt2x00_dev
*rt2x00dev
,
598 struct queue_entry
*entry
)
600 struct queue_entry_priv_pci_rx
*priv_rx
= entry
->priv_data
;
603 rt2x00_desc_read(priv_rx
->desc
, 2, &word
);
604 rt2x00_set_field32(&word
, RXD_W2_BUFFER_LENGTH
, entry
->queue
->data_size
);
605 rt2x00_desc_write(priv_rx
->desc
, 2, word
);
607 rt2x00_desc_read(priv_rx
->desc
, 1, &word
);
608 rt2x00_set_field32(&word
, RXD_W1_BUFFER_ADDRESS
, priv_rx
->dma
);
609 rt2x00_desc_write(priv_rx
->desc
, 1, word
);
611 rt2x00_desc_read(priv_rx
->desc
, 0, &word
);
612 rt2x00_set_field32(&word
, RXD_W0_OWNER_NIC
, 1);
613 rt2x00_desc_write(priv_rx
->desc
, 0, word
);
616 static void rt2400pci_init_txentry(struct rt2x00_dev
*rt2x00dev
,
617 struct queue_entry
*entry
)
619 struct queue_entry_priv_pci_tx
*priv_tx
= entry
->priv_data
;
622 rt2x00_desc_read(priv_tx
->desc
, 1, &word
);
623 rt2x00_set_field32(&word
, TXD_W1_BUFFER_ADDRESS
, priv_tx
->dma
);
624 rt2x00_desc_write(priv_tx
->desc
, 1, word
);
626 rt2x00_desc_read(priv_tx
->desc
, 2, &word
);
627 rt2x00_set_field32(&word
, TXD_W2_BUFFER_LENGTH
,
628 entry
->queue
->data_size
);
629 rt2x00_desc_write(priv_tx
->desc
, 2, word
);
631 rt2x00_desc_read(priv_tx
->desc
, 0, &word
);
632 rt2x00_set_field32(&word
, TXD_W0_VALID
, 0);
633 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 0);
634 rt2x00_desc_write(priv_tx
->desc
, 0, word
);
637 static int rt2400pci_init_queues(struct rt2x00_dev
*rt2x00dev
)
639 struct queue_entry_priv_pci_rx
*priv_rx
;
640 struct queue_entry_priv_pci_tx
*priv_tx
;
644 * Initialize registers.
646 rt2x00pci_register_read(rt2x00dev
, TXCSR2
, ®
);
647 rt2x00_set_field32(®
, TXCSR2_TXD_SIZE
, rt2x00dev
->tx
[0].desc_size
);
648 rt2x00_set_field32(®
, TXCSR2_NUM_TXD
, rt2x00dev
->tx
[1].limit
);
649 rt2x00_set_field32(®
, TXCSR2_NUM_ATIM
, rt2x00dev
->bcn
[1].limit
);
650 rt2x00_set_field32(®
, TXCSR2_NUM_PRIO
, rt2x00dev
->tx
[0].limit
);
651 rt2x00pci_register_write(rt2x00dev
, TXCSR2
, reg
);
653 priv_tx
= rt2x00dev
->tx
[1].entries
[0].priv_data
;
654 rt2x00pci_register_read(rt2x00dev
, TXCSR3
, ®
);
655 rt2x00_set_field32(®
, TXCSR3_TX_RING_REGISTER
, priv_tx
->dma
);
656 rt2x00pci_register_write(rt2x00dev
, TXCSR3
, reg
);
658 priv_tx
= rt2x00dev
->tx
[0].entries
[0].priv_data
;
659 rt2x00pci_register_read(rt2x00dev
, TXCSR5
, ®
);
660 rt2x00_set_field32(®
, TXCSR5_PRIO_RING_REGISTER
, priv_tx
->dma
);
661 rt2x00pci_register_write(rt2x00dev
, TXCSR5
, reg
);
663 priv_tx
= rt2x00dev
->bcn
[1].entries
[0].priv_data
;
664 rt2x00pci_register_read(rt2x00dev
, TXCSR4
, ®
);
665 rt2x00_set_field32(®
, TXCSR4_ATIM_RING_REGISTER
, priv_tx
->dma
);
666 rt2x00pci_register_write(rt2x00dev
, TXCSR4
, reg
);
668 priv_tx
= rt2x00dev
->bcn
[0].entries
[0].priv_data
;
669 rt2x00pci_register_read(rt2x00dev
, TXCSR6
, ®
);
670 rt2x00_set_field32(®
, TXCSR6_BEACON_RING_REGISTER
, priv_tx
->dma
);
671 rt2x00pci_register_write(rt2x00dev
, TXCSR6
, reg
);
673 rt2x00pci_register_read(rt2x00dev
, RXCSR1
, ®
);
674 rt2x00_set_field32(®
, RXCSR1_RXD_SIZE
, rt2x00dev
->rx
->desc_size
);
675 rt2x00_set_field32(®
, RXCSR1_NUM_RXD
, rt2x00dev
->rx
->limit
);
676 rt2x00pci_register_write(rt2x00dev
, RXCSR1
, reg
);
678 priv_rx
= rt2x00dev
->rx
->entries
[0].priv_data
;
679 rt2x00pci_register_read(rt2x00dev
, RXCSR2
, ®
);
680 rt2x00_set_field32(®
, RXCSR2_RX_RING_REGISTER
, priv_tx
->dma
);
681 rt2x00pci_register_write(rt2x00dev
, RXCSR2
, reg
);
686 static int rt2400pci_init_registers(struct rt2x00_dev
*rt2x00dev
)
690 rt2x00pci_register_write(rt2x00dev
, PSCSR0
, 0x00020002);
691 rt2x00pci_register_write(rt2x00dev
, PSCSR1
, 0x00000002);
692 rt2x00pci_register_write(rt2x00dev
, PSCSR2
, 0x00023f20);
693 rt2x00pci_register_write(rt2x00dev
, PSCSR3
, 0x00000002);
695 rt2x00pci_register_read(rt2x00dev
, TIMECSR
, ®
);
696 rt2x00_set_field32(®
, TIMECSR_US_COUNT
, 33);
697 rt2x00_set_field32(®
, TIMECSR_US_64_COUNT
, 63);
698 rt2x00_set_field32(®
, TIMECSR_BEACON_EXPECT
, 0);
699 rt2x00pci_register_write(rt2x00dev
, TIMECSR
, reg
);
701 rt2x00pci_register_read(rt2x00dev
, CSR9
, ®
);
702 rt2x00_set_field32(®
, CSR9_MAX_FRAME_UNIT
,
703 (rt2x00dev
->rx
->data_size
/ 128));
704 rt2x00pci_register_write(rt2x00dev
, CSR9
, reg
);
706 rt2x00pci_register_write(rt2x00dev
, CNT3
, 0x3f080000);
708 rt2x00pci_register_read(rt2x00dev
, ARCSR0
, ®
);
709 rt2x00_set_field32(®
, ARCSR0_AR_BBP_DATA0
, 133);
710 rt2x00_set_field32(®
, ARCSR0_AR_BBP_ID0
, 134);
711 rt2x00_set_field32(®
, ARCSR0_AR_BBP_DATA1
, 136);
712 rt2x00_set_field32(®
, ARCSR0_AR_BBP_ID1
, 135);
713 rt2x00pci_register_write(rt2x00dev
, ARCSR0
, reg
);
715 rt2x00pci_register_read(rt2x00dev
, RXCSR3
, ®
);
716 rt2x00_set_field32(®
, RXCSR3_BBP_ID0
, 3); /* Tx power.*/
717 rt2x00_set_field32(®
, RXCSR3_BBP_ID0_VALID
, 1);
718 rt2x00_set_field32(®
, RXCSR3_BBP_ID1
, 32); /* Signal */
719 rt2x00_set_field32(®
, RXCSR3_BBP_ID1_VALID
, 1);
720 rt2x00_set_field32(®
, RXCSR3_BBP_ID2
, 36); /* Rssi */
721 rt2x00_set_field32(®
, RXCSR3_BBP_ID2_VALID
, 1);
722 rt2x00pci_register_write(rt2x00dev
, RXCSR3
, reg
);
724 rt2x00pci_register_write(rt2x00dev
, PWRCSR0
, 0x3f3b3100);
726 if (rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, STATE_AWAKE
))
729 rt2x00pci_register_write(rt2x00dev
, MACCSR0
, 0x00217223);
730 rt2x00pci_register_write(rt2x00dev
, MACCSR1
, 0x00235518);
732 rt2x00pci_register_read(rt2x00dev
, MACCSR2
, ®
);
733 rt2x00_set_field32(®
, MACCSR2_DELAY
, 64);
734 rt2x00pci_register_write(rt2x00dev
, MACCSR2
, reg
);
736 rt2x00pci_register_read(rt2x00dev
, RALINKCSR
, ®
);
737 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_DATA0
, 17);
738 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_ID0
, 154);
739 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_DATA1
, 0);
740 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_ID1
, 154);
741 rt2x00pci_register_write(rt2x00dev
, RALINKCSR
, reg
);
743 rt2x00pci_register_read(rt2x00dev
, CSR1
, ®
);
744 rt2x00_set_field32(®
, CSR1_SOFT_RESET
, 1);
745 rt2x00_set_field32(®
, CSR1_BBP_RESET
, 0);
746 rt2x00_set_field32(®
, CSR1_HOST_READY
, 0);
747 rt2x00pci_register_write(rt2x00dev
, CSR1
, reg
);
749 rt2x00pci_register_read(rt2x00dev
, CSR1
, ®
);
750 rt2x00_set_field32(®
, CSR1_SOFT_RESET
, 0);
751 rt2x00_set_field32(®
, CSR1_HOST_READY
, 1);
752 rt2x00pci_register_write(rt2x00dev
, CSR1
, reg
);
755 * We must clear the FCS and FIFO error count.
756 * These registers are cleared on read,
757 * so we may pass a useless variable to store the value.
759 rt2x00pci_register_read(rt2x00dev
, CNT0
, ®
);
760 rt2x00pci_register_read(rt2x00dev
, CNT4
, ®
);
765 static int rt2400pci_init_bbp(struct rt2x00_dev
*rt2x00dev
)
772 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
773 rt2400pci_bbp_read(rt2x00dev
, 0, &value
);
774 if ((value
!= 0xff) && (value
!= 0x00))
775 goto continue_csr_init
;
776 NOTICE(rt2x00dev
, "Waiting for BBP register.\n");
777 udelay(REGISTER_BUSY_DELAY
);
780 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
784 rt2400pci_bbp_write(rt2x00dev
, 1, 0x00);
785 rt2400pci_bbp_write(rt2x00dev
, 3, 0x27);
786 rt2400pci_bbp_write(rt2x00dev
, 4, 0x08);
787 rt2400pci_bbp_write(rt2x00dev
, 10, 0x0f);
788 rt2400pci_bbp_write(rt2x00dev
, 15, 0x72);
789 rt2400pci_bbp_write(rt2x00dev
, 16, 0x74);
790 rt2400pci_bbp_write(rt2x00dev
, 17, 0x20);
791 rt2400pci_bbp_write(rt2x00dev
, 18, 0x72);
792 rt2400pci_bbp_write(rt2x00dev
, 19, 0x0b);
793 rt2400pci_bbp_write(rt2x00dev
, 20, 0x00);
794 rt2400pci_bbp_write(rt2x00dev
, 28, 0x11);
795 rt2400pci_bbp_write(rt2x00dev
, 29, 0x04);
796 rt2400pci_bbp_write(rt2x00dev
, 30, 0x21);
797 rt2400pci_bbp_write(rt2x00dev
, 31, 0x00);
799 DEBUG(rt2x00dev
, "Start initialization from EEPROM...\n");
800 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
801 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
803 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
804 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
805 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
806 DEBUG(rt2x00dev
, "BBP: 0x%02x, value: 0x%02x.\n",
808 rt2400pci_bbp_write(rt2x00dev
, reg_id
, value
);
811 DEBUG(rt2x00dev
, "...End initialization from EEPROM.\n");
817 * Device state switch handlers.
819 static void rt2400pci_toggle_rx(struct rt2x00_dev
*rt2x00dev
,
820 enum dev_state state
)
824 rt2x00pci_register_read(rt2x00dev
, RXCSR0
, ®
);
825 rt2x00_set_field32(®
, RXCSR0_DISABLE_RX
,
826 state
== STATE_RADIO_RX_OFF
);
827 rt2x00pci_register_write(rt2x00dev
, RXCSR0
, reg
);
830 static void rt2400pci_toggle_irq(struct rt2x00_dev
*rt2x00dev
,
831 enum dev_state state
)
833 int mask
= (state
== STATE_RADIO_IRQ_OFF
);
837 * When interrupts are being enabled, the interrupt registers
838 * should clear the register to assure a clean state.
840 if (state
== STATE_RADIO_IRQ_ON
) {
841 rt2x00pci_register_read(rt2x00dev
, CSR7
, ®
);
842 rt2x00pci_register_write(rt2x00dev
, CSR7
, reg
);
846 * Only toggle the interrupts bits we are going to use.
847 * Non-checked interrupt bits are disabled by default.
849 rt2x00pci_register_read(rt2x00dev
, CSR8
, ®
);
850 rt2x00_set_field32(®
, CSR8_TBCN_EXPIRE
, mask
);
851 rt2x00_set_field32(®
, CSR8_TXDONE_TXRING
, mask
);
852 rt2x00_set_field32(®
, CSR8_TXDONE_ATIMRING
, mask
);
853 rt2x00_set_field32(®
, CSR8_TXDONE_PRIORING
, mask
);
854 rt2x00_set_field32(®
, CSR8_RXDONE
, mask
);
855 rt2x00pci_register_write(rt2x00dev
, CSR8
, reg
);
858 static int rt2400pci_enable_radio(struct rt2x00_dev
*rt2x00dev
)
861 * Initialize all registers.
863 if (rt2400pci_init_queues(rt2x00dev
) ||
864 rt2400pci_init_registers(rt2x00dev
) ||
865 rt2400pci_init_bbp(rt2x00dev
)) {
866 ERROR(rt2x00dev
, "Register initialization failed.\n");
873 rt2400pci_toggle_irq(rt2x00dev
, STATE_RADIO_IRQ_ON
);
878 rt2400pci_enable_led(rt2x00dev
);
883 static void rt2400pci_disable_radio(struct rt2x00_dev
*rt2x00dev
)
890 rt2400pci_disable_led(rt2x00dev
);
892 rt2x00pci_register_write(rt2x00dev
, PWRCSR0
, 0);
895 * Disable synchronisation.
897 rt2x00pci_register_write(rt2x00dev
, CSR14
, 0);
902 rt2x00pci_register_read(rt2x00dev
, TXCSR0
, ®
);
903 rt2x00_set_field32(®
, TXCSR0_ABORT
, 1);
904 rt2x00pci_register_write(rt2x00dev
, TXCSR0
, reg
);
907 * Disable interrupts.
909 rt2400pci_toggle_irq(rt2x00dev
, STATE_RADIO_IRQ_OFF
);
912 static int rt2400pci_set_state(struct rt2x00_dev
*rt2x00dev
,
913 enum dev_state state
)
921 put_to_sleep
= (state
!= STATE_AWAKE
);
923 rt2x00pci_register_read(rt2x00dev
, PWRCSR1
, ®
);
924 rt2x00_set_field32(®
, PWRCSR1_SET_STATE
, 1);
925 rt2x00_set_field32(®
, PWRCSR1_BBP_DESIRE_STATE
, state
);
926 rt2x00_set_field32(®
, PWRCSR1_RF_DESIRE_STATE
, state
);
927 rt2x00_set_field32(®
, PWRCSR1_PUT_TO_SLEEP
, put_to_sleep
);
928 rt2x00pci_register_write(rt2x00dev
, PWRCSR1
, reg
);
931 * Device is not guaranteed to be in the requested state yet.
932 * We must wait until the register indicates that the
933 * device has entered the correct state.
935 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
936 rt2x00pci_register_read(rt2x00dev
, PWRCSR1
, ®
);
937 bbp_state
= rt2x00_get_field32(reg
, PWRCSR1_BBP_CURR_STATE
);
938 rf_state
= rt2x00_get_field32(reg
, PWRCSR1_RF_CURR_STATE
);
939 if (bbp_state
== state
&& rf_state
== state
)
944 NOTICE(rt2x00dev
, "Device failed to enter state %d, "
945 "current device state: bbp %d and rf %d.\n",
946 state
, bbp_state
, rf_state
);
951 static int rt2400pci_set_device_state(struct rt2x00_dev
*rt2x00dev
,
952 enum dev_state state
)
958 retval
= rt2400pci_enable_radio(rt2x00dev
);
960 case STATE_RADIO_OFF
:
961 rt2400pci_disable_radio(rt2x00dev
);
963 case STATE_RADIO_RX_ON
:
964 case STATE_RADIO_RX_ON_LINK
:
965 rt2400pci_toggle_rx(rt2x00dev
, STATE_RADIO_RX_ON
);
967 case STATE_RADIO_RX_OFF
:
968 case STATE_RADIO_RX_OFF_LINK
:
969 rt2400pci_toggle_rx(rt2x00dev
, STATE_RADIO_RX_OFF
);
971 case STATE_DEEP_SLEEP
:
975 retval
= rt2400pci_set_state(rt2x00dev
, state
);
986 * TX descriptor initialization
988 static void rt2400pci_write_tx_desc(struct rt2x00_dev
*rt2x00dev
,
990 struct txentry_desc
*txdesc
,
991 struct ieee80211_tx_control
*control
)
993 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(skb
);
994 __le32
*txd
= skbdesc
->desc
;
998 * Start writing the descriptor words.
1000 rt2x00_desc_read(txd
, 2, &word
);
1001 rt2x00_set_field32(&word
, TXD_W2_DATABYTE_COUNT
, skbdesc
->data_len
);
1002 rt2x00_desc_write(txd
, 2, word
);
1004 rt2x00_desc_read(txd
, 3, &word
);
1005 rt2x00_set_field32(&word
, TXD_W3_PLCP_SIGNAL
, txdesc
->signal
);
1006 rt2x00_set_field32(&word
, TXD_W3_PLCP_SIGNAL_REGNUM
, 5);
1007 rt2x00_set_field32(&word
, TXD_W3_PLCP_SIGNAL_BUSY
, 1);
1008 rt2x00_set_field32(&word
, TXD_W3_PLCP_SERVICE
, txdesc
->service
);
1009 rt2x00_set_field32(&word
, TXD_W3_PLCP_SERVICE_REGNUM
, 6);
1010 rt2x00_set_field32(&word
, TXD_W3_PLCP_SERVICE_BUSY
, 1);
1011 rt2x00_desc_write(txd
, 3, word
);
1013 rt2x00_desc_read(txd
, 4, &word
);
1014 rt2x00_set_field32(&word
, TXD_W4_PLCP_LENGTH_LOW
, txdesc
->length_low
);
1015 rt2x00_set_field32(&word
, TXD_W3_PLCP_LENGTH_LOW_REGNUM
, 8);
1016 rt2x00_set_field32(&word
, TXD_W3_PLCP_LENGTH_LOW_BUSY
, 1);
1017 rt2x00_set_field32(&word
, TXD_W4_PLCP_LENGTH_HIGH
, txdesc
->length_high
);
1018 rt2x00_set_field32(&word
, TXD_W3_PLCP_LENGTH_HIGH_REGNUM
, 7);
1019 rt2x00_set_field32(&word
, TXD_W3_PLCP_LENGTH_HIGH_BUSY
, 1);
1020 rt2x00_desc_write(txd
, 4, word
);
1022 rt2x00_desc_read(txd
, 0, &word
);
1023 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 1);
1024 rt2x00_set_field32(&word
, TXD_W0_VALID
, 1);
1025 rt2x00_set_field32(&word
, TXD_W0_MORE_FRAG
,
1026 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
1027 rt2x00_set_field32(&word
, TXD_W0_ACK
,
1028 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
1029 rt2x00_set_field32(&word
, TXD_W0_TIMESTAMP
,
1030 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
1031 rt2x00_set_field32(&word
, TXD_W0_RTS
,
1032 test_bit(ENTRY_TXD_RTS_FRAME
, &txdesc
->flags
));
1033 rt2x00_set_field32(&word
, TXD_W0_IFS
, txdesc
->ifs
);
1034 rt2x00_set_field32(&word
, TXD_W0_RETRY_MODE
,
1036 IEEE80211_TXCTL_LONG_RETRY_LIMIT
));
1037 rt2x00_desc_write(txd
, 0, word
);
1041 * TX data initialization
1043 static void rt2400pci_kick_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1044 const unsigned int queue
)
1048 if (queue
== RT2X00_BCN_QUEUE_BEACON
) {
1049 rt2x00pci_register_read(rt2x00dev
, CSR14
, ®
);
1050 if (!rt2x00_get_field32(reg
, CSR14_BEACON_GEN
)) {
1051 rt2x00_set_field32(®
, CSR14_BEACON_GEN
, 1);
1052 rt2x00pci_register_write(rt2x00dev
, CSR14
, reg
);
1057 rt2x00pci_register_read(rt2x00dev
, TXCSR0
, ®
);
1058 rt2x00_set_field32(®
, TXCSR0_KICK_PRIO
,
1059 (queue
== IEEE80211_TX_QUEUE_DATA0
));
1060 rt2x00_set_field32(®
, TXCSR0_KICK_TX
,
1061 (queue
== IEEE80211_TX_QUEUE_DATA1
));
1062 rt2x00_set_field32(®
, TXCSR0_KICK_ATIM
,
1063 (queue
== RT2X00_BCN_QUEUE_ATIM
));
1064 rt2x00pci_register_write(rt2x00dev
, TXCSR0
, reg
);
1068 * RX control handlers
1070 static void rt2400pci_fill_rxdone(struct queue_entry
*entry
,
1071 struct rxdone_entry_desc
*rxdesc
)
1073 struct queue_entry_priv_pci_rx
*priv_rx
= entry
->priv_data
;
1077 rt2x00_desc_read(priv_rx
->desc
, 0, &word0
);
1078 rt2x00_desc_read(priv_rx
->desc
, 2, &word2
);
1081 if (rt2x00_get_field32(word0
, RXD_W0_CRC_ERROR
))
1082 rxdesc
->flags
|= RX_FLAG_FAILED_FCS_CRC
;
1083 if (rt2x00_get_field32(word0
, RXD_W0_PHYSICAL_ERROR
))
1084 rxdesc
->flags
|= RX_FLAG_FAILED_PLCP_CRC
;
1087 * Obtain the status about this packet.
1089 rxdesc
->signal
= rt2x00_get_field32(word2
, RXD_W2_SIGNAL
);
1090 rxdesc
->rssi
= rt2x00_get_field32(word2
, RXD_W2_RSSI
) -
1091 entry
->queue
->rt2x00dev
->rssi_offset
;
1093 rxdesc
->size
= rt2x00_get_field32(word0
, RXD_W0_DATABYTE_COUNT
);
1094 rxdesc
->my_bss
= !!rt2x00_get_field32(word0
, RXD_W0_MY_BSS
);
1098 * Interrupt functions.
1100 static void rt2400pci_txdone(struct rt2x00_dev
*rt2x00dev
,
1101 const enum ieee80211_tx_queue queue_idx
)
1103 struct data_queue
*queue
= rt2x00queue_get_queue(rt2x00dev
, queue_idx
);
1104 struct queue_entry_priv_pci_tx
*priv_tx
;
1105 struct queue_entry
*entry
;
1106 struct txdone_entry_desc txdesc
;
1109 while (!rt2x00queue_empty(queue
)) {
1110 entry
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
1111 priv_tx
= entry
->priv_data
;
1112 rt2x00_desc_read(priv_tx
->desc
, 0, &word
);
1114 if (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
1115 !rt2x00_get_field32(word
, TXD_W0_VALID
))
1119 * Obtain the status about this packet.
1121 txdesc
.status
= rt2x00_get_field32(word
, TXD_W0_RESULT
);
1122 txdesc
.retry
= rt2x00_get_field32(word
, TXD_W0_RETRY_COUNT
);
1124 rt2x00pci_txdone(rt2x00dev
, entry
, &txdesc
);
1128 static irqreturn_t
rt2400pci_interrupt(int irq
, void *dev_instance
)
1130 struct rt2x00_dev
*rt2x00dev
= dev_instance
;
1134 * Get the interrupt sources & saved to local variable.
1135 * Write register value back to clear pending interrupts.
1137 rt2x00pci_register_read(rt2x00dev
, CSR7
, ®
);
1138 rt2x00pci_register_write(rt2x00dev
, CSR7
, reg
);
1143 if (!test_bit(DEVICE_ENABLED_RADIO
, &rt2x00dev
->flags
))
1147 * Handle interrupts, walk through all bits
1148 * and run the tasks, the bits are checked in order of
1153 * 1 - Beacon timer expired interrupt.
1155 if (rt2x00_get_field32(reg
, CSR7_TBCN_EXPIRE
))
1156 rt2x00lib_beacondone(rt2x00dev
);
1159 * 2 - Rx ring done interrupt.
1161 if (rt2x00_get_field32(reg
, CSR7_RXDONE
))
1162 rt2x00pci_rxdone(rt2x00dev
);
1165 * 3 - Atim ring transmit done interrupt.
1167 if (rt2x00_get_field32(reg
, CSR7_TXDONE_ATIMRING
))
1168 rt2400pci_txdone(rt2x00dev
, RT2X00_BCN_QUEUE_ATIM
);
1171 * 4 - Priority ring transmit done interrupt.
1173 if (rt2x00_get_field32(reg
, CSR7_TXDONE_PRIORING
))
1174 rt2400pci_txdone(rt2x00dev
, IEEE80211_TX_QUEUE_DATA0
);
1177 * 5 - Tx ring transmit done interrupt.
1179 if (rt2x00_get_field32(reg
, CSR7_TXDONE_TXRING
))
1180 rt2400pci_txdone(rt2x00dev
, IEEE80211_TX_QUEUE_DATA1
);
1186 * Device probe functions.
1188 static int rt2400pci_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
1190 struct eeprom_93cx6 eeprom
;
1195 rt2x00pci_register_read(rt2x00dev
, CSR21
, ®
);
1197 eeprom
.data
= rt2x00dev
;
1198 eeprom
.register_read
= rt2400pci_eepromregister_read
;
1199 eeprom
.register_write
= rt2400pci_eepromregister_write
;
1200 eeprom
.width
= rt2x00_get_field32(reg
, CSR21_TYPE_93C46
) ?
1201 PCI_EEPROM_WIDTH_93C46
: PCI_EEPROM_WIDTH_93C66
;
1202 eeprom
.reg_data_in
= 0;
1203 eeprom
.reg_data_out
= 0;
1204 eeprom
.reg_data_clock
= 0;
1205 eeprom
.reg_chip_select
= 0;
1207 eeprom_93cx6_multiread(&eeprom
, EEPROM_BASE
, rt2x00dev
->eeprom
,
1208 EEPROM_SIZE
/ sizeof(u16
));
1211 * Start validation of the data that has been read.
1213 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
1214 if (!is_valid_ether_addr(mac
)) {
1215 DECLARE_MAC_BUF(macbuf
);
1217 random_ether_addr(mac
);
1218 EEPROM(rt2x00dev
, "MAC: %s\n", print_mac(macbuf
, mac
));
1221 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
1222 if (word
== 0xffff) {
1223 ERROR(rt2x00dev
, "Invalid EEPROM data detected.\n");
1230 static int rt2400pci_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
1237 * Read EEPROM word for configuration.
1239 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
1242 * Identify RF chipset.
1244 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
1245 rt2x00pci_register_read(rt2x00dev
, CSR0
, ®
);
1246 rt2x00_set_chip(rt2x00dev
, RT2460
, value
, reg
);
1248 if (!rt2x00_rf(&rt2x00dev
->chip
, RF2420
) &&
1249 !rt2x00_rf(&rt2x00dev
->chip
, RF2421
)) {
1250 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
1255 * Identify default antenna configuration.
1257 rt2x00dev
->default_ant
.tx
=
1258 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TX_DEFAULT
);
1259 rt2x00dev
->default_ant
.rx
=
1260 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RX_DEFAULT
);
1263 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1264 * I am not 100% sure about this, but the legacy drivers do not
1265 * indicate antenna swapping in software is required when
1266 * diversity is enabled.
1268 if (rt2x00dev
->default_ant
.tx
== ANTENNA_SW_DIVERSITY
)
1269 rt2x00dev
->default_ant
.tx
= ANTENNA_HW_DIVERSITY
;
1270 if (rt2x00dev
->default_ant
.rx
== ANTENNA_SW_DIVERSITY
)
1271 rt2x00dev
->default_ant
.rx
= ANTENNA_HW_DIVERSITY
;
1274 * Store led mode, for correct led behaviour.
1276 rt2x00dev
->led_mode
=
1277 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_LED_MODE
);
1280 * Detect if this device has an hardware controlled radio.
1282 #ifdef CONFIG_RT2400PCI_RFKILL
1283 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_HARDWARE_RADIO
))
1284 __set_bit(CONFIG_SUPPORT_HW_BUTTON
, &rt2x00dev
->flags
);
1285 #endif /* CONFIG_RT2400PCI_RFKILL */
1288 * Check if the BBP tuning should be enabled.
1290 if (!rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RX_AGCVGC_TUNING
))
1291 __set_bit(CONFIG_DISABLE_LINK_TUNING
, &rt2x00dev
->flags
);
1297 * RF value list for RF2420 & RF2421
1300 static const struct rf_channel rf_vals_bg
[] = {
1301 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1302 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1303 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1304 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1305 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1306 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1307 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1308 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1309 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1310 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1311 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1312 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1313 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1314 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1317 static void rt2400pci_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
1319 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
1324 * Initialize all hw fields.
1326 rt2x00dev
->hw
->flags
= IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
;
1327 rt2x00dev
->hw
->extra_tx_headroom
= 0;
1328 rt2x00dev
->hw
->max_signal
= MAX_SIGNAL
;
1329 rt2x00dev
->hw
->max_rssi
= MAX_RX_SSI
;
1330 rt2x00dev
->hw
->queues
= 2;
1332 SET_IEEE80211_DEV(rt2x00dev
->hw
, &rt2x00dev_pci(rt2x00dev
)->dev
);
1333 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
1334 rt2x00_eeprom_addr(rt2x00dev
,
1335 EEPROM_MAC_ADDR_0
));
1338 * Convert tx_power array in eeprom.
1340 txpower
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_START
);
1341 for (i
= 0; i
< 14; i
++)
1342 txpower
[i
] = TXPOWER_FROM_DEV(txpower
[i
]);
1345 * Initialize hw_mode information.
1347 spec
->num_modes
= 1;
1348 spec
->num_rates
= 4;
1349 spec
->tx_power_a
= NULL
;
1350 spec
->tx_power_bg
= txpower
;
1351 spec
->tx_power_default
= DEFAULT_TXPOWER
;
1353 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg
);
1354 spec
->channels
= rf_vals_bg
;
1357 static int rt2400pci_probe_hw(struct rt2x00_dev
*rt2x00dev
)
1362 * Allocate eeprom data.
1364 retval
= rt2400pci_validate_eeprom(rt2x00dev
);
1368 retval
= rt2400pci_init_eeprom(rt2x00dev
);
1373 * Initialize hw specifications.
1375 rt2400pci_probe_hw_mode(rt2x00dev
);
1378 * This device requires the atim queue
1380 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE
, &rt2x00dev
->flags
);
1383 * Set the rssi offset.
1385 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
1391 * IEEE80211 stack callback functions.
1393 static void rt2400pci_configure_filter(struct ieee80211_hw
*hw
,
1394 unsigned int changed_flags
,
1395 unsigned int *total_flags
,
1397 struct dev_addr_list
*mc_list
)
1399 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1403 * Mask off any flags we are going to ignore from
1404 * the total_flags field.
1415 * Apply some rules to the filters:
1416 * - Some filters imply different filters to be set.
1417 * - Some things we can't filter out at all.
1419 *total_flags
|= FIF_ALLMULTI
;
1420 if (*total_flags
& FIF_OTHER_BSS
||
1421 *total_flags
& FIF_PROMISC_IN_BSS
)
1422 *total_flags
|= FIF_PROMISC_IN_BSS
| FIF_OTHER_BSS
;
1425 * Check if there is any work left for us.
1427 if (rt2x00dev
->packet_filter
== *total_flags
)
1429 rt2x00dev
->packet_filter
= *total_flags
;
1432 * Start configuration steps.
1433 * Note that the version error will always be dropped
1434 * since there is no filter for it at this time.
1436 rt2x00pci_register_read(rt2x00dev
, RXCSR0
, ®
);
1437 rt2x00_set_field32(®
, RXCSR0_DROP_CRC
,
1438 !(*total_flags
& FIF_FCSFAIL
));
1439 rt2x00_set_field32(®
, RXCSR0_DROP_PHYSICAL
,
1440 !(*total_flags
& FIF_PLCPFAIL
));
1441 rt2x00_set_field32(®
, RXCSR0_DROP_CONTROL
,
1442 !(*total_flags
& FIF_CONTROL
));
1443 rt2x00_set_field32(®
, RXCSR0_DROP_NOT_TO_ME
,
1444 !(*total_flags
& FIF_PROMISC_IN_BSS
));
1445 rt2x00_set_field32(®
, RXCSR0_DROP_TODS
,
1446 !(*total_flags
& FIF_PROMISC_IN_BSS
));
1447 rt2x00_set_field32(®
, RXCSR0_DROP_VERSION_ERROR
, 1);
1448 rt2x00pci_register_write(rt2x00dev
, RXCSR0
, reg
);
1451 static int rt2400pci_set_retry_limit(struct ieee80211_hw
*hw
,
1452 u32 short_retry
, u32 long_retry
)
1454 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1457 rt2x00pci_register_read(rt2x00dev
, CSR11
, ®
);
1458 rt2x00_set_field32(®
, CSR11_LONG_RETRY
, long_retry
);
1459 rt2x00_set_field32(®
, CSR11_SHORT_RETRY
, short_retry
);
1460 rt2x00pci_register_write(rt2x00dev
, CSR11
, reg
);
1465 static int rt2400pci_conf_tx(struct ieee80211_hw
*hw
,
1467 const struct ieee80211_tx_queue_params
*params
)
1469 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1472 * We don't support variating cw_min and cw_max variables
1473 * per queue. So by default we only configure the TX queue,
1474 * and ignore all other configurations.
1476 if (queue
!= IEEE80211_TX_QUEUE_DATA0
)
1479 if (rt2x00mac_conf_tx(hw
, queue
, params
))
1483 * Write configuration to register.
1485 rt2400pci_config_cw(rt2x00dev
,
1486 rt2x00dev
->tx
->cw_min
, rt2x00dev
->tx
->cw_max
);
1491 static u64
rt2400pci_get_tsf(struct ieee80211_hw
*hw
)
1493 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1497 rt2x00pci_register_read(rt2x00dev
, CSR17
, ®
);
1498 tsf
= (u64
) rt2x00_get_field32(reg
, CSR17_HIGH_TSFTIMER
) << 32;
1499 rt2x00pci_register_read(rt2x00dev
, CSR16
, ®
);
1500 tsf
|= rt2x00_get_field32(reg
, CSR16_LOW_TSFTIMER
);
1505 static void rt2400pci_reset_tsf(struct ieee80211_hw
*hw
)
1507 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1509 rt2x00pci_register_write(rt2x00dev
, CSR16
, 0);
1510 rt2x00pci_register_write(rt2x00dev
, CSR17
, 0);
1513 static int rt2400pci_beacon_update(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
1514 struct ieee80211_tx_control
*control
)
1516 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1517 struct rt2x00_intf
*intf
= vif_to_intf(control
->vif
);
1518 struct queue_entry_priv_pci_tx
*priv_tx
;
1519 struct skb_frame_desc
*skbdesc
;
1521 if (unlikely(!intf
->beacon
))
1524 priv_tx
= intf
->beacon
->priv_data
;
1527 * Fill in skb descriptor
1529 skbdesc
= get_skb_frame_desc(skb
);
1530 memset(skbdesc
, 0, sizeof(*skbdesc
));
1531 skbdesc
->data
= skb
->data
;
1532 skbdesc
->data_len
= skb
->len
;
1533 skbdesc
->desc
= priv_tx
->desc
;
1534 skbdesc
->desc_len
= intf
->beacon
->queue
->desc_size
;
1535 skbdesc
->entry
= intf
->beacon
;
1538 * mac80211 doesn't provide the control->queue variable
1539 * for beacons. Set our own queue identification so
1540 * it can be used during descriptor initialization.
1542 control
->queue
= RT2X00_BCN_QUEUE_BEACON
;
1543 rt2x00lib_write_tx_desc(rt2x00dev
, skb
, control
);
1546 * Enable beacon generation.
1547 * Write entire beacon with descriptor to register,
1548 * and kick the beacon generator.
1550 memcpy(priv_tx
->data
, skb
->data
, skb
->len
);
1551 rt2x00dev
->ops
->lib
->kick_tx_queue(rt2x00dev
, control
->queue
);
1556 static int rt2400pci_tx_last_beacon(struct ieee80211_hw
*hw
)
1558 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1561 rt2x00pci_register_read(rt2x00dev
, CSR15
, ®
);
1562 return rt2x00_get_field32(reg
, CSR15_BEACON_SENT
);
1565 static const struct ieee80211_ops rt2400pci_mac80211_ops
= {
1567 .start
= rt2x00mac_start
,
1568 .stop
= rt2x00mac_stop
,
1569 .add_interface
= rt2x00mac_add_interface
,
1570 .remove_interface
= rt2x00mac_remove_interface
,
1571 .config
= rt2x00mac_config
,
1572 .config_interface
= rt2x00mac_config_interface
,
1573 .configure_filter
= rt2400pci_configure_filter
,
1574 .get_stats
= rt2x00mac_get_stats
,
1575 .set_retry_limit
= rt2400pci_set_retry_limit
,
1576 .bss_info_changed
= rt2x00mac_bss_info_changed
,
1577 .conf_tx
= rt2400pci_conf_tx
,
1578 .get_tx_stats
= rt2x00mac_get_tx_stats
,
1579 .get_tsf
= rt2400pci_get_tsf
,
1580 .reset_tsf
= rt2400pci_reset_tsf
,
1581 .beacon_update
= rt2400pci_beacon_update
,
1582 .tx_last_beacon
= rt2400pci_tx_last_beacon
,
1585 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops
= {
1586 .irq_handler
= rt2400pci_interrupt
,
1587 .probe_hw
= rt2400pci_probe_hw
,
1588 .initialize
= rt2x00pci_initialize
,
1589 .uninitialize
= rt2x00pci_uninitialize
,
1590 .init_rxentry
= rt2400pci_init_rxentry
,
1591 .init_txentry
= rt2400pci_init_txentry
,
1592 .set_device_state
= rt2400pci_set_device_state
,
1593 .rfkill_poll
= rt2400pci_rfkill_poll
,
1594 .link_stats
= rt2400pci_link_stats
,
1595 .reset_tuner
= rt2400pci_reset_tuner
,
1596 .link_tuner
= rt2400pci_link_tuner
,
1597 .write_tx_desc
= rt2400pci_write_tx_desc
,
1598 .write_tx_data
= rt2x00pci_write_tx_data
,
1599 .kick_tx_queue
= rt2400pci_kick_tx_queue
,
1600 .fill_rxdone
= rt2400pci_fill_rxdone
,
1601 .config_intf
= rt2400pci_config_intf
,
1602 .config_preamble
= rt2400pci_config_preamble
,
1603 .config
= rt2400pci_config
,
1606 static const struct data_queue_desc rt2400pci_queue_rx
= {
1607 .entry_num
= RX_ENTRIES
,
1608 .data_size
= DATA_FRAME_SIZE
,
1609 .desc_size
= RXD_DESC_SIZE
,
1610 .priv_size
= sizeof(struct queue_entry_priv_pci_rx
),
1613 static const struct data_queue_desc rt2400pci_queue_tx
= {
1614 .entry_num
= TX_ENTRIES
,
1615 .data_size
= DATA_FRAME_SIZE
,
1616 .desc_size
= TXD_DESC_SIZE
,
1617 .priv_size
= sizeof(struct queue_entry_priv_pci_tx
),
1620 static const struct data_queue_desc rt2400pci_queue_bcn
= {
1621 .entry_num
= BEACON_ENTRIES
,
1622 .data_size
= MGMT_FRAME_SIZE
,
1623 .desc_size
= TXD_DESC_SIZE
,
1624 .priv_size
= sizeof(struct queue_entry_priv_pci_tx
),
1627 static const struct data_queue_desc rt2400pci_queue_atim
= {
1628 .entry_num
= ATIM_ENTRIES
,
1629 .data_size
= DATA_FRAME_SIZE
,
1630 .desc_size
= TXD_DESC_SIZE
,
1631 .priv_size
= sizeof(struct queue_entry_priv_pci_tx
),
1634 static const struct rt2x00_ops rt2400pci_ops
= {
1635 .name
= KBUILD_MODNAME
,
1638 .eeprom_size
= EEPROM_SIZE
,
1640 .rx
= &rt2400pci_queue_rx
,
1641 .tx
= &rt2400pci_queue_tx
,
1642 .bcn
= &rt2400pci_queue_bcn
,
1643 .atim
= &rt2400pci_queue_atim
,
1644 .lib
= &rt2400pci_rt2x00_ops
,
1645 .hw
= &rt2400pci_mac80211_ops
,
1646 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1647 .debugfs
= &rt2400pci_rt2x00debug
,
1648 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1652 * RT2400pci module information.
1654 static struct pci_device_id rt2400pci_device_table
[] = {
1655 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops
) },
1659 MODULE_AUTHOR(DRV_PROJECT
);
1660 MODULE_VERSION(DRV_VERSION
);
1661 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1662 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1663 MODULE_DEVICE_TABLE(pci
, rt2400pci_device_table
);
1664 MODULE_LICENSE("GPL");
1666 static struct pci_driver rt2400pci_driver
= {
1667 .name
= KBUILD_MODNAME
,
1668 .id_table
= rt2400pci_device_table
,
1669 .probe
= rt2x00pci_probe
,
1670 .remove
= __devexit_p(rt2x00pci_remove
),
1671 .suspend
= rt2x00pci_suspend
,
1672 .resume
= rt2x00pci_resume
,
1675 static int __init
rt2400pci_init(void)
1677 return pci_register_driver(&rt2400pci_driver
);
1680 static void __exit
rt2400pci_exit(void)
1682 pci_unregister_driver(&rt2400pci_driver
);
1685 module_init(rt2400pci_init
);
1686 module_exit(rt2400pci_exit
);