2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34 #include <linux/slab.h>
37 #include "rt2x00pci.h"
38 #include "rt2500pci.h"
42 * All access to the CSR registers will go through the methods
43 * rt2x00pci_register_read and rt2x00pci_register_write.
44 * BBP and RF register require indirect register access,
45 * and use the CSR registers BBPCSR and RFCSR to achieve this.
46 * These indirect registers work with busy bits,
47 * and we will try maximal REGISTER_BUSY_COUNT times to access
48 * the register while taking a REGISTER_BUSY_DELAY us delay
49 * between each attampt. When the busy bit is still set at that time,
50 * the access attempt is considered to have failed,
51 * and we will print an error.
53 #define WAIT_FOR_BBP(__dev, __reg) \
54 rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
55 #define WAIT_FOR_RF(__dev, __reg) \
56 rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
58 static void rt2500pci_bbp_write(struct rt2x00_dev
*rt2x00dev
,
59 const unsigned int word
, const u8 value
)
63 mutex_lock(&rt2x00dev
->csr_mutex
);
66 * Wait until the BBP becomes available, afterwards we
67 * can safely write the new data into the register.
69 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
71 rt2x00_set_field32(®
, BBPCSR_VALUE
, value
);
72 rt2x00_set_field32(®
, BBPCSR_REGNUM
, word
);
73 rt2x00_set_field32(®
, BBPCSR_BUSY
, 1);
74 rt2x00_set_field32(®
, BBPCSR_WRITE_CONTROL
, 1);
76 rt2x00pci_register_write(rt2x00dev
, BBPCSR
, reg
);
79 mutex_unlock(&rt2x00dev
->csr_mutex
);
82 static void rt2500pci_bbp_read(struct rt2x00_dev
*rt2x00dev
,
83 const unsigned int word
, u8
*value
)
87 mutex_lock(&rt2x00dev
->csr_mutex
);
90 * Wait until the BBP becomes available, afterwards we
91 * can safely write the read request into the register.
92 * After the data has been written, we wait until hardware
93 * returns the correct value, if at any time the register
94 * doesn't become available in time, reg will be 0xffffffff
95 * which means we return 0xff to the caller.
97 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
99 rt2x00_set_field32(®
, BBPCSR_REGNUM
, word
);
100 rt2x00_set_field32(®
, BBPCSR_BUSY
, 1);
101 rt2x00_set_field32(®
, BBPCSR_WRITE_CONTROL
, 0);
103 rt2x00pci_register_write(rt2x00dev
, BBPCSR
, reg
);
105 WAIT_FOR_BBP(rt2x00dev
, ®
);
108 *value
= rt2x00_get_field32(reg
, BBPCSR_VALUE
);
110 mutex_unlock(&rt2x00dev
->csr_mutex
);
113 static void rt2500pci_rf_write(struct rt2x00_dev
*rt2x00dev
,
114 const unsigned int word
, const u32 value
)
118 mutex_lock(&rt2x00dev
->csr_mutex
);
121 * Wait until the RF becomes available, afterwards we
122 * can safely write the new data into the register.
124 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
126 rt2x00_set_field32(®
, RFCSR_VALUE
, value
);
127 rt2x00_set_field32(®
, RFCSR_NUMBER_OF_BITS
, 20);
128 rt2x00_set_field32(®
, RFCSR_IF_SELECT
, 0);
129 rt2x00_set_field32(®
, RFCSR_BUSY
, 1);
131 rt2x00pci_register_write(rt2x00dev
, RFCSR
, reg
);
132 rt2x00_rf_write(rt2x00dev
, word
, value
);
135 mutex_unlock(&rt2x00dev
->csr_mutex
);
138 static void rt2500pci_eepromregister_read(struct eeprom_93cx6
*eeprom
)
140 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
143 rt2x00pci_register_read(rt2x00dev
, CSR21
, ®
);
145 eeprom
->reg_data_in
= !!rt2x00_get_field32(reg
, CSR21_EEPROM_DATA_IN
);
146 eeprom
->reg_data_out
= !!rt2x00_get_field32(reg
, CSR21_EEPROM_DATA_OUT
);
147 eeprom
->reg_data_clock
=
148 !!rt2x00_get_field32(reg
, CSR21_EEPROM_DATA_CLOCK
);
149 eeprom
->reg_chip_select
=
150 !!rt2x00_get_field32(reg
, CSR21_EEPROM_CHIP_SELECT
);
153 static void rt2500pci_eepromregister_write(struct eeprom_93cx6
*eeprom
)
155 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
158 rt2x00_set_field32(®
, CSR21_EEPROM_DATA_IN
, !!eeprom
->reg_data_in
);
159 rt2x00_set_field32(®
, CSR21_EEPROM_DATA_OUT
, !!eeprom
->reg_data_out
);
160 rt2x00_set_field32(®
, CSR21_EEPROM_DATA_CLOCK
,
161 !!eeprom
->reg_data_clock
);
162 rt2x00_set_field32(®
, CSR21_EEPROM_CHIP_SELECT
,
163 !!eeprom
->reg_chip_select
);
165 rt2x00pci_register_write(rt2x00dev
, CSR21
, reg
);
168 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
169 static const struct rt2x00debug rt2500pci_rt2x00debug
= {
170 .owner
= THIS_MODULE
,
172 .read
= rt2x00pci_register_read
,
173 .write
= rt2x00pci_register_write
,
174 .flags
= RT2X00DEBUGFS_OFFSET
,
175 .word_base
= CSR_REG_BASE
,
176 .word_size
= sizeof(u32
),
177 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
180 .read
= rt2x00_eeprom_read
,
181 .write
= rt2x00_eeprom_write
,
182 .word_base
= EEPROM_BASE
,
183 .word_size
= sizeof(u16
),
184 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
187 .read
= rt2500pci_bbp_read
,
188 .write
= rt2500pci_bbp_write
,
189 .word_base
= BBP_BASE
,
190 .word_size
= sizeof(u8
),
191 .word_count
= BBP_SIZE
/ sizeof(u8
),
194 .read
= rt2x00_rf_read
,
195 .write
= rt2500pci_rf_write
,
196 .word_base
= RF_BASE
,
197 .word_size
= sizeof(u32
),
198 .word_count
= RF_SIZE
/ sizeof(u32
),
201 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
203 static int rt2500pci_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
207 rt2x00pci_register_read(rt2x00dev
, GPIOCSR
, ®
);
208 return rt2x00_get_field32(reg
, GPIOCSR_BIT0
);
211 #ifdef CONFIG_RT2X00_LIB_LEDS
212 static void rt2500pci_brightness_set(struct led_classdev
*led_cdev
,
213 enum led_brightness brightness
)
215 struct rt2x00_led
*led
=
216 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
217 unsigned int enabled
= brightness
!= LED_OFF
;
220 rt2x00pci_register_read(led
->rt2x00dev
, LEDCSR
, ®
);
222 if (led
->type
== LED_TYPE_RADIO
|| led
->type
== LED_TYPE_ASSOC
)
223 rt2x00_set_field32(®
, LEDCSR_LINK
, enabled
);
224 else if (led
->type
== LED_TYPE_ACTIVITY
)
225 rt2x00_set_field32(®
, LEDCSR_ACTIVITY
, enabled
);
227 rt2x00pci_register_write(led
->rt2x00dev
, LEDCSR
, reg
);
230 static int rt2500pci_blink_set(struct led_classdev
*led_cdev
,
231 unsigned long *delay_on
,
232 unsigned long *delay_off
)
234 struct rt2x00_led
*led
=
235 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
238 rt2x00pci_register_read(led
->rt2x00dev
, LEDCSR
, ®
);
239 rt2x00_set_field32(®
, LEDCSR_ON_PERIOD
, *delay_on
);
240 rt2x00_set_field32(®
, LEDCSR_OFF_PERIOD
, *delay_off
);
241 rt2x00pci_register_write(led
->rt2x00dev
, LEDCSR
, reg
);
246 static void rt2500pci_init_led(struct rt2x00_dev
*rt2x00dev
,
247 struct rt2x00_led
*led
,
250 led
->rt2x00dev
= rt2x00dev
;
252 led
->led_dev
.brightness_set
= rt2500pci_brightness_set
;
253 led
->led_dev
.blink_set
= rt2500pci_blink_set
;
254 led
->flags
= LED_INITIALIZED
;
256 #endif /* CONFIG_RT2X00_LIB_LEDS */
259 * Configuration handlers.
261 static void rt2500pci_config_filter(struct rt2x00_dev
*rt2x00dev
,
262 const unsigned int filter_flags
)
267 * Start configuration steps.
268 * Note that the version error will always be dropped
269 * and broadcast frames will always be accepted since
270 * there is no filter for it at this time.
272 rt2x00pci_register_read(rt2x00dev
, RXCSR0
, ®
);
273 rt2x00_set_field32(®
, RXCSR0_DROP_CRC
,
274 !(filter_flags
& FIF_FCSFAIL
));
275 rt2x00_set_field32(®
, RXCSR0_DROP_PHYSICAL
,
276 !(filter_flags
& FIF_PLCPFAIL
));
277 rt2x00_set_field32(®
, RXCSR0_DROP_CONTROL
,
278 !(filter_flags
& FIF_CONTROL
));
279 rt2x00_set_field32(®
, RXCSR0_DROP_NOT_TO_ME
,
280 !(filter_flags
& FIF_PROMISC_IN_BSS
));
281 rt2x00_set_field32(®
, RXCSR0_DROP_TODS
,
282 !(filter_flags
& FIF_PROMISC_IN_BSS
) &&
283 !rt2x00dev
->intf_ap_count
);
284 rt2x00_set_field32(®
, RXCSR0_DROP_VERSION_ERROR
, 1);
285 rt2x00_set_field32(®
, RXCSR0_DROP_MCAST
,
286 !(filter_flags
& FIF_ALLMULTI
));
287 rt2x00_set_field32(®
, RXCSR0_DROP_BCAST
, 0);
288 rt2x00pci_register_write(rt2x00dev
, RXCSR0
, reg
);
291 static void rt2500pci_config_intf(struct rt2x00_dev
*rt2x00dev
,
292 struct rt2x00_intf
*intf
,
293 struct rt2x00intf_conf
*conf
,
294 const unsigned int flags
)
296 struct data_queue
*queue
= rt2x00queue_get_queue(rt2x00dev
, QID_BEACON
);
297 unsigned int bcn_preload
;
300 if (flags
& CONFIG_UPDATE_TYPE
) {
302 * Enable beacon config
304 bcn_preload
= PREAMBLE
+ GET_DURATION(IEEE80211_HEADER
, 20);
305 rt2x00pci_register_read(rt2x00dev
, BCNCSR1
, ®
);
306 rt2x00_set_field32(®
, BCNCSR1_PRELOAD
, bcn_preload
);
307 rt2x00_set_field32(®
, BCNCSR1_BEACON_CWMIN
, queue
->cw_min
);
308 rt2x00pci_register_write(rt2x00dev
, BCNCSR1
, reg
);
311 * Enable synchronisation.
313 rt2x00pci_register_read(rt2x00dev
, CSR14
, ®
);
314 rt2x00_set_field32(®
, CSR14_TSF_COUNT
, 1);
315 rt2x00_set_field32(®
, CSR14_TSF_SYNC
, conf
->sync
);
316 rt2x00_set_field32(®
, CSR14_TBCN
, 1);
317 rt2x00pci_register_write(rt2x00dev
, CSR14
, reg
);
320 if (flags
& CONFIG_UPDATE_MAC
)
321 rt2x00pci_register_multiwrite(rt2x00dev
, CSR3
,
322 conf
->mac
, sizeof(conf
->mac
));
324 if (flags
& CONFIG_UPDATE_BSSID
)
325 rt2x00pci_register_multiwrite(rt2x00dev
, CSR5
,
326 conf
->bssid
, sizeof(conf
->bssid
));
329 static void rt2500pci_config_erp(struct rt2x00_dev
*rt2x00dev
,
330 struct rt2x00lib_erp
*erp
)
336 * When short preamble is enabled, we should set bit 0x08
338 preamble_mask
= erp
->short_preamble
<< 3;
340 rt2x00pci_register_read(rt2x00dev
, TXCSR1
, ®
);
341 rt2x00_set_field32(®
, TXCSR1_ACK_TIMEOUT
, 0x162);
342 rt2x00_set_field32(®
, TXCSR1_ACK_CONSUME_TIME
, 0xa2);
343 rt2x00_set_field32(®
, TXCSR1_TSF_OFFSET
, IEEE80211_HEADER
);
344 rt2x00_set_field32(®
, TXCSR1_AUTORESPONDER
, 1);
345 rt2x00pci_register_write(rt2x00dev
, TXCSR1
, reg
);
347 rt2x00pci_register_read(rt2x00dev
, ARCSR2
, ®
);
348 rt2x00_set_field32(®
, ARCSR2_SIGNAL
, 0x00);
349 rt2x00_set_field32(®
, ARCSR2_SERVICE
, 0x04);
350 rt2x00_set_field32(®
, ARCSR2_LENGTH
, GET_DURATION(ACK_SIZE
, 10));
351 rt2x00pci_register_write(rt2x00dev
, ARCSR2
, reg
);
353 rt2x00pci_register_read(rt2x00dev
, ARCSR3
, ®
);
354 rt2x00_set_field32(®
, ARCSR3_SIGNAL
, 0x01 | preamble_mask
);
355 rt2x00_set_field32(®
, ARCSR3_SERVICE
, 0x04);
356 rt2x00_set_field32(®
, ARCSR2_LENGTH
, GET_DURATION(ACK_SIZE
, 20));
357 rt2x00pci_register_write(rt2x00dev
, ARCSR3
, reg
);
359 rt2x00pci_register_read(rt2x00dev
, ARCSR4
, ®
);
360 rt2x00_set_field32(®
, ARCSR4_SIGNAL
, 0x02 | preamble_mask
);
361 rt2x00_set_field32(®
, ARCSR4_SERVICE
, 0x04);
362 rt2x00_set_field32(®
, ARCSR2_LENGTH
, GET_DURATION(ACK_SIZE
, 55));
363 rt2x00pci_register_write(rt2x00dev
, ARCSR4
, reg
);
365 rt2x00pci_register_read(rt2x00dev
, ARCSR5
, ®
);
366 rt2x00_set_field32(®
, ARCSR5_SIGNAL
, 0x03 | preamble_mask
);
367 rt2x00_set_field32(®
, ARCSR5_SERVICE
, 0x84);
368 rt2x00_set_field32(®
, ARCSR2_LENGTH
, GET_DURATION(ACK_SIZE
, 110));
369 rt2x00pci_register_write(rt2x00dev
, ARCSR5
, reg
);
371 rt2x00pci_register_write(rt2x00dev
, ARCSR1
, erp
->basic_rates
);
373 rt2x00pci_register_read(rt2x00dev
, CSR11
, ®
);
374 rt2x00_set_field32(®
, CSR11_SLOT_TIME
, erp
->slot_time
);
375 rt2x00pci_register_write(rt2x00dev
, CSR11
, reg
);
377 rt2x00pci_register_read(rt2x00dev
, CSR12
, ®
);
378 rt2x00_set_field32(®
, CSR12_BEACON_INTERVAL
, erp
->beacon_int
* 16);
379 rt2x00_set_field32(®
, CSR12_CFP_MAX_DURATION
, erp
->beacon_int
* 16);
380 rt2x00pci_register_write(rt2x00dev
, CSR12
, reg
);
382 rt2x00pci_register_read(rt2x00dev
, CSR18
, ®
);
383 rt2x00_set_field32(®
, CSR18_SIFS
, erp
->sifs
);
384 rt2x00_set_field32(®
, CSR18_PIFS
, erp
->pifs
);
385 rt2x00pci_register_write(rt2x00dev
, CSR18
, reg
);
387 rt2x00pci_register_read(rt2x00dev
, CSR19
, ®
);
388 rt2x00_set_field32(®
, CSR19_DIFS
, erp
->difs
);
389 rt2x00_set_field32(®
, CSR19_EIFS
, erp
->eifs
);
390 rt2x00pci_register_write(rt2x00dev
, CSR19
, reg
);
393 static void rt2500pci_config_ant(struct rt2x00_dev
*rt2x00dev
,
394 struct antenna_setup
*ant
)
401 * We should never come here because rt2x00lib is supposed
402 * to catch this and send us the correct antenna explicitely.
404 BUG_ON(ant
->rx
== ANTENNA_SW_DIVERSITY
||
405 ant
->tx
== ANTENNA_SW_DIVERSITY
);
407 rt2x00pci_register_read(rt2x00dev
, BBPCSR1
, ®
);
408 rt2500pci_bbp_read(rt2x00dev
, 14, &r14
);
409 rt2500pci_bbp_read(rt2x00dev
, 2, &r2
);
412 * Configure the TX antenna.
416 rt2x00_set_field8(&r2
, BBP_R2_TX_ANTENNA
, 0);
417 rt2x00_set_field32(®
, BBPCSR1_CCK
, 0);
418 rt2x00_set_field32(®
, BBPCSR1_OFDM
, 0);
422 rt2x00_set_field8(&r2
, BBP_R2_TX_ANTENNA
, 2);
423 rt2x00_set_field32(®
, BBPCSR1_CCK
, 2);
424 rt2x00_set_field32(®
, BBPCSR1_OFDM
, 2);
429 * Configure the RX antenna.
433 rt2x00_set_field8(&r14
, BBP_R14_RX_ANTENNA
, 0);
437 rt2x00_set_field8(&r14
, BBP_R14_RX_ANTENNA
, 2);
442 * RT2525E and RT5222 need to flip TX I/Q
444 if (rt2x00_rf(rt2x00dev
, RF2525E
) || rt2x00_rf(rt2x00dev
, RF5222
)) {
445 rt2x00_set_field8(&r2
, BBP_R2_TX_IQ_FLIP
, 1);
446 rt2x00_set_field32(®
, BBPCSR1_CCK_FLIP
, 1);
447 rt2x00_set_field32(®
, BBPCSR1_OFDM_FLIP
, 1);
450 * RT2525E does not need RX I/Q Flip.
452 if (rt2x00_rf(rt2x00dev
, RF2525E
))
453 rt2x00_set_field8(&r14
, BBP_R14_RX_IQ_FLIP
, 0);
455 rt2x00_set_field32(®
, BBPCSR1_CCK_FLIP
, 0);
456 rt2x00_set_field32(®
, BBPCSR1_OFDM_FLIP
, 0);
459 rt2x00pci_register_write(rt2x00dev
, BBPCSR1
, reg
);
460 rt2500pci_bbp_write(rt2x00dev
, 14, r14
);
461 rt2500pci_bbp_write(rt2x00dev
, 2, r2
);
464 static void rt2500pci_config_channel(struct rt2x00_dev
*rt2x00dev
,
465 struct rf_channel
*rf
, const int txpower
)
472 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER
, TXPOWER_TO_DEV(txpower
));
475 * Switch on tuning bits.
476 * For RT2523 devices we do not need to update the R1 register.
478 if (!rt2x00_rf(rt2x00dev
, RF2523
))
479 rt2x00_set_field32(&rf
->rf1
, RF1_TUNER
, 1);
480 rt2x00_set_field32(&rf
->rf3
, RF3_TUNER
, 1);
483 * For RT2525 we should first set the channel to half band higher.
485 if (rt2x00_rf(rt2x00dev
, RF2525
)) {
486 static const u32 vals
[] = {
487 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
488 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
489 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
490 0x00080d2e, 0x00080d3a
493 rt2500pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
494 rt2500pci_rf_write(rt2x00dev
, 2, vals
[rf
->channel
- 1]);
495 rt2500pci_rf_write(rt2x00dev
, 3, rf
->rf3
);
497 rt2500pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
500 rt2500pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
501 rt2500pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
502 rt2500pci_rf_write(rt2x00dev
, 3, rf
->rf3
);
504 rt2500pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
507 * Channel 14 requires the Japan filter bit to be set.
510 rt2x00_set_field8(&r70
, BBP_R70_JAPAN_FILTER
, rf
->channel
== 14);
511 rt2500pci_bbp_write(rt2x00dev
, 70, r70
);
516 * Switch off tuning bits.
517 * For RT2523 devices we do not need to update the R1 register.
519 if (!rt2x00_rf(rt2x00dev
, RF2523
)) {
520 rt2x00_set_field32(&rf
->rf1
, RF1_TUNER
, 0);
521 rt2500pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
524 rt2x00_set_field32(&rf
->rf3
, RF3_TUNER
, 0);
525 rt2500pci_rf_write(rt2x00dev
, 3, rf
->rf3
);
528 * Clear false CRC during channel switch.
530 rt2x00pci_register_read(rt2x00dev
, CNT0
, &rf
->rf1
);
533 static void rt2500pci_config_txpower(struct rt2x00_dev
*rt2x00dev
,
538 rt2x00_rf_read(rt2x00dev
, 3, &rf3
);
539 rt2x00_set_field32(&rf3
, RF3_TXPOWER
, TXPOWER_TO_DEV(txpower
));
540 rt2500pci_rf_write(rt2x00dev
, 3, rf3
);
543 static void rt2500pci_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
544 struct rt2x00lib_conf
*libconf
)
548 rt2x00pci_register_read(rt2x00dev
, CSR11
, ®
);
549 rt2x00_set_field32(®
, CSR11_LONG_RETRY
,
550 libconf
->conf
->long_frame_max_tx_count
);
551 rt2x00_set_field32(®
, CSR11_SHORT_RETRY
,
552 libconf
->conf
->short_frame_max_tx_count
);
553 rt2x00pci_register_write(rt2x00dev
, CSR11
, reg
);
556 static void rt2500pci_config_ps(struct rt2x00_dev
*rt2x00dev
,
557 struct rt2x00lib_conf
*libconf
)
559 enum dev_state state
=
560 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
561 STATE_SLEEP
: STATE_AWAKE
;
564 if (state
== STATE_SLEEP
) {
565 rt2x00pci_register_read(rt2x00dev
, CSR20
, ®
);
566 rt2x00_set_field32(®
, CSR20_DELAY_AFTER_TBCN
,
567 (rt2x00dev
->beacon_int
- 20) * 16);
568 rt2x00_set_field32(®
, CSR20_TBCN_BEFORE_WAKEUP
,
569 libconf
->conf
->listen_interval
- 1);
571 /* We must first disable autowake before it can be enabled */
572 rt2x00_set_field32(®
, CSR20_AUTOWAKE
, 0);
573 rt2x00pci_register_write(rt2x00dev
, CSR20
, reg
);
575 rt2x00_set_field32(®
, CSR20_AUTOWAKE
, 1);
576 rt2x00pci_register_write(rt2x00dev
, CSR20
, reg
);
578 rt2x00pci_register_read(rt2x00dev
, CSR20
, ®
);
579 rt2x00_set_field32(®
, CSR20_AUTOWAKE
, 0);
580 rt2x00pci_register_write(rt2x00dev
, CSR20
, reg
);
583 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
586 static void rt2500pci_config(struct rt2x00_dev
*rt2x00dev
,
587 struct rt2x00lib_conf
*libconf
,
588 const unsigned int flags
)
590 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
)
591 rt2500pci_config_channel(rt2x00dev
, &libconf
->rf
,
592 libconf
->conf
->power_level
);
593 if ((flags
& IEEE80211_CONF_CHANGE_POWER
) &&
594 !(flags
& IEEE80211_CONF_CHANGE_CHANNEL
))
595 rt2500pci_config_txpower(rt2x00dev
,
596 libconf
->conf
->power_level
);
597 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
598 rt2500pci_config_retry_limit(rt2x00dev
, libconf
);
599 if (flags
& IEEE80211_CONF_CHANGE_PS
)
600 rt2500pci_config_ps(rt2x00dev
, libconf
);
606 static void rt2500pci_link_stats(struct rt2x00_dev
*rt2x00dev
,
607 struct link_qual
*qual
)
612 * Update FCS error count from register.
614 rt2x00pci_register_read(rt2x00dev
, CNT0
, ®
);
615 qual
->rx_failed
= rt2x00_get_field32(reg
, CNT0_FCS_ERROR
);
618 * Update False CCA count from register.
620 rt2x00pci_register_read(rt2x00dev
, CNT3
, ®
);
621 qual
->false_cca
= rt2x00_get_field32(reg
, CNT3_FALSE_CCA
);
624 static inline void rt2500pci_set_vgc(struct rt2x00_dev
*rt2x00dev
,
625 struct link_qual
*qual
, u8 vgc_level
)
627 if (qual
->vgc_level_reg
!= vgc_level
) {
628 rt2500pci_bbp_write(rt2x00dev
, 17, vgc_level
);
629 qual
->vgc_level_reg
= vgc_level
;
633 static void rt2500pci_reset_tuner(struct rt2x00_dev
*rt2x00dev
,
634 struct link_qual
*qual
)
636 rt2500pci_set_vgc(rt2x00dev
, qual
, 0x48);
639 static void rt2500pci_link_tuner(struct rt2x00_dev
*rt2x00dev
,
640 struct link_qual
*qual
, const u32 count
)
643 * To prevent collisions with MAC ASIC on chipsets
644 * up to version C the link tuning should halt after 20
645 * seconds while being associated.
647 if (rt2x00_rev(rt2x00dev
) < RT2560_VERSION_D
&&
648 rt2x00dev
->intf_associated
&& count
> 20)
652 * Chipset versions C and lower should directly continue
653 * to the dynamic CCA tuning. Chipset version D and higher
654 * should go straight to dynamic CCA tuning when they
655 * are not associated.
657 if (rt2x00_rev(rt2x00dev
) < RT2560_VERSION_D
||
658 !rt2x00dev
->intf_associated
)
659 goto dynamic_cca_tune
;
662 * A too low RSSI will cause too much false CCA which will
663 * then corrupt the R17 tuning. To remidy this the tuning should
664 * be stopped (While making sure the R17 value will not exceed limits)
666 if (qual
->rssi
< -80 && count
> 20) {
667 if (qual
->vgc_level_reg
>= 0x41)
668 rt2500pci_set_vgc(rt2x00dev
, qual
, qual
->vgc_level
);
673 * Special big-R17 for short distance
675 if (qual
->rssi
>= -58) {
676 rt2500pci_set_vgc(rt2x00dev
, qual
, 0x50);
681 * Special mid-R17 for middle distance
683 if (qual
->rssi
>= -74) {
684 rt2500pci_set_vgc(rt2x00dev
, qual
, 0x41);
689 * Leave short or middle distance condition, restore r17
690 * to the dynamic tuning range.
692 if (qual
->vgc_level_reg
>= 0x41) {
693 rt2500pci_set_vgc(rt2x00dev
, qual
, qual
->vgc_level
);
700 * R17 is inside the dynamic tuning range,
701 * start tuning the link based on the false cca counter.
703 if (qual
->false_cca
> 512 && qual
->vgc_level_reg
< 0x40) {
704 rt2500pci_set_vgc(rt2x00dev
, qual
, ++qual
->vgc_level_reg
);
705 qual
->vgc_level
= qual
->vgc_level_reg
;
706 } else if (qual
->false_cca
< 100 && qual
->vgc_level_reg
> 0x32) {
707 rt2500pci_set_vgc(rt2x00dev
, qual
, --qual
->vgc_level_reg
);
708 qual
->vgc_level
= qual
->vgc_level_reg
;
713 * Initialization functions.
715 static bool rt2500pci_get_entry_state(struct queue_entry
*entry
)
717 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
720 if (entry
->queue
->qid
== QID_RX
) {
721 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
723 return rt2x00_get_field32(word
, RXD_W0_OWNER_NIC
);
725 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
727 return (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
728 rt2x00_get_field32(word
, TXD_W0_VALID
));
732 static void rt2500pci_clear_entry(struct queue_entry
*entry
)
734 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
735 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
738 if (entry
->queue
->qid
== QID_RX
) {
739 rt2x00_desc_read(entry_priv
->desc
, 1, &word
);
740 rt2x00_set_field32(&word
, RXD_W1_BUFFER_ADDRESS
, skbdesc
->skb_dma
);
741 rt2x00_desc_write(entry_priv
->desc
, 1, word
);
743 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
744 rt2x00_set_field32(&word
, RXD_W0_OWNER_NIC
, 1);
745 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
747 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
748 rt2x00_set_field32(&word
, TXD_W0_VALID
, 0);
749 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 0);
750 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
754 static int rt2500pci_init_queues(struct rt2x00_dev
*rt2x00dev
)
756 struct queue_entry_priv_pci
*entry_priv
;
760 * Initialize registers.
762 rt2x00pci_register_read(rt2x00dev
, TXCSR2
, ®
);
763 rt2x00_set_field32(®
, TXCSR2_TXD_SIZE
, rt2x00dev
->tx
[0].desc_size
);
764 rt2x00_set_field32(®
, TXCSR2_NUM_TXD
, rt2x00dev
->tx
[1].limit
);
765 rt2x00_set_field32(®
, TXCSR2_NUM_ATIM
, rt2x00dev
->bcn
[1].limit
);
766 rt2x00_set_field32(®
, TXCSR2_NUM_PRIO
, rt2x00dev
->tx
[0].limit
);
767 rt2x00pci_register_write(rt2x00dev
, TXCSR2
, reg
);
769 entry_priv
= rt2x00dev
->tx
[1].entries
[0].priv_data
;
770 rt2x00pci_register_read(rt2x00dev
, TXCSR3
, ®
);
771 rt2x00_set_field32(®
, TXCSR3_TX_RING_REGISTER
,
772 entry_priv
->desc_dma
);
773 rt2x00pci_register_write(rt2x00dev
, TXCSR3
, reg
);
775 entry_priv
= rt2x00dev
->tx
[0].entries
[0].priv_data
;
776 rt2x00pci_register_read(rt2x00dev
, TXCSR5
, ®
);
777 rt2x00_set_field32(®
, TXCSR5_PRIO_RING_REGISTER
,
778 entry_priv
->desc_dma
);
779 rt2x00pci_register_write(rt2x00dev
, TXCSR5
, reg
);
781 entry_priv
= rt2x00dev
->bcn
[1].entries
[0].priv_data
;
782 rt2x00pci_register_read(rt2x00dev
, TXCSR4
, ®
);
783 rt2x00_set_field32(®
, TXCSR4_ATIM_RING_REGISTER
,
784 entry_priv
->desc_dma
);
785 rt2x00pci_register_write(rt2x00dev
, TXCSR4
, reg
);
787 entry_priv
= rt2x00dev
->bcn
[0].entries
[0].priv_data
;
788 rt2x00pci_register_read(rt2x00dev
, TXCSR6
, ®
);
789 rt2x00_set_field32(®
, TXCSR6_BEACON_RING_REGISTER
,
790 entry_priv
->desc_dma
);
791 rt2x00pci_register_write(rt2x00dev
, TXCSR6
, reg
);
793 rt2x00pci_register_read(rt2x00dev
, RXCSR1
, ®
);
794 rt2x00_set_field32(®
, RXCSR1_RXD_SIZE
, rt2x00dev
->rx
->desc_size
);
795 rt2x00_set_field32(®
, RXCSR1_NUM_RXD
, rt2x00dev
->rx
->limit
);
796 rt2x00pci_register_write(rt2x00dev
, RXCSR1
, reg
);
798 entry_priv
= rt2x00dev
->rx
->entries
[0].priv_data
;
799 rt2x00pci_register_read(rt2x00dev
, RXCSR2
, ®
);
800 rt2x00_set_field32(®
, RXCSR2_RX_RING_REGISTER
,
801 entry_priv
->desc_dma
);
802 rt2x00pci_register_write(rt2x00dev
, RXCSR2
, reg
);
807 static int rt2500pci_init_registers(struct rt2x00_dev
*rt2x00dev
)
811 rt2x00pci_register_write(rt2x00dev
, PSCSR0
, 0x00020002);
812 rt2x00pci_register_write(rt2x00dev
, PSCSR1
, 0x00000002);
813 rt2x00pci_register_write(rt2x00dev
, PSCSR2
, 0x00020002);
814 rt2x00pci_register_write(rt2x00dev
, PSCSR3
, 0x00000002);
816 rt2x00pci_register_read(rt2x00dev
, TIMECSR
, ®
);
817 rt2x00_set_field32(®
, TIMECSR_US_COUNT
, 33);
818 rt2x00_set_field32(®
, TIMECSR_US_64_COUNT
, 63);
819 rt2x00_set_field32(®
, TIMECSR_BEACON_EXPECT
, 0);
820 rt2x00pci_register_write(rt2x00dev
, TIMECSR
, reg
);
822 rt2x00pci_register_read(rt2x00dev
, CSR9
, ®
);
823 rt2x00_set_field32(®
, CSR9_MAX_FRAME_UNIT
,
824 rt2x00dev
->rx
->data_size
/ 128);
825 rt2x00pci_register_write(rt2x00dev
, CSR9
, reg
);
828 * Always use CWmin and CWmax set in descriptor.
830 rt2x00pci_register_read(rt2x00dev
, CSR11
, ®
);
831 rt2x00_set_field32(®
, CSR11_CW_SELECT
, 0);
832 rt2x00pci_register_write(rt2x00dev
, CSR11
, reg
);
834 rt2x00pci_register_read(rt2x00dev
, CSR14
, ®
);
835 rt2x00_set_field32(®
, CSR14_TSF_COUNT
, 0);
836 rt2x00_set_field32(®
, CSR14_TSF_SYNC
, 0);
837 rt2x00_set_field32(®
, CSR14_TBCN
, 0);
838 rt2x00_set_field32(®
, CSR14_TCFP
, 0);
839 rt2x00_set_field32(®
, CSR14_TATIMW
, 0);
840 rt2x00_set_field32(®
, CSR14_BEACON_GEN
, 0);
841 rt2x00_set_field32(®
, CSR14_CFP_COUNT_PRELOAD
, 0);
842 rt2x00_set_field32(®
, CSR14_TBCM_PRELOAD
, 0);
843 rt2x00pci_register_write(rt2x00dev
, CSR14
, reg
);
845 rt2x00pci_register_write(rt2x00dev
, CNT3
, 0);
847 rt2x00pci_register_read(rt2x00dev
, TXCSR8
, ®
);
848 rt2x00_set_field32(®
, TXCSR8_BBP_ID0
, 10);
849 rt2x00_set_field32(®
, TXCSR8_BBP_ID0_VALID
, 1);
850 rt2x00_set_field32(®
, TXCSR8_BBP_ID1
, 11);
851 rt2x00_set_field32(®
, TXCSR8_BBP_ID1_VALID
, 1);
852 rt2x00_set_field32(®
, TXCSR8_BBP_ID2
, 13);
853 rt2x00_set_field32(®
, TXCSR8_BBP_ID2_VALID
, 1);
854 rt2x00_set_field32(®
, TXCSR8_BBP_ID3
, 12);
855 rt2x00_set_field32(®
, TXCSR8_BBP_ID3_VALID
, 1);
856 rt2x00pci_register_write(rt2x00dev
, TXCSR8
, reg
);
858 rt2x00pci_register_read(rt2x00dev
, ARTCSR0
, ®
);
859 rt2x00_set_field32(®
, ARTCSR0_ACK_CTS_1MBS
, 112);
860 rt2x00_set_field32(®
, ARTCSR0_ACK_CTS_2MBS
, 56);
861 rt2x00_set_field32(®
, ARTCSR0_ACK_CTS_5_5MBS
, 20);
862 rt2x00_set_field32(®
, ARTCSR0_ACK_CTS_11MBS
, 10);
863 rt2x00pci_register_write(rt2x00dev
, ARTCSR0
, reg
);
865 rt2x00pci_register_read(rt2x00dev
, ARTCSR1
, ®
);
866 rt2x00_set_field32(®
, ARTCSR1_ACK_CTS_6MBS
, 45);
867 rt2x00_set_field32(®
, ARTCSR1_ACK_CTS_9MBS
, 37);
868 rt2x00_set_field32(®
, ARTCSR1_ACK_CTS_12MBS
, 33);
869 rt2x00_set_field32(®
, ARTCSR1_ACK_CTS_18MBS
, 29);
870 rt2x00pci_register_write(rt2x00dev
, ARTCSR1
, reg
);
872 rt2x00pci_register_read(rt2x00dev
, ARTCSR2
, ®
);
873 rt2x00_set_field32(®
, ARTCSR2_ACK_CTS_24MBS
, 29);
874 rt2x00_set_field32(®
, ARTCSR2_ACK_CTS_36MBS
, 25);
875 rt2x00_set_field32(®
, ARTCSR2_ACK_CTS_48MBS
, 25);
876 rt2x00_set_field32(®
, ARTCSR2_ACK_CTS_54MBS
, 25);
877 rt2x00pci_register_write(rt2x00dev
, ARTCSR2
, reg
);
879 rt2x00pci_register_read(rt2x00dev
, RXCSR3
, ®
);
880 rt2x00_set_field32(®
, RXCSR3_BBP_ID0
, 47); /* CCK Signal */
881 rt2x00_set_field32(®
, RXCSR3_BBP_ID0_VALID
, 1);
882 rt2x00_set_field32(®
, RXCSR3_BBP_ID1
, 51); /* Rssi */
883 rt2x00_set_field32(®
, RXCSR3_BBP_ID1_VALID
, 1);
884 rt2x00_set_field32(®
, RXCSR3_BBP_ID2
, 42); /* OFDM Rate */
885 rt2x00_set_field32(®
, RXCSR3_BBP_ID2_VALID
, 1);
886 rt2x00_set_field32(®
, RXCSR3_BBP_ID3
, 51); /* RSSI */
887 rt2x00_set_field32(®
, RXCSR3_BBP_ID3_VALID
, 1);
888 rt2x00pci_register_write(rt2x00dev
, RXCSR3
, reg
);
890 rt2x00pci_register_read(rt2x00dev
, PCICSR
, ®
);
891 rt2x00_set_field32(®
, PCICSR_BIG_ENDIAN
, 0);
892 rt2x00_set_field32(®
, PCICSR_RX_TRESHOLD
, 0);
893 rt2x00_set_field32(®
, PCICSR_TX_TRESHOLD
, 3);
894 rt2x00_set_field32(®
, PCICSR_BURST_LENTH
, 1);
895 rt2x00_set_field32(®
, PCICSR_ENABLE_CLK
, 1);
896 rt2x00_set_field32(®
, PCICSR_READ_MULTIPLE
, 1);
897 rt2x00_set_field32(®
, PCICSR_WRITE_INVALID
, 1);
898 rt2x00pci_register_write(rt2x00dev
, PCICSR
, reg
);
900 rt2x00pci_register_write(rt2x00dev
, PWRCSR0
, 0x3f3b3100);
902 rt2x00pci_register_write(rt2x00dev
, GPIOCSR
, 0x0000ff00);
903 rt2x00pci_register_write(rt2x00dev
, TESTCSR
, 0x000000f0);
905 if (rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, STATE_AWAKE
))
908 rt2x00pci_register_write(rt2x00dev
, MACCSR0
, 0x00213223);
909 rt2x00pci_register_write(rt2x00dev
, MACCSR1
, 0x00235518);
911 rt2x00pci_register_read(rt2x00dev
, MACCSR2
, ®
);
912 rt2x00_set_field32(®
, MACCSR2_DELAY
, 64);
913 rt2x00pci_register_write(rt2x00dev
, MACCSR2
, reg
);
915 rt2x00pci_register_read(rt2x00dev
, RALINKCSR
, ®
);
916 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_DATA0
, 17);
917 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_ID0
, 26);
918 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_VALID0
, 1);
919 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_DATA1
, 0);
920 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_ID1
, 26);
921 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_VALID1
, 1);
922 rt2x00pci_register_write(rt2x00dev
, RALINKCSR
, reg
);
924 rt2x00pci_register_write(rt2x00dev
, BBPCSR1
, 0x82188200);
926 rt2x00pci_register_write(rt2x00dev
, TXACKCSR0
, 0x00000020);
928 rt2x00pci_register_read(rt2x00dev
, CSR1
, ®
);
929 rt2x00_set_field32(®
, CSR1_SOFT_RESET
, 1);
930 rt2x00_set_field32(®
, CSR1_BBP_RESET
, 0);
931 rt2x00_set_field32(®
, CSR1_HOST_READY
, 0);
932 rt2x00pci_register_write(rt2x00dev
, CSR1
, reg
);
934 rt2x00pci_register_read(rt2x00dev
, CSR1
, ®
);
935 rt2x00_set_field32(®
, CSR1_SOFT_RESET
, 0);
936 rt2x00_set_field32(®
, CSR1_HOST_READY
, 1);
937 rt2x00pci_register_write(rt2x00dev
, CSR1
, reg
);
940 * We must clear the FCS and FIFO error count.
941 * These registers are cleared on read,
942 * so we may pass a useless variable to store the value.
944 rt2x00pci_register_read(rt2x00dev
, CNT0
, ®
);
945 rt2x00pci_register_read(rt2x00dev
, CNT4
, ®
);
950 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
955 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
956 rt2500pci_bbp_read(rt2x00dev
, 0, &value
);
957 if ((value
!= 0xff) && (value
!= 0x00))
959 udelay(REGISTER_BUSY_DELAY
);
962 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
966 static int rt2500pci_init_bbp(struct rt2x00_dev
*rt2x00dev
)
973 if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev
)))
976 rt2500pci_bbp_write(rt2x00dev
, 3, 0x02);
977 rt2500pci_bbp_write(rt2x00dev
, 4, 0x19);
978 rt2500pci_bbp_write(rt2x00dev
, 14, 0x1c);
979 rt2500pci_bbp_write(rt2x00dev
, 15, 0x30);
980 rt2500pci_bbp_write(rt2x00dev
, 16, 0xac);
981 rt2500pci_bbp_write(rt2x00dev
, 18, 0x18);
982 rt2500pci_bbp_write(rt2x00dev
, 19, 0xff);
983 rt2500pci_bbp_write(rt2x00dev
, 20, 0x1e);
984 rt2500pci_bbp_write(rt2x00dev
, 21, 0x08);
985 rt2500pci_bbp_write(rt2x00dev
, 22, 0x08);
986 rt2500pci_bbp_write(rt2x00dev
, 23, 0x08);
987 rt2500pci_bbp_write(rt2x00dev
, 24, 0x70);
988 rt2500pci_bbp_write(rt2x00dev
, 25, 0x40);
989 rt2500pci_bbp_write(rt2x00dev
, 26, 0x08);
990 rt2500pci_bbp_write(rt2x00dev
, 27, 0x23);
991 rt2500pci_bbp_write(rt2x00dev
, 30, 0x10);
992 rt2500pci_bbp_write(rt2x00dev
, 31, 0x2b);
993 rt2500pci_bbp_write(rt2x00dev
, 32, 0xb9);
994 rt2500pci_bbp_write(rt2x00dev
, 34, 0x12);
995 rt2500pci_bbp_write(rt2x00dev
, 35, 0x50);
996 rt2500pci_bbp_write(rt2x00dev
, 39, 0xc4);
997 rt2500pci_bbp_write(rt2x00dev
, 40, 0x02);
998 rt2500pci_bbp_write(rt2x00dev
, 41, 0x60);
999 rt2500pci_bbp_write(rt2x00dev
, 53, 0x10);
1000 rt2500pci_bbp_write(rt2x00dev
, 54, 0x18);
1001 rt2500pci_bbp_write(rt2x00dev
, 56, 0x08);
1002 rt2500pci_bbp_write(rt2x00dev
, 57, 0x10);
1003 rt2500pci_bbp_write(rt2x00dev
, 58, 0x08);
1004 rt2500pci_bbp_write(rt2x00dev
, 61, 0x6d);
1005 rt2500pci_bbp_write(rt2x00dev
, 62, 0x10);
1007 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
1008 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
1010 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
1011 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
1012 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
1013 rt2500pci_bbp_write(rt2x00dev
, reg_id
, value
);
1021 * Device state switch handlers.
1023 static void rt2500pci_toggle_rx(struct rt2x00_dev
*rt2x00dev
,
1024 enum dev_state state
)
1028 rt2x00pci_register_read(rt2x00dev
, RXCSR0
, ®
);
1029 rt2x00_set_field32(®
, RXCSR0_DISABLE_RX
,
1030 (state
== STATE_RADIO_RX_OFF
) ||
1031 (state
== STATE_RADIO_RX_OFF_LINK
));
1032 rt2x00pci_register_write(rt2x00dev
, RXCSR0
, reg
);
1035 static void rt2500pci_toggle_irq(struct rt2x00_dev
*rt2x00dev
,
1036 enum dev_state state
)
1038 int mask
= (state
== STATE_RADIO_IRQ_OFF
);
1042 * When interrupts are being enabled, the interrupt registers
1043 * should clear the register to assure a clean state.
1045 if (state
== STATE_RADIO_IRQ_ON
) {
1046 rt2x00pci_register_read(rt2x00dev
, CSR7
, ®
);
1047 rt2x00pci_register_write(rt2x00dev
, CSR7
, reg
);
1051 * Only toggle the interrupts bits we are going to use.
1052 * Non-checked interrupt bits are disabled by default.
1054 rt2x00pci_register_read(rt2x00dev
, CSR8
, ®
);
1055 rt2x00_set_field32(®
, CSR8_TBCN_EXPIRE
, mask
);
1056 rt2x00_set_field32(®
, CSR8_TXDONE_TXRING
, mask
);
1057 rt2x00_set_field32(®
, CSR8_TXDONE_ATIMRING
, mask
);
1058 rt2x00_set_field32(®
, CSR8_TXDONE_PRIORING
, mask
);
1059 rt2x00_set_field32(®
, CSR8_RXDONE
, mask
);
1060 rt2x00pci_register_write(rt2x00dev
, CSR8
, reg
);
1063 static int rt2500pci_enable_radio(struct rt2x00_dev
*rt2x00dev
)
1066 * Initialize all registers.
1068 if (unlikely(rt2500pci_init_queues(rt2x00dev
) ||
1069 rt2500pci_init_registers(rt2x00dev
) ||
1070 rt2500pci_init_bbp(rt2x00dev
)))
1076 static void rt2500pci_disable_radio(struct rt2x00_dev
*rt2x00dev
)
1081 rt2x00pci_register_write(rt2x00dev
, PWRCSR0
, 0);
1084 static int rt2500pci_set_state(struct rt2x00_dev
*rt2x00dev
,
1085 enum dev_state state
)
1093 put_to_sleep
= (state
!= STATE_AWAKE
);
1095 rt2x00pci_register_read(rt2x00dev
, PWRCSR1
, ®
);
1096 rt2x00_set_field32(®
, PWRCSR1_SET_STATE
, 1);
1097 rt2x00_set_field32(®
, PWRCSR1_BBP_DESIRE_STATE
, state
);
1098 rt2x00_set_field32(®
, PWRCSR1_RF_DESIRE_STATE
, state
);
1099 rt2x00_set_field32(®
, PWRCSR1_PUT_TO_SLEEP
, put_to_sleep
);
1100 rt2x00pci_register_write(rt2x00dev
, PWRCSR1
, reg
);
1103 * Device is not guaranteed to be in the requested state yet.
1104 * We must wait until the register indicates that the
1105 * device has entered the correct state.
1107 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1108 rt2x00pci_register_read(rt2x00dev
, PWRCSR1
, ®2
);
1109 bbp_state
= rt2x00_get_field32(reg2
, PWRCSR1_BBP_CURR_STATE
);
1110 rf_state
= rt2x00_get_field32(reg2
, PWRCSR1_RF_CURR_STATE
);
1111 if (bbp_state
== state
&& rf_state
== state
)
1113 rt2x00pci_register_write(rt2x00dev
, PWRCSR1
, reg
);
1120 static int rt2500pci_set_device_state(struct rt2x00_dev
*rt2x00dev
,
1121 enum dev_state state
)
1126 case STATE_RADIO_ON
:
1127 retval
= rt2500pci_enable_radio(rt2x00dev
);
1129 case STATE_RADIO_OFF
:
1130 rt2500pci_disable_radio(rt2x00dev
);
1132 case STATE_RADIO_RX_ON
:
1133 case STATE_RADIO_RX_ON_LINK
:
1134 case STATE_RADIO_RX_OFF
:
1135 case STATE_RADIO_RX_OFF_LINK
:
1136 rt2500pci_toggle_rx(rt2x00dev
, state
);
1138 case STATE_RADIO_IRQ_ON
:
1139 case STATE_RADIO_IRQ_OFF
:
1140 rt2500pci_toggle_irq(rt2x00dev
, state
);
1142 case STATE_DEEP_SLEEP
:
1146 retval
= rt2500pci_set_state(rt2x00dev
, state
);
1153 if (unlikely(retval
))
1154 ERROR(rt2x00dev
, "Device failed to enter state %d (%d).\n",
1161 * TX descriptor initialization
1163 static void rt2500pci_write_tx_desc(struct rt2x00_dev
*rt2x00dev
,
1164 struct sk_buff
*skb
,
1165 struct txentry_desc
*txdesc
)
1167 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(skb
);
1168 struct queue_entry_priv_pci
*entry_priv
= skbdesc
->entry
->priv_data
;
1169 __le32
*txd
= entry_priv
->desc
;
1173 * Start writing the descriptor words.
1175 rt2x00_desc_read(txd
, 1, &word
);
1176 rt2x00_set_field32(&word
, TXD_W1_BUFFER_ADDRESS
, skbdesc
->skb_dma
);
1177 rt2x00_desc_write(txd
, 1, word
);
1179 rt2x00_desc_read(txd
, 2, &word
);
1180 rt2x00_set_field32(&word
, TXD_W2_IV_OFFSET
, IEEE80211_HEADER
);
1181 rt2x00_set_field32(&word
, TXD_W2_AIFS
, txdesc
->aifs
);
1182 rt2x00_set_field32(&word
, TXD_W2_CWMIN
, txdesc
->cw_min
);
1183 rt2x00_set_field32(&word
, TXD_W2_CWMAX
, txdesc
->cw_max
);
1184 rt2x00_desc_write(txd
, 2, word
);
1186 rt2x00_desc_read(txd
, 3, &word
);
1187 rt2x00_set_field32(&word
, TXD_W3_PLCP_SIGNAL
, txdesc
->signal
);
1188 rt2x00_set_field32(&word
, TXD_W3_PLCP_SERVICE
, txdesc
->service
);
1189 rt2x00_set_field32(&word
, TXD_W3_PLCP_LENGTH_LOW
, txdesc
->length_low
);
1190 rt2x00_set_field32(&word
, TXD_W3_PLCP_LENGTH_HIGH
, txdesc
->length_high
);
1191 rt2x00_desc_write(txd
, 3, word
);
1193 rt2x00_desc_read(txd
, 10, &word
);
1194 rt2x00_set_field32(&word
, TXD_W10_RTS
,
1195 test_bit(ENTRY_TXD_RTS_FRAME
, &txdesc
->flags
));
1196 rt2x00_desc_write(txd
, 10, word
);
1199 * Writing TXD word 0 must the last to prevent a race condition with
1200 * the device, whereby the device may take hold of the TXD before we
1201 * finished updating it.
1203 rt2x00_desc_read(txd
, 0, &word
);
1204 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 1);
1205 rt2x00_set_field32(&word
, TXD_W0_VALID
, 1);
1206 rt2x00_set_field32(&word
, TXD_W0_MORE_FRAG
,
1207 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
1208 rt2x00_set_field32(&word
, TXD_W0_ACK
,
1209 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
1210 rt2x00_set_field32(&word
, TXD_W0_TIMESTAMP
,
1211 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
1212 rt2x00_set_field32(&word
, TXD_W0_OFDM
,
1213 (txdesc
->rate_mode
== RATE_MODE_OFDM
));
1214 rt2x00_set_field32(&word
, TXD_W0_CIPHER_OWNER
, 1);
1215 rt2x00_set_field32(&word
, TXD_W0_IFS
, txdesc
->ifs
);
1216 rt2x00_set_field32(&word
, TXD_W0_RETRY_MODE
,
1217 test_bit(ENTRY_TXD_RETRY_MODE
, &txdesc
->flags
));
1218 rt2x00_set_field32(&word
, TXD_W0_DATABYTE_COUNT
, txdesc
->length
);
1219 rt2x00_set_field32(&word
, TXD_W0_CIPHER_ALG
, CIPHER_NONE
);
1220 rt2x00_desc_write(txd
, 0, word
);
1223 * Register descriptor details in skb frame descriptor.
1225 skbdesc
->desc
= txd
;
1226 skbdesc
->desc_len
= TXD_DESC_SIZE
;
1230 * TX data initialization
1232 static void rt2500pci_write_beacon(struct queue_entry
*entry
,
1233 struct txentry_desc
*txdesc
)
1235 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
1239 * Disable beaconing while we are reloading the beacon data,
1240 * otherwise we might be sending out invalid data.
1242 rt2x00pci_register_read(rt2x00dev
, CSR14
, ®
);
1243 rt2x00_set_field32(®
, CSR14_BEACON_GEN
, 0);
1244 rt2x00pci_register_write(rt2x00dev
, CSR14
, reg
);
1246 rt2x00queue_map_txskb(rt2x00dev
, entry
->skb
);
1249 * Write the TX descriptor for the beacon.
1251 rt2500pci_write_tx_desc(rt2x00dev
, entry
->skb
, txdesc
);
1254 * Dump beacon to userspace through debugfs.
1256 rt2x00debug_dump_frame(rt2x00dev
, DUMP_FRAME_BEACON
, entry
->skb
);
1259 * Enable beaconing again.
1261 rt2x00_set_field32(®
, CSR14_TSF_COUNT
, 1);
1262 rt2x00_set_field32(®
, CSR14_TBCN
, 1);
1263 rt2x00_set_field32(®
, CSR14_BEACON_GEN
, 1);
1264 rt2x00pci_register_write(rt2x00dev
, CSR14
, reg
);
1267 static void rt2500pci_kick_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1268 const enum data_queue_qid queue
)
1272 rt2x00pci_register_read(rt2x00dev
, TXCSR0
, ®
);
1273 rt2x00_set_field32(®
, TXCSR0_KICK_PRIO
, (queue
== QID_AC_BE
));
1274 rt2x00_set_field32(®
, TXCSR0_KICK_TX
, (queue
== QID_AC_BK
));
1275 rt2x00_set_field32(®
, TXCSR0_KICK_ATIM
, (queue
== QID_ATIM
));
1276 rt2x00pci_register_write(rt2x00dev
, TXCSR0
, reg
);
1279 static void rt2500pci_kill_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1280 const enum data_queue_qid qid
)
1284 if (qid
== QID_BEACON
) {
1285 rt2x00pci_register_write(rt2x00dev
, CSR14
, 0);
1287 rt2x00pci_register_read(rt2x00dev
, TXCSR0
, ®
);
1288 rt2x00_set_field32(®
, TXCSR0_ABORT
, 1);
1289 rt2x00pci_register_write(rt2x00dev
, TXCSR0
, reg
);
1294 * RX control handlers
1296 static void rt2500pci_fill_rxdone(struct queue_entry
*entry
,
1297 struct rxdone_entry_desc
*rxdesc
)
1299 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1303 rt2x00_desc_read(entry_priv
->desc
, 0, &word0
);
1304 rt2x00_desc_read(entry_priv
->desc
, 2, &word2
);
1306 if (rt2x00_get_field32(word0
, RXD_W0_CRC_ERROR
))
1307 rxdesc
->flags
|= RX_FLAG_FAILED_FCS_CRC
;
1308 if (rt2x00_get_field32(word0
, RXD_W0_PHYSICAL_ERROR
))
1309 rxdesc
->flags
|= RX_FLAG_FAILED_PLCP_CRC
;
1312 * Obtain the status about this packet.
1313 * When frame was received with an OFDM bitrate,
1314 * the signal is the PLCP value. If it was received with
1315 * a CCK bitrate the signal is the rate in 100kbit/s.
1317 rxdesc
->signal
= rt2x00_get_field32(word2
, RXD_W2_SIGNAL
);
1318 rxdesc
->rssi
= rt2x00_get_field32(word2
, RXD_W2_RSSI
) -
1319 entry
->queue
->rt2x00dev
->rssi_offset
;
1320 rxdesc
->size
= rt2x00_get_field32(word0
, RXD_W0_DATABYTE_COUNT
);
1322 if (rt2x00_get_field32(word0
, RXD_W0_OFDM
))
1323 rxdesc
->dev_flags
|= RXDONE_SIGNAL_PLCP
;
1325 rxdesc
->dev_flags
|= RXDONE_SIGNAL_BITRATE
;
1326 if (rt2x00_get_field32(word0
, RXD_W0_MY_BSS
))
1327 rxdesc
->dev_flags
|= RXDONE_MY_BSS
;
1331 * Interrupt functions.
1333 static void rt2500pci_txdone(struct rt2x00_dev
*rt2x00dev
,
1334 const enum data_queue_qid queue_idx
)
1336 struct data_queue
*queue
= rt2x00queue_get_queue(rt2x00dev
, queue_idx
);
1337 struct queue_entry_priv_pci
*entry_priv
;
1338 struct queue_entry
*entry
;
1339 struct txdone_entry_desc txdesc
;
1342 while (!rt2x00queue_empty(queue
)) {
1343 entry
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
1344 entry_priv
= entry
->priv_data
;
1345 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1347 if (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
1348 !rt2x00_get_field32(word
, TXD_W0_VALID
))
1352 * Obtain the status about this packet.
1355 switch (rt2x00_get_field32(word
, TXD_W0_RESULT
)) {
1356 case 0: /* Success */
1357 case 1: /* Success with retry */
1358 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
1360 case 2: /* Failure, excessive retries */
1361 __set_bit(TXDONE_EXCESSIVE_RETRY
, &txdesc
.flags
);
1362 /* Don't break, this is a failed frame! */
1363 default: /* Failure */
1364 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
1366 txdesc
.retry
= rt2x00_get_field32(word
, TXD_W0_RETRY_COUNT
);
1368 rt2x00lib_txdone(entry
, &txdesc
);
1372 static irqreturn_t
rt2500pci_interrupt(int irq
, void *dev_instance
)
1374 struct rt2x00_dev
*rt2x00dev
= dev_instance
;
1378 * Get the interrupt sources & saved to local variable.
1379 * Write register value back to clear pending interrupts.
1381 rt2x00pci_register_read(rt2x00dev
, CSR7
, ®
);
1382 rt2x00pci_register_write(rt2x00dev
, CSR7
, reg
);
1387 if (!test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
1391 * Handle interrupts, walk through all bits
1392 * and run the tasks, the bits are checked in order of
1397 * 1 - Beacon timer expired interrupt.
1399 if (rt2x00_get_field32(reg
, CSR7_TBCN_EXPIRE
))
1400 rt2x00lib_beacondone(rt2x00dev
);
1403 * 2 - Rx ring done interrupt.
1405 if (rt2x00_get_field32(reg
, CSR7_RXDONE
))
1406 rt2x00pci_rxdone(rt2x00dev
);
1409 * 3 - Atim ring transmit done interrupt.
1411 if (rt2x00_get_field32(reg
, CSR7_TXDONE_ATIMRING
))
1412 rt2500pci_txdone(rt2x00dev
, QID_ATIM
);
1415 * 4 - Priority ring transmit done interrupt.
1417 if (rt2x00_get_field32(reg
, CSR7_TXDONE_PRIORING
))
1418 rt2500pci_txdone(rt2x00dev
, QID_AC_BE
);
1421 * 5 - Tx ring transmit done interrupt.
1423 if (rt2x00_get_field32(reg
, CSR7_TXDONE_TXRING
))
1424 rt2500pci_txdone(rt2x00dev
, QID_AC_BK
);
1430 * Device probe functions.
1432 static int rt2500pci_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
1434 struct eeprom_93cx6 eeprom
;
1439 rt2x00pci_register_read(rt2x00dev
, CSR21
, ®
);
1441 eeprom
.data
= rt2x00dev
;
1442 eeprom
.register_read
= rt2500pci_eepromregister_read
;
1443 eeprom
.register_write
= rt2500pci_eepromregister_write
;
1444 eeprom
.width
= rt2x00_get_field32(reg
, CSR21_TYPE_93C46
) ?
1445 PCI_EEPROM_WIDTH_93C46
: PCI_EEPROM_WIDTH_93C66
;
1446 eeprom
.reg_data_in
= 0;
1447 eeprom
.reg_data_out
= 0;
1448 eeprom
.reg_data_clock
= 0;
1449 eeprom
.reg_chip_select
= 0;
1451 eeprom_93cx6_multiread(&eeprom
, EEPROM_BASE
, rt2x00dev
->eeprom
,
1452 EEPROM_SIZE
/ sizeof(u16
));
1455 * Start validation of the data that has been read.
1457 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
1458 if (!is_valid_ether_addr(mac
)) {
1459 random_ether_addr(mac
);
1460 EEPROM(rt2x00dev
, "MAC: %pM\n", mac
);
1463 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
1464 if (word
== 0xffff) {
1465 rt2x00_set_field16(&word
, EEPROM_ANTENNA_NUM
, 2);
1466 rt2x00_set_field16(&word
, EEPROM_ANTENNA_TX_DEFAULT
,
1467 ANTENNA_SW_DIVERSITY
);
1468 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RX_DEFAULT
,
1469 ANTENNA_SW_DIVERSITY
);
1470 rt2x00_set_field16(&word
, EEPROM_ANTENNA_LED_MODE
,
1472 rt2x00_set_field16(&word
, EEPROM_ANTENNA_DYN_TXAGC
, 0);
1473 rt2x00_set_field16(&word
, EEPROM_ANTENNA_HARDWARE_RADIO
, 0);
1474 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RF_TYPE
, RF2522
);
1475 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
1476 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
1479 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &word
);
1480 if (word
== 0xffff) {
1481 rt2x00_set_field16(&word
, EEPROM_NIC_CARDBUS_ACCEL
, 0);
1482 rt2x00_set_field16(&word
, EEPROM_NIC_DYN_BBP_TUNE
, 0);
1483 rt2x00_set_field16(&word
, EEPROM_NIC_CCK_TX_POWER
, 0);
1484 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC
, word
);
1485 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
1488 rt2x00_eeprom_read(rt2x00dev
, EEPROM_CALIBRATE_OFFSET
, &word
);
1489 if (word
== 0xffff) {
1490 rt2x00_set_field16(&word
, EEPROM_CALIBRATE_OFFSET_RSSI
,
1491 DEFAULT_RSSI_OFFSET
);
1492 rt2x00_eeprom_write(rt2x00dev
, EEPROM_CALIBRATE_OFFSET
, word
);
1493 EEPROM(rt2x00dev
, "Calibrate offset: 0x%04x\n", word
);
1499 static int rt2500pci_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
1506 * Read EEPROM word for configuration.
1508 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
1511 * Identify RF chipset.
1513 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
1514 rt2x00pci_register_read(rt2x00dev
, CSR0
, ®
);
1515 rt2x00_set_chip(rt2x00dev
, RT2560
, value
,
1516 rt2x00_get_field32(reg
, CSR0_REVISION
));
1518 if (!rt2x00_rf(rt2x00dev
, RF2522
) &&
1519 !rt2x00_rf(rt2x00dev
, RF2523
) &&
1520 !rt2x00_rf(rt2x00dev
, RF2524
) &&
1521 !rt2x00_rf(rt2x00dev
, RF2525
) &&
1522 !rt2x00_rf(rt2x00dev
, RF2525E
) &&
1523 !rt2x00_rf(rt2x00dev
, RF5222
)) {
1524 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
1529 * Identify default antenna configuration.
1531 rt2x00dev
->default_ant
.tx
=
1532 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TX_DEFAULT
);
1533 rt2x00dev
->default_ant
.rx
=
1534 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RX_DEFAULT
);
1537 * Store led mode, for correct led behaviour.
1539 #ifdef CONFIG_RT2X00_LIB_LEDS
1540 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_LED_MODE
);
1542 rt2500pci_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
1543 if (value
== LED_MODE_TXRX_ACTIVITY
||
1544 value
== LED_MODE_DEFAULT
||
1545 value
== LED_MODE_ASUS
)
1546 rt2500pci_init_led(rt2x00dev
, &rt2x00dev
->led_qual
,
1548 #endif /* CONFIG_RT2X00_LIB_LEDS */
1551 * Detect if this device has an hardware controlled radio.
1553 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_HARDWARE_RADIO
))
1554 __set_bit(CONFIG_SUPPORT_HW_BUTTON
, &rt2x00dev
->flags
);
1557 * Check if the BBP tuning should be enabled.
1559 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
1560 if (!rt2x00_get_field16(eeprom
, EEPROM_NIC_DYN_BBP_TUNE
))
1561 __set_bit(DRIVER_SUPPORT_LINK_TUNING
, &rt2x00dev
->flags
);
1564 * Read the RSSI <-> dBm offset information.
1566 rt2x00_eeprom_read(rt2x00dev
, EEPROM_CALIBRATE_OFFSET
, &eeprom
);
1567 rt2x00dev
->rssi_offset
=
1568 rt2x00_get_field16(eeprom
, EEPROM_CALIBRATE_OFFSET_RSSI
);
1574 * RF value list for RF2522
1577 static const struct rf_channel rf_vals_bg_2522
[] = {
1578 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1579 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1580 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1581 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1582 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1583 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1584 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1585 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1586 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1587 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1588 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1589 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1590 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1591 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1595 * RF value list for RF2523
1598 static const struct rf_channel rf_vals_bg_2523
[] = {
1599 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1600 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1601 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1602 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1603 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1604 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1605 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1606 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1607 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1608 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1609 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1610 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1611 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1612 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1616 * RF value list for RF2524
1619 static const struct rf_channel rf_vals_bg_2524
[] = {
1620 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1621 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1622 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1623 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1624 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1625 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1626 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1627 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1628 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1629 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1630 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1631 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1632 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1633 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1637 * RF value list for RF2525
1640 static const struct rf_channel rf_vals_bg_2525
[] = {
1641 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1642 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1643 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1644 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1645 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1646 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1647 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1648 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1649 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1650 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1651 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1652 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1653 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1654 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1658 * RF value list for RF2525e
1661 static const struct rf_channel rf_vals_bg_2525e
[] = {
1662 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1663 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1664 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1665 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1666 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1667 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1668 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1669 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1670 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1671 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1672 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1673 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1674 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1675 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1679 * RF value list for RF5222
1680 * Supports: 2.4 GHz & 5.2 GHz
1682 static const struct rf_channel rf_vals_5222
[] = {
1683 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1684 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1685 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1686 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1687 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1688 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1689 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1690 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1691 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1692 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1693 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1694 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1695 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1696 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1698 /* 802.11 UNI / HyperLan 2 */
1699 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1700 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1701 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1702 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1703 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1704 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1705 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1706 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1708 /* 802.11 HyperLan 2 */
1709 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1710 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1711 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1712 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1713 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1714 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1715 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1716 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1717 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1718 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1721 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1722 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1723 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1724 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1725 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1728 static int rt2500pci_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
1730 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
1731 struct channel_info
*info
;
1736 * Initialize all hw fields.
1738 rt2x00dev
->hw
->flags
= IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
1739 IEEE80211_HW_SIGNAL_DBM
|
1740 IEEE80211_HW_SUPPORTS_PS
|
1741 IEEE80211_HW_PS_NULLFUNC_STACK
;
1743 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
1744 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
1745 rt2x00_eeprom_addr(rt2x00dev
,
1746 EEPROM_MAC_ADDR_0
));
1749 * Initialize hw_mode information.
1751 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
1752 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
1754 if (rt2x00_rf(rt2x00dev
, RF2522
)) {
1755 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2522
);
1756 spec
->channels
= rf_vals_bg_2522
;
1757 } else if (rt2x00_rf(rt2x00dev
, RF2523
)) {
1758 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2523
);
1759 spec
->channels
= rf_vals_bg_2523
;
1760 } else if (rt2x00_rf(rt2x00dev
, RF2524
)) {
1761 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2524
);
1762 spec
->channels
= rf_vals_bg_2524
;
1763 } else if (rt2x00_rf(rt2x00dev
, RF2525
)) {
1764 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2525
);
1765 spec
->channels
= rf_vals_bg_2525
;
1766 } else if (rt2x00_rf(rt2x00dev
, RF2525E
)) {
1767 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2525e
);
1768 spec
->channels
= rf_vals_bg_2525e
;
1769 } else if (rt2x00_rf(rt2x00dev
, RF5222
)) {
1770 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
1771 spec
->num_channels
= ARRAY_SIZE(rf_vals_5222
);
1772 spec
->channels
= rf_vals_5222
;
1776 * Create channel information array
1778 info
= kzalloc(spec
->num_channels
* sizeof(*info
), GFP_KERNEL
);
1782 spec
->channels_info
= info
;
1784 tx_power
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_START
);
1785 for (i
= 0; i
< 14; i
++)
1786 info
[i
].tx_power1
= TXPOWER_FROM_DEV(tx_power
[i
]);
1788 if (spec
->num_channels
> 14) {
1789 for (i
= 14; i
< spec
->num_channels
; i
++)
1790 info
[i
].tx_power1
= DEFAULT_TXPOWER
;
1796 static int rt2500pci_probe_hw(struct rt2x00_dev
*rt2x00dev
)
1801 * Allocate eeprom data.
1803 retval
= rt2500pci_validate_eeprom(rt2x00dev
);
1807 retval
= rt2500pci_init_eeprom(rt2x00dev
);
1812 * Initialize hw specifications.
1814 retval
= rt2500pci_probe_hw_mode(rt2x00dev
);
1819 * This device requires the atim queue and DMA-mapped skbs.
1821 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE
, &rt2x00dev
->flags
);
1822 __set_bit(DRIVER_REQUIRE_DMA
, &rt2x00dev
->flags
);
1825 * Set the rssi offset.
1827 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
1833 * IEEE80211 stack callback functions.
1835 static u64
rt2500pci_get_tsf(struct ieee80211_hw
*hw
)
1837 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1841 rt2x00pci_register_read(rt2x00dev
, CSR17
, ®
);
1842 tsf
= (u64
) rt2x00_get_field32(reg
, CSR17_HIGH_TSFTIMER
) << 32;
1843 rt2x00pci_register_read(rt2x00dev
, CSR16
, ®
);
1844 tsf
|= rt2x00_get_field32(reg
, CSR16_LOW_TSFTIMER
);
1849 static int rt2500pci_tx_last_beacon(struct ieee80211_hw
*hw
)
1851 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1854 rt2x00pci_register_read(rt2x00dev
, CSR15
, ®
);
1855 return rt2x00_get_field32(reg
, CSR15_BEACON_SENT
);
1858 static const struct ieee80211_ops rt2500pci_mac80211_ops
= {
1860 .start
= rt2x00mac_start
,
1861 .stop
= rt2x00mac_stop
,
1862 .add_interface
= rt2x00mac_add_interface
,
1863 .remove_interface
= rt2x00mac_remove_interface
,
1864 .config
= rt2x00mac_config
,
1865 .configure_filter
= rt2x00mac_configure_filter
,
1866 .set_tim
= rt2x00mac_set_tim
,
1867 .sw_scan_start
= rt2x00mac_sw_scan_start
,
1868 .sw_scan_complete
= rt2x00mac_sw_scan_complete
,
1869 .get_stats
= rt2x00mac_get_stats
,
1870 .bss_info_changed
= rt2x00mac_bss_info_changed
,
1871 .conf_tx
= rt2x00mac_conf_tx
,
1872 .get_tsf
= rt2500pci_get_tsf
,
1873 .tx_last_beacon
= rt2500pci_tx_last_beacon
,
1874 .rfkill_poll
= rt2x00mac_rfkill_poll
,
1877 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops
= {
1878 .irq_handler
= rt2500pci_interrupt
,
1879 .probe_hw
= rt2500pci_probe_hw
,
1880 .initialize
= rt2x00pci_initialize
,
1881 .uninitialize
= rt2x00pci_uninitialize
,
1882 .get_entry_state
= rt2500pci_get_entry_state
,
1883 .clear_entry
= rt2500pci_clear_entry
,
1884 .set_device_state
= rt2500pci_set_device_state
,
1885 .rfkill_poll
= rt2500pci_rfkill_poll
,
1886 .link_stats
= rt2500pci_link_stats
,
1887 .reset_tuner
= rt2500pci_reset_tuner
,
1888 .link_tuner
= rt2500pci_link_tuner
,
1889 .write_tx_desc
= rt2500pci_write_tx_desc
,
1890 .write_beacon
= rt2500pci_write_beacon
,
1891 .kick_tx_queue
= rt2500pci_kick_tx_queue
,
1892 .kill_tx_queue
= rt2500pci_kill_tx_queue
,
1893 .fill_rxdone
= rt2500pci_fill_rxdone
,
1894 .config_filter
= rt2500pci_config_filter
,
1895 .config_intf
= rt2500pci_config_intf
,
1896 .config_erp
= rt2500pci_config_erp
,
1897 .config_ant
= rt2500pci_config_ant
,
1898 .config
= rt2500pci_config
,
1901 static const struct data_queue_desc rt2500pci_queue_rx
= {
1902 .entry_num
= RX_ENTRIES
,
1903 .data_size
= DATA_FRAME_SIZE
,
1904 .desc_size
= RXD_DESC_SIZE
,
1905 .priv_size
= sizeof(struct queue_entry_priv_pci
),
1908 static const struct data_queue_desc rt2500pci_queue_tx
= {
1909 .entry_num
= TX_ENTRIES
,
1910 .data_size
= DATA_FRAME_SIZE
,
1911 .desc_size
= TXD_DESC_SIZE
,
1912 .priv_size
= sizeof(struct queue_entry_priv_pci
),
1915 static const struct data_queue_desc rt2500pci_queue_bcn
= {
1916 .entry_num
= BEACON_ENTRIES
,
1917 .data_size
= MGMT_FRAME_SIZE
,
1918 .desc_size
= TXD_DESC_SIZE
,
1919 .priv_size
= sizeof(struct queue_entry_priv_pci
),
1922 static const struct data_queue_desc rt2500pci_queue_atim
= {
1923 .entry_num
= ATIM_ENTRIES
,
1924 .data_size
= DATA_FRAME_SIZE
,
1925 .desc_size
= TXD_DESC_SIZE
,
1926 .priv_size
= sizeof(struct queue_entry_priv_pci
),
1929 static const struct rt2x00_ops rt2500pci_ops
= {
1930 .name
= KBUILD_MODNAME
,
1933 .eeprom_size
= EEPROM_SIZE
,
1935 .tx_queues
= NUM_TX_QUEUES
,
1936 .extra_tx_headroom
= 0,
1937 .rx
= &rt2500pci_queue_rx
,
1938 .tx
= &rt2500pci_queue_tx
,
1939 .bcn
= &rt2500pci_queue_bcn
,
1940 .atim
= &rt2500pci_queue_atim
,
1941 .lib
= &rt2500pci_rt2x00_ops
,
1942 .hw
= &rt2500pci_mac80211_ops
,
1943 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1944 .debugfs
= &rt2500pci_rt2x00debug
,
1945 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1949 * RT2500pci module information.
1951 static DEFINE_PCI_DEVICE_TABLE(rt2500pci_device_table
) = {
1952 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops
) },
1956 MODULE_AUTHOR(DRV_PROJECT
);
1957 MODULE_VERSION(DRV_VERSION
);
1958 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1959 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1960 MODULE_DEVICE_TABLE(pci
, rt2500pci_device_table
);
1961 MODULE_LICENSE("GPL");
1963 static struct pci_driver rt2500pci_driver
= {
1964 .name
= KBUILD_MODNAME
,
1965 .id_table
= rt2500pci_device_table
,
1966 .probe
= rt2x00pci_probe
,
1967 .remove
= __devexit_p(rt2x00pci_remove
),
1968 .suspend
= rt2x00pci_suspend
,
1969 .resume
= rt2x00pci_resume
,
1972 static int __init
rt2500pci_init(void)
1974 return pci_register_driver(&rt2500pci_driver
);
1977 static void __exit
rt2500pci_exit(void)
1979 pci_unregister_driver(&rt2500pci_driver
);
1982 module_init(rt2500pci_init
);
1983 module_exit(rt2500pci_exit
);