2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
36 #include "rt2x00pci.h"
37 #include "rt2500pci.h"
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
52 static u32
rt2500pci_bbp_check(struct rt2x00_dev
*rt2x00dev
)
57 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
58 rt2x00pci_register_read(rt2x00dev
, BBPCSR
, ®
);
59 if (!rt2x00_get_field32(reg
, BBPCSR_BUSY
))
61 udelay(REGISTER_BUSY_DELAY
);
67 static void rt2500pci_bbp_write(struct rt2x00_dev
*rt2x00dev
,
68 const unsigned int word
, const u8 value
)
73 * Wait until the BBP becomes ready.
75 reg
= rt2500pci_bbp_check(rt2x00dev
);
76 if (rt2x00_get_field32(reg
, BBPCSR_BUSY
)) {
77 ERROR(rt2x00dev
, "BBPCSR register busy. Write failed.\n");
82 * Write the data into the BBP.
85 rt2x00_set_field32(®
, BBPCSR_VALUE
, value
);
86 rt2x00_set_field32(®
, BBPCSR_REGNUM
, word
);
87 rt2x00_set_field32(®
, BBPCSR_BUSY
, 1);
88 rt2x00_set_field32(®
, BBPCSR_WRITE_CONTROL
, 1);
90 rt2x00pci_register_write(rt2x00dev
, BBPCSR
, reg
);
93 static void rt2500pci_bbp_read(struct rt2x00_dev
*rt2x00dev
,
94 const unsigned int word
, u8
*value
)
99 * Wait until the BBP becomes ready.
101 reg
= rt2500pci_bbp_check(rt2x00dev
);
102 if (rt2x00_get_field32(reg
, BBPCSR_BUSY
)) {
103 ERROR(rt2x00dev
, "BBPCSR register busy. Read failed.\n");
108 * Write the request into the BBP.
111 rt2x00_set_field32(®
, BBPCSR_REGNUM
, word
);
112 rt2x00_set_field32(®
, BBPCSR_BUSY
, 1);
113 rt2x00_set_field32(®
, BBPCSR_WRITE_CONTROL
, 0);
115 rt2x00pci_register_write(rt2x00dev
, BBPCSR
, reg
);
118 * Wait until the BBP becomes ready.
120 reg
= rt2500pci_bbp_check(rt2x00dev
);
121 if (rt2x00_get_field32(reg
, BBPCSR_BUSY
)) {
122 ERROR(rt2x00dev
, "BBPCSR register busy. Read failed.\n");
127 *value
= rt2x00_get_field32(reg
, BBPCSR_VALUE
);
130 static void rt2500pci_rf_write(struct rt2x00_dev
*rt2x00dev
,
131 const unsigned int word
, const u32 value
)
139 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
140 rt2x00pci_register_read(rt2x00dev
, RFCSR
, ®
);
141 if (!rt2x00_get_field32(reg
, RFCSR_BUSY
))
143 udelay(REGISTER_BUSY_DELAY
);
146 ERROR(rt2x00dev
, "RFCSR register busy. Write failed.\n");
151 rt2x00_set_field32(®
, RFCSR_VALUE
, value
);
152 rt2x00_set_field32(®
, RFCSR_NUMBER_OF_BITS
, 20);
153 rt2x00_set_field32(®
, RFCSR_IF_SELECT
, 0);
154 rt2x00_set_field32(®
, RFCSR_BUSY
, 1);
156 rt2x00pci_register_write(rt2x00dev
, RFCSR
, reg
);
157 rt2x00_rf_write(rt2x00dev
, word
, value
);
160 static void rt2500pci_eepromregister_read(struct eeprom_93cx6
*eeprom
)
162 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
165 rt2x00pci_register_read(rt2x00dev
, CSR21
, ®
);
167 eeprom
->reg_data_in
= !!rt2x00_get_field32(reg
, CSR21_EEPROM_DATA_IN
);
168 eeprom
->reg_data_out
= !!rt2x00_get_field32(reg
, CSR21_EEPROM_DATA_OUT
);
169 eeprom
->reg_data_clock
=
170 !!rt2x00_get_field32(reg
, CSR21_EEPROM_DATA_CLOCK
);
171 eeprom
->reg_chip_select
=
172 !!rt2x00_get_field32(reg
, CSR21_EEPROM_CHIP_SELECT
);
175 static void rt2500pci_eepromregister_write(struct eeprom_93cx6
*eeprom
)
177 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
180 rt2x00_set_field32(®
, CSR21_EEPROM_DATA_IN
, !!eeprom
->reg_data_in
);
181 rt2x00_set_field32(®
, CSR21_EEPROM_DATA_OUT
, !!eeprom
->reg_data_out
);
182 rt2x00_set_field32(®
, CSR21_EEPROM_DATA_CLOCK
,
183 !!eeprom
->reg_data_clock
);
184 rt2x00_set_field32(®
, CSR21_EEPROM_CHIP_SELECT
,
185 !!eeprom
->reg_chip_select
);
187 rt2x00pci_register_write(rt2x00dev
, CSR21
, reg
);
190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
191 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
193 static void rt2500pci_read_csr(struct rt2x00_dev
*rt2x00dev
,
194 const unsigned int word
, u32
*data
)
196 rt2x00pci_register_read(rt2x00dev
, CSR_OFFSET(word
), data
);
199 static void rt2500pci_write_csr(struct rt2x00_dev
*rt2x00dev
,
200 const unsigned int word
, u32 data
)
202 rt2x00pci_register_write(rt2x00dev
, CSR_OFFSET(word
), data
);
205 static const struct rt2x00debug rt2500pci_rt2x00debug
= {
206 .owner
= THIS_MODULE
,
208 .read
= rt2500pci_read_csr
,
209 .write
= rt2500pci_write_csr
,
210 .word_size
= sizeof(u32
),
211 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
214 .read
= rt2x00_eeprom_read
,
215 .write
= rt2x00_eeprom_write
,
216 .word_size
= sizeof(u16
),
217 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
220 .read
= rt2500pci_bbp_read
,
221 .write
= rt2500pci_bbp_write
,
222 .word_size
= sizeof(u8
),
223 .word_count
= BBP_SIZE
/ sizeof(u8
),
226 .read
= rt2x00_rf_read
,
227 .write
= rt2500pci_rf_write
,
228 .word_size
= sizeof(u32
),
229 .word_count
= RF_SIZE
/ sizeof(u32
),
232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
234 #ifdef CONFIG_RT2500PCI_RFKILL
235 static int rt2500pci_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
239 rt2x00pci_register_read(rt2x00dev
, GPIOCSR
, ®
);
240 return rt2x00_get_field32(reg
, GPIOCSR_BIT0
);
243 #define rt2500pci_rfkill_poll NULL
244 #endif /* CONFIG_RT2500PCI_RFKILL */
247 * Configuration handlers.
249 static void rt2500pci_config_mac_addr(struct rt2x00_dev
*rt2x00dev
,
252 rt2x00pci_register_multiwrite(rt2x00dev
, CSR3
, mac
,
253 (2 * sizeof(__le32
)));
256 static void rt2500pci_config_bssid(struct rt2x00_dev
*rt2x00dev
,
259 rt2x00pci_register_multiwrite(rt2x00dev
, CSR5
, bssid
,
260 (2 * sizeof(__le32
)));
263 static void rt2500pci_config_type(struct rt2x00_dev
*rt2x00dev
, const int type
,
266 struct data_queue
*queue
=
267 rt2x00queue_get_queue(rt2x00dev
, IEEE80211_TX_QUEUE_BEACON
);
270 rt2x00pci_register_write(rt2x00dev
, CSR14
, 0);
273 * Enable beacon config
275 rt2x00pci_register_read(rt2x00dev
, BCNCSR1
, ®
);
276 rt2x00_set_field32(®
, BCNCSR1_PRELOAD
,
277 PREAMBLE
+ get_duration(IEEE80211_HEADER
, 20));
278 rt2x00_set_field32(®
, BCNCSR1_BEACON_CWMIN
, queue
->cw_min
);
279 rt2x00pci_register_write(rt2x00dev
, BCNCSR1
, reg
);
282 * Enable synchronisation.
284 rt2x00pci_register_read(rt2x00dev
, CSR14
, ®
);
285 rt2x00_set_field32(®
, CSR14_TSF_COUNT
, 1);
286 rt2x00_set_field32(®
, CSR14_TBCN
, (tsf_sync
== TSF_SYNC_BEACON
));
287 rt2x00_set_field32(®
, CSR14_BEACON_GEN
, 0);
288 rt2x00_set_field32(®
, CSR14_TSF_SYNC
, tsf_sync
);
289 rt2x00pci_register_write(rt2x00dev
, CSR14
, reg
);
292 static void rt2500pci_config_preamble(struct rt2x00_dev
*rt2x00dev
,
293 const int short_preamble
,
294 const int ack_timeout
,
295 const int ack_consume_time
)
301 * When short preamble is enabled, we should set bit 0x08
303 preamble_mask
= short_preamble
<< 3;
305 rt2x00pci_register_read(rt2x00dev
, TXCSR1
, ®
);
306 rt2x00_set_field32(®
, TXCSR1_ACK_TIMEOUT
, ack_timeout
);
307 rt2x00_set_field32(®
, TXCSR1_ACK_CONSUME_TIME
, ack_consume_time
);
308 rt2x00pci_register_write(rt2x00dev
, TXCSR1
, reg
);
310 rt2x00pci_register_read(rt2x00dev
, ARCSR2
, ®
);
311 rt2x00_set_field32(®
, ARCSR2_SIGNAL
, 0x00 | preamble_mask
);
312 rt2x00_set_field32(®
, ARCSR2_SERVICE
, 0x04);
313 rt2x00_set_field32(®
, ARCSR2_LENGTH
, get_duration(ACK_SIZE
, 10));
314 rt2x00pci_register_write(rt2x00dev
, ARCSR2
, reg
);
316 rt2x00pci_register_read(rt2x00dev
, ARCSR3
, ®
);
317 rt2x00_set_field32(®
, ARCSR3_SIGNAL
, 0x01 | preamble_mask
);
318 rt2x00_set_field32(®
, ARCSR3_SERVICE
, 0x04);
319 rt2x00_set_field32(®
, ARCSR2_LENGTH
, get_duration(ACK_SIZE
, 20));
320 rt2x00pci_register_write(rt2x00dev
, ARCSR3
, reg
);
322 rt2x00pci_register_read(rt2x00dev
, ARCSR4
, ®
);
323 rt2x00_set_field32(®
, ARCSR4_SIGNAL
, 0x02 | preamble_mask
);
324 rt2x00_set_field32(®
, ARCSR4_SERVICE
, 0x04);
325 rt2x00_set_field32(®
, ARCSR2_LENGTH
, get_duration(ACK_SIZE
, 55));
326 rt2x00pci_register_write(rt2x00dev
, ARCSR4
, reg
);
328 rt2x00pci_register_read(rt2x00dev
, ARCSR5
, ®
);
329 rt2x00_set_field32(®
, ARCSR5_SIGNAL
, 0x03 | preamble_mask
);
330 rt2x00_set_field32(®
, ARCSR5_SERVICE
, 0x84);
331 rt2x00_set_field32(®
, ARCSR2_LENGTH
, get_duration(ACK_SIZE
, 110));
332 rt2x00pci_register_write(rt2x00dev
, ARCSR5
, reg
);
335 static void rt2500pci_config_phymode(struct rt2x00_dev
*rt2x00dev
,
336 const int basic_rate_mask
)
338 rt2x00pci_register_write(rt2x00dev
, ARCSR1
, basic_rate_mask
);
341 static void rt2500pci_config_channel(struct rt2x00_dev
*rt2x00dev
,
342 struct rf_channel
*rf
, const int txpower
)
349 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER
, TXPOWER_TO_DEV(txpower
));
352 * Switch on tuning bits.
353 * For RT2523 devices we do not need to update the R1 register.
355 if (!rt2x00_rf(&rt2x00dev
->chip
, RF2523
))
356 rt2x00_set_field32(&rf
->rf1
, RF1_TUNER
, 1);
357 rt2x00_set_field32(&rf
->rf3
, RF3_TUNER
, 1);
360 * For RT2525 we should first set the channel to half band higher.
362 if (rt2x00_rf(&rt2x00dev
->chip
, RF2525
)) {
363 static const u32 vals
[] = {
364 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
365 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
366 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
367 0x00080d2e, 0x00080d3a
370 rt2500pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
371 rt2500pci_rf_write(rt2x00dev
, 2, vals
[rf
->channel
- 1]);
372 rt2500pci_rf_write(rt2x00dev
, 3, rf
->rf3
);
374 rt2500pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
377 rt2500pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
378 rt2500pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
379 rt2500pci_rf_write(rt2x00dev
, 3, rf
->rf3
);
381 rt2500pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
384 * Channel 14 requires the Japan filter bit to be set.
387 rt2x00_set_field8(&r70
, BBP_R70_JAPAN_FILTER
, rf
->channel
== 14);
388 rt2500pci_bbp_write(rt2x00dev
, 70, r70
);
393 * Switch off tuning bits.
394 * For RT2523 devices we do not need to update the R1 register.
396 if (!rt2x00_rf(&rt2x00dev
->chip
, RF2523
)) {
397 rt2x00_set_field32(&rf
->rf1
, RF1_TUNER
, 0);
398 rt2500pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
401 rt2x00_set_field32(&rf
->rf3
, RF3_TUNER
, 0);
402 rt2500pci_rf_write(rt2x00dev
, 3, rf
->rf3
);
405 * Clear false CRC during channel switch.
407 rt2x00pci_register_read(rt2x00dev
, CNT0
, &rf
->rf1
);
410 static void rt2500pci_config_txpower(struct rt2x00_dev
*rt2x00dev
,
415 rt2x00_rf_read(rt2x00dev
, 3, &rf3
);
416 rt2x00_set_field32(&rf3
, RF3_TXPOWER
, TXPOWER_TO_DEV(txpower
));
417 rt2500pci_rf_write(rt2x00dev
, 3, rf3
);
420 static void rt2500pci_config_antenna(struct rt2x00_dev
*rt2x00dev
,
421 struct antenna_setup
*ant
)
427 rt2x00pci_register_read(rt2x00dev
, BBPCSR1
, ®
);
428 rt2500pci_bbp_read(rt2x00dev
, 14, &r14
);
429 rt2500pci_bbp_read(rt2x00dev
, 2, &r2
);
432 * Configure the TX antenna.
436 rt2x00_set_field8(&r2
, BBP_R2_TX_ANTENNA
, 0);
437 rt2x00_set_field32(®
, BBPCSR1_CCK
, 0);
438 rt2x00_set_field32(®
, BBPCSR1_OFDM
, 0);
440 case ANTENNA_HW_DIVERSITY
:
441 case ANTENNA_SW_DIVERSITY
:
443 * NOTE: We should never come here because rt2x00lib is
444 * supposed to catch this and send us the correct antenna
445 * explicitely. However we are nog going to bug about this.
446 * Instead, just default to antenna B.
449 rt2x00_set_field8(&r2
, BBP_R2_TX_ANTENNA
, 2);
450 rt2x00_set_field32(®
, BBPCSR1_CCK
, 2);
451 rt2x00_set_field32(®
, BBPCSR1_OFDM
, 2);
456 * Configure the RX antenna.
460 rt2x00_set_field8(&r14
, BBP_R14_RX_ANTENNA
, 0);
462 case ANTENNA_HW_DIVERSITY
:
463 case ANTENNA_SW_DIVERSITY
:
465 * NOTE: We should never come here because rt2x00lib is
466 * supposed to catch this and send us the correct antenna
467 * explicitely. However we are nog going to bug about this.
468 * Instead, just default to antenna B.
471 rt2x00_set_field8(&r14
, BBP_R14_RX_ANTENNA
, 2);
476 * RT2525E and RT5222 need to flip TX I/Q
478 if (rt2x00_rf(&rt2x00dev
->chip
, RF2525E
) ||
479 rt2x00_rf(&rt2x00dev
->chip
, RF5222
)) {
480 rt2x00_set_field8(&r2
, BBP_R2_TX_IQ_FLIP
, 1);
481 rt2x00_set_field32(®
, BBPCSR1_CCK_FLIP
, 1);
482 rt2x00_set_field32(®
, BBPCSR1_OFDM_FLIP
, 1);
485 * RT2525E does not need RX I/Q Flip.
487 if (rt2x00_rf(&rt2x00dev
->chip
, RF2525E
))
488 rt2x00_set_field8(&r14
, BBP_R14_RX_IQ_FLIP
, 0);
490 rt2x00_set_field32(®
, BBPCSR1_CCK_FLIP
, 0);
491 rt2x00_set_field32(®
, BBPCSR1_OFDM_FLIP
, 0);
494 rt2x00pci_register_write(rt2x00dev
, BBPCSR1
, reg
);
495 rt2500pci_bbp_write(rt2x00dev
, 14, r14
);
496 rt2500pci_bbp_write(rt2x00dev
, 2, r2
);
499 static void rt2500pci_config_duration(struct rt2x00_dev
*rt2x00dev
,
500 struct rt2x00lib_conf
*libconf
)
504 rt2x00pci_register_read(rt2x00dev
, CSR11
, ®
);
505 rt2x00_set_field32(®
, CSR11_SLOT_TIME
, libconf
->slot_time
);
506 rt2x00pci_register_write(rt2x00dev
, CSR11
, reg
);
508 rt2x00pci_register_read(rt2x00dev
, CSR18
, ®
);
509 rt2x00_set_field32(®
, CSR18_SIFS
, libconf
->sifs
);
510 rt2x00_set_field32(®
, CSR18_PIFS
, libconf
->pifs
);
511 rt2x00pci_register_write(rt2x00dev
, CSR18
, reg
);
513 rt2x00pci_register_read(rt2x00dev
, CSR19
, ®
);
514 rt2x00_set_field32(®
, CSR19_DIFS
, libconf
->difs
);
515 rt2x00_set_field32(®
, CSR19_EIFS
, libconf
->eifs
);
516 rt2x00pci_register_write(rt2x00dev
, CSR19
, reg
);
518 rt2x00pci_register_read(rt2x00dev
, TXCSR1
, ®
);
519 rt2x00_set_field32(®
, TXCSR1_TSF_OFFSET
, IEEE80211_HEADER
);
520 rt2x00_set_field32(®
, TXCSR1_AUTORESPONDER
, 1);
521 rt2x00pci_register_write(rt2x00dev
, TXCSR1
, reg
);
523 rt2x00pci_register_read(rt2x00dev
, CSR12
, ®
);
524 rt2x00_set_field32(®
, CSR12_BEACON_INTERVAL
,
525 libconf
->conf
->beacon_int
* 16);
526 rt2x00_set_field32(®
, CSR12_CFP_MAX_DURATION
,
527 libconf
->conf
->beacon_int
* 16);
528 rt2x00pci_register_write(rt2x00dev
, CSR12
, reg
);
531 static void rt2500pci_config(struct rt2x00_dev
*rt2x00dev
,
532 const unsigned int flags
,
533 struct rt2x00lib_conf
*libconf
)
535 if (flags
& CONFIG_UPDATE_PHYMODE
)
536 rt2500pci_config_phymode(rt2x00dev
, libconf
->basic_rates
);
537 if (flags
& CONFIG_UPDATE_CHANNEL
)
538 rt2500pci_config_channel(rt2x00dev
, &libconf
->rf
,
539 libconf
->conf
->power_level
);
540 if ((flags
& CONFIG_UPDATE_TXPOWER
) && !(flags
& CONFIG_UPDATE_CHANNEL
))
541 rt2500pci_config_txpower(rt2x00dev
,
542 libconf
->conf
->power_level
);
543 if (flags
& CONFIG_UPDATE_ANTENNA
)
544 rt2500pci_config_antenna(rt2x00dev
, &libconf
->ant
);
545 if (flags
& (CONFIG_UPDATE_SLOT_TIME
| CONFIG_UPDATE_BEACON_INT
))
546 rt2500pci_config_duration(rt2x00dev
, libconf
);
552 static void rt2500pci_enable_led(struct rt2x00_dev
*rt2x00dev
)
556 rt2x00pci_register_read(rt2x00dev
, LEDCSR
, ®
);
558 rt2x00_set_field32(®
, LEDCSR_ON_PERIOD
, 70);
559 rt2x00_set_field32(®
, LEDCSR_OFF_PERIOD
, 30);
560 rt2x00_set_field32(®
, LEDCSR_LINK
,
561 (rt2x00dev
->led_mode
!= LED_MODE_ASUS
));
562 rt2x00_set_field32(®
, LEDCSR_ACTIVITY
,
563 (rt2x00dev
->led_mode
!= LED_MODE_TXRX_ACTIVITY
));
564 rt2x00pci_register_write(rt2x00dev
, LEDCSR
, reg
);
567 static void rt2500pci_disable_led(struct rt2x00_dev
*rt2x00dev
)
571 rt2x00pci_register_read(rt2x00dev
, LEDCSR
, ®
);
572 rt2x00_set_field32(®
, LEDCSR_LINK
, 0);
573 rt2x00_set_field32(®
, LEDCSR_ACTIVITY
, 0);
574 rt2x00pci_register_write(rt2x00dev
, LEDCSR
, reg
);
580 static void rt2500pci_link_stats(struct rt2x00_dev
*rt2x00dev
,
581 struct link_qual
*qual
)
586 * Update FCS error count from register.
588 rt2x00pci_register_read(rt2x00dev
, CNT0
, ®
);
589 qual
->rx_failed
= rt2x00_get_field32(reg
, CNT0_FCS_ERROR
);
592 * Update False CCA count from register.
594 rt2x00pci_register_read(rt2x00dev
, CNT3
, ®
);
595 qual
->false_cca
= rt2x00_get_field32(reg
, CNT3_FALSE_CCA
);
598 static void rt2500pci_reset_tuner(struct rt2x00_dev
*rt2x00dev
)
600 rt2500pci_bbp_write(rt2x00dev
, 17, 0x48);
601 rt2x00dev
->link
.vgc_level
= 0x48;
604 static void rt2500pci_link_tuner(struct rt2x00_dev
*rt2x00dev
)
606 int rssi
= rt2x00_get_link_rssi(&rt2x00dev
->link
);
610 * To prevent collisions with MAC ASIC on chipsets
611 * up to version C the link tuning should halt after 20
614 if (rt2x00_rev(&rt2x00dev
->chip
) < RT2560_VERSION_D
&&
615 rt2x00dev
->link
.count
> 20)
618 rt2500pci_bbp_read(rt2x00dev
, 17, &r17
);
621 * Chipset versions C and lower should directly continue
622 * to the dynamic CCA tuning.
624 if (rt2x00_rev(&rt2x00dev
->chip
) < RT2560_VERSION_D
)
625 goto dynamic_cca_tune
;
628 * A too low RSSI will cause too much false CCA which will
629 * then corrupt the R17 tuning. To remidy this the tuning should
630 * be stopped (While making sure the R17 value will not exceed limits)
632 if (rssi
< -80 && rt2x00dev
->link
.count
> 20) {
634 r17
= rt2x00dev
->link
.vgc_level
;
635 rt2500pci_bbp_write(rt2x00dev
, 17, r17
);
641 * Special big-R17 for short distance
645 rt2500pci_bbp_write(rt2x00dev
, 17, 0x50);
650 * Special mid-R17 for middle distance
654 rt2500pci_bbp_write(rt2x00dev
, 17, 0x41);
659 * Leave short or middle distance condition, restore r17
660 * to the dynamic tuning range.
663 rt2500pci_bbp_write(rt2x00dev
, 17, rt2x00dev
->link
.vgc_level
);
670 * R17 is inside the dynamic tuning range,
671 * start tuning the link based on the false cca counter.
673 if (rt2x00dev
->link
.qual
.false_cca
> 512 && r17
< 0x40) {
674 rt2500pci_bbp_write(rt2x00dev
, 17, ++r17
);
675 rt2x00dev
->link
.vgc_level
= r17
;
676 } else if (rt2x00dev
->link
.qual
.false_cca
< 100 && r17
> 0x32) {
677 rt2500pci_bbp_write(rt2x00dev
, 17, --r17
);
678 rt2x00dev
->link
.vgc_level
= r17
;
683 * Initialization functions.
685 static void rt2500pci_init_rxentry(struct rt2x00_dev
*rt2x00dev
,
686 struct queue_entry
*entry
)
688 struct queue_entry_priv_pci_rx
*priv_rx
= entry
->priv_data
;
691 rt2x00_desc_read(priv_rx
->desc
, 1, &word
);
692 rt2x00_set_field32(&word
, RXD_W1_BUFFER_ADDRESS
, priv_rx
->dma
);
693 rt2x00_desc_write(priv_rx
->desc
, 1, word
);
695 rt2x00_desc_read(priv_rx
->desc
, 0, &word
);
696 rt2x00_set_field32(&word
, RXD_W0_OWNER_NIC
, 1);
697 rt2x00_desc_write(priv_rx
->desc
, 0, word
);
700 static void rt2500pci_init_txentry(struct rt2x00_dev
*rt2x00dev
,
701 struct queue_entry
*entry
)
703 struct queue_entry_priv_pci_tx
*priv_tx
= entry
->priv_data
;
706 rt2x00_desc_read(priv_tx
->desc
, 1, &word
);
707 rt2x00_set_field32(&word
, TXD_W1_BUFFER_ADDRESS
, priv_tx
->dma
);
708 rt2x00_desc_write(priv_tx
->desc
, 1, word
);
710 rt2x00_desc_read(priv_tx
->desc
, 0, &word
);
711 rt2x00_set_field32(&word
, TXD_W0_VALID
, 0);
712 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 0);
713 rt2x00_desc_write(priv_tx
->desc
, 0, word
);
716 static int rt2500pci_init_queues(struct rt2x00_dev
*rt2x00dev
)
718 struct queue_entry_priv_pci_rx
*priv_rx
;
719 struct queue_entry_priv_pci_tx
*priv_tx
;
723 * Initialize registers.
725 rt2x00pci_register_read(rt2x00dev
, TXCSR2
, ®
);
726 rt2x00_set_field32(®
, TXCSR2_TXD_SIZE
, rt2x00dev
->tx
[0].desc_size
);
727 rt2x00_set_field32(®
, TXCSR2_NUM_TXD
, rt2x00dev
->tx
[1].limit
);
728 rt2x00_set_field32(®
, TXCSR2_NUM_ATIM
, rt2x00dev
->bcn
[1].limit
);
729 rt2x00_set_field32(®
, TXCSR2_NUM_PRIO
, rt2x00dev
->tx
[0].limit
);
730 rt2x00pci_register_write(rt2x00dev
, TXCSR2
, reg
);
732 priv_tx
= rt2x00dev
->tx
[1].entries
[0].priv_data
;
733 rt2x00pci_register_read(rt2x00dev
, TXCSR3
, ®
);
734 rt2x00_set_field32(®
, TXCSR3_TX_RING_REGISTER
, priv_tx
->dma
);
735 rt2x00pci_register_write(rt2x00dev
, TXCSR3
, reg
);
737 priv_tx
= rt2x00dev
->tx
[0].entries
[0].priv_data
;
738 rt2x00pci_register_read(rt2x00dev
, TXCSR5
, ®
);
739 rt2x00_set_field32(®
, TXCSR5_PRIO_RING_REGISTER
, priv_tx
->dma
);
740 rt2x00pci_register_write(rt2x00dev
, TXCSR5
, reg
);
742 priv_tx
= rt2x00dev
->bcn
[1].entries
[0].priv_data
;
743 rt2x00pci_register_read(rt2x00dev
, TXCSR4
, ®
);
744 rt2x00_set_field32(®
, TXCSR4_ATIM_RING_REGISTER
, priv_tx
->dma
);
745 rt2x00pci_register_write(rt2x00dev
, TXCSR4
, reg
);
747 priv_tx
= rt2x00dev
->bcn
[0].entries
[0].priv_data
;
748 rt2x00pci_register_read(rt2x00dev
, TXCSR6
, ®
);
749 rt2x00_set_field32(®
, TXCSR6_BEACON_RING_REGISTER
, priv_tx
->dma
);
750 rt2x00pci_register_write(rt2x00dev
, TXCSR6
, reg
);
752 rt2x00pci_register_read(rt2x00dev
, RXCSR1
, ®
);
753 rt2x00_set_field32(®
, RXCSR1_RXD_SIZE
, rt2x00dev
->rx
->desc_size
);
754 rt2x00_set_field32(®
, RXCSR1_NUM_RXD
, rt2x00dev
->rx
->limit
);
755 rt2x00pci_register_write(rt2x00dev
, RXCSR1
, reg
);
757 priv_rx
= rt2x00dev
->rx
->entries
[0].priv_data
;
758 rt2x00pci_register_read(rt2x00dev
, RXCSR2
, ®
);
759 rt2x00_set_field32(®
, RXCSR2_RX_RING_REGISTER
, priv_tx
->dma
);
760 rt2x00pci_register_write(rt2x00dev
, RXCSR2
, reg
);
765 static int rt2500pci_init_registers(struct rt2x00_dev
*rt2x00dev
)
769 rt2x00pci_register_write(rt2x00dev
, PSCSR0
, 0x00020002);
770 rt2x00pci_register_write(rt2x00dev
, PSCSR1
, 0x00000002);
771 rt2x00pci_register_write(rt2x00dev
, PSCSR2
, 0x00020002);
772 rt2x00pci_register_write(rt2x00dev
, PSCSR3
, 0x00000002);
774 rt2x00pci_register_read(rt2x00dev
, TIMECSR
, ®
);
775 rt2x00_set_field32(®
, TIMECSR_US_COUNT
, 33);
776 rt2x00_set_field32(®
, TIMECSR_US_64_COUNT
, 63);
777 rt2x00_set_field32(®
, TIMECSR_BEACON_EXPECT
, 0);
778 rt2x00pci_register_write(rt2x00dev
, TIMECSR
, reg
);
780 rt2x00pci_register_read(rt2x00dev
, CSR9
, ®
);
781 rt2x00_set_field32(®
, CSR9_MAX_FRAME_UNIT
,
782 rt2x00dev
->rx
->data_size
/ 128);
783 rt2x00pci_register_write(rt2x00dev
, CSR9
, reg
);
786 * Always use CWmin and CWmax set in descriptor.
788 rt2x00pci_register_read(rt2x00dev
, CSR11
, ®
);
789 rt2x00_set_field32(®
, CSR11_CW_SELECT
, 0);
790 rt2x00pci_register_write(rt2x00dev
, CSR11
, reg
);
792 rt2x00pci_register_write(rt2x00dev
, CNT3
, 0);
794 rt2x00pci_register_read(rt2x00dev
, TXCSR8
, ®
);
795 rt2x00_set_field32(®
, TXCSR8_BBP_ID0
, 10);
796 rt2x00_set_field32(®
, TXCSR8_BBP_ID0_VALID
, 1);
797 rt2x00_set_field32(®
, TXCSR8_BBP_ID1
, 11);
798 rt2x00_set_field32(®
, TXCSR8_BBP_ID1_VALID
, 1);
799 rt2x00_set_field32(®
, TXCSR8_BBP_ID2
, 13);
800 rt2x00_set_field32(®
, TXCSR8_BBP_ID2_VALID
, 1);
801 rt2x00_set_field32(®
, TXCSR8_BBP_ID3
, 12);
802 rt2x00_set_field32(®
, TXCSR8_BBP_ID3_VALID
, 1);
803 rt2x00pci_register_write(rt2x00dev
, TXCSR8
, reg
);
805 rt2x00pci_register_read(rt2x00dev
, ARTCSR0
, ®
);
806 rt2x00_set_field32(®
, ARTCSR0_ACK_CTS_1MBS
, 112);
807 rt2x00_set_field32(®
, ARTCSR0_ACK_CTS_2MBS
, 56);
808 rt2x00_set_field32(®
, ARTCSR0_ACK_CTS_5_5MBS
, 20);
809 rt2x00_set_field32(®
, ARTCSR0_ACK_CTS_11MBS
, 10);
810 rt2x00pci_register_write(rt2x00dev
, ARTCSR0
, reg
);
812 rt2x00pci_register_read(rt2x00dev
, ARTCSR1
, ®
);
813 rt2x00_set_field32(®
, ARTCSR1_ACK_CTS_6MBS
, 45);
814 rt2x00_set_field32(®
, ARTCSR1_ACK_CTS_9MBS
, 37);
815 rt2x00_set_field32(®
, ARTCSR1_ACK_CTS_12MBS
, 33);
816 rt2x00_set_field32(®
, ARTCSR1_ACK_CTS_18MBS
, 29);
817 rt2x00pci_register_write(rt2x00dev
, ARTCSR1
, reg
);
819 rt2x00pci_register_read(rt2x00dev
, ARTCSR2
, ®
);
820 rt2x00_set_field32(®
, ARTCSR2_ACK_CTS_24MBS
, 29);
821 rt2x00_set_field32(®
, ARTCSR2_ACK_CTS_36MBS
, 25);
822 rt2x00_set_field32(®
, ARTCSR2_ACK_CTS_48MBS
, 25);
823 rt2x00_set_field32(®
, ARTCSR2_ACK_CTS_54MBS
, 25);
824 rt2x00pci_register_write(rt2x00dev
, ARTCSR2
, reg
);
826 rt2x00pci_register_read(rt2x00dev
, RXCSR3
, ®
);
827 rt2x00_set_field32(®
, RXCSR3_BBP_ID0
, 47); /* CCK Signal */
828 rt2x00_set_field32(®
, RXCSR3_BBP_ID0_VALID
, 1);
829 rt2x00_set_field32(®
, RXCSR3_BBP_ID1
, 51); /* Rssi */
830 rt2x00_set_field32(®
, RXCSR3_BBP_ID1_VALID
, 1);
831 rt2x00_set_field32(®
, RXCSR3_BBP_ID2
, 42); /* OFDM Rate */
832 rt2x00_set_field32(®
, RXCSR3_BBP_ID2_VALID
, 1);
833 rt2x00_set_field32(®
, RXCSR3_BBP_ID3
, 51); /* RSSI */
834 rt2x00_set_field32(®
, RXCSR3_BBP_ID3_VALID
, 1);
835 rt2x00pci_register_write(rt2x00dev
, RXCSR3
, reg
);
837 rt2x00pci_register_read(rt2x00dev
, PCICSR
, ®
);
838 rt2x00_set_field32(®
, PCICSR_BIG_ENDIAN
, 0);
839 rt2x00_set_field32(®
, PCICSR_RX_TRESHOLD
, 0);
840 rt2x00_set_field32(®
, PCICSR_TX_TRESHOLD
, 3);
841 rt2x00_set_field32(®
, PCICSR_BURST_LENTH
, 1);
842 rt2x00_set_field32(®
, PCICSR_ENABLE_CLK
, 1);
843 rt2x00_set_field32(®
, PCICSR_READ_MULTIPLE
, 1);
844 rt2x00_set_field32(®
, PCICSR_WRITE_INVALID
, 1);
845 rt2x00pci_register_write(rt2x00dev
, PCICSR
, reg
);
847 rt2x00pci_register_write(rt2x00dev
, PWRCSR0
, 0x3f3b3100);
849 rt2x00pci_register_write(rt2x00dev
, GPIOCSR
, 0x0000ff00);
850 rt2x00pci_register_write(rt2x00dev
, TESTCSR
, 0x000000f0);
852 if (rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, STATE_AWAKE
))
855 rt2x00pci_register_write(rt2x00dev
, MACCSR0
, 0x00213223);
856 rt2x00pci_register_write(rt2x00dev
, MACCSR1
, 0x00235518);
858 rt2x00pci_register_read(rt2x00dev
, MACCSR2
, ®
);
859 rt2x00_set_field32(®
, MACCSR2_DELAY
, 64);
860 rt2x00pci_register_write(rt2x00dev
, MACCSR2
, reg
);
862 rt2x00pci_register_read(rt2x00dev
, RALINKCSR
, ®
);
863 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_DATA0
, 17);
864 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_ID0
, 26);
865 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_VALID0
, 1);
866 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_DATA1
, 0);
867 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_ID1
, 26);
868 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_VALID1
, 1);
869 rt2x00pci_register_write(rt2x00dev
, RALINKCSR
, reg
);
871 rt2x00pci_register_write(rt2x00dev
, BBPCSR1
, 0x82188200);
873 rt2x00pci_register_write(rt2x00dev
, TXACKCSR0
, 0x00000020);
875 rt2x00pci_register_read(rt2x00dev
, CSR1
, ®
);
876 rt2x00_set_field32(®
, CSR1_SOFT_RESET
, 1);
877 rt2x00_set_field32(®
, CSR1_BBP_RESET
, 0);
878 rt2x00_set_field32(®
, CSR1_HOST_READY
, 0);
879 rt2x00pci_register_write(rt2x00dev
, CSR1
, reg
);
881 rt2x00pci_register_read(rt2x00dev
, CSR1
, ®
);
882 rt2x00_set_field32(®
, CSR1_SOFT_RESET
, 0);
883 rt2x00_set_field32(®
, CSR1_HOST_READY
, 1);
884 rt2x00pci_register_write(rt2x00dev
, CSR1
, reg
);
887 * We must clear the FCS and FIFO error count.
888 * These registers are cleared on read,
889 * so we may pass a useless variable to store the value.
891 rt2x00pci_register_read(rt2x00dev
, CNT0
, ®
);
892 rt2x00pci_register_read(rt2x00dev
, CNT4
, ®
);
897 static int rt2500pci_init_bbp(struct rt2x00_dev
*rt2x00dev
)
904 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
905 rt2500pci_bbp_read(rt2x00dev
, 0, &value
);
906 if ((value
!= 0xff) && (value
!= 0x00))
907 goto continue_csr_init
;
908 NOTICE(rt2x00dev
, "Waiting for BBP register.\n");
909 udelay(REGISTER_BUSY_DELAY
);
912 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
916 rt2500pci_bbp_write(rt2x00dev
, 3, 0x02);
917 rt2500pci_bbp_write(rt2x00dev
, 4, 0x19);
918 rt2500pci_bbp_write(rt2x00dev
, 14, 0x1c);
919 rt2500pci_bbp_write(rt2x00dev
, 15, 0x30);
920 rt2500pci_bbp_write(rt2x00dev
, 16, 0xac);
921 rt2500pci_bbp_write(rt2x00dev
, 18, 0x18);
922 rt2500pci_bbp_write(rt2x00dev
, 19, 0xff);
923 rt2500pci_bbp_write(rt2x00dev
, 20, 0x1e);
924 rt2500pci_bbp_write(rt2x00dev
, 21, 0x08);
925 rt2500pci_bbp_write(rt2x00dev
, 22, 0x08);
926 rt2500pci_bbp_write(rt2x00dev
, 23, 0x08);
927 rt2500pci_bbp_write(rt2x00dev
, 24, 0x70);
928 rt2500pci_bbp_write(rt2x00dev
, 25, 0x40);
929 rt2500pci_bbp_write(rt2x00dev
, 26, 0x08);
930 rt2500pci_bbp_write(rt2x00dev
, 27, 0x23);
931 rt2500pci_bbp_write(rt2x00dev
, 30, 0x10);
932 rt2500pci_bbp_write(rt2x00dev
, 31, 0x2b);
933 rt2500pci_bbp_write(rt2x00dev
, 32, 0xb9);
934 rt2500pci_bbp_write(rt2x00dev
, 34, 0x12);
935 rt2500pci_bbp_write(rt2x00dev
, 35, 0x50);
936 rt2500pci_bbp_write(rt2x00dev
, 39, 0xc4);
937 rt2500pci_bbp_write(rt2x00dev
, 40, 0x02);
938 rt2500pci_bbp_write(rt2x00dev
, 41, 0x60);
939 rt2500pci_bbp_write(rt2x00dev
, 53, 0x10);
940 rt2500pci_bbp_write(rt2x00dev
, 54, 0x18);
941 rt2500pci_bbp_write(rt2x00dev
, 56, 0x08);
942 rt2500pci_bbp_write(rt2x00dev
, 57, 0x10);
943 rt2500pci_bbp_write(rt2x00dev
, 58, 0x08);
944 rt2500pci_bbp_write(rt2x00dev
, 61, 0x6d);
945 rt2500pci_bbp_write(rt2x00dev
, 62, 0x10);
947 DEBUG(rt2x00dev
, "Start initialization from EEPROM...\n");
948 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
949 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
951 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
952 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
953 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
954 DEBUG(rt2x00dev
, "BBP: 0x%02x, value: 0x%02x.\n",
956 rt2500pci_bbp_write(rt2x00dev
, reg_id
, value
);
959 DEBUG(rt2x00dev
, "...End initialization from EEPROM.\n");
965 * Device state switch handlers.
967 static void rt2500pci_toggle_rx(struct rt2x00_dev
*rt2x00dev
,
968 enum dev_state state
)
972 rt2x00pci_register_read(rt2x00dev
, RXCSR0
, ®
);
973 rt2x00_set_field32(®
, RXCSR0_DISABLE_RX
,
974 state
== STATE_RADIO_RX_OFF
);
975 rt2x00pci_register_write(rt2x00dev
, RXCSR0
, reg
);
978 static void rt2500pci_toggle_irq(struct rt2x00_dev
*rt2x00dev
,
979 enum dev_state state
)
981 int mask
= (state
== STATE_RADIO_IRQ_OFF
);
985 * When interrupts are being enabled, the interrupt registers
986 * should clear the register to assure a clean state.
988 if (state
== STATE_RADIO_IRQ_ON
) {
989 rt2x00pci_register_read(rt2x00dev
, CSR7
, ®
);
990 rt2x00pci_register_write(rt2x00dev
, CSR7
, reg
);
994 * Only toggle the interrupts bits we are going to use.
995 * Non-checked interrupt bits are disabled by default.
997 rt2x00pci_register_read(rt2x00dev
, CSR8
, ®
);
998 rt2x00_set_field32(®
, CSR8_TBCN_EXPIRE
, mask
);
999 rt2x00_set_field32(®
, CSR8_TXDONE_TXRING
, mask
);
1000 rt2x00_set_field32(®
, CSR8_TXDONE_ATIMRING
, mask
);
1001 rt2x00_set_field32(®
, CSR8_TXDONE_PRIORING
, mask
);
1002 rt2x00_set_field32(®
, CSR8_RXDONE
, mask
);
1003 rt2x00pci_register_write(rt2x00dev
, CSR8
, reg
);
1006 static int rt2500pci_enable_radio(struct rt2x00_dev
*rt2x00dev
)
1009 * Initialize all registers.
1011 if (rt2500pci_init_queues(rt2x00dev
) ||
1012 rt2500pci_init_registers(rt2x00dev
) ||
1013 rt2500pci_init_bbp(rt2x00dev
)) {
1014 ERROR(rt2x00dev
, "Register initialization failed.\n");
1019 * Enable interrupts.
1021 rt2500pci_toggle_irq(rt2x00dev
, STATE_RADIO_IRQ_ON
);
1026 rt2500pci_enable_led(rt2x00dev
);
1031 static void rt2500pci_disable_radio(struct rt2x00_dev
*rt2x00dev
)
1038 rt2500pci_disable_led(rt2x00dev
);
1040 rt2x00pci_register_write(rt2x00dev
, PWRCSR0
, 0);
1043 * Disable synchronisation.
1045 rt2x00pci_register_write(rt2x00dev
, CSR14
, 0);
1050 rt2x00pci_register_read(rt2x00dev
, TXCSR0
, ®
);
1051 rt2x00_set_field32(®
, TXCSR0_ABORT
, 1);
1052 rt2x00pci_register_write(rt2x00dev
, TXCSR0
, reg
);
1055 * Disable interrupts.
1057 rt2500pci_toggle_irq(rt2x00dev
, STATE_RADIO_IRQ_OFF
);
1060 static int rt2500pci_set_state(struct rt2x00_dev
*rt2x00dev
,
1061 enum dev_state state
)
1069 put_to_sleep
= (state
!= STATE_AWAKE
);
1071 rt2x00pci_register_read(rt2x00dev
, PWRCSR1
, ®
);
1072 rt2x00_set_field32(®
, PWRCSR1_SET_STATE
, 1);
1073 rt2x00_set_field32(®
, PWRCSR1_BBP_DESIRE_STATE
, state
);
1074 rt2x00_set_field32(®
, PWRCSR1_RF_DESIRE_STATE
, state
);
1075 rt2x00_set_field32(®
, PWRCSR1_PUT_TO_SLEEP
, put_to_sleep
);
1076 rt2x00pci_register_write(rt2x00dev
, PWRCSR1
, reg
);
1079 * Device is not guaranteed to be in the requested state yet.
1080 * We must wait until the register indicates that the
1081 * device has entered the correct state.
1083 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1084 rt2x00pci_register_read(rt2x00dev
, PWRCSR1
, ®
);
1085 bbp_state
= rt2x00_get_field32(reg
, PWRCSR1_BBP_CURR_STATE
);
1086 rf_state
= rt2x00_get_field32(reg
, PWRCSR1_RF_CURR_STATE
);
1087 if (bbp_state
== state
&& rf_state
== state
)
1092 NOTICE(rt2x00dev
, "Device failed to enter state %d, "
1093 "current device state: bbp %d and rf %d.\n",
1094 state
, bbp_state
, rf_state
);
1099 static int rt2500pci_set_device_state(struct rt2x00_dev
*rt2x00dev
,
1100 enum dev_state state
)
1105 case STATE_RADIO_ON
:
1106 retval
= rt2500pci_enable_radio(rt2x00dev
);
1108 case STATE_RADIO_OFF
:
1109 rt2500pci_disable_radio(rt2x00dev
);
1111 case STATE_RADIO_RX_ON
:
1112 case STATE_RADIO_RX_ON_LINK
:
1113 rt2500pci_toggle_rx(rt2x00dev
, STATE_RADIO_RX_ON
);
1115 case STATE_RADIO_RX_OFF
:
1116 case STATE_RADIO_RX_OFF_LINK
:
1117 rt2500pci_toggle_rx(rt2x00dev
, STATE_RADIO_RX_OFF
);
1119 case STATE_DEEP_SLEEP
:
1123 retval
= rt2500pci_set_state(rt2x00dev
, state
);
1134 * TX descriptor initialization
1136 static void rt2500pci_write_tx_desc(struct rt2x00_dev
*rt2x00dev
,
1137 struct sk_buff
*skb
,
1138 struct txentry_desc
*txdesc
,
1139 struct ieee80211_tx_control
*control
)
1141 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(skb
);
1142 __le32
*txd
= skbdesc
->desc
;
1146 * Start writing the descriptor words.
1148 rt2x00_desc_read(txd
, 2, &word
);
1149 rt2x00_set_field32(&word
, TXD_W2_IV_OFFSET
, IEEE80211_HEADER
);
1150 rt2x00_set_field32(&word
, TXD_W2_AIFS
, txdesc
->aifs
);
1151 rt2x00_set_field32(&word
, TXD_W2_CWMIN
, txdesc
->cw_min
);
1152 rt2x00_set_field32(&word
, TXD_W2_CWMAX
, txdesc
->cw_max
);
1153 rt2x00_desc_write(txd
, 2, word
);
1155 rt2x00_desc_read(txd
, 3, &word
);
1156 rt2x00_set_field32(&word
, TXD_W3_PLCP_SIGNAL
, txdesc
->signal
);
1157 rt2x00_set_field32(&word
, TXD_W3_PLCP_SERVICE
, txdesc
->service
);
1158 rt2x00_set_field32(&word
, TXD_W3_PLCP_LENGTH_LOW
, txdesc
->length_low
);
1159 rt2x00_set_field32(&word
, TXD_W3_PLCP_LENGTH_HIGH
, txdesc
->length_high
);
1160 rt2x00_desc_write(txd
, 3, word
);
1162 rt2x00_desc_read(txd
, 10, &word
);
1163 rt2x00_set_field32(&word
, TXD_W10_RTS
,
1164 test_bit(ENTRY_TXD_RTS_FRAME
, &txdesc
->flags
));
1165 rt2x00_desc_write(txd
, 10, word
);
1167 rt2x00_desc_read(txd
, 0, &word
);
1168 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 1);
1169 rt2x00_set_field32(&word
, TXD_W0_VALID
, 1);
1170 rt2x00_set_field32(&word
, TXD_W0_MORE_FRAG
,
1171 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
1172 rt2x00_set_field32(&word
, TXD_W0_ACK
,
1173 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
1174 rt2x00_set_field32(&word
, TXD_W0_TIMESTAMP
,
1175 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
1176 rt2x00_set_field32(&word
, TXD_W0_OFDM
,
1177 test_bit(ENTRY_TXD_OFDM_RATE
, &txdesc
->flags
));
1178 rt2x00_set_field32(&word
, TXD_W0_CIPHER_OWNER
, 1);
1179 rt2x00_set_field32(&word
, TXD_W0_IFS
, txdesc
->ifs
);
1180 rt2x00_set_field32(&word
, TXD_W0_RETRY_MODE
,
1182 IEEE80211_TXCTL_LONG_RETRY_LIMIT
));
1183 rt2x00_set_field32(&word
, TXD_W0_DATABYTE_COUNT
, skbdesc
->data_len
);
1184 rt2x00_set_field32(&word
, TXD_W0_CIPHER_ALG
, CIPHER_NONE
);
1185 rt2x00_desc_write(txd
, 0, word
);
1189 * TX data initialization
1191 static void rt2500pci_kick_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1196 if (queue
== IEEE80211_TX_QUEUE_BEACON
) {
1197 rt2x00pci_register_read(rt2x00dev
, CSR14
, ®
);
1198 if (!rt2x00_get_field32(reg
, CSR14_BEACON_GEN
)) {
1199 rt2x00_set_field32(®
, CSR14_BEACON_GEN
, 1);
1200 rt2x00pci_register_write(rt2x00dev
, CSR14
, reg
);
1205 rt2x00pci_register_read(rt2x00dev
, TXCSR0
, ®
);
1206 rt2x00_set_field32(®
, TXCSR0_KICK_PRIO
,
1207 (queue
== IEEE80211_TX_QUEUE_DATA0
));
1208 rt2x00_set_field32(®
, TXCSR0_KICK_TX
,
1209 (queue
== IEEE80211_TX_QUEUE_DATA1
));
1210 rt2x00_set_field32(®
, TXCSR0_KICK_ATIM
,
1211 (queue
== IEEE80211_TX_QUEUE_AFTER_BEACON
));
1212 rt2x00pci_register_write(rt2x00dev
, TXCSR0
, reg
);
1216 * RX control handlers
1218 static void rt2500pci_fill_rxdone(struct queue_entry
*entry
,
1219 struct rxdone_entry_desc
*rxdesc
)
1221 struct queue_entry_priv_pci_rx
*priv_rx
= entry
->priv_data
;
1225 rt2x00_desc_read(priv_rx
->desc
, 0, &word0
);
1226 rt2x00_desc_read(priv_rx
->desc
, 2, &word2
);
1229 if (rt2x00_get_field32(word0
, RXD_W0_CRC_ERROR
))
1230 rxdesc
->flags
|= RX_FLAG_FAILED_FCS_CRC
;
1231 if (rt2x00_get_field32(word0
, RXD_W0_PHYSICAL_ERROR
))
1232 rxdesc
->flags
|= RX_FLAG_FAILED_PLCP_CRC
;
1234 rxdesc
->signal
= rt2x00_get_field32(word2
, RXD_W2_SIGNAL
);
1235 rxdesc
->rssi
= rt2x00_get_field32(word2
, RXD_W2_RSSI
) -
1236 entry
->queue
->rt2x00dev
->rssi_offset
;
1237 rxdesc
->ofdm
= rt2x00_get_field32(word0
, RXD_W0_OFDM
);
1238 rxdesc
->size
= rt2x00_get_field32(word0
, RXD_W0_DATABYTE_COUNT
);
1239 rxdesc
->my_bss
= !!rt2x00_get_field32(word0
, RXD_W0_MY_BSS
);
1243 * Interrupt functions.
1245 static void rt2500pci_txdone(struct rt2x00_dev
*rt2x00dev
,
1246 const enum ieee80211_tx_queue queue_idx
)
1248 struct data_queue
*queue
= rt2x00queue_get_queue(rt2x00dev
, queue_idx
);
1249 struct queue_entry_priv_pci_tx
*priv_tx
;
1250 struct queue_entry
*entry
;
1251 struct txdone_entry_desc txdesc
;
1254 while (!rt2x00queue_empty(queue
)) {
1255 entry
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
1256 priv_tx
= entry
->priv_data
;
1257 rt2x00_desc_read(priv_tx
->desc
, 0, &word
);
1259 if (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
1260 !rt2x00_get_field32(word
, TXD_W0_VALID
))
1264 * Obtain the status about this packet.
1266 txdesc
.status
= rt2x00_get_field32(word
, TXD_W0_RESULT
);
1267 txdesc
.retry
= rt2x00_get_field32(word
, TXD_W0_RETRY_COUNT
);
1269 rt2x00pci_txdone(rt2x00dev
, entry
, &txdesc
);
1273 static irqreturn_t
rt2500pci_interrupt(int irq
, void *dev_instance
)
1275 struct rt2x00_dev
*rt2x00dev
= dev_instance
;
1279 * Get the interrupt sources & saved to local variable.
1280 * Write register value back to clear pending interrupts.
1282 rt2x00pci_register_read(rt2x00dev
, CSR7
, ®
);
1283 rt2x00pci_register_write(rt2x00dev
, CSR7
, reg
);
1288 if (!test_bit(DEVICE_ENABLED_RADIO
, &rt2x00dev
->flags
))
1292 * Handle interrupts, walk through all bits
1293 * and run the tasks, the bits are checked in order of
1298 * 1 - Beacon timer expired interrupt.
1300 if (rt2x00_get_field32(reg
, CSR7_TBCN_EXPIRE
))
1301 rt2x00lib_beacondone(rt2x00dev
);
1304 * 2 - Rx ring done interrupt.
1306 if (rt2x00_get_field32(reg
, CSR7_RXDONE
))
1307 rt2x00pci_rxdone(rt2x00dev
);
1310 * 3 - Atim ring transmit done interrupt.
1312 if (rt2x00_get_field32(reg
, CSR7_TXDONE_ATIMRING
))
1313 rt2500pci_txdone(rt2x00dev
, IEEE80211_TX_QUEUE_AFTER_BEACON
);
1316 * 4 - Priority ring transmit done interrupt.
1318 if (rt2x00_get_field32(reg
, CSR7_TXDONE_PRIORING
))
1319 rt2500pci_txdone(rt2x00dev
, IEEE80211_TX_QUEUE_DATA0
);
1322 * 5 - Tx ring transmit done interrupt.
1324 if (rt2x00_get_field32(reg
, CSR7_TXDONE_TXRING
))
1325 rt2500pci_txdone(rt2x00dev
, IEEE80211_TX_QUEUE_DATA1
);
1331 * Device probe functions.
1333 static int rt2500pci_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
1335 struct eeprom_93cx6 eeprom
;
1340 rt2x00pci_register_read(rt2x00dev
, CSR21
, ®
);
1342 eeprom
.data
= rt2x00dev
;
1343 eeprom
.register_read
= rt2500pci_eepromregister_read
;
1344 eeprom
.register_write
= rt2500pci_eepromregister_write
;
1345 eeprom
.width
= rt2x00_get_field32(reg
, CSR21_TYPE_93C46
) ?
1346 PCI_EEPROM_WIDTH_93C46
: PCI_EEPROM_WIDTH_93C66
;
1347 eeprom
.reg_data_in
= 0;
1348 eeprom
.reg_data_out
= 0;
1349 eeprom
.reg_data_clock
= 0;
1350 eeprom
.reg_chip_select
= 0;
1352 eeprom_93cx6_multiread(&eeprom
, EEPROM_BASE
, rt2x00dev
->eeprom
,
1353 EEPROM_SIZE
/ sizeof(u16
));
1356 * Start validation of the data that has been read.
1358 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
1359 if (!is_valid_ether_addr(mac
)) {
1360 DECLARE_MAC_BUF(macbuf
);
1362 random_ether_addr(mac
);
1363 EEPROM(rt2x00dev
, "MAC: %s\n",
1364 print_mac(macbuf
, mac
));
1367 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
1368 if (word
== 0xffff) {
1369 rt2x00_set_field16(&word
, EEPROM_ANTENNA_NUM
, 2);
1370 rt2x00_set_field16(&word
, EEPROM_ANTENNA_TX_DEFAULT
,
1371 ANTENNA_SW_DIVERSITY
);
1372 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RX_DEFAULT
,
1373 ANTENNA_SW_DIVERSITY
);
1374 rt2x00_set_field16(&word
, EEPROM_ANTENNA_LED_MODE
,
1376 rt2x00_set_field16(&word
, EEPROM_ANTENNA_DYN_TXAGC
, 0);
1377 rt2x00_set_field16(&word
, EEPROM_ANTENNA_HARDWARE_RADIO
, 0);
1378 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RF_TYPE
, RF2522
);
1379 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
1380 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
1383 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &word
);
1384 if (word
== 0xffff) {
1385 rt2x00_set_field16(&word
, EEPROM_NIC_CARDBUS_ACCEL
, 0);
1386 rt2x00_set_field16(&word
, EEPROM_NIC_DYN_BBP_TUNE
, 0);
1387 rt2x00_set_field16(&word
, EEPROM_NIC_CCK_TX_POWER
, 0);
1388 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC
, word
);
1389 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
1392 rt2x00_eeprom_read(rt2x00dev
, EEPROM_CALIBRATE_OFFSET
, &word
);
1393 if (word
== 0xffff) {
1394 rt2x00_set_field16(&word
, EEPROM_CALIBRATE_OFFSET_RSSI
,
1395 DEFAULT_RSSI_OFFSET
);
1396 rt2x00_eeprom_write(rt2x00dev
, EEPROM_CALIBRATE_OFFSET
, word
);
1397 EEPROM(rt2x00dev
, "Calibrate offset: 0x%04x\n", word
);
1403 static int rt2500pci_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
1410 * Read EEPROM word for configuration.
1412 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
1415 * Identify RF chipset.
1417 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
1418 rt2x00pci_register_read(rt2x00dev
, CSR0
, ®
);
1419 rt2x00_set_chip(rt2x00dev
, RT2560
, value
, reg
);
1421 if (!rt2x00_rf(&rt2x00dev
->chip
, RF2522
) &&
1422 !rt2x00_rf(&rt2x00dev
->chip
, RF2523
) &&
1423 !rt2x00_rf(&rt2x00dev
->chip
, RF2524
) &&
1424 !rt2x00_rf(&rt2x00dev
->chip
, RF2525
) &&
1425 !rt2x00_rf(&rt2x00dev
->chip
, RF2525E
) &&
1426 !rt2x00_rf(&rt2x00dev
->chip
, RF5222
)) {
1427 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
1432 * Identify default antenna configuration.
1434 rt2x00dev
->default_ant
.tx
=
1435 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TX_DEFAULT
);
1436 rt2x00dev
->default_ant
.rx
=
1437 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RX_DEFAULT
);
1440 * Store led mode, for correct led behaviour.
1442 rt2x00dev
->led_mode
=
1443 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_LED_MODE
);
1446 * Detect if this device has an hardware controlled radio.
1448 #ifdef CONFIG_RT2500PCI_RFKILL
1449 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_HARDWARE_RADIO
))
1450 __set_bit(CONFIG_SUPPORT_HW_BUTTON
, &rt2x00dev
->flags
);
1451 #endif /* CONFIG_RT2500PCI_RFKILL */
1454 * Check if the BBP tuning should be enabled.
1456 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
1458 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_DYN_BBP_TUNE
))
1459 __set_bit(CONFIG_DISABLE_LINK_TUNING
, &rt2x00dev
->flags
);
1462 * Read the RSSI <-> dBm offset information.
1464 rt2x00_eeprom_read(rt2x00dev
, EEPROM_CALIBRATE_OFFSET
, &eeprom
);
1465 rt2x00dev
->rssi_offset
=
1466 rt2x00_get_field16(eeprom
, EEPROM_CALIBRATE_OFFSET_RSSI
);
1472 * RF value list for RF2522
1475 static const struct rf_channel rf_vals_bg_2522
[] = {
1476 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1477 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1478 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1479 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1480 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1481 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1482 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1483 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1484 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1485 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1486 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1487 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1488 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1489 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1493 * RF value list for RF2523
1496 static const struct rf_channel rf_vals_bg_2523
[] = {
1497 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1498 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1499 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1500 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1501 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1502 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1503 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1504 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1505 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1506 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1507 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1508 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1509 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1510 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1514 * RF value list for RF2524
1517 static const struct rf_channel rf_vals_bg_2524
[] = {
1518 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1519 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1520 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1521 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1522 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1523 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1524 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1525 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1526 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1527 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1528 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1529 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1530 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1531 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1535 * RF value list for RF2525
1538 static const struct rf_channel rf_vals_bg_2525
[] = {
1539 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1540 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1541 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1542 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1543 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1544 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1545 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1546 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1547 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1548 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1549 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1550 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1551 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1552 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1556 * RF value list for RF2525e
1559 static const struct rf_channel rf_vals_bg_2525e
[] = {
1560 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1561 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1562 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1563 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1564 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1565 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1566 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1567 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1568 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1569 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1570 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1571 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1572 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1573 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1577 * RF value list for RF5222
1578 * Supports: 2.4 GHz & 5.2 GHz
1580 static const struct rf_channel rf_vals_5222
[] = {
1581 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1582 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1583 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1584 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1585 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1586 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1587 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1588 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1589 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1590 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1591 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1592 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1593 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1594 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1596 /* 802.11 UNI / HyperLan 2 */
1597 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1598 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1599 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1600 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1601 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1602 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1603 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1604 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1606 /* 802.11 HyperLan 2 */
1607 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1608 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1609 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1610 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1611 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1612 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1613 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1614 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1615 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1616 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1619 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1620 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1621 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1622 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1623 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1626 static void rt2500pci_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
1628 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
1633 * Initialize all hw fields.
1635 rt2x00dev
->hw
->flags
= IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
;
1636 rt2x00dev
->hw
->extra_tx_headroom
= 0;
1637 rt2x00dev
->hw
->max_signal
= MAX_SIGNAL
;
1638 rt2x00dev
->hw
->max_rssi
= MAX_RX_SSI
;
1639 rt2x00dev
->hw
->queues
= 2;
1641 SET_IEEE80211_DEV(rt2x00dev
->hw
, &rt2x00dev_pci(rt2x00dev
)->dev
);
1642 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
1643 rt2x00_eeprom_addr(rt2x00dev
,
1644 EEPROM_MAC_ADDR_0
));
1647 * Convert tx_power array in eeprom.
1649 txpower
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_START
);
1650 for (i
= 0; i
< 14; i
++)
1651 txpower
[i
] = TXPOWER_FROM_DEV(txpower
[i
]);
1654 * Initialize hw_mode information.
1656 spec
->num_modes
= 2;
1657 spec
->num_rates
= 12;
1658 spec
->tx_power_a
= NULL
;
1659 spec
->tx_power_bg
= txpower
;
1660 spec
->tx_power_default
= DEFAULT_TXPOWER
;
1662 if (rt2x00_rf(&rt2x00dev
->chip
, RF2522
)) {
1663 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2522
);
1664 spec
->channels
= rf_vals_bg_2522
;
1665 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF2523
)) {
1666 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2523
);
1667 spec
->channels
= rf_vals_bg_2523
;
1668 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF2524
)) {
1669 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2524
);
1670 spec
->channels
= rf_vals_bg_2524
;
1671 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF2525
)) {
1672 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2525
);
1673 spec
->channels
= rf_vals_bg_2525
;
1674 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF2525E
)) {
1675 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2525e
);
1676 spec
->channels
= rf_vals_bg_2525e
;
1677 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF5222
)) {
1678 spec
->num_channels
= ARRAY_SIZE(rf_vals_5222
);
1679 spec
->channels
= rf_vals_5222
;
1680 spec
->num_modes
= 3;
1684 static int rt2500pci_probe_hw(struct rt2x00_dev
*rt2x00dev
)
1689 * Allocate eeprom data.
1691 retval
= rt2500pci_validate_eeprom(rt2x00dev
);
1695 retval
= rt2500pci_init_eeprom(rt2x00dev
);
1700 * Initialize hw specifications.
1702 rt2500pci_probe_hw_mode(rt2x00dev
);
1705 * This device requires the atim queue
1707 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE
, &rt2x00dev
->flags
);
1710 * Set the rssi offset.
1712 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
1718 * IEEE80211 stack callback functions.
1720 static void rt2500pci_configure_filter(struct ieee80211_hw
*hw
,
1721 unsigned int changed_flags
,
1722 unsigned int *total_flags
,
1724 struct dev_addr_list
*mc_list
)
1726 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1730 * Mask off any flags we are going to ignore from
1731 * the total_flags field.
1742 * Apply some rules to the filters:
1743 * - Some filters imply different filters to be set.
1744 * - Some things we can't filter out at all.
1747 *total_flags
|= FIF_ALLMULTI
;
1748 if (*total_flags
& FIF_OTHER_BSS
||
1749 *total_flags
& FIF_PROMISC_IN_BSS
)
1750 *total_flags
|= FIF_PROMISC_IN_BSS
| FIF_OTHER_BSS
;
1753 * Check if there is any work left for us.
1755 if (rt2x00dev
->packet_filter
== *total_flags
)
1757 rt2x00dev
->packet_filter
= *total_flags
;
1760 * Start configuration steps.
1761 * Note that the version error will always be dropped
1762 * and broadcast frames will always be accepted since
1763 * there is no filter for it at this time.
1765 rt2x00pci_register_read(rt2x00dev
, RXCSR0
, ®
);
1766 rt2x00_set_field32(®
, RXCSR0_DROP_CRC
,
1767 !(*total_flags
& FIF_FCSFAIL
));
1768 rt2x00_set_field32(®
, RXCSR0_DROP_PHYSICAL
,
1769 !(*total_flags
& FIF_PLCPFAIL
));
1770 rt2x00_set_field32(®
, RXCSR0_DROP_CONTROL
,
1771 !(*total_flags
& FIF_CONTROL
));
1772 rt2x00_set_field32(®
, RXCSR0_DROP_NOT_TO_ME
,
1773 !(*total_flags
& FIF_PROMISC_IN_BSS
));
1774 rt2x00_set_field32(®
, RXCSR0_DROP_TODS
,
1775 !(*total_flags
& FIF_PROMISC_IN_BSS
));
1776 rt2x00_set_field32(®
, RXCSR0_DROP_VERSION_ERROR
, 1);
1777 rt2x00_set_field32(®
, RXCSR0_DROP_MCAST
,
1778 !(*total_flags
& FIF_ALLMULTI
));
1779 rt2x00_set_field32(®
, RXCSR0_DROP_BCAST
, 0);
1780 rt2x00pci_register_write(rt2x00dev
, RXCSR0
, reg
);
1783 static int rt2500pci_set_retry_limit(struct ieee80211_hw
*hw
,
1784 u32 short_retry
, u32 long_retry
)
1786 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1789 rt2x00pci_register_read(rt2x00dev
, CSR11
, ®
);
1790 rt2x00_set_field32(®
, CSR11_LONG_RETRY
, long_retry
);
1791 rt2x00_set_field32(®
, CSR11_SHORT_RETRY
, short_retry
);
1792 rt2x00pci_register_write(rt2x00dev
, CSR11
, reg
);
1797 static u64
rt2500pci_get_tsf(struct ieee80211_hw
*hw
)
1799 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1803 rt2x00pci_register_read(rt2x00dev
, CSR17
, ®
);
1804 tsf
= (u64
) rt2x00_get_field32(reg
, CSR17_HIGH_TSFTIMER
) << 32;
1805 rt2x00pci_register_read(rt2x00dev
, CSR16
, ®
);
1806 tsf
|= rt2x00_get_field32(reg
, CSR16_LOW_TSFTIMER
);
1811 static void rt2500pci_reset_tsf(struct ieee80211_hw
*hw
)
1813 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1815 rt2x00pci_register_write(rt2x00dev
, CSR16
, 0);
1816 rt2x00pci_register_write(rt2x00dev
, CSR17
, 0);
1819 static int rt2500pci_tx_last_beacon(struct ieee80211_hw
*hw
)
1821 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1824 rt2x00pci_register_read(rt2x00dev
, CSR15
, ®
);
1825 return rt2x00_get_field32(reg
, CSR15_BEACON_SENT
);
1828 static const struct ieee80211_ops rt2500pci_mac80211_ops
= {
1830 .start
= rt2x00mac_start
,
1831 .stop
= rt2x00mac_stop
,
1832 .add_interface
= rt2x00mac_add_interface
,
1833 .remove_interface
= rt2x00mac_remove_interface
,
1834 .config
= rt2x00mac_config
,
1835 .config_interface
= rt2x00mac_config_interface
,
1836 .configure_filter
= rt2500pci_configure_filter
,
1837 .get_stats
= rt2x00mac_get_stats
,
1838 .set_retry_limit
= rt2500pci_set_retry_limit
,
1839 .bss_info_changed
= rt2x00mac_bss_info_changed
,
1840 .conf_tx
= rt2x00mac_conf_tx
,
1841 .get_tx_stats
= rt2x00mac_get_tx_stats
,
1842 .get_tsf
= rt2500pci_get_tsf
,
1843 .reset_tsf
= rt2500pci_reset_tsf
,
1844 .beacon_update
= rt2x00pci_beacon_update
,
1845 .tx_last_beacon
= rt2500pci_tx_last_beacon
,
1848 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops
= {
1849 .irq_handler
= rt2500pci_interrupt
,
1850 .probe_hw
= rt2500pci_probe_hw
,
1851 .initialize
= rt2x00pci_initialize
,
1852 .uninitialize
= rt2x00pci_uninitialize
,
1853 .init_rxentry
= rt2500pci_init_rxentry
,
1854 .init_txentry
= rt2500pci_init_txentry
,
1855 .set_device_state
= rt2500pci_set_device_state
,
1856 .rfkill_poll
= rt2500pci_rfkill_poll
,
1857 .link_stats
= rt2500pci_link_stats
,
1858 .reset_tuner
= rt2500pci_reset_tuner
,
1859 .link_tuner
= rt2500pci_link_tuner
,
1860 .write_tx_desc
= rt2500pci_write_tx_desc
,
1861 .write_tx_data
= rt2x00pci_write_tx_data
,
1862 .kick_tx_queue
= rt2500pci_kick_tx_queue
,
1863 .fill_rxdone
= rt2500pci_fill_rxdone
,
1864 .config_mac_addr
= rt2500pci_config_mac_addr
,
1865 .config_bssid
= rt2500pci_config_bssid
,
1866 .config_type
= rt2500pci_config_type
,
1867 .config_preamble
= rt2500pci_config_preamble
,
1868 .config
= rt2500pci_config
,
1871 static const struct data_queue_desc rt2500pci_queue_rx
= {
1872 .entry_num
= RX_ENTRIES
,
1873 .data_size
= DATA_FRAME_SIZE
,
1874 .desc_size
= RXD_DESC_SIZE
,
1875 .priv_size
= sizeof(struct queue_entry_priv_pci_rx
),
1878 static const struct data_queue_desc rt2500pci_queue_tx
= {
1879 .entry_num
= TX_ENTRIES
,
1880 .data_size
= DATA_FRAME_SIZE
,
1881 .desc_size
= TXD_DESC_SIZE
,
1882 .priv_size
= sizeof(struct queue_entry_priv_pci_tx
),
1885 static const struct data_queue_desc rt2500pci_queue_bcn
= {
1886 .entry_num
= BEACON_ENTRIES
,
1887 .data_size
= MGMT_FRAME_SIZE
,
1888 .desc_size
= TXD_DESC_SIZE
,
1889 .priv_size
= sizeof(struct queue_entry_priv_pci_tx
),
1892 static const struct data_queue_desc rt2500pci_queue_atim
= {
1893 .entry_num
= ATIM_ENTRIES
,
1894 .data_size
= DATA_FRAME_SIZE
,
1895 .desc_size
= TXD_DESC_SIZE
,
1896 .priv_size
= sizeof(struct queue_entry_priv_pci_tx
),
1899 static const struct rt2x00_ops rt2500pci_ops
= {
1900 .name
= KBUILD_MODNAME
,
1901 .eeprom_size
= EEPROM_SIZE
,
1903 .rx
= &rt2500pci_queue_rx
,
1904 .tx
= &rt2500pci_queue_tx
,
1905 .bcn
= &rt2500pci_queue_bcn
,
1906 .atim
= &rt2500pci_queue_atim
,
1907 .lib
= &rt2500pci_rt2x00_ops
,
1908 .hw
= &rt2500pci_mac80211_ops
,
1909 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1910 .debugfs
= &rt2500pci_rt2x00debug
,
1911 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1915 * RT2500pci module information.
1917 static struct pci_device_id rt2500pci_device_table
[] = {
1918 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops
) },
1922 MODULE_AUTHOR(DRV_PROJECT
);
1923 MODULE_VERSION(DRV_VERSION
);
1924 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1925 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1926 MODULE_DEVICE_TABLE(pci
, rt2500pci_device_table
);
1927 MODULE_LICENSE("GPL");
1929 static struct pci_driver rt2500pci_driver
= {
1930 .name
= KBUILD_MODNAME
,
1931 .id_table
= rt2500pci_device_table
,
1932 .probe
= rt2x00pci_probe
,
1933 .remove
= __devexit_p(rt2x00pci_remove
),
1934 .suspend
= rt2x00pci_suspend
,
1935 .resume
= rt2x00pci_resume
,
1938 static int __init
rt2500pci_init(void)
1940 return pci_register_driver(&rt2500pci_driver
);
1943 static void __exit
rt2500pci_exit(void)
1945 pci_unregister_driver(&rt2500pci_driver
);
1948 module_init(rt2500pci_init
);
1949 module_exit(rt2500pci_exit
);