2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
36 #include "rt2x00pci.h"
37 #include "rt2500pci.h"
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
52 #define WAIT_FOR_BBP(__dev, __reg) \
53 rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
54 #define WAIT_FOR_RF(__dev, __reg) \
55 rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
57 static void rt2500pci_bbp_write(struct rt2x00_dev
*rt2x00dev
,
58 const unsigned int word
, const u8 value
)
62 mutex_lock(&rt2x00dev
->csr_mutex
);
65 * Wait until the BBP becomes available, afterwards we
66 * can safely write the new data into the register.
68 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
70 rt2x00_set_field32(®
, BBPCSR_VALUE
, value
);
71 rt2x00_set_field32(®
, BBPCSR_REGNUM
, word
);
72 rt2x00_set_field32(®
, BBPCSR_BUSY
, 1);
73 rt2x00_set_field32(®
, BBPCSR_WRITE_CONTROL
, 1);
75 rt2x00pci_register_write(rt2x00dev
, BBPCSR
, reg
);
78 mutex_unlock(&rt2x00dev
->csr_mutex
);
81 static void rt2500pci_bbp_read(struct rt2x00_dev
*rt2x00dev
,
82 const unsigned int word
, u8
*value
)
86 mutex_lock(&rt2x00dev
->csr_mutex
);
89 * Wait until the BBP becomes available, afterwards we
90 * can safely write the read request into the register.
91 * After the data has been written, we wait until hardware
92 * returns the correct value, if at any time the register
93 * doesn't become available in time, reg will be 0xffffffff
94 * which means we return 0xff to the caller.
96 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
98 rt2x00_set_field32(®
, BBPCSR_REGNUM
, word
);
99 rt2x00_set_field32(®
, BBPCSR_BUSY
, 1);
100 rt2x00_set_field32(®
, BBPCSR_WRITE_CONTROL
, 0);
102 rt2x00pci_register_write(rt2x00dev
, BBPCSR
, reg
);
104 WAIT_FOR_BBP(rt2x00dev
, ®
);
107 *value
= rt2x00_get_field32(reg
, BBPCSR_VALUE
);
109 mutex_unlock(&rt2x00dev
->csr_mutex
);
112 static void rt2500pci_rf_write(struct rt2x00_dev
*rt2x00dev
,
113 const unsigned int word
, const u32 value
)
117 mutex_lock(&rt2x00dev
->csr_mutex
);
120 * Wait until the RF becomes available, afterwards we
121 * can safely write the new data into the register.
123 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
125 rt2x00_set_field32(®
, RFCSR_VALUE
, value
);
126 rt2x00_set_field32(®
, RFCSR_NUMBER_OF_BITS
, 20);
127 rt2x00_set_field32(®
, RFCSR_IF_SELECT
, 0);
128 rt2x00_set_field32(®
, RFCSR_BUSY
, 1);
130 rt2x00pci_register_write(rt2x00dev
, RFCSR
, reg
);
131 rt2x00_rf_write(rt2x00dev
, word
, value
);
134 mutex_unlock(&rt2x00dev
->csr_mutex
);
137 static void rt2500pci_eepromregister_read(struct eeprom_93cx6
*eeprom
)
139 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
142 rt2x00pci_register_read(rt2x00dev
, CSR21
, ®
);
144 eeprom
->reg_data_in
= !!rt2x00_get_field32(reg
, CSR21_EEPROM_DATA_IN
);
145 eeprom
->reg_data_out
= !!rt2x00_get_field32(reg
, CSR21_EEPROM_DATA_OUT
);
146 eeprom
->reg_data_clock
=
147 !!rt2x00_get_field32(reg
, CSR21_EEPROM_DATA_CLOCK
);
148 eeprom
->reg_chip_select
=
149 !!rt2x00_get_field32(reg
, CSR21_EEPROM_CHIP_SELECT
);
152 static void rt2500pci_eepromregister_write(struct eeprom_93cx6
*eeprom
)
154 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
157 rt2x00_set_field32(®
, CSR21_EEPROM_DATA_IN
, !!eeprom
->reg_data_in
);
158 rt2x00_set_field32(®
, CSR21_EEPROM_DATA_OUT
, !!eeprom
->reg_data_out
);
159 rt2x00_set_field32(®
, CSR21_EEPROM_DATA_CLOCK
,
160 !!eeprom
->reg_data_clock
);
161 rt2x00_set_field32(®
, CSR21_EEPROM_CHIP_SELECT
,
162 !!eeprom
->reg_chip_select
);
164 rt2x00pci_register_write(rt2x00dev
, CSR21
, reg
);
167 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
168 static const struct rt2x00debug rt2500pci_rt2x00debug
= {
169 .owner
= THIS_MODULE
,
171 .read
= rt2x00pci_register_read
,
172 .write
= rt2x00pci_register_write
,
173 .flags
= RT2X00DEBUGFS_OFFSET
,
174 .word_base
= CSR_REG_BASE
,
175 .word_size
= sizeof(u32
),
176 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
179 .read
= rt2x00_eeprom_read
,
180 .write
= rt2x00_eeprom_write
,
181 .word_base
= EEPROM_BASE
,
182 .word_size
= sizeof(u16
),
183 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
186 .read
= rt2500pci_bbp_read
,
187 .write
= rt2500pci_bbp_write
,
188 .word_base
= BBP_BASE
,
189 .word_size
= sizeof(u8
),
190 .word_count
= BBP_SIZE
/ sizeof(u8
),
193 .read
= rt2x00_rf_read
,
194 .write
= rt2500pci_rf_write
,
195 .word_base
= RF_BASE
,
196 .word_size
= sizeof(u32
),
197 .word_count
= RF_SIZE
/ sizeof(u32
),
200 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
202 #ifdef CONFIG_RT2X00_LIB_RFKILL
203 static int rt2500pci_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
207 rt2x00pci_register_read(rt2x00dev
, GPIOCSR
, ®
);
208 return rt2x00_get_field32(reg
, GPIOCSR_BIT0
);
211 #define rt2500pci_rfkill_poll NULL
212 #endif /* CONFIG_RT2X00_LIB_RFKILL */
214 #ifdef CONFIG_RT2X00_LIB_LEDS
215 static void rt2500pci_brightness_set(struct led_classdev
*led_cdev
,
216 enum led_brightness brightness
)
218 struct rt2x00_led
*led
=
219 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
220 unsigned int enabled
= brightness
!= LED_OFF
;
223 rt2x00pci_register_read(led
->rt2x00dev
, LEDCSR
, ®
);
225 if (led
->type
== LED_TYPE_RADIO
|| led
->type
== LED_TYPE_ASSOC
)
226 rt2x00_set_field32(®
, LEDCSR_LINK
, enabled
);
227 else if (led
->type
== LED_TYPE_ACTIVITY
)
228 rt2x00_set_field32(®
, LEDCSR_ACTIVITY
, enabled
);
230 rt2x00pci_register_write(led
->rt2x00dev
, LEDCSR
, reg
);
233 static int rt2500pci_blink_set(struct led_classdev
*led_cdev
,
234 unsigned long *delay_on
,
235 unsigned long *delay_off
)
237 struct rt2x00_led
*led
=
238 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
241 rt2x00pci_register_read(led
->rt2x00dev
, LEDCSR
, ®
);
242 rt2x00_set_field32(®
, LEDCSR_ON_PERIOD
, *delay_on
);
243 rt2x00_set_field32(®
, LEDCSR_OFF_PERIOD
, *delay_off
);
244 rt2x00pci_register_write(led
->rt2x00dev
, LEDCSR
, reg
);
249 static void rt2500pci_init_led(struct rt2x00_dev
*rt2x00dev
,
250 struct rt2x00_led
*led
,
253 led
->rt2x00dev
= rt2x00dev
;
255 led
->led_dev
.brightness_set
= rt2500pci_brightness_set
;
256 led
->led_dev
.blink_set
= rt2500pci_blink_set
;
257 led
->flags
= LED_INITIALIZED
;
259 #endif /* CONFIG_RT2X00_LIB_LEDS */
262 * Configuration handlers.
264 static void rt2500pci_config_filter(struct rt2x00_dev
*rt2x00dev
,
265 const unsigned int filter_flags
)
270 * Start configuration steps.
271 * Note that the version error will always be dropped
272 * and broadcast frames will always be accepted since
273 * there is no filter for it at this time.
275 rt2x00pci_register_read(rt2x00dev
, RXCSR0
, ®
);
276 rt2x00_set_field32(®
, RXCSR0_DROP_CRC
,
277 !(filter_flags
& FIF_FCSFAIL
));
278 rt2x00_set_field32(®
, RXCSR0_DROP_PHYSICAL
,
279 !(filter_flags
& FIF_PLCPFAIL
));
280 rt2x00_set_field32(®
, RXCSR0_DROP_CONTROL
,
281 !(filter_flags
& FIF_CONTROL
));
282 rt2x00_set_field32(®
, RXCSR0_DROP_NOT_TO_ME
,
283 !(filter_flags
& FIF_PROMISC_IN_BSS
));
284 rt2x00_set_field32(®
, RXCSR0_DROP_TODS
,
285 !(filter_flags
& FIF_PROMISC_IN_BSS
) &&
286 !rt2x00dev
->intf_ap_count
);
287 rt2x00_set_field32(®
, RXCSR0_DROP_VERSION_ERROR
, 1);
288 rt2x00_set_field32(®
, RXCSR0_DROP_MCAST
,
289 !(filter_flags
& FIF_ALLMULTI
));
290 rt2x00_set_field32(®
, RXCSR0_DROP_BCAST
, 0);
291 rt2x00pci_register_write(rt2x00dev
, RXCSR0
, reg
);
294 static void rt2500pci_config_intf(struct rt2x00_dev
*rt2x00dev
,
295 struct rt2x00_intf
*intf
,
296 struct rt2x00intf_conf
*conf
,
297 const unsigned int flags
)
299 struct data_queue
*queue
= rt2x00queue_get_queue(rt2x00dev
, QID_BEACON
);
300 unsigned int bcn_preload
;
303 if (flags
& CONFIG_UPDATE_TYPE
) {
305 * Enable beacon config
307 bcn_preload
= PREAMBLE
+ GET_DURATION(IEEE80211_HEADER
, 20);
308 rt2x00pci_register_read(rt2x00dev
, BCNCSR1
, ®
);
309 rt2x00_set_field32(®
, BCNCSR1_PRELOAD
, bcn_preload
);
310 rt2x00_set_field32(®
, BCNCSR1_BEACON_CWMIN
, queue
->cw_min
);
311 rt2x00pci_register_write(rt2x00dev
, BCNCSR1
, reg
);
314 * Enable synchronisation.
316 rt2x00pci_register_read(rt2x00dev
, CSR14
, ®
);
317 rt2x00_set_field32(®
, CSR14_TSF_COUNT
, 1);
318 rt2x00_set_field32(®
, CSR14_TSF_SYNC
, conf
->sync
);
319 rt2x00_set_field32(®
, CSR14_TBCN
, 1);
320 rt2x00pci_register_write(rt2x00dev
, CSR14
, reg
);
323 if (flags
& CONFIG_UPDATE_MAC
)
324 rt2x00pci_register_multiwrite(rt2x00dev
, CSR3
,
325 conf
->mac
, sizeof(conf
->mac
));
327 if (flags
& CONFIG_UPDATE_BSSID
)
328 rt2x00pci_register_multiwrite(rt2x00dev
, CSR5
,
329 conf
->bssid
, sizeof(conf
->bssid
));
332 static void rt2500pci_config_erp(struct rt2x00_dev
*rt2x00dev
,
333 struct rt2x00lib_erp
*erp
)
339 * When short preamble is enabled, we should set bit 0x08
341 preamble_mask
= erp
->short_preamble
<< 3;
343 rt2x00pci_register_read(rt2x00dev
, TXCSR1
, ®
);
344 rt2x00_set_field32(®
, TXCSR1_ACK_TIMEOUT
,
346 rt2x00_set_field32(®
, TXCSR1_ACK_CONSUME_TIME
,
347 erp
->ack_consume_time
);
348 rt2x00pci_register_write(rt2x00dev
, TXCSR1
, reg
);
350 rt2x00pci_register_read(rt2x00dev
, ARCSR2
, ®
);
351 rt2x00_set_field32(®
, ARCSR2_SIGNAL
, 0x00);
352 rt2x00_set_field32(®
, ARCSR2_SERVICE
, 0x04);
353 rt2x00_set_field32(®
, ARCSR2_LENGTH
, GET_DURATION(ACK_SIZE
, 10));
354 rt2x00pci_register_write(rt2x00dev
, ARCSR2
, reg
);
356 rt2x00pci_register_read(rt2x00dev
, ARCSR3
, ®
);
357 rt2x00_set_field32(®
, ARCSR3_SIGNAL
, 0x01 | preamble_mask
);
358 rt2x00_set_field32(®
, ARCSR3_SERVICE
, 0x04);
359 rt2x00_set_field32(®
, ARCSR2_LENGTH
, GET_DURATION(ACK_SIZE
, 20));
360 rt2x00pci_register_write(rt2x00dev
, ARCSR3
, reg
);
362 rt2x00pci_register_read(rt2x00dev
, ARCSR4
, ®
);
363 rt2x00_set_field32(®
, ARCSR4_SIGNAL
, 0x02 | preamble_mask
);
364 rt2x00_set_field32(®
, ARCSR4_SERVICE
, 0x04);
365 rt2x00_set_field32(®
, ARCSR2_LENGTH
, GET_DURATION(ACK_SIZE
, 55));
366 rt2x00pci_register_write(rt2x00dev
, ARCSR4
, reg
);
368 rt2x00pci_register_read(rt2x00dev
, ARCSR5
, ®
);
369 rt2x00_set_field32(®
, ARCSR5_SIGNAL
, 0x03 | preamble_mask
);
370 rt2x00_set_field32(®
, ARCSR5_SERVICE
, 0x84);
371 rt2x00_set_field32(®
, ARCSR2_LENGTH
, GET_DURATION(ACK_SIZE
, 110));
372 rt2x00pci_register_write(rt2x00dev
, ARCSR5
, reg
);
374 rt2x00pci_register_write(rt2x00dev
, ARCSR1
, erp
->basic_rates
);
376 rt2x00pci_register_read(rt2x00dev
, CSR11
, ®
);
377 rt2x00_set_field32(®
, CSR11_SLOT_TIME
, erp
->slot_time
);
378 rt2x00pci_register_write(rt2x00dev
, CSR11
, reg
);
380 rt2x00pci_register_read(rt2x00dev
, CSR18
, ®
);
381 rt2x00_set_field32(®
, CSR18_SIFS
, erp
->sifs
);
382 rt2x00_set_field32(®
, CSR18_PIFS
, erp
->pifs
);
383 rt2x00pci_register_write(rt2x00dev
, CSR18
, reg
);
385 rt2x00pci_register_read(rt2x00dev
, CSR19
, ®
);
386 rt2x00_set_field32(®
, CSR19_DIFS
, erp
->difs
);
387 rt2x00_set_field32(®
, CSR19_EIFS
, erp
->eifs
);
388 rt2x00pci_register_write(rt2x00dev
, CSR19
, reg
);
391 static void rt2500pci_config_ant(struct rt2x00_dev
*rt2x00dev
,
392 struct antenna_setup
*ant
)
399 * We should never come here because rt2x00lib is supposed
400 * to catch this and send us the correct antenna explicitely.
402 BUG_ON(ant
->rx
== ANTENNA_SW_DIVERSITY
||
403 ant
->tx
== ANTENNA_SW_DIVERSITY
);
405 rt2x00pci_register_read(rt2x00dev
, BBPCSR1
, ®
);
406 rt2500pci_bbp_read(rt2x00dev
, 14, &r14
);
407 rt2500pci_bbp_read(rt2x00dev
, 2, &r2
);
410 * Configure the TX antenna.
414 rt2x00_set_field8(&r2
, BBP_R2_TX_ANTENNA
, 0);
415 rt2x00_set_field32(®
, BBPCSR1_CCK
, 0);
416 rt2x00_set_field32(®
, BBPCSR1_OFDM
, 0);
420 rt2x00_set_field8(&r2
, BBP_R2_TX_ANTENNA
, 2);
421 rt2x00_set_field32(®
, BBPCSR1_CCK
, 2);
422 rt2x00_set_field32(®
, BBPCSR1_OFDM
, 2);
427 * Configure the RX antenna.
431 rt2x00_set_field8(&r14
, BBP_R14_RX_ANTENNA
, 0);
435 rt2x00_set_field8(&r14
, BBP_R14_RX_ANTENNA
, 2);
440 * RT2525E and RT5222 need to flip TX I/Q
442 if (rt2x00_rf(&rt2x00dev
->chip
, RF2525E
) ||
443 rt2x00_rf(&rt2x00dev
->chip
, RF5222
)) {
444 rt2x00_set_field8(&r2
, BBP_R2_TX_IQ_FLIP
, 1);
445 rt2x00_set_field32(®
, BBPCSR1_CCK_FLIP
, 1);
446 rt2x00_set_field32(®
, BBPCSR1_OFDM_FLIP
, 1);
449 * RT2525E does not need RX I/Q Flip.
451 if (rt2x00_rf(&rt2x00dev
->chip
, RF2525E
))
452 rt2x00_set_field8(&r14
, BBP_R14_RX_IQ_FLIP
, 0);
454 rt2x00_set_field32(®
, BBPCSR1_CCK_FLIP
, 0);
455 rt2x00_set_field32(®
, BBPCSR1_OFDM_FLIP
, 0);
458 rt2x00pci_register_write(rt2x00dev
, BBPCSR1
, reg
);
459 rt2500pci_bbp_write(rt2x00dev
, 14, r14
);
460 rt2500pci_bbp_write(rt2x00dev
, 2, r2
);
463 static void rt2500pci_config_channel(struct rt2x00_dev
*rt2x00dev
,
464 struct rf_channel
*rf
, const int txpower
)
471 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER
, TXPOWER_TO_DEV(txpower
));
474 * Switch on tuning bits.
475 * For RT2523 devices we do not need to update the R1 register.
477 if (!rt2x00_rf(&rt2x00dev
->chip
, RF2523
))
478 rt2x00_set_field32(&rf
->rf1
, RF1_TUNER
, 1);
479 rt2x00_set_field32(&rf
->rf3
, RF3_TUNER
, 1);
482 * For RT2525 we should first set the channel to half band higher.
484 if (rt2x00_rf(&rt2x00dev
->chip
, RF2525
)) {
485 static const u32 vals
[] = {
486 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
487 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
488 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
489 0x00080d2e, 0x00080d3a
492 rt2500pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
493 rt2500pci_rf_write(rt2x00dev
, 2, vals
[rf
->channel
- 1]);
494 rt2500pci_rf_write(rt2x00dev
, 3, rf
->rf3
);
496 rt2500pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
499 rt2500pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
500 rt2500pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
501 rt2500pci_rf_write(rt2x00dev
, 3, rf
->rf3
);
503 rt2500pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
506 * Channel 14 requires the Japan filter bit to be set.
509 rt2x00_set_field8(&r70
, BBP_R70_JAPAN_FILTER
, rf
->channel
== 14);
510 rt2500pci_bbp_write(rt2x00dev
, 70, r70
);
515 * Switch off tuning bits.
516 * For RT2523 devices we do not need to update the R1 register.
518 if (!rt2x00_rf(&rt2x00dev
->chip
, RF2523
)) {
519 rt2x00_set_field32(&rf
->rf1
, RF1_TUNER
, 0);
520 rt2500pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
523 rt2x00_set_field32(&rf
->rf3
, RF3_TUNER
, 0);
524 rt2500pci_rf_write(rt2x00dev
, 3, rf
->rf3
);
527 * Clear false CRC during channel switch.
529 rt2x00pci_register_read(rt2x00dev
, CNT0
, &rf
->rf1
);
532 static void rt2500pci_config_txpower(struct rt2x00_dev
*rt2x00dev
,
537 rt2x00_rf_read(rt2x00dev
, 3, &rf3
);
538 rt2x00_set_field32(&rf3
, RF3_TXPOWER
, TXPOWER_TO_DEV(txpower
));
539 rt2500pci_rf_write(rt2x00dev
, 3, rf3
);
542 static void rt2500pci_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
543 struct rt2x00lib_conf
*libconf
)
547 rt2x00pci_register_read(rt2x00dev
, CSR11
, ®
);
548 rt2x00_set_field32(®
, CSR11_LONG_RETRY
,
549 libconf
->conf
->long_frame_max_tx_count
);
550 rt2x00_set_field32(®
, CSR11_SHORT_RETRY
,
551 libconf
->conf
->short_frame_max_tx_count
);
552 rt2x00pci_register_write(rt2x00dev
, CSR11
, reg
);
555 static void rt2500pci_config_duration(struct rt2x00_dev
*rt2x00dev
,
556 struct rt2x00lib_conf
*libconf
)
560 rt2x00pci_register_read(rt2x00dev
, TXCSR1
, ®
);
561 rt2x00_set_field32(®
, TXCSR1_TSF_OFFSET
, IEEE80211_HEADER
);
562 rt2x00_set_field32(®
, TXCSR1_AUTORESPONDER
, 1);
563 rt2x00pci_register_write(rt2x00dev
, TXCSR1
, reg
);
565 rt2x00pci_register_read(rt2x00dev
, CSR12
, ®
);
566 rt2x00_set_field32(®
, CSR12_BEACON_INTERVAL
,
567 libconf
->conf
->beacon_int
* 16);
568 rt2x00_set_field32(®
, CSR12_CFP_MAX_DURATION
,
569 libconf
->conf
->beacon_int
* 16);
570 rt2x00pci_register_write(rt2x00dev
, CSR12
, reg
);
573 static void rt2500pci_config_ps(struct rt2x00_dev
*rt2x00dev
,
574 struct rt2x00lib_conf
*libconf
)
576 enum dev_state state
=
577 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
578 STATE_SLEEP
: STATE_AWAKE
;
581 if (state
== STATE_SLEEP
) {
582 rt2x00pci_register_read(rt2x00dev
, CSR20
, ®
);
583 rt2x00_set_field32(®
, CSR20_DELAY_AFTER_TBCN
,
584 (libconf
->conf
->beacon_int
- 20) * 16);
585 rt2x00_set_field32(®
, CSR20_TBCN_BEFORE_WAKEUP
,
586 libconf
->conf
->listen_interval
- 1);
588 /* We must first disable autowake before it can be enabled */
589 rt2x00_set_field32(®
, CSR20_AUTOWAKE
, 0);
590 rt2x00pci_register_write(rt2x00dev
, CSR20
, reg
);
592 rt2x00_set_field32(®
, CSR20_AUTOWAKE
, 1);
593 rt2x00pci_register_write(rt2x00dev
, CSR20
, reg
);
596 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
599 static void rt2500pci_config(struct rt2x00_dev
*rt2x00dev
,
600 struct rt2x00lib_conf
*libconf
,
601 const unsigned int flags
)
603 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
)
604 rt2500pci_config_channel(rt2x00dev
, &libconf
->rf
,
605 libconf
->conf
->power_level
);
606 if ((flags
& IEEE80211_CONF_CHANGE_POWER
) &&
607 !(flags
& IEEE80211_CONF_CHANGE_CHANNEL
))
608 rt2500pci_config_txpower(rt2x00dev
,
609 libconf
->conf
->power_level
);
610 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
611 rt2500pci_config_retry_limit(rt2x00dev
, libconf
);
612 if (flags
& IEEE80211_CONF_CHANGE_BEACON_INTERVAL
)
613 rt2500pci_config_duration(rt2x00dev
, libconf
);
614 if (flags
& IEEE80211_CONF_CHANGE_PS
)
615 rt2500pci_config_ps(rt2x00dev
, libconf
);
621 static void rt2500pci_link_stats(struct rt2x00_dev
*rt2x00dev
,
622 struct link_qual
*qual
)
627 * Update FCS error count from register.
629 rt2x00pci_register_read(rt2x00dev
, CNT0
, ®
);
630 qual
->rx_failed
= rt2x00_get_field32(reg
, CNT0_FCS_ERROR
);
633 * Update False CCA count from register.
635 rt2x00pci_register_read(rt2x00dev
, CNT3
, ®
);
636 qual
->false_cca
= rt2x00_get_field32(reg
, CNT3_FALSE_CCA
);
639 static inline void rt2500pci_set_vgc(struct rt2x00_dev
*rt2x00dev
,
640 struct link_qual
*qual
, u8 vgc_level
)
642 if (qual
->vgc_level_reg
!= vgc_level
) {
643 rt2500pci_bbp_write(rt2x00dev
, 17, vgc_level
);
644 qual
->vgc_level_reg
= vgc_level
;
648 static void rt2500pci_reset_tuner(struct rt2x00_dev
*rt2x00dev
,
649 struct link_qual
*qual
)
651 rt2500pci_set_vgc(rt2x00dev
, qual
, 0x48);
654 static void rt2500pci_link_tuner(struct rt2x00_dev
*rt2x00dev
,
655 struct link_qual
*qual
, const u32 count
)
658 * To prevent collisions with MAC ASIC on chipsets
659 * up to version C the link tuning should halt after 20
660 * seconds while being associated.
662 if (rt2x00_rev(&rt2x00dev
->chip
) < RT2560_VERSION_D
&&
663 rt2x00dev
->intf_associated
&& count
> 20)
667 * Chipset versions C and lower should directly continue
668 * to the dynamic CCA tuning. Chipset version D and higher
669 * should go straight to dynamic CCA tuning when they
670 * are not associated.
672 if (rt2x00_rev(&rt2x00dev
->chip
) < RT2560_VERSION_D
||
673 !rt2x00dev
->intf_associated
)
674 goto dynamic_cca_tune
;
677 * A too low RSSI will cause too much false CCA which will
678 * then corrupt the R17 tuning. To remidy this the tuning should
679 * be stopped (While making sure the R17 value will not exceed limits)
681 if (qual
->rssi
< -80 && count
> 20) {
682 if (qual
->vgc_level_reg
>= 0x41)
683 rt2500pci_set_vgc(rt2x00dev
, qual
, qual
->vgc_level
);
688 * Special big-R17 for short distance
690 if (qual
->rssi
>= -58) {
691 rt2500pci_set_vgc(rt2x00dev
, qual
, 0x50);
696 * Special mid-R17 for middle distance
698 if (qual
->rssi
>= -74) {
699 rt2500pci_set_vgc(rt2x00dev
, qual
, 0x41);
704 * Leave short or middle distance condition, restore r17
705 * to the dynamic tuning range.
707 if (qual
->vgc_level_reg
>= 0x41) {
708 rt2500pci_set_vgc(rt2x00dev
, qual
, qual
->vgc_level
);
715 * R17 is inside the dynamic tuning range,
716 * start tuning the link based on the false cca counter.
718 if (qual
->false_cca
> 512 && qual
->vgc_level_reg
< 0x40) {
719 rt2500pci_set_vgc(rt2x00dev
, qual
, ++qual
->vgc_level_reg
);
720 qual
->vgc_level
= qual
->vgc_level_reg
;
721 } else if (qual
->false_cca
< 100 && qual
->vgc_level_reg
> 0x32) {
722 rt2500pci_set_vgc(rt2x00dev
, qual
, --qual
->vgc_level_reg
);
723 qual
->vgc_level
= qual
->vgc_level_reg
;
728 * Initialization functions.
730 static bool rt2500pci_get_entry_state(struct queue_entry
*entry
)
732 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
735 if (entry
->queue
->qid
== QID_RX
) {
736 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
738 return rt2x00_get_field32(word
, RXD_W0_OWNER_NIC
);
740 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
742 return (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
743 rt2x00_get_field32(word
, TXD_W0_VALID
));
747 static void rt2500pci_clear_entry(struct queue_entry
*entry
)
749 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
750 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
753 if (entry
->queue
->qid
== QID_RX
) {
754 rt2x00_desc_read(entry_priv
->desc
, 1, &word
);
755 rt2x00_set_field32(&word
, RXD_W1_BUFFER_ADDRESS
, skbdesc
->skb_dma
);
756 rt2x00_desc_write(entry_priv
->desc
, 1, word
);
758 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
759 rt2x00_set_field32(&word
, RXD_W0_OWNER_NIC
, 1);
760 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
762 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
763 rt2x00_set_field32(&word
, TXD_W0_VALID
, 0);
764 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 0);
765 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
769 static int rt2500pci_init_queues(struct rt2x00_dev
*rt2x00dev
)
771 struct queue_entry_priv_pci
*entry_priv
;
775 * Initialize registers.
777 rt2x00pci_register_read(rt2x00dev
, TXCSR2
, ®
);
778 rt2x00_set_field32(®
, TXCSR2_TXD_SIZE
, rt2x00dev
->tx
[0].desc_size
);
779 rt2x00_set_field32(®
, TXCSR2_NUM_TXD
, rt2x00dev
->tx
[1].limit
);
780 rt2x00_set_field32(®
, TXCSR2_NUM_ATIM
, rt2x00dev
->bcn
[1].limit
);
781 rt2x00_set_field32(®
, TXCSR2_NUM_PRIO
, rt2x00dev
->tx
[0].limit
);
782 rt2x00pci_register_write(rt2x00dev
, TXCSR2
, reg
);
784 entry_priv
= rt2x00dev
->tx
[1].entries
[0].priv_data
;
785 rt2x00pci_register_read(rt2x00dev
, TXCSR3
, ®
);
786 rt2x00_set_field32(®
, TXCSR3_TX_RING_REGISTER
,
787 entry_priv
->desc_dma
);
788 rt2x00pci_register_write(rt2x00dev
, TXCSR3
, reg
);
790 entry_priv
= rt2x00dev
->tx
[0].entries
[0].priv_data
;
791 rt2x00pci_register_read(rt2x00dev
, TXCSR5
, ®
);
792 rt2x00_set_field32(®
, TXCSR5_PRIO_RING_REGISTER
,
793 entry_priv
->desc_dma
);
794 rt2x00pci_register_write(rt2x00dev
, TXCSR5
, reg
);
796 entry_priv
= rt2x00dev
->bcn
[1].entries
[0].priv_data
;
797 rt2x00pci_register_read(rt2x00dev
, TXCSR4
, ®
);
798 rt2x00_set_field32(®
, TXCSR4_ATIM_RING_REGISTER
,
799 entry_priv
->desc_dma
);
800 rt2x00pci_register_write(rt2x00dev
, TXCSR4
, reg
);
802 entry_priv
= rt2x00dev
->bcn
[0].entries
[0].priv_data
;
803 rt2x00pci_register_read(rt2x00dev
, TXCSR6
, ®
);
804 rt2x00_set_field32(®
, TXCSR6_BEACON_RING_REGISTER
,
805 entry_priv
->desc_dma
);
806 rt2x00pci_register_write(rt2x00dev
, TXCSR6
, reg
);
808 rt2x00pci_register_read(rt2x00dev
, RXCSR1
, ®
);
809 rt2x00_set_field32(®
, RXCSR1_RXD_SIZE
, rt2x00dev
->rx
->desc_size
);
810 rt2x00_set_field32(®
, RXCSR1_NUM_RXD
, rt2x00dev
->rx
->limit
);
811 rt2x00pci_register_write(rt2x00dev
, RXCSR1
, reg
);
813 entry_priv
= rt2x00dev
->rx
->entries
[0].priv_data
;
814 rt2x00pci_register_read(rt2x00dev
, RXCSR2
, ®
);
815 rt2x00_set_field32(®
, RXCSR2_RX_RING_REGISTER
,
816 entry_priv
->desc_dma
);
817 rt2x00pci_register_write(rt2x00dev
, RXCSR2
, reg
);
822 static int rt2500pci_init_registers(struct rt2x00_dev
*rt2x00dev
)
826 rt2x00pci_register_write(rt2x00dev
, PSCSR0
, 0x00020002);
827 rt2x00pci_register_write(rt2x00dev
, PSCSR1
, 0x00000002);
828 rt2x00pci_register_write(rt2x00dev
, PSCSR2
, 0x00020002);
829 rt2x00pci_register_write(rt2x00dev
, PSCSR3
, 0x00000002);
831 rt2x00pci_register_read(rt2x00dev
, TIMECSR
, ®
);
832 rt2x00_set_field32(®
, TIMECSR_US_COUNT
, 33);
833 rt2x00_set_field32(®
, TIMECSR_US_64_COUNT
, 63);
834 rt2x00_set_field32(®
, TIMECSR_BEACON_EXPECT
, 0);
835 rt2x00pci_register_write(rt2x00dev
, TIMECSR
, reg
);
837 rt2x00pci_register_read(rt2x00dev
, CSR9
, ®
);
838 rt2x00_set_field32(®
, CSR9_MAX_FRAME_UNIT
,
839 rt2x00dev
->rx
->data_size
/ 128);
840 rt2x00pci_register_write(rt2x00dev
, CSR9
, reg
);
843 * Always use CWmin and CWmax set in descriptor.
845 rt2x00pci_register_read(rt2x00dev
, CSR11
, ®
);
846 rt2x00_set_field32(®
, CSR11_CW_SELECT
, 0);
847 rt2x00pci_register_write(rt2x00dev
, CSR11
, reg
);
849 rt2x00pci_register_read(rt2x00dev
, CSR14
, ®
);
850 rt2x00_set_field32(®
, CSR14_TSF_COUNT
, 0);
851 rt2x00_set_field32(®
, CSR14_TSF_SYNC
, 0);
852 rt2x00_set_field32(®
, CSR14_TBCN
, 0);
853 rt2x00_set_field32(®
, CSR14_TCFP
, 0);
854 rt2x00_set_field32(®
, CSR14_TATIMW
, 0);
855 rt2x00_set_field32(®
, CSR14_BEACON_GEN
, 0);
856 rt2x00_set_field32(®
, CSR14_CFP_COUNT_PRELOAD
, 0);
857 rt2x00_set_field32(®
, CSR14_TBCM_PRELOAD
, 0);
858 rt2x00pci_register_write(rt2x00dev
, CSR14
, reg
);
860 rt2x00pci_register_write(rt2x00dev
, CNT3
, 0);
862 rt2x00pci_register_read(rt2x00dev
, TXCSR8
, ®
);
863 rt2x00_set_field32(®
, TXCSR8_BBP_ID0
, 10);
864 rt2x00_set_field32(®
, TXCSR8_BBP_ID0_VALID
, 1);
865 rt2x00_set_field32(®
, TXCSR8_BBP_ID1
, 11);
866 rt2x00_set_field32(®
, TXCSR8_BBP_ID1_VALID
, 1);
867 rt2x00_set_field32(®
, TXCSR8_BBP_ID2
, 13);
868 rt2x00_set_field32(®
, TXCSR8_BBP_ID2_VALID
, 1);
869 rt2x00_set_field32(®
, TXCSR8_BBP_ID3
, 12);
870 rt2x00_set_field32(®
, TXCSR8_BBP_ID3_VALID
, 1);
871 rt2x00pci_register_write(rt2x00dev
, TXCSR8
, reg
);
873 rt2x00pci_register_read(rt2x00dev
, ARTCSR0
, ®
);
874 rt2x00_set_field32(®
, ARTCSR0_ACK_CTS_1MBS
, 112);
875 rt2x00_set_field32(®
, ARTCSR0_ACK_CTS_2MBS
, 56);
876 rt2x00_set_field32(®
, ARTCSR0_ACK_CTS_5_5MBS
, 20);
877 rt2x00_set_field32(®
, ARTCSR0_ACK_CTS_11MBS
, 10);
878 rt2x00pci_register_write(rt2x00dev
, ARTCSR0
, reg
);
880 rt2x00pci_register_read(rt2x00dev
, ARTCSR1
, ®
);
881 rt2x00_set_field32(®
, ARTCSR1_ACK_CTS_6MBS
, 45);
882 rt2x00_set_field32(®
, ARTCSR1_ACK_CTS_9MBS
, 37);
883 rt2x00_set_field32(®
, ARTCSR1_ACK_CTS_12MBS
, 33);
884 rt2x00_set_field32(®
, ARTCSR1_ACK_CTS_18MBS
, 29);
885 rt2x00pci_register_write(rt2x00dev
, ARTCSR1
, reg
);
887 rt2x00pci_register_read(rt2x00dev
, ARTCSR2
, ®
);
888 rt2x00_set_field32(®
, ARTCSR2_ACK_CTS_24MBS
, 29);
889 rt2x00_set_field32(®
, ARTCSR2_ACK_CTS_36MBS
, 25);
890 rt2x00_set_field32(®
, ARTCSR2_ACK_CTS_48MBS
, 25);
891 rt2x00_set_field32(®
, ARTCSR2_ACK_CTS_54MBS
, 25);
892 rt2x00pci_register_write(rt2x00dev
, ARTCSR2
, reg
);
894 rt2x00pci_register_read(rt2x00dev
, RXCSR3
, ®
);
895 rt2x00_set_field32(®
, RXCSR3_BBP_ID0
, 47); /* CCK Signal */
896 rt2x00_set_field32(®
, RXCSR3_BBP_ID0_VALID
, 1);
897 rt2x00_set_field32(®
, RXCSR3_BBP_ID1
, 51); /* Rssi */
898 rt2x00_set_field32(®
, RXCSR3_BBP_ID1_VALID
, 1);
899 rt2x00_set_field32(®
, RXCSR3_BBP_ID2
, 42); /* OFDM Rate */
900 rt2x00_set_field32(®
, RXCSR3_BBP_ID2_VALID
, 1);
901 rt2x00_set_field32(®
, RXCSR3_BBP_ID3
, 51); /* RSSI */
902 rt2x00_set_field32(®
, RXCSR3_BBP_ID3_VALID
, 1);
903 rt2x00pci_register_write(rt2x00dev
, RXCSR3
, reg
);
905 rt2x00pci_register_read(rt2x00dev
, PCICSR
, ®
);
906 rt2x00_set_field32(®
, PCICSR_BIG_ENDIAN
, 0);
907 rt2x00_set_field32(®
, PCICSR_RX_TRESHOLD
, 0);
908 rt2x00_set_field32(®
, PCICSR_TX_TRESHOLD
, 3);
909 rt2x00_set_field32(®
, PCICSR_BURST_LENTH
, 1);
910 rt2x00_set_field32(®
, PCICSR_ENABLE_CLK
, 1);
911 rt2x00_set_field32(®
, PCICSR_READ_MULTIPLE
, 1);
912 rt2x00_set_field32(®
, PCICSR_WRITE_INVALID
, 1);
913 rt2x00pci_register_write(rt2x00dev
, PCICSR
, reg
);
915 rt2x00pci_register_write(rt2x00dev
, PWRCSR0
, 0x3f3b3100);
917 rt2x00pci_register_write(rt2x00dev
, GPIOCSR
, 0x0000ff00);
918 rt2x00pci_register_write(rt2x00dev
, TESTCSR
, 0x000000f0);
920 if (rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, STATE_AWAKE
))
923 rt2x00pci_register_write(rt2x00dev
, MACCSR0
, 0x00213223);
924 rt2x00pci_register_write(rt2x00dev
, MACCSR1
, 0x00235518);
926 rt2x00pci_register_read(rt2x00dev
, MACCSR2
, ®
);
927 rt2x00_set_field32(®
, MACCSR2_DELAY
, 64);
928 rt2x00pci_register_write(rt2x00dev
, MACCSR2
, reg
);
930 rt2x00pci_register_read(rt2x00dev
, RALINKCSR
, ®
);
931 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_DATA0
, 17);
932 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_ID0
, 26);
933 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_VALID0
, 1);
934 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_DATA1
, 0);
935 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_ID1
, 26);
936 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_VALID1
, 1);
937 rt2x00pci_register_write(rt2x00dev
, RALINKCSR
, reg
);
939 rt2x00pci_register_write(rt2x00dev
, BBPCSR1
, 0x82188200);
941 rt2x00pci_register_write(rt2x00dev
, TXACKCSR0
, 0x00000020);
943 rt2x00pci_register_read(rt2x00dev
, CSR1
, ®
);
944 rt2x00_set_field32(®
, CSR1_SOFT_RESET
, 1);
945 rt2x00_set_field32(®
, CSR1_BBP_RESET
, 0);
946 rt2x00_set_field32(®
, CSR1_HOST_READY
, 0);
947 rt2x00pci_register_write(rt2x00dev
, CSR1
, reg
);
949 rt2x00pci_register_read(rt2x00dev
, CSR1
, ®
);
950 rt2x00_set_field32(®
, CSR1_SOFT_RESET
, 0);
951 rt2x00_set_field32(®
, CSR1_HOST_READY
, 1);
952 rt2x00pci_register_write(rt2x00dev
, CSR1
, reg
);
955 * We must clear the FCS and FIFO error count.
956 * These registers are cleared on read,
957 * so we may pass a useless variable to store the value.
959 rt2x00pci_register_read(rt2x00dev
, CNT0
, ®
);
960 rt2x00pci_register_read(rt2x00dev
, CNT4
, ®
);
965 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
970 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
971 rt2500pci_bbp_read(rt2x00dev
, 0, &value
);
972 if ((value
!= 0xff) && (value
!= 0x00))
974 udelay(REGISTER_BUSY_DELAY
);
977 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
981 static int rt2500pci_init_bbp(struct rt2x00_dev
*rt2x00dev
)
988 if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev
)))
991 rt2500pci_bbp_write(rt2x00dev
, 3, 0x02);
992 rt2500pci_bbp_write(rt2x00dev
, 4, 0x19);
993 rt2500pci_bbp_write(rt2x00dev
, 14, 0x1c);
994 rt2500pci_bbp_write(rt2x00dev
, 15, 0x30);
995 rt2500pci_bbp_write(rt2x00dev
, 16, 0xac);
996 rt2500pci_bbp_write(rt2x00dev
, 18, 0x18);
997 rt2500pci_bbp_write(rt2x00dev
, 19, 0xff);
998 rt2500pci_bbp_write(rt2x00dev
, 20, 0x1e);
999 rt2500pci_bbp_write(rt2x00dev
, 21, 0x08);
1000 rt2500pci_bbp_write(rt2x00dev
, 22, 0x08);
1001 rt2500pci_bbp_write(rt2x00dev
, 23, 0x08);
1002 rt2500pci_bbp_write(rt2x00dev
, 24, 0x70);
1003 rt2500pci_bbp_write(rt2x00dev
, 25, 0x40);
1004 rt2500pci_bbp_write(rt2x00dev
, 26, 0x08);
1005 rt2500pci_bbp_write(rt2x00dev
, 27, 0x23);
1006 rt2500pci_bbp_write(rt2x00dev
, 30, 0x10);
1007 rt2500pci_bbp_write(rt2x00dev
, 31, 0x2b);
1008 rt2500pci_bbp_write(rt2x00dev
, 32, 0xb9);
1009 rt2500pci_bbp_write(rt2x00dev
, 34, 0x12);
1010 rt2500pci_bbp_write(rt2x00dev
, 35, 0x50);
1011 rt2500pci_bbp_write(rt2x00dev
, 39, 0xc4);
1012 rt2500pci_bbp_write(rt2x00dev
, 40, 0x02);
1013 rt2500pci_bbp_write(rt2x00dev
, 41, 0x60);
1014 rt2500pci_bbp_write(rt2x00dev
, 53, 0x10);
1015 rt2500pci_bbp_write(rt2x00dev
, 54, 0x18);
1016 rt2500pci_bbp_write(rt2x00dev
, 56, 0x08);
1017 rt2500pci_bbp_write(rt2x00dev
, 57, 0x10);
1018 rt2500pci_bbp_write(rt2x00dev
, 58, 0x08);
1019 rt2500pci_bbp_write(rt2x00dev
, 61, 0x6d);
1020 rt2500pci_bbp_write(rt2x00dev
, 62, 0x10);
1022 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
1023 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
1025 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
1026 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
1027 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
1028 rt2500pci_bbp_write(rt2x00dev
, reg_id
, value
);
1036 * Device state switch handlers.
1038 static void rt2500pci_toggle_rx(struct rt2x00_dev
*rt2x00dev
,
1039 enum dev_state state
)
1043 rt2x00pci_register_read(rt2x00dev
, RXCSR0
, ®
);
1044 rt2x00_set_field32(®
, RXCSR0_DISABLE_RX
,
1045 (state
== STATE_RADIO_RX_OFF
) ||
1046 (state
== STATE_RADIO_RX_OFF_LINK
));
1047 rt2x00pci_register_write(rt2x00dev
, RXCSR0
, reg
);
1050 static void rt2500pci_toggle_irq(struct rt2x00_dev
*rt2x00dev
,
1051 enum dev_state state
)
1053 int mask
= (state
== STATE_RADIO_IRQ_OFF
);
1057 * When interrupts are being enabled, the interrupt registers
1058 * should clear the register to assure a clean state.
1060 if (state
== STATE_RADIO_IRQ_ON
) {
1061 rt2x00pci_register_read(rt2x00dev
, CSR7
, ®
);
1062 rt2x00pci_register_write(rt2x00dev
, CSR7
, reg
);
1066 * Only toggle the interrupts bits we are going to use.
1067 * Non-checked interrupt bits are disabled by default.
1069 rt2x00pci_register_read(rt2x00dev
, CSR8
, ®
);
1070 rt2x00_set_field32(®
, CSR8_TBCN_EXPIRE
, mask
);
1071 rt2x00_set_field32(®
, CSR8_TXDONE_TXRING
, mask
);
1072 rt2x00_set_field32(®
, CSR8_TXDONE_ATIMRING
, mask
);
1073 rt2x00_set_field32(®
, CSR8_TXDONE_PRIORING
, mask
);
1074 rt2x00_set_field32(®
, CSR8_RXDONE
, mask
);
1075 rt2x00pci_register_write(rt2x00dev
, CSR8
, reg
);
1078 static int rt2500pci_enable_radio(struct rt2x00_dev
*rt2x00dev
)
1081 * Initialize all registers.
1083 if (unlikely(rt2500pci_init_queues(rt2x00dev
) ||
1084 rt2500pci_init_registers(rt2x00dev
) ||
1085 rt2500pci_init_bbp(rt2x00dev
)))
1091 static void rt2500pci_disable_radio(struct rt2x00_dev
*rt2x00dev
)
1096 rt2x00pci_register_write(rt2x00dev
, PWRCSR0
, 0);
1099 static int rt2500pci_set_state(struct rt2x00_dev
*rt2x00dev
,
1100 enum dev_state state
)
1108 put_to_sleep
= (state
!= STATE_AWAKE
);
1110 rt2x00pci_register_read(rt2x00dev
, PWRCSR1
, ®
);
1111 rt2x00_set_field32(®
, PWRCSR1_SET_STATE
, 1);
1112 rt2x00_set_field32(®
, PWRCSR1_BBP_DESIRE_STATE
, state
);
1113 rt2x00_set_field32(®
, PWRCSR1_RF_DESIRE_STATE
, state
);
1114 rt2x00_set_field32(®
, PWRCSR1_PUT_TO_SLEEP
, put_to_sleep
);
1115 rt2x00pci_register_write(rt2x00dev
, PWRCSR1
, reg
);
1118 * Device is not guaranteed to be in the requested state yet.
1119 * We must wait until the register indicates that the
1120 * device has entered the correct state.
1122 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1123 rt2x00pci_register_read(rt2x00dev
, PWRCSR1
, ®
);
1124 bbp_state
= rt2x00_get_field32(reg
, PWRCSR1_BBP_CURR_STATE
);
1125 rf_state
= rt2x00_get_field32(reg
, PWRCSR1_RF_CURR_STATE
);
1126 if (bbp_state
== state
&& rf_state
== state
)
1134 static int rt2500pci_set_device_state(struct rt2x00_dev
*rt2x00dev
,
1135 enum dev_state state
)
1140 case STATE_RADIO_ON
:
1141 retval
= rt2500pci_enable_radio(rt2x00dev
);
1143 case STATE_RADIO_OFF
:
1144 rt2500pci_disable_radio(rt2x00dev
);
1146 case STATE_RADIO_RX_ON
:
1147 case STATE_RADIO_RX_ON_LINK
:
1148 case STATE_RADIO_RX_OFF
:
1149 case STATE_RADIO_RX_OFF_LINK
:
1150 rt2500pci_toggle_rx(rt2x00dev
, state
);
1152 case STATE_RADIO_IRQ_ON
:
1153 case STATE_RADIO_IRQ_OFF
:
1154 rt2500pci_toggle_irq(rt2x00dev
, state
);
1156 case STATE_DEEP_SLEEP
:
1160 retval
= rt2500pci_set_state(rt2x00dev
, state
);
1167 if (unlikely(retval
))
1168 ERROR(rt2x00dev
, "Device failed to enter state %d (%d).\n",
1175 * TX descriptor initialization
1177 static void rt2500pci_write_tx_desc(struct rt2x00_dev
*rt2x00dev
,
1178 struct sk_buff
*skb
,
1179 struct txentry_desc
*txdesc
)
1181 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(skb
);
1182 struct queue_entry_priv_pci
*entry_priv
= skbdesc
->entry
->priv_data
;
1183 __le32
*txd
= skbdesc
->desc
;
1187 * Start writing the descriptor words.
1189 rt2x00_desc_read(entry_priv
->desc
, 1, &word
);
1190 rt2x00_set_field32(&word
, TXD_W1_BUFFER_ADDRESS
, skbdesc
->skb_dma
);
1191 rt2x00_desc_write(entry_priv
->desc
, 1, word
);
1193 rt2x00_desc_read(txd
, 2, &word
);
1194 rt2x00_set_field32(&word
, TXD_W2_IV_OFFSET
, IEEE80211_HEADER
);
1195 rt2x00_set_field32(&word
, TXD_W2_AIFS
, txdesc
->aifs
);
1196 rt2x00_set_field32(&word
, TXD_W2_CWMIN
, txdesc
->cw_min
);
1197 rt2x00_set_field32(&word
, TXD_W2_CWMAX
, txdesc
->cw_max
);
1198 rt2x00_desc_write(txd
, 2, word
);
1200 rt2x00_desc_read(txd
, 3, &word
);
1201 rt2x00_set_field32(&word
, TXD_W3_PLCP_SIGNAL
, txdesc
->signal
);
1202 rt2x00_set_field32(&word
, TXD_W3_PLCP_SERVICE
, txdesc
->service
);
1203 rt2x00_set_field32(&word
, TXD_W3_PLCP_LENGTH_LOW
, txdesc
->length_low
);
1204 rt2x00_set_field32(&word
, TXD_W3_PLCP_LENGTH_HIGH
, txdesc
->length_high
);
1205 rt2x00_desc_write(txd
, 3, word
);
1207 rt2x00_desc_read(txd
, 10, &word
);
1208 rt2x00_set_field32(&word
, TXD_W10_RTS
,
1209 test_bit(ENTRY_TXD_RTS_FRAME
, &txdesc
->flags
));
1210 rt2x00_desc_write(txd
, 10, word
);
1212 rt2x00_desc_read(txd
, 0, &word
);
1213 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 1);
1214 rt2x00_set_field32(&word
, TXD_W0_VALID
, 1);
1215 rt2x00_set_field32(&word
, TXD_W0_MORE_FRAG
,
1216 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
1217 rt2x00_set_field32(&word
, TXD_W0_ACK
,
1218 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
1219 rt2x00_set_field32(&word
, TXD_W0_TIMESTAMP
,
1220 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
1221 rt2x00_set_field32(&word
, TXD_W0_OFDM
,
1222 (txdesc
->rate_mode
== RATE_MODE_OFDM
));
1223 rt2x00_set_field32(&word
, TXD_W0_CIPHER_OWNER
, 1);
1224 rt2x00_set_field32(&word
, TXD_W0_IFS
, txdesc
->ifs
);
1225 rt2x00_set_field32(&word
, TXD_W0_RETRY_MODE
,
1226 test_bit(ENTRY_TXD_RETRY_MODE
, &txdesc
->flags
));
1227 rt2x00_set_field32(&word
, TXD_W0_DATABYTE_COUNT
, skb
->len
);
1228 rt2x00_set_field32(&word
, TXD_W0_CIPHER_ALG
, CIPHER_NONE
);
1229 rt2x00_desc_write(txd
, 0, word
);
1233 * TX data initialization
1235 static void rt2500pci_write_beacon(struct queue_entry
*entry
)
1237 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
1238 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1239 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
1244 * Disable beaconing while we are reloading the beacon data,
1245 * otherwise we might be sending out invalid data.
1247 rt2x00pci_register_read(rt2x00dev
, CSR14
, ®
);
1248 rt2x00_set_field32(®
, CSR14_TSF_COUNT
, 0);
1249 rt2x00_set_field32(®
, CSR14_TBCN
, 0);
1250 rt2x00_set_field32(®
, CSR14_BEACON_GEN
, 0);
1251 rt2x00pci_register_write(rt2x00dev
, CSR14
, reg
);
1254 * Replace rt2x00lib allocated descriptor with the
1255 * pointer to the _real_ hardware descriptor.
1256 * After that, map the beacon to DMA and update the
1259 memcpy(entry_priv
->desc
, skbdesc
->desc
, skbdesc
->desc_len
);
1260 skbdesc
->desc
= entry_priv
->desc
;
1262 rt2x00queue_map_txskb(rt2x00dev
, entry
->skb
);
1264 rt2x00_desc_read(entry_priv
->desc
, 1, &word
);
1265 rt2x00_set_field32(&word
, TXD_W1_BUFFER_ADDRESS
, skbdesc
->skb_dma
);
1266 rt2x00_desc_write(entry_priv
->desc
, 1, word
);
1269 static void rt2500pci_kick_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1270 const enum data_queue_qid queue
)
1274 if (queue
== QID_BEACON
) {
1275 rt2x00pci_register_read(rt2x00dev
, CSR14
, ®
);
1276 if (!rt2x00_get_field32(reg
, CSR14_BEACON_GEN
)) {
1277 rt2x00_set_field32(®
, CSR14_TSF_COUNT
, 1);
1278 rt2x00_set_field32(®
, CSR14_TBCN
, 1);
1279 rt2x00_set_field32(®
, CSR14_BEACON_GEN
, 1);
1280 rt2x00pci_register_write(rt2x00dev
, CSR14
, reg
);
1285 rt2x00pci_register_read(rt2x00dev
, TXCSR0
, ®
);
1286 rt2x00_set_field32(®
, TXCSR0_KICK_PRIO
, (queue
== QID_AC_BE
));
1287 rt2x00_set_field32(®
, TXCSR0_KICK_TX
, (queue
== QID_AC_BK
));
1288 rt2x00_set_field32(®
, TXCSR0_KICK_ATIM
, (queue
== QID_ATIM
));
1289 rt2x00pci_register_write(rt2x00dev
, TXCSR0
, reg
);
1292 static void rt2500pci_kill_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1293 const enum data_queue_qid qid
)
1297 if (qid
== QID_BEACON
) {
1298 rt2x00pci_register_write(rt2x00dev
, CSR14
, 0);
1300 rt2x00pci_register_read(rt2x00dev
, TXCSR0
, ®
);
1301 rt2x00_set_field32(®
, TXCSR0_ABORT
, 1);
1302 rt2x00pci_register_write(rt2x00dev
, TXCSR0
, reg
);
1307 * RX control handlers
1309 static void rt2500pci_fill_rxdone(struct queue_entry
*entry
,
1310 struct rxdone_entry_desc
*rxdesc
)
1312 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1316 rt2x00_desc_read(entry_priv
->desc
, 0, &word0
);
1317 rt2x00_desc_read(entry_priv
->desc
, 2, &word2
);
1319 if (rt2x00_get_field32(word0
, RXD_W0_CRC_ERROR
))
1320 rxdesc
->flags
|= RX_FLAG_FAILED_FCS_CRC
;
1321 if (rt2x00_get_field32(word0
, RXD_W0_PHYSICAL_ERROR
))
1322 rxdesc
->flags
|= RX_FLAG_FAILED_PLCP_CRC
;
1325 * Obtain the status about this packet.
1326 * When frame was received with an OFDM bitrate,
1327 * the signal is the PLCP value. If it was received with
1328 * a CCK bitrate the signal is the rate in 100kbit/s.
1330 rxdesc
->signal
= rt2x00_get_field32(word2
, RXD_W2_SIGNAL
);
1331 rxdesc
->rssi
= rt2x00_get_field32(word2
, RXD_W2_RSSI
) -
1332 entry
->queue
->rt2x00dev
->rssi_offset
;
1333 rxdesc
->size
= rt2x00_get_field32(word0
, RXD_W0_DATABYTE_COUNT
);
1335 if (rt2x00_get_field32(word0
, RXD_W0_OFDM
))
1336 rxdesc
->dev_flags
|= RXDONE_SIGNAL_PLCP
;
1338 rxdesc
->dev_flags
|= RXDONE_SIGNAL_BITRATE
;
1339 if (rt2x00_get_field32(word0
, RXD_W0_MY_BSS
))
1340 rxdesc
->dev_flags
|= RXDONE_MY_BSS
;
1344 * Interrupt functions.
1346 static void rt2500pci_txdone(struct rt2x00_dev
*rt2x00dev
,
1347 const enum data_queue_qid queue_idx
)
1349 struct data_queue
*queue
= rt2x00queue_get_queue(rt2x00dev
, queue_idx
);
1350 struct queue_entry_priv_pci
*entry_priv
;
1351 struct queue_entry
*entry
;
1352 struct txdone_entry_desc txdesc
;
1355 while (!rt2x00queue_empty(queue
)) {
1356 entry
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
1357 entry_priv
= entry
->priv_data
;
1358 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1360 if (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
1361 !rt2x00_get_field32(word
, TXD_W0_VALID
))
1365 * Obtain the status about this packet.
1368 switch (rt2x00_get_field32(word
, TXD_W0_RESULT
)) {
1369 case 0: /* Success */
1370 case 1: /* Success with retry */
1371 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
1373 case 2: /* Failure, excessive retries */
1374 __set_bit(TXDONE_EXCESSIVE_RETRY
, &txdesc
.flags
);
1375 /* Don't break, this is a failed frame! */
1376 default: /* Failure */
1377 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
1379 txdesc
.retry
= rt2x00_get_field32(word
, TXD_W0_RETRY_COUNT
);
1381 rt2x00lib_txdone(entry
, &txdesc
);
1385 static irqreturn_t
rt2500pci_interrupt(int irq
, void *dev_instance
)
1387 struct rt2x00_dev
*rt2x00dev
= dev_instance
;
1391 * Get the interrupt sources & saved to local variable.
1392 * Write register value back to clear pending interrupts.
1394 rt2x00pci_register_read(rt2x00dev
, CSR7
, ®
);
1395 rt2x00pci_register_write(rt2x00dev
, CSR7
, reg
);
1400 if (!test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
1404 * Handle interrupts, walk through all bits
1405 * and run the tasks, the bits are checked in order of
1410 * 1 - Beacon timer expired interrupt.
1412 if (rt2x00_get_field32(reg
, CSR7_TBCN_EXPIRE
))
1413 rt2x00lib_beacondone(rt2x00dev
);
1416 * 2 - Rx ring done interrupt.
1418 if (rt2x00_get_field32(reg
, CSR7_RXDONE
))
1419 rt2x00pci_rxdone(rt2x00dev
);
1422 * 3 - Atim ring transmit done interrupt.
1424 if (rt2x00_get_field32(reg
, CSR7_TXDONE_ATIMRING
))
1425 rt2500pci_txdone(rt2x00dev
, QID_ATIM
);
1428 * 4 - Priority ring transmit done interrupt.
1430 if (rt2x00_get_field32(reg
, CSR7_TXDONE_PRIORING
))
1431 rt2500pci_txdone(rt2x00dev
, QID_AC_BE
);
1434 * 5 - Tx ring transmit done interrupt.
1436 if (rt2x00_get_field32(reg
, CSR7_TXDONE_TXRING
))
1437 rt2500pci_txdone(rt2x00dev
, QID_AC_BK
);
1443 * Device probe functions.
1445 static int rt2500pci_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
1447 struct eeprom_93cx6 eeprom
;
1452 rt2x00pci_register_read(rt2x00dev
, CSR21
, ®
);
1454 eeprom
.data
= rt2x00dev
;
1455 eeprom
.register_read
= rt2500pci_eepromregister_read
;
1456 eeprom
.register_write
= rt2500pci_eepromregister_write
;
1457 eeprom
.width
= rt2x00_get_field32(reg
, CSR21_TYPE_93C46
) ?
1458 PCI_EEPROM_WIDTH_93C46
: PCI_EEPROM_WIDTH_93C66
;
1459 eeprom
.reg_data_in
= 0;
1460 eeprom
.reg_data_out
= 0;
1461 eeprom
.reg_data_clock
= 0;
1462 eeprom
.reg_chip_select
= 0;
1464 eeprom_93cx6_multiread(&eeprom
, EEPROM_BASE
, rt2x00dev
->eeprom
,
1465 EEPROM_SIZE
/ sizeof(u16
));
1468 * Start validation of the data that has been read.
1470 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
1471 if (!is_valid_ether_addr(mac
)) {
1472 random_ether_addr(mac
);
1473 EEPROM(rt2x00dev
, "MAC: %pM\n", mac
);
1476 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
1477 if (word
== 0xffff) {
1478 rt2x00_set_field16(&word
, EEPROM_ANTENNA_NUM
, 2);
1479 rt2x00_set_field16(&word
, EEPROM_ANTENNA_TX_DEFAULT
,
1480 ANTENNA_SW_DIVERSITY
);
1481 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RX_DEFAULT
,
1482 ANTENNA_SW_DIVERSITY
);
1483 rt2x00_set_field16(&word
, EEPROM_ANTENNA_LED_MODE
,
1485 rt2x00_set_field16(&word
, EEPROM_ANTENNA_DYN_TXAGC
, 0);
1486 rt2x00_set_field16(&word
, EEPROM_ANTENNA_HARDWARE_RADIO
, 0);
1487 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RF_TYPE
, RF2522
);
1488 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
1489 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
1492 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &word
);
1493 if (word
== 0xffff) {
1494 rt2x00_set_field16(&word
, EEPROM_NIC_CARDBUS_ACCEL
, 0);
1495 rt2x00_set_field16(&word
, EEPROM_NIC_DYN_BBP_TUNE
, 0);
1496 rt2x00_set_field16(&word
, EEPROM_NIC_CCK_TX_POWER
, 0);
1497 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC
, word
);
1498 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
1501 rt2x00_eeprom_read(rt2x00dev
, EEPROM_CALIBRATE_OFFSET
, &word
);
1502 if (word
== 0xffff) {
1503 rt2x00_set_field16(&word
, EEPROM_CALIBRATE_OFFSET_RSSI
,
1504 DEFAULT_RSSI_OFFSET
);
1505 rt2x00_eeprom_write(rt2x00dev
, EEPROM_CALIBRATE_OFFSET
, word
);
1506 EEPROM(rt2x00dev
, "Calibrate offset: 0x%04x\n", word
);
1512 static int rt2500pci_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
1519 * Read EEPROM word for configuration.
1521 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
1524 * Identify RF chipset.
1526 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
1527 rt2x00pci_register_read(rt2x00dev
, CSR0
, ®
);
1528 rt2x00_set_chip_rf(rt2x00dev
, value
, reg
);
1530 if (!rt2x00_rf(&rt2x00dev
->chip
, RF2522
) &&
1531 !rt2x00_rf(&rt2x00dev
->chip
, RF2523
) &&
1532 !rt2x00_rf(&rt2x00dev
->chip
, RF2524
) &&
1533 !rt2x00_rf(&rt2x00dev
->chip
, RF2525
) &&
1534 !rt2x00_rf(&rt2x00dev
->chip
, RF2525E
) &&
1535 !rt2x00_rf(&rt2x00dev
->chip
, RF5222
)) {
1536 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
1541 * Identify default antenna configuration.
1543 rt2x00dev
->default_ant
.tx
=
1544 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TX_DEFAULT
);
1545 rt2x00dev
->default_ant
.rx
=
1546 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RX_DEFAULT
);
1549 * Store led mode, for correct led behaviour.
1551 #ifdef CONFIG_RT2X00_LIB_LEDS
1552 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_LED_MODE
);
1554 rt2500pci_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
1555 if (value
== LED_MODE_TXRX_ACTIVITY
||
1556 value
== LED_MODE_DEFAULT
||
1557 value
== LED_MODE_ASUS
)
1558 rt2500pci_init_led(rt2x00dev
, &rt2x00dev
->led_qual
,
1560 #endif /* CONFIG_RT2X00_LIB_LEDS */
1563 * Detect if this device has an hardware controlled radio.
1565 #ifdef CONFIG_RT2X00_LIB_RFKILL
1566 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_HARDWARE_RADIO
))
1567 __set_bit(CONFIG_SUPPORT_HW_BUTTON
, &rt2x00dev
->flags
);
1568 #endif /* CONFIG_RT2X00_LIB_RFKILL */
1571 * Check if the BBP tuning should be enabled.
1573 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
1575 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_DYN_BBP_TUNE
))
1576 __set_bit(CONFIG_DISABLE_LINK_TUNING
, &rt2x00dev
->flags
);
1579 * Read the RSSI <-> dBm offset information.
1581 rt2x00_eeprom_read(rt2x00dev
, EEPROM_CALIBRATE_OFFSET
, &eeprom
);
1582 rt2x00dev
->rssi_offset
=
1583 rt2x00_get_field16(eeprom
, EEPROM_CALIBRATE_OFFSET_RSSI
);
1589 * RF value list for RF2522
1592 static const struct rf_channel rf_vals_bg_2522
[] = {
1593 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1594 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1595 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1596 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1597 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1598 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1599 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1600 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1601 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1602 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1603 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1604 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1605 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1606 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1610 * RF value list for RF2523
1613 static const struct rf_channel rf_vals_bg_2523
[] = {
1614 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1615 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1616 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1617 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1618 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1619 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1620 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1621 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1622 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1623 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1624 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1625 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1626 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1627 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1631 * RF value list for RF2524
1634 static const struct rf_channel rf_vals_bg_2524
[] = {
1635 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1636 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1637 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1638 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1639 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1640 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1641 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1642 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1643 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1644 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1645 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1646 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1647 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1648 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1652 * RF value list for RF2525
1655 static const struct rf_channel rf_vals_bg_2525
[] = {
1656 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1657 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1658 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1659 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1660 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1661 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1662 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1663 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1664 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1665 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1666 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1667 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1668 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1669 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1673 * RF value list for RF2525e
1676 static const struct rf_channel rf_vals_bg_2525e
[] = {
1677 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1678 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1679 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1680 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1681 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1682 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1683 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1684 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1685 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1686 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1687 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1688 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1689 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1690 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1694 * RF value list for RF5222
1695 * Supports: 2.4 GHz & 5.2 GHz
1697 static const struct rf_channel rf_vals_5222
[] = {
1698 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1699 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1700 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1701 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1702 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1703 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1704 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1705 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1706 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1707 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1708 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1709 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1710 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1711 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1713 /* 802.11 UNI / HyperLan 2 */
1714 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1715 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1716 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1717 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1718 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1719 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1720 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1721 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1723 /* 802.11 HyperLan 2 */
1724 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1725 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1726 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1727 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1728 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1729 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1730 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1731 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1732 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1733 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1736 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1737 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1738 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1739 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1740 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1743 static int rt2500pci_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
1745 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
1746 struct channel_info
*info
;
1751 * Initialize all hw fields.
1753 rt2x00dev
->hw
->flags
= IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
1754 IEEE80211_HW_SIGNAL_DBM
|
1755 IEEE80211_HW_SUPPORTS_PS
|
1756 IEEE80211_HW_PS_NULLFUNC_STACK
;
1758 rt2x00dev
->hw
->extra_tx_headroom
= 0;
1760 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
1761 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
1762 rt2x00_eeprom_addr(rt2x00dev
,
1763 EEPROM_MAC_ADDR_0
));
1766 * Initialize hw_mode information.
1768 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
1769 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
1771 if (rt2x00_rf(&rt2x00dev
->chip
, RF2522
)) {
1772 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2522
);
1773 spec
->channels
= rf_vals_bg_2522
;
1774 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF2523
)) {
1775 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2523
);
1776 spec
->channels
= rf_vals_bg_2523
;
1777 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF2524
)) {
1778 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2524
);
1779 spec
->channels
= rf_vals_bg_2524
;
1780 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF2525
)) {
1781 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2525
);
1782 spec
->channels
= rf_vals_bg_2525
;
1783 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF2525E
)) {
1784 spec
->num_channels
= ARRAY_SIZE(rf_vals_bg_2525e
);
1785 spec
->channels
= rf_vals_bg_2525e
;
1786 } else if (rt2x00_rf(&rt2x00dev
->chip
, RF5222
)) {
1787 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
1788 spec
->num_channels
= ARRAY_SIZE(rf_vals_5222
);
1789 spec
->channels
= rf_vals_5222
;
1793 * Create channel information array
1795 info
= kzalloc(spec
->num_channels
* sizeof(*info
), GFP_KERNEL
);
1799 spec
->channels_info
= info
;
1801 tx_power
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_START
);
1802 for (i
= 0; i
< 14; i
++)
1803 info
[i
].tx_power1
= TXPOWER_FROM_DEV(tx_power
[i
]);
1805 if (spec
->num_channels
> 14) {
1806 for (i
= 14; i
< spec
->num_channels
; i
++)
1807 info
[i
].tx_power1
= DEFAULT_TXPOWER
;
1813 static int rt2500pci_probe_hw(struct rt2x00_dev
*rt2x00dev
)
1818 * Allocate eeprom data.
1820 retval
= rt2500pci_validate_eeprom(rt2x00dev
);
1824 retval
= rt2500pci_init_eeprom(rt2x00dev
);
1829 * Initialize hw specifications.
1831 retval
= rt2500pci_probe_hw_mode(rt2x00dev
);
1836 * This device requires the atim queue and DMA-mapped skbs.
1838 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE
, &rt2x00dev
->flags
);
1839 __set_bit(DRIVER_REQUIRE_DMA
, &rt2x00dev
->flags
);
1842 * Set the rssi offset.
1844 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
1850 * IEEE80211 stack callback functions.
1852 static u64
rt2500pci_get_tsf(struct ieee80211_hw
*hw
)
1854 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1858 rt2x00pci_register_read(rt2x00dev
, CSR17
, ®
);
1859 tsf
= (u64
) rt2x00_get_field32(reg
, CSR17_HIGH_TSFTIMER
) << 32;
1860 rt2x00pci_register_read(rt2x00dev
, CSR16
, ®
);
1861 tsf
|= rt2x00_get_field32(reg
, CSR16_LOW_TSFTIMER
);
1866 static int rt2500pci_tx_last_beacon(struct ieee80211_hw
*hw
)
1868 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1871 rt2x00pci_register_read(rt2x00dev
, CSR15
, ®
);
1872 return rt2x00_get_field32(reg
, CSR15_BEACON_SENT
);
1875 static const struct ieee80211_ops rt2500pci_mac80211_ops
= {
1877 .start
= rt2x00mac_start
,
1878 .stop
= rt2x00mac_stop
,
1879 .add_interface
= rt2x00mac_add_interface
,
1880 .remove_interface
= rt2x00mac_remove_interface
,
1881 .config
= rt2x00mac_config
,
1882 .configure_filter
= rt2x00mac_configure_filter
,
1883 .get_stats
= rt2x00mac_get_stats
,
1884 .bss_info_changed
= rt2x00mac_bss_info_changed
,
1885 .conf_tx
= rt2x00mac_conf_tx
,
1886 .get_tx_stats
= rt2x00mac_get_tx_stats
,
1887 .get_tsf
= rt2500pci_get_tsf
,
1888 .tx_last_beacon
= rt2500pci_tx_last_beacon
,
1891 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops
= {
1892 .irq_handler
= rt2500pci_interrupt
,
1893 .probe_hw
= rt2500pci_probe_hw
,
1894 .initialize
= rt2x00pci_initialize
,
1895 .uninitialize
= rt2x00pci_uninitialize
,
1896 .get_entry_state
= rt2500pci_get_entry_state
,
1897 .clear_entry
= rt2500pci_clear_entry
,
1898 .set_device_state
= rt2500pci_set_device_state
,
1899 .rfkill_poll
= rt2500pci_rfkill_poll
,
1900 .link_stats
= rt2500pci_link_stats
,
1901 .reset_tuner
= rt2500pci_reset_tuner
,
1902 .link_tuner
= rt2500pci_link_tuner
,
1903 .write_tx_desc
= rt2500pci_write_tx_desc
,
1904 .write_tx_data
= rt2x00pci_write_tx_data
,
1905 .write_beacon
= rt2500pci_write_beacon
,
1906 .kick_tx_queue
= rt2500pci_kick_tx_queue
,
1907 .kill_tx_queue
= rt2500pci_kill_tx_queue
,
1908 .fill_rxdone
= rt2500pci_fill_rxdone
,
1909 .config_filter
= rt2500pci_config_filter
,
1910 .config_intf
= rt2500pci_config_intf
,
1911 .config_erp
= rt2500pci_config_erp
,
1912 .config_ant
= rt2500pci_config_ant
,
1913 .config
= rt2500pci_config
,
1916 static const struct data_queue_desc rt2500pci_queue_rx
= {
1917 .entry_num
= RX_ENTRIES
,
1918 .data_size
= DATA_FRAME_SIZE
,
1919 .desc_size
= RXD_DESC_SIZE
,
1920 .priv_size
= sizeof(struct queue_entry_priv_pci
),
1923 static const struct data_queue_desc rt2500pci_queue_tx
= {
1924 .entry_num
= TX_ENTRIES
,
1925 .data_size
= DATA_FRAME_SIZE
,
1926 .desc_size
= TXD_DESC_SIZE
,
1927 .priv_size
= sizeof(struct queue_entry_priv_pci
),
1930 static const struct data_queue_desc rt2500pci_queue_bcn
= {
1931 .entry_num
= BEACON_ENTRIES
,
1932 .data_size
= MGMT_FRAME_SIZE
,
1933 .desc_size
= TXD_DESC_SIZE
,
1934 .priv_size
= sizeof(struct queue_entry_priv_pci
),
1937 static const struct data_queue_desc rt2500pci_queue_atim
= {
1938 .entry_num
= ATIM_ENTRIES
,
1939 .data_size
= DATA_FRAME_SIZE
,
1940 .desc_size
= TXD_DESC_SIZE
,
1941 .priv_size
= sizeof(struct queue_entry_priv_pci
),
1944 static const struct rt2x00_ops rt2500pci_ops
= {
1945 .name
= KBUILD_MODNAME
,
1948 .eeprom_size
= EEPROM_SIZE
,
1950 .tx_queues
= NUM_TX_QUEUES
,
1951 .rx
= &rt2500pci_queue_rx
,
1952 .tx
= &rt2500pci_queue_tx
,
1953 .bcn
= &rt2500pci_queue_bcn
,
1954 .atim
= &rt2500pci_queue_atim
,
1955 .lib
= &rt2500pci_rt2x00_ops
,
1956 .hw
= &rt2500pci_mac80211_ops
,
1957 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1958 .debugfs
= &rt2500pci_rt2x00debug
,
1959 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1963 * RT2500pci module information.
1965 static struct pci_device_id rt2500pci_device_table
[] = {
1966 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops
) },
1970 MODULE_AUTHOR(DRV_PROJECT
);
1971 MODULE_VERSION(DRV_VERSION
);
1972 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1973 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1974 MODULE_DEVICE_TABLE(pci
, rt2500pci_device_table
);
1975 MODULE_LICENSE("GPL");
1977 static struct pci_driver rt2500pci_driver
= {
1978 .name
= KBUILD_MODNAME
,
1979 .id_table
= rt2500pci_device_table
,
1980 .probe
= rt2x00pci_probe
,
1981 .remove
= __devexit_p(rt2x00pci_remove
),
1982 .suspend
= rt2x00pci_suspend
,
1983 .resume
= rt2x00pci_resume
,
1986 static int __init
rt2500pci_init(void)
1988 return pci_register_driver(&rt2500pci_driver
);
1991 static void __exit
rt2500pci_exit(void)
1993 pci_unregister_driver(&rt2500pci_driver
);
1996 module_init(rt2500pci_init
);
1997 module_exit(rt2500pci_exit
);