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[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
1 /*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt2500pci
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
25 */
26
27 /*
28 * Set enviroment defines for rt2x00.h
29 */
30 #define DRV_NAME "rt2500pci"
31
32 #include <linux/delay.h>
33 #include <linux/etherdevice.h>
34 #include <linux/init.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/eeprom_93cx6.h>
39
40 #include "rt2x00.h"
41 #include "rt2x00pci.h"
42 #include "rt2500pci.h"
43
44 /*
45 * Register access.
46 * All access to the CSR registers will go through the methods
47 * rt2x00pci_register_read and rt2x00pci_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 */
57 static u32 rt2500pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
58 {
59 u32 reg;
60 unsigned int i;
61
62 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
63 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
64 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
65 break;
66 udelay(REGISTER_BUSY_DELAY);
67 }
68
69 return reg;
70 }
71
72 static void rt2500pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
73 const unsigned int word, const u8 value)
74 {
75 u32 reg;
76
77 /*
78 * Wait until the BBP becomes ready.
79 */
80 reg = rt2500pci_bbp_check(rt2x00dev);
81 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
82 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
83 return;
84 }
85
86 /*
87 * Write the data into the BBP.
88 */
89 reg = 0;
90 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
91 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
92 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
93 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
94
95 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
96 }
97
98 static void rt2500pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
99 const unsigned int word, u8 *value)
100 {
101 u32 reg;
102
103 /*
104 * Wait until the BBP becomes ready.
105 */
106 reg = rt2500pci_bbp_check(rt2x00dev);
107 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
108 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
109 return;
110 }
111
112 /*
113 * Write the request into the BBP.
114 */
115 reg = 0;
116 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
117 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
118 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
119
120 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
121
122 /*
123 * Wait until the BBP becomes ready.
124 */
125 reg = rt2500pci_bbp_check(rt2x00dev);
126 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
127 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
128 *value = 0xff;
129 return;
130 }
131
132 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
133 }
134
135 static void rt2500pci_rf_write(const struct rt2x00_dev *rt2x00dev,
136 const unsigned int word, const u32 value)
137 {
138 u32 reg;
139 unsigned int i;
140
141 if (!word)
142 return;
143
144 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
145 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
146 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
147 goto rf_write;
148 udelay(REGISTER_BUSY_DELAY);
149 }
150
151 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
152 return;
153
154 rf_write:
155 reg = 0;
156 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
157 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
158 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
159 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
160
161 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
162 rt2x00_rf_write(rt2x00dev, word, value);
163 }
164
165 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
166 {
167 struct rt2x00_dev *rt2x00dev = eeprom->data;
168 u32 reg;
169
170 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
171
172 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
173 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
174 eeprom->reg_data_clock =
175 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
176 eeprom->reg_chip_select =
177 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
178 }
179
180 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
181 {
182 struct rt2x00_dev *rt2x00dev = eeprom->data;
183 u32 reg = 0;
184
185 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
186 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
187 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
188 !!eeprom->reg_data_clock);
189 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
190 !!eeprom->reg_chip_select);
191
192 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
193 }
194
195 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
196 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
197
198 static void rt2500pci_read_csr(const struct rt2x00_dev *rt2x00dev,
199 const unsigned int word, u32 *data)
200 {
201 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
202 }
203
204 static void rt2500pci_write_csr(const struct rt2x00_dev *rt2x00dev,
205 const unsigned int word, u32 data)
206 {
207 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
208 }
209
210 static const struct rt2x00debug rt2500pci_rt2x00debug = {
211 .owner = THIS_MODULE,
212 .csr = {
213 .read = rt2500pci_read_csr,
214 .write = rt2500pci_write_csr,
215 .word_size = sizeof(u32),
216 .word_count = CSR_REG_SIZE / sizeof(u32),
217 },
218 .eeprom = {
219 .read = rt2x00_eeprom_read,
220 .write = rt2x00_eeprom_write,
221 .word_size = sizeof(u16),
222 .word_count = EEPROM_SIZE / sizeof(u16),
223 },
224 .bbp = {
225 .read = rt2500pci_bbp_read,
226 .write = rt2500pci_bbp_write,
227 .word_size = sizeof(u8),
228 .word_count = BBP_SIZE / sizeof(u8),
229 },
230 .rf = {
231 .read = rt2x00_rf_read,
232 .write = rt2500pci_rf_write,
233 .word_size = sizeof(u32),
234 .word_count = RF_SIZE / sizeof(u32),
235 },
236 };
237 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
238
239 #ifdef CONFIG_RT2500PCI_RFKILL
240 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
241 {
242 u32 reg;
243
244 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
245 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
246 }
247 #endif /* CONFIG_RT2400PCI_RFKILL */
248
249 /*
250 * Configuration handlers.
251 */
252 static void rt2500pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, u8 *addr)
253 {
254 __le32 reg[2];
255
256 memset(&reg, 0, sizeof(reg));
257 memcpy(&reg, addr, ETH_ALEN);
258
259 /*
260 * The MAC address is passed to us as an array of bytes,
261 * that array is little endian, so no need for byte ordering.
262 */
263 rt2x00pci_register_multiwrite(rt2x00dev, CSR3, &reg, sizeof(reg));
264 }
265
266 static void rt2500pci_config_bssid(struct rt2x00_dev *rt2x00dev, u8 *bssid)
267 {
268 __le32 reg[2];
269
270 memset(&reg, 0, sizeof(reg));
271 memcpy(&reg, bssid, ETH_ALEN);
272
273 /*
274 * The BSSID is passed to us as an array of bytes,
275 * that array is little endian, so no need for byte ordering.
276 */
277 rt2x00pci_register_multiwrite(rt2x00dev, CSR5, &reg, sizeof(reg));
278 }
279
280 static void rt2500pci_config_type(struct rt2x00_dev *rt2x00dev, const int type)
281 {
282 struct interface *intf = &rt2x00dev->interface;
283 u32 reg;
284
285 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
286
287 /*
288 * Enable beacon config
289 */
290 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
291 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
292 PREAMBLE + get_duration(IEEE80211_HEADER, 2));
293 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN,
294 rt2x00lib_get_ring(rt2x00dev,
295 IEEE80211_TX_QUEUE_BEACON)
296 ->tx_params.cw_min);
297 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
298
299 /*
300 * Enable synchronisation.
301 */
302 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
303 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
304 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
305 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
306 if (is_interface_type(intf, IEEE80211_IF_TYPE_IBSS) ||
307 is_interface_type(intf, IEEE80211_IF_TYPE_AP))
308 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 2);
309 else if (is_interface_type(intf, IEEE80211_IF_TYPE_STA))
310 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 1);
311 else
312 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
313 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
314 }
315
316 static void rt2500pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
317 {
318 struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
319 u32 reg;
320 u32 preamble;
321 u16 value;
322
323 if (DEVICE_GET_RATE_FIELD(rate, PREAMBLE))
324 preamble = SHORT_PREAMBLE;
325 else
326 preamble = PREAMBLE;
327
328 reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATEMASK;
329 rt2x00pci_register_write(rt2x00dev, ARCSR1, reg);
330
331 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
332 value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
333 SHORT_DIFS : DIFS) +
334 PLCP + preamble + get_duration(ACK_SIZE, 10);
335 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, value);
336 value = SIFS + PLCP + preamble + get_duration(ACK_SIZE, 10);
337 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, value);
338 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
339
340 preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE) ? 0x08 : 0x00;
341
342 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
343 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble);
344 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
345 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
346 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
347
348 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
349 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble);
350 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
351 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
352 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
353
354 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
355 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble);
356 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
357 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
358 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
359
360 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
361 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble);
362 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
363 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
364 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
365 }
366
367 static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
368 const int phymode)
369 {
370 struct ieee80211_hw_mode *mode;
371 struct ieee80211_rate *rate;
372
373 if (phymode == MODE_IEEE80211A)
374 rt2x00dev->curr_hwmode = HWMODE_A;
375 else if (phymode == MODE_IEEE80211B)
376 rt2x00dev->curr_hwmode = HWMODE_B;
377 else
378 rt2x00dev->curr_hwmode = HWMODE_G;
379
380 mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
381 rate = &mode->rates[mode->num_rates - 1];
382
383 rt2500pci_config_rate(rt2x00dev, rate->val2);
384 }
385
386 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
387 const int index, const int channel,
388 const int txpower)
389 {
390 struct rf_channel reg;
391 u8 r70;
392
393 /*
394 * Fill rf_reg structure.
395 */
396 memcpy(&reg, &rt2x00dev->spec.channels[index], sizeof(reg));
397
398 /*
399 * Set TXpower.
400 */
401 rt2x00_set_field32(&reg.rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
402
403 /*
404 * Switch on tuning bits.
405 * For RT2523 devices we do not need to update the R1 register.
406 */
407 if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
408 rt2x00_set_field32(&reg.rf1, RF1_TUNER, 1);
409 rt2x00_set_field32(&reg.rf3, RF3_TUNER, 1);
410
411 /*
412 * For RT2525 we should first set the channel to half band higher.
413 */
414 if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
415 static const u32 vals[] = {
416 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
417 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
418 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
419 0x00080d2e, 0x00080d3a
420 };
421
422 rt2500pci_rf_write(rt2x00dev, 1, reg.rf1);
423 rt2500pci_rf_write(rt2x00dev, 2, vals[channel - 1]);
424 rt2500pci_rf_write(rt2x00dev, 3, reg.rf3);
425 if (reg.rf4)
426 rt2500pci_rf_write(rt2x00dev, 4, reg.rf4);
427 }
428
429 rt2500pci_rf_write(rt2x00dev, 1, reg.rf1);
430 rt2500pci_rf_write(rt2x00dev, 2, reg.rf2);
431 rt2500pci_rf_write(rt2x00dev, 3, reg.rf3);
432 if (reg.rf4)
433 rt2500pci_rf_write(rt2x00dev, 4, reg.rf4);
434
435 /*
436 * Channel 14 requires the Japan filter bit to be set.
437 */
438 r70 = 0x46;
439 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, channel == 14);
440 rt2500pci_bbp_write(rt2x00dev, 70, r70);
441
442 msleep(1);
443
444 /*
445 * Switch off tuning bits.
446 * For RT2523 devices we do not need to update the R1 register.
447 */
448 if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
449 rt2x00_set_field32(&reg.rf1, RF1_TUNER, 0);
450 rt2500pci_rf_write(rt2x00dev, 1, reg.rf1);
451 }
452
453 rt2x00_set_field32(&reg.rf3, RF3_TUNER, 0);
454 rt2500pci_rf_write(rt2x00dev, 3, reg.rf3);
455
456 /*
457 * Clear false CRC during channel switch.
458 */
459 rt2x00pci_register_read(rt2x00dev, CNT0, &reg.rf1);
460 }
461
462 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
463 const int txpower)
464 {
465 u32 rf3;
466
467 rt2x00_rf_read(rt2x00dev, 3, &rf3);
468 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
469 rt2500pci_rf_write(rt2x00dev, 3, rf3);
470 }
471
472 static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
473 const int antenna_tx, const int antenna_rx)
474 {
475 u32 reg;
476 u8 r14;
477 u8 r2;
478
479 rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
480 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
481 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
482
483 /*
484 * Configure the TX antenna.
485 */
486 switch (antenna_tx) {
487 case ANTENNA_SW_DIVERSITY:
488 case ANTENNA_HW_DIVERSITY:
489 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
490 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
491 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
492 break;
493 case ANTENNA_A:
494 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
495 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
496 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
497 break;
498 case ANTENNA_B:
499 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
500 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
501 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
502 break;
503 }
504
505 /*
506 * Configure the RX antenna.
507 */
508 switch (antenna_rx) {
509 case ANTENNA_SW_DIVERSITY:
510 case ANTENNA_HW_DIVERSITY:
511 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
512 break;
513 case ANTENNA_A:
514 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
515 break;
516 case ANTENNA_B:
517 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
518 break;
519 }
520
521 /*
522 * RT2525E and RT5222 need to flip TX I/Q
523 */
524 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
525 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
526 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
527 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
528 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
529
530 /*
531 * RT2525E does not need RX I/Q Flip.
532 */
533 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
534 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
535 } else {
536 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
537 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
538 }
539
540 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
541 rt2500pci_bbp_write(rt2x00dev, 14, r14);
542 rt2500pci_bbp_write(rt2x00dev, 2, r2);
543 }
544
545 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
546 const int short_slot_time,
547 const int beacon_int)
548 {
549 u32 reg;
550
551 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
552 rt2x00_set_field32(&reg, CSR11_SLOT_TIME,
553 short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
554 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
555
556 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
557 rt2x00_set_field32(&reg, CSR18_SIFS, SIFS);
558 rt2x00_set_field32(&reg, CSR18_PIFS,
559 short_slot_time ? SHORT_PIFS : PIFS);
560 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
561
562 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
563 rt2x00_set_field32(&reg, CSR19_DIFS,
564 short_slot_time ? SHORT_DIFS : DIFS);
565 rt2x00_set_field32(&reg, CSR19_EIFS, EIFS);
566 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
567
568 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
569 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
570 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
571 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
572
573 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
574 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, beacon_int * 16);
575 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, beacon_int * 16);
576 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
577 }
578
579 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
580 const unsigned int flags,
581 struct ieee80211_conf *conf)
582 {
583 int short_slot_time = conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME;
584
585 if (flags & CONFIG_UPDATE_PHYMODE)
586 rt2500pci_config_phymode(rt2x00dev, conf->phymode);
587 if (flags & CONFIG_UPDATE_CHANNEL)
588 rt2500pci_config_channel(rt2x00dev, conf->channel_val,
589 conf->channel, conf->power_level);
590 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
591 rt2500pci_config_txpower(rt2x00dev, conf->power_level);
592 if (flags & CONFIG_UPDATE_ANTENNA)
593 rt2500pci_config_antenna(rt2x00dev, conf->antenna_sel_tx,
594 conf->antenna_sel_rx);
595 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
596 rt2500pci_config_duration(rt2x00dev, short_slot_time,
597 conf->beacon_int);
598 }
599
600 /*
601 * LED functions.
602 */
603 static void rt2500pci_enable_led(struct rt2x00_dev *rt2x00dev)
604 {
605 u32 reg;
606
607 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
608
609 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
610 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
611
612 if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
613 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
614 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
615 } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
616 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
617 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
618 } else {
619 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
620 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
621 }
622
623 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
624 }
625
626 static void rt2500pci_disable_led(struct rt2x00_dev *rt2x00dev)
627 {
628 u32 reg;
629
630 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
631 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
632 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
633 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
634 }
635
636 /*
637 * Link tuning
638 */
639 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev)
640 {
641 u32 reg;
642
643 /*
644 * Update FCS error count from register.
645 */
646 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
647 rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
648
649 /*
650 * Update False CCA count from register.
651 */
652 rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
653 rt2x00dev->link.false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
654 }
655
656 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
657 {
658 rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
659 rt2x00dev->link.vgc_level = 0x48;
660 }
661
662 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
663 {
664 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
665 u8 r17;
666
667 /*
668 * To prevent collisions with MAC ASIC on chipsets
669 * up to version C the link tuning should halt after 20
670 * seconds.
671 */
672 if (rt2x00_get_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
673 rt2x00dev->link.count > 20)
674 return;
675
676 rt2500pci_bbp_read(rt2x00dev, 17, &r17);
677
678 /*
679 * Chipset versions C and lower should directly continue
680 * to the dynamic CCA tuning.
681 */
682 if (rt2x00_get_rev(&rt2x00dev->chip) < RT2560_VERSION_D)
683 goto dynamic_cca_tune;
684
685 /*
686 * A too low RSSI will cause too much false CCA which will
687 * then corrupt the R17 tuning. To remidy this the tuning should
688 * be stopped (While making sure the R17 value will not exceed limits)
689 */
690 if (rssi < -80 && rt2x00dev->link.count > 20) {
691 if (r17 >= 0x41) {
692 r17 = rt2x00dev->link.vgc_level;
693 rt2500pci_bbp_write(rt2x00dev, 17, r17);
694 }
695 return;
696 }
697
698 /*
699 * Special big-R17 for short distance
700 */
701 if (rssi >= -58) {
702 if (r17 != 0x50)
703 rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
704 return;
705 }
706
707 /*
708 * Special mid-R17 for middle distance
709 */
710 if (rssi >= -74) {
711 if (r17 != 0x41)
712 rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
713 return;
714 }
715
716 /*
717 * Leave short or middle distance condition, restore r17
718 * to the dynamic tuning range.
719 */
720 if (r17 >= 0x41) {
721 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
722 return;
723 }
724
725 dynamic_cca_tune:
726
727 /*
728 * R17 is inside the dynamic tuning range,
729 * start tuning the link based on the false cca counter.
730 */
731 if (rt2x00dev->link.false_cca > 512 && r17 < 0x40) {
732 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
733 rt2x00dev->link.vgc_level = r17;
734 } else if (rt2x00dev->link.false_cca < 100 && r17 > 0x32) {
735 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
736 rt2x00dev->link.vgc_level = r17;
737 }
738 }
739
740 /*
741 * Initialization functions.
742 */
743 static void rt2500pci_init_rxring(struct rt2x00_dev *rt2x00dev)
744 {
745 struct data_ring *ring = rt2x00dev->rx;
746 struct data_desc *rxd;
747 unsigned int i;
748 u32 word;
749
750 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
751
752 for (i = 0; i < ring->stats.limit; i++) {
753 rxd = ring->entry[i].priv;
754
755 rt2x00_desc_read(rxd, 1, &word);
756 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
757 ring->entry[i].data_dma);
758 rt2x00_desc_write(rxd, 1, word);
759
760 rt2x00_desc_read(rxd, 0, &word);
761 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
762 rt2x00_desc_write(rxd, 0, word);
763 }
764
765 rt2x00_ring_index_clear(rt2x00dev->rx);
766 }
767
768 static void rt2500pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
769 {
770 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
771 struct data_desc *txd;
772 unsigned int i;
773 u32 word;
774
775 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
776
777 for (i = 0; i < ring->stats.limit; i++) {
778 txd = ring->entry[i].priv;
779
780 rt2x00_desc_read(txd, 1, &word);
781 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
782 ring->entry[i].data_dma);
783 rt2x00_desc_write(txd, 1, word);
784
785 rt2x00_desc_read(txd, 0, &word);
786 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
787 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
788 rt2x00_desc_write(txd, 0, word);
789 }
790
791 rt2x00_ring_index_clear(ring);
792 }
793
794 static int rt2500pci_init_rings(struct rt2x00_dev *rt2x00dev)
795 {
796 u32 reg;
797
798 /*
799 * Initialize rings.
800 */
801 rt2500pci_init_rxring(rt2x00dev);
802 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
803 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
804 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
805 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
806
807 /*
808 * Initialize registers.
809 */
810 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
811 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
812 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
813 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
814 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
815 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
816 rt2x00dev->bcn[1].stats.limit);
817 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
818 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
819 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
820
821 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
822 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
823 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
824 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
825
826 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
827 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
828 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
829 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
830
831 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
832 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
833 rt2x00dev->bcn[1].data_dma);
834 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
835
836 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
837 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
838 rt2x00dev->bcn[0].data_dma);
839 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
840
841 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
842 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
843 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
844 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
845
846 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
847 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
848 rt2x00dev->rx->data_dma);
849 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
850
851 return 0;
852 }
853
854 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
855 {
856 u32 reg;
857
858 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
859 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
860 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
861 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
862
863 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
864 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
865 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
866 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
867 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
868
869 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
870 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
871 rt2x00dev->rx->data_size / 128);
872 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
873
874 /*
875 * Always use CWmin and CWmax set in descriptor.
876 */
877 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
878 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
879 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
880
881 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
882
883 rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
884 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
885 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
886 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
887 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
888 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
889 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
890 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
891 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
892 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
893
894 rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
895 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
896 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
897 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
898 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
899 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
900
901 rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
902 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
903 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
904 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
905 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
906 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
907
908 rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
909 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
910 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
911 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
912 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
913 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
914
915 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
916 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
917 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
918 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
919 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
920 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
921 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
922 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
923 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
924 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
925
926 rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
927 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
928 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
929 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
930 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
931 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
932 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
933 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
934 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
935
936 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
937
938 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
939 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
940
941 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
942 return -EBUSY;
943
944 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
945 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
946
947 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
948 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
949 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
950
951 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
952 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
953 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
954 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
955 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
956 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
957 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
958 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
959
960 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
961
962 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
963
964 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
965 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
966 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
967 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
968 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
969
970 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
971 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
972 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
973 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
974
975 /*
976 * We must clear the FCS and FIFO error count.
977 * These registers are cleared on read,
978 * so we may pass a useless variable to store the value.
979 */
980 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
981 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
982
983 return 0;
984 }
985
986 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
987 {
988 unsigned int i;
989 u16 eeprom;
990 u8 reg_id;
991 u8 value;
992
993 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
994 rt2500pci_bbp_read(rt2x00dev, 0, &value);
995 if ((value != 0xff) && (value != 0x00))
996 goto continue_csr_init;
997 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
998 udelay(REGISTER_BUSY_DELAY);
999 }
1000
1001 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1002 return -EACCES;
1003
1004 continue_csr_init:
1005 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
1006 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
1007 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
1008 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
1009 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
1010 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
1011 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
1012 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
1013 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
1014 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
1015 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
1016 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
1017 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
1018 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
1019 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
1020 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
1021 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
1022 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
1023 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
1024 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
1025 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
1026 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
1027 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
1028 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1029 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1030 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1031 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1032 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1033 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1034 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1035
1036 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1037 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1038 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1039
1040 if (eeprom != 0xffff && eeprom != 0x0000) {
1041 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1042 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1043 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1044 reg_id, value);
1045 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1046 }
1047 }
1048 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1049
1050 return 0;
1051 }
1052
1053 /*
1054 * Device state switch handlers.
1055 */
1056 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1057 enum dev_state state)
1058 {
1059 u32 reg;
1060
1061 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1062 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1063 state == STATE_RADIO_RX_OFF);
1064 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1065 }
1066
1067 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1068 enum dev_state state)
1069 {
1070 int mask = (state == STATE_RADIO_IRQ_OFF);
1071 u32 reg;
1072
1073 /*
1074 * When interrupts are being enabled, the interrupt registers
1075 * should clear the register to assure a clean state.
1076 */
1077 if (state == STATE_RADIO_IRQ_ON) {
1078 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1079 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1080 }
1081
1082 /*
1083 * Only toggle the interrupts bits we are going to use.
1084 * Non-checked interrupt bits are disabled by default.
1085 */
1086 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1087 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1088 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1089 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1090 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1091 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1092 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1093 }
1094
1095 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1096 {
1097 /*
1098 * Initialize all registers.
1099 */
1100 if (rt2500pci_init_rings(rt2x00dev) ||
1101 rt2500pci_init_registers(rt2x00dev) ||
1102 rt2500pci_init_bbp(rt2x00dev)) {
1103 ERROR(rt2x00dev, "Register initialization failed.\n");
1104 return -EIO;
1105 }
1106
1107 /*
1108 * Enable interrupts.
1109 */
1110 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1111
1112 /*
1113 * Enable LED
1114 */
1115 rt2500pci_enable_led(rt2x00dev);
1116
1117 return 0;
1118 }
1119
1120 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1121 {
1122 u32 reg;
1123
1124 /*
1125 * Disable LED
1126 */
1127 rt2500pci_disable_led(rt2x00dev);
1128
1129 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1130
1131 /*
1132 * Disable synchronisation.
1133 */
1134 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1135
1136 /*
1137 * Cancel RX and TX.
1138 */
1139 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1140 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1141 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1142
1143 /*
1144 * Disable interrupts.
1145 */
1146 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1147 }
1148
1149 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1150 enum dev_state state)
1151 {
1152 u32 reg;
1153 unsigned int i;
1154 char put_to_sleep;
1155 char bbp_state;
1156 char rf_state;
1157
1158 put_to_sleep = (state != STATE_AWAKE);
1159
1160 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1161 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1162 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1163 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1164 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1165 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1166
1167 /*
1168 * Device is not guaranteed to be in the requested state yet.
1169 * We must wait until the register indicates that the
1170 * device has entered the correct state.
1171 */
1172 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1173 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1174 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1175 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1176 if (bbp_state == state && rf_state == state)
1177 return 0;
1178 msleep(10);
1179 }
1180
1181 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1182 "current device state: bbp %d and rf %d.\n",
1183 state, bbp_state, rf_state);
1184
1185 return -EBUSY;
1186 }
1187
1188 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1189 enum dev_state state)
1190 {
1191 int retval = 0;
1192
1193 switch (state) {
1194 case STATE_RADIO_ON:
1195 retval = rt2500pci_enable_radio(rt2x00dev);
1196 break;
1197 case STATE_RADIO_OFF:
1198 rt2500pci_disable_radio(rt2x00dev);
1199 break;
1200 case STATE_RADIO_RX_ON:
1201 case STATE_RADIO_RX_OFF:
1202 rt2500pci_toggle_rx(rt2x00dev, state);
1203 break;
1204 case STATE_DEEP_SLEEP:
1205 case STATE_SLEEP:
1206 case STATE_STANDBY:
1207 case STATE_AWAKE:
1208 retval = rt2500pci_set_state(rt2x00dev, state);
1209 break;
1210 default:
1211 retval = -ENOTSUPP;
1212 break;
1213 }
1214
1215 return retval;
1216 }
1217
1218 /*
1219 * TX descriptor initialization
1220 */
1221 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1222 struct data_desc *txd,
1223 struct txdata_entry_desc *desc,
1224 struct ieee80211_hdr *ieee80211hdr,
1225 unsigned int length,
1226 struct ieee80211_tx_control *control)
1227 {
1228 u32 word;
1229
1230 /*
1231 * Start writing the descriptor words.
1232 */
1233 rt2x00_desc_read(txd, 2, &word);
1234 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1235 rt2x00_set_field32(&word, TXD_W2_AIFS, desc->aifs);
1236 rt2x00_set_field32(&word, TXD_W2_CWMIN, desc->cw_min);
1237 rt2x00_set_field32(&word, TXD_W2_CWMAX, desc->cw_max);
1238 rt2x00_desc_write(txd, 2, word);
1239
1240 rt2x00_desc_read(txd, 3, &word);
1241 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, desc->signal);
1242 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, desc->service);
1243 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, desc->length_low);
1244 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, desc->length_high);
1245 rt2x00_desc_write(txd, 3, word);
1246
1247 rt2x00_desc_read(txd, 10, &word);
1248 rt2x00_set_field32(&word, TXD_W10_RTS,
1249 test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
1250 rt2x00_desc_write(txd, 10, word);
1251
1252 rt2x00_desc_read(txd, 0, &word);
1253 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1254 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1255 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1256 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1257 rt2x00_set_field32(&word, TXD_W0_ACK,
1258 !(control->flags & IEEE80211_TXCTL_NO_ACK));
1259 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1260 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1261 rt2x00_set_field32(&word, TXD_W0_OFDM,
1262 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1263 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1264 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1265 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1266 !!(control->flags &
1267 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1268 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1269 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1270 rt2x00_desc_write(txd, 0, word);
1271 }
1272
1273 /*
1274 * TX data initialization
1275 */
1276 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1277 unsigned int queue)
1278 {
1279 u32 reg;
1280
1281 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1282 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1283 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1284 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1285 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1286 }
1287 return;
1288 }
1289
1290 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1291 if (queue == IEEE80211_TX_QUEUE_DATA0)
1292 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
1293 else if (queue == IEEE80211_TX_QUEUE_DATA1)
1294 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
1295 else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
1296 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
1297 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1298 }
1299
1300 /*
1301 * RX control handlers
1302 */
1303 static void rt2500pci_fill_rxdone(struct data_entry *entry,
1304 struct rxdata_entry_desc *desc)
1305 {
1306 struct data_desc *rxd = entry->priv;
1307 u32 word0;
1308 u32 word2;
1309
1310 rt2x00_desc_read(rxd, 0, &word0);
1311 rt2x00_desc_read(rxd, 2, &word2);
1312
1313 desc->flags = 0;
1314 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1315 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1316 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1317 desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1318
1319 desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1320 desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1321 entry->ring->rt2x00dev->rssi_offset;
1322 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1323 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1324 }
1325
1326 /*
1327 * Interrupt functions.
1328 */
1329 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1330 {
1331 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1332 struct data_entry *entry;
1333 struct data_desc *txd;
1334 u32 word;
1335 int tx_status;
1336 int retry;
1337
1338 while (!rt2x00_ring_empty(ring)) {
1339 entry = rt2x00_get_data_entry_done(ring);
1340 txd = entry->priv;
1341 rt2x00_desc_read(txd, 0, &word);
1342
1343 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1344 !rt2x00_get_field32(word, TXD_W0_VALID))
1345 break;
1346
1347 /*
1348 * Obtain the status about this packet.
1349 */
1350 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1351 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1352
1353 rt2x00lib_txdone(entry, tx_status, retry);
1354
1355 /*
1356 * Make this entry available for reuse.
1357 */
1358 entry->flags = 0;
1359 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1360 rt2x00_desc_write(txd, 0, word);
1361 rt2x00_ring_index_done_inc(ring);
1362 }
1363
1364 /*
1365 * If the data ring was full before the txdone handler
1366 * we must make sure the packet queue in the mac80211 stack
1367 * is reenabled when the txdone handler has finished.
1368 */
1369 entry = ring->entry;
1370 if (!rt2x00_ring_full(ring))
1371 ieee80211_wake_queue(rt2x00dev->hw,
1372 entry->tx_status.control.queue);
1373 }
1374
1375 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1376 {
1377 struct rt2x00_dev *rt2x00dev = dev_instance;
1378 u32 reg;
1379
1380 /*
1381 * Get the interrupt sources & saved to local variable.
1382 * Write register value back to clear pending interrupts.
1383 */
1384 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1385 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1386
1387 if (!reg)
1388 return IRQ_NONE;
1389
1390 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1391 return IRQ_HANDLED;
1392
1393 /*
1394 * Handle interrupts, walk through all bits
1395 * and run the tasks, the bits are checked in order of
1396 * priority.
1397 */
1398
1399 /*
1400 * 1 - Beacon timer expired interrupt.
1401 */
1402 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1403 rt2x00lib_beacondone(rt2x00dev);
1404
1405 /*
1406 * 2 - Rx ring done interrupt.
1407 */
1408 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1409 rt2x00pci_rxdone(rt2x00dev);
1410
1411 /*
1412 * 3 - Atim ring transmit done interrupt.
1413 */
1414 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1415 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1416
1417 /*
1418 * 4 - Priority ring transmit done interrupt.
1419 */
1420 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1421 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1422
1423 /*
1424 * 5 - Tx ring transmit done interrupt.
1425 */
1426 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1427 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1428
1429 return IRQ_HANDLED;
1430 }
1431
1432 /*
1433 * Device probe functions.
1434 */
1435 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1436 {
1437 struct eeprom_93cx6 eeprom;
1438 u32 reg;
1439 u16 word;
1440 u8 *mac;
1441
1442 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1443
1444 eeprom.data = rt2x00dev;
1445 eeprom.register_read = rt2500pci_eepromregister_read;
1446 eeprom.register_write = rt2500pci_eepromregister_write;
1447 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1448 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1449 eeprom.reg_data_in = 0;
1450 eeprom.reg_data_out = 0;
1451 eeprom.reg_data_clock = 0;
1452 eeprom.reg_chip_select = 0;
1453
1454 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1455 EEPROM_SIZE / sizeof(u16));
1456
1457 /*
1458 * Start validation of the data that has been read.
1459 */
1460 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1461 if (!is_valid_ether_addr(mac)) {
1462 DECLARE_MAC_BUF(macbuf);
1463
1464 random_ether_addr(mac);
1465 EEPROM(rt2x00dev, "MAC: %s\n",
1466 print_mac(macbuf, mac));
1467 }
1468
1469 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1470 if (word == 0xffff) {
1471 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1472 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 0);
1473 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 0);
1474 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE, 0);
1475 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1476 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1477 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1478 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1479 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1480 }
1481
1482 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1483 if (word == 0xffff) {
1484 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1485 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1486 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1487 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1488 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1489 }
1490
1491 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1492 if (word == 0xffff) {
1493 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1494 DEFAULT_RSSI_OFFSET);
1495 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1496 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1497 }
1498
1499 return 0;
1500 }
1501
1502 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1503 {
1504 u32 reg;
1505 u16 value;
1506 u16 eeprom;
1507
1508 /*
1509 * Read EEPROM word for configuration.
1510 */
1511 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1512
1513 /*
1514 * Identify RF chipset.
1515 */
1516 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1517 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1518 rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1519
1520 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1521 !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1522 !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1523 !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1524 !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1525 !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1526 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1527 return -ENODEV;
1528 }
1529
1530 /*
1531 * Identify default antenna configuration.
1532 */
1533 rt2x00dev->hw->conf.antenna_sel_tx =
1534 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1535 rt2x00dev->hw->conf.antenna_sel_rx =
1536 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1537
1538 /*
1539 * Store led mode, for correct led behaviour.
1540 */
1541 rt2x00dev->led_mode =
1542 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1543
1544 /*
1545 * Detect if this device has an hardware controlled radio.
1546 */
1547 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1548 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1549
1550 /*
1551 * Check if the BBP tuning should be enabled.
1552 */
1553 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1554
1555 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1556 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1557
1558 /*
1559 * Read the RSSI <-> dBm offset information.
1560 */
1561 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1562 rt2x00dev->rssi_offset =
1563 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1564
1565 return 0;
1566 }
1567
1568 /*
1569 * RF value list for RF2522
1570 * Supports: 2.4 GHz
1571 */
1572 static const struct rf_channel rf_vals_bg_2522[] = {
1573 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1574 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1575 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1576 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1577 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1578 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1579 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1580 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1581 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1582 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1583 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1584 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1585 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1586 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1587 };
1588
1589 /*
1590 * RF value list for RF2523
1591 * Supports: 2.4 GHz
1592 */
1593 static const struct rf_channel rf_vals_bg_2523[] = {
1594 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1595 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1596 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1597 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1598 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1599 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1600 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1601 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1602 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1603 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1604 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1605 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1606 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1607 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1608 };
1609
1610 /*
1611 * RF value list for RF2524
1612 * Supports: 2.4 GHz
1613 */
1614 static const struct rf_channel rf_vals_bg_2524[] = {
1615 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1616 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1617 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1618 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1619 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1620 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1621 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1622 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1623 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1624 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1625 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1626 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1627 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1628 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1629 };
1630
1631 /*
1632 * RF value list for RF2525
1633 * Supports: 2.4 GHz
1634 */
1635 static const struct rf_channel rf_vals_bg_2525[] = {
1636 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1637 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1638 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1639 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1640 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1641 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1642 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1643 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1644 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1645 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1646 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1647 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1648 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1649 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1650 };
1651
1652 /*
1653 * RF value list for RF2525e
1654 * Supports: 2.4 GHz
1655 */
1656 static const struct rf_channel rf_vals_bg_2525e[] = {
1657 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1658 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1659 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1660 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1661 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1662 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1663 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1664 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1665 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1666 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1667 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1668 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1669 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1670 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1671 };
1672
1673 /*
1674 * RF value list for RF5222
1675 * Supports: 2.4 GHz & 5.2 GHz
1676 */
1677 static const struct rf_channel rf_vals_5222[] = {
1678 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1679 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1680 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1681 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1682 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1683 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1684 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1685 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1686 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1687 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1688 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1689 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1690 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1691 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1692
1693 /* 802.11 UNI / HyperLan 2 */
1694 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1695 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1696 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1697 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1698 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1699 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1700 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1701 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1702
1703 /* 802.11 HyperLan 2 */
1704 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1705 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1706 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1707 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1708 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1709 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1710 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1711 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1712 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1713 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1714
1715 /* 802.11 UNII */
1716 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1717 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1718 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1719 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1720 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1721 };
1722
1723 static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1724 {
1725 struct hw_mode_spec *spec = &rt2x00dev->spec;
1726 u8 *txpower;
1727 unsigned int i;
1728
1729 /*
1730 * Initialize all hw fields.
1731 */
1732 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1733 rt2x00dev->hw->extra_tx_headroom = 0;
1734 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1735 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1736 rt2x00dev->hw->queues = 2;
1737
1738 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1739 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1740 rt2x00_eeprom_addr(rt2x00dev,
1741 EEPROM_MAC_ADDR_0));
1742
1743 /*
1744 * Convert tx_power array in eeprom.
1745 */
1746 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1747 for (i = 0; i < 14; i++)
1748 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1749
1750 /*
1751 * Initialize hw_mode information.
1752 */
1753 spec->num_modes = 2;
1754 spec->num_rates = 12;
1755 spec->tx_power_a = NULL;
1756 spec->tx_power_bg = txpower;
1757 spec->tx_power_default = DEFAULT_TXPOWER;
1758
1759 if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1760 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1761 spec->channels = rf_vals_bg_2522;
1762 } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1763 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1764 spec->channels = rf_vals_bg_2523;
1765 } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1766 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1767 spec->channels = rf_vals_bg_2524;
1768 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1769 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1770 spec->channels = rf_vals_bg_2525;
1771 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1772 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1773 spec->channels = rf_vals_bg_2525e;
1774 } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1775 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1776 spec->channels = rf_vals_5222;
1777 spec->num_modes = 3;
1778 }
1779 }
1780
1781 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1782 {
1783 int retval;
1784
1785 /*
1786 * Allocate eeprom data.
1787 */
1788 retval = rt2500pci_validate_eeprom(rt2x00dev);
1789 if (retval)
1790 return retval;
1791
1792 retval = rt2500pci_init_eeprom(rt2x00dev);
1793 if (retval)
1794 return retval;
1795
1796 /*
1797 * Initialize hw specifications.
1798 */
1799 rt2500pci_probe_hw_mode(rt2x00dev);
1800
1801 /*
1802 * This device requires the beacon ring
1803 */
1804 __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
1805
1806 /*
1807 * Set the rssi offset.
1808 */
1809 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1810
1811 return 0;
1812 }
1813
1814 /*
1815 * IEEE80211 stack callback functions.
1816 */
1817 static void rt2500pci_configure_filter(struct ieee80211_hw *hw,
1818 unsigned int changed_flags,
1819 unsigned int *total_flags,
1820 int mc_count,
1821 struct dev_addr_list *mc_list)
1822 {
1823 struct rt2x00_dev *rt2x00dev = hw->priv;
1824 struct interface *intf = &rt2x00dev->interface;
1825 u32 reg;
1826
1827 /*
1828 * Mask off any flags we are going to ignore from
1829 * the total_flags field.
1830 */
1831 *total_flags &=
1832 FIF_ALLMULTI |
1833 FIF_FCSFAIL |
1834 FIF_PLCPFAIL |
1835 FIF_CONTROL |
1836 FIF_OTHER_BSS |
1837 FIF_PROMISC_IN_BSS;
1838
1839 /*
1840 * Apply some rules to the filters:
1841 * - Some filters imply different filters to be set.
1842 * - Some things we can't filter out at all.
1843 * - Some filters are set based on interface type.
1844 */
1845 if (mc_count)
1846 *total_flags |= FIF_ALLMULTI;
1847 if (changed_flags & FIF_OTHER_BSS ||
1848 changed_flags & FIF_PROMISC_IN_BSS)
1849 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1850 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
1851 *total_flags |= FIF_PROMISC_IN_BSS;
1852
1853 /*
1854 * Check if there is any work left for us.
1855 */
1856 if (intf->filter == *total_flags)
1857 return;
1858 intf->filter = *total_flags;
1859
1860 /*
1861 * Start configuration steps.
1862 * Note that the version error will always be dropped
1863 * and broadcast frames will always be accepted since
1864 * there is no filter for it at this time.
1865 */
1866 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1867 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1868 !(*total_flags & FIF_FCSFAIL));
1869 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1870 !(*total_flags & FIF_PLCPFAIL));
1871 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1872 !(*total_flags & FIF_CONTROL));
1873 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1874 !(*total_flags & FIF_PROMISC_IN_BSS));
1875 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1876 !(*total_flags & FIF_PROMISC_IN_BSS));
1877 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1878 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
1879 !(*total_flags & FIF_ALLMULTI));
1880 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
1881 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1882 }
1883
1884 static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1885 u32 short_retry, u32 long_retry)
1886 {
1887 struct rt2x00_dev *rt2x00dev = hw->priv;
1888 u32 reg;
1889
1890 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1891 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1892 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1893 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1894
1895 return 0;
1896 }
1897
1898 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1899 {
1900 struct rt2x00_dev *rt2x00dev = hw->priv;
1901 u64 tsf;
1902 u32 reg;
1903
1904 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1905 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1906 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1907 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1908
1909 return tsf;
1910 }
1911
1912 static void rt2500pci_reset_tsf(struct ieee80211_hw *hw)
1913 {
1914 struct rt2x00_dev *rt2x00dev = hw->priv;
1915
1916 rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1917 rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1918 }
1919
1920 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1921 {
1922 struct rt2x00_dev *rt2x00dev = hw->priv;
1923 u32 reg;
1924
1925 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1926 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1927 }
1928
1929 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1930 .tx = rt2x00mac_tx,
1931 .start = rt2x00mac_start,
1932 .stop = rt2x00mac_stop,
1933 .add_interface = rt2x00mac_add_interface,
1934 .remove_interface = rt2x00mac_remove_interface,
1935 .config = rt2x00mac_config,
1936 .config_interface = rt2x00mac_config_interface,
1937 .configure_filter = rt2500pci_configure_filter,
1938 .get_stats = rt2x00mac_get_stats,
1939 .set_retry_limit = rt2500pci_set_retry_limit,
1940 .conf_tx = rt2x00mac_conf_tx,
1941 .get_tx_stats = rt2x00mac_get_tx_stats,
1942 .get_tsf = rt2500pci_get_tsf,
1943 .reset_tsf = rt2500pci_reset_tsf,
1944 .beacon_update = rt2x00pci_beacon_update,
1945 .tx_last_beacon = rt2500pci_tx_last_beacon,
1946 };
1947
1948 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1949 .irq_handler = rt2500pci_interrupt,
1950 .probe_hw = rt2500pci_probe_hw,
1951 .initialize = rt2x00pci_initialize,
1952 .uninitialize = rt2x00pci_uninitialize,
1953 .set_device_state = rt2500pci_set_device_state,
1954 #ifdef CONFIG_RT2500PCI_RFKILL
1955 .rfkill_poll = rt2500pci_rfkill_poll,
1956 #endif /* CONFIG_RT2500PCI_RFKILL */
1957 .link_stats = rt2500pci_link_stats,
1958 .reset_tuner = rt2500pci_reset_tuner,
1959 .link_tuner = rt2500pci_link_tuner,
1960 .write_tx_desc = rt2500pci_write_tx_desc,
1961 .write_tx_data = rt2x00pci_write_tx_data,
1962 .kick_tx_queue = rt2500pci_kick_tx_queue,
1963 .fill_rxdone = rt2500pci_fill_rxdone,
1964 .config_mac_addr = rt2500pci_config_mac_addr,
1965 .config_bssid = rt2500pci_config_bssid,
1966 .config_type = rt2500pci_config_type,
1967 .config = rt2500pci_config,
1968 };
1969
1970 static const struct rt2x00_ops rt2500pci_ops = {
1971 .name = DRV_NAME,
1972 .rxd_size = RXD_DESC_SIZE,
1973 .txd_size = TXD_DESC_SIZE,
1974 .eeprom_size = EEPROM_SIZE,
1975 .rf_size = RF_SIZE,
1976 .lib = &rt2500pci_rt2x00_ops,
1977 .hw = &rt2500pci_mac80211_ops,
1978 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1979 .debugfs = &rt2500pci_rt2x00debug,
1980 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1981 };
1982
1983 /*
1984 * RT2500pci module information.
1985 */
1986 static struct pci_device_id rt2500pci_device_table[] = {
1987 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1988 { 0, }
1989 };
1990
1991 MODULE_AUTHOR(DRV_PROJECT);
1992 MODULE_VERSION(DRV_VERSION);
1993 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1994 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1995 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1996 MODULE_LICENSE("GPL");
1997
1998 static struct pci_driver rt2500pci_driver = {
1999 .name = DRV_NAME,
2000 .id_table = rt2500pci_device_table,
2001 .probe = rt2x00pci_probe,
2002 .remove = __devexit_p(rt2x00pci_remove),
2003 .suspend = rt2x00pci_suspend,
2004 .resume = rt2x00pci_resume,
2005 };
2006
2007 static int __init rt2500pci_init(void)
2008 {
2009 return pci_register_driver(&rt2500pci_driver);
2010 }
2011
2012 static void __exit rt2500pci_exit(void)
2013 {
2014 pci_unregister_driver(&rt2500pci_driver);
2015 }
2016
2017 module_init(rt2500pci_init);
2018 module_exit(rt2500pci_exit);
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